11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 24baa9922430662431231ac637adedddbb0cfb2d7Russell King * arch/arm/include/asm/vfp.h 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * VFP register definitions. 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * First, the standard VFP set. 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSID cr0 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR cr1 1025ebee020bd34d1f4c5678538204f0b10bf9f6d5Catalin Marinas#define MVFR1 cr6 1125ebee020bd34d1f4c5678538204f0b10bf9f6d5Catalin Marinas#define MVFR0 cr7 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPEXC cr8 13c98929c07a01c9ec2e1e5253456acc7168da8b66Catalin Marinas#define FPINST cr9 14c98929c07a01c9ec2e1e5253456acc7168da8b66Catalin Marinas#define FPINST2 cr10 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* FPSID bits */ 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSID_IMPLEMENTER_BIT (24) 181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSID_IMPLEMENTER_MASK (0xff << FPSID_IMPLEMENTER_BIT) 191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSID_SOFTWARE (1<<23) 201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSID_FORMAT_BIT (21) 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSID_FORMAT_MASK (0x3 << FPSID_FORMAT_BIT) 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSID_NODOUBLE (1<<20) 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSID_ARCH_BIT (16) 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT) 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSID_PART_BIT (8) 261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSID_PART_MASK (0xFF << FPSID_PART_BIT) 271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSID_VARIANT_BIT (4) 281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT) 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSID_REV_BIT (0) 301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSID_REV_MASK (0xF << FPSID_REV_BIT) 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* FPEXC bits */ 33228adef16d6e7b7725ef6b9ba760810d5966afa5Russell King#define FPEXC_EX (1 << 31) 34228adef16d6e7b7725ef6b9ba760810d5966afa5Russell King#define FPEXC_EN (1 << 30) 35c98929c07a01c9ec2e1e5253456acc7168da8b66Catalin Marinas#define FPEXC_DEX (1 << 29) 36c98929c07a01c9ec2e1e5253456acc7168da8b66Catalin Marinas#define FPEXC_FP2V (1 << 28) 37c98929c07a01c9ec2e1e5253456acc7168da8b66Catalin Marinas#define FPEXC_VV (1 << 27) 38c98929c07a01c9ec2e1e5253456acc7168da8b66Catalin Marinas#define FPEXC_TFV (1 << 26) 39c98929c07a01c9ec2e1e5253456acc7168da8b66Catalin Marinas#define FPEXC_LENGTH_BIT (8) 40c98929c07a01c9ec2e1e5253456acc7168da8b66Catalin Marinas#define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT) 41c98929c07a01c9ec2e1e5253456acc7168da8b66Catalin Marinas#define FPEXC_IDF (1 << 7) 42c98929c07a01c9ec2e1e5253456acc7168da8b66Catalin Marinas#define FPEXC_IXF (1 << 4) 43c98929c07a01c9ec2e1e5253456acc7168da8b66Catalin Marinas#define FPEXC_UFF (1 << 3) 44c98929c07a01c9ec2e1e5253456acc7168da8b66Catalin Marinas#define FPEXC_OFF (1 << 2) 45c98929c07a01c9ec2e1e5253456acc7168da8b66Catalin Marinas#define FPEXC_DZF (1 << 1) 46c98929c07a01c9ec2e1e5253456acc7168da8b66Catalin Marinas#define FPEXC_IOF (1 << 0) 47c98929c07a01c9ec2e1e5253456acc7168da8b66Catalin Marinas#define FPEXC_TRAP_MASK (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF) 481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* FPSCR bits */ 501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_DEFAULT_NAN (1<<25) 511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_FLUSHTOZERO (1<<24) 521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_ROUND_NEAREST (0<<22) 531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_ROUND_PLUSINF (1<<22) 541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_ROUND_MINUSINF (2<<22) 551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_ROUND_TOZERO (3<<22) 561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_RMODE_BIT (22) 571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT) 581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_STRIDE_BIT (20) 591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT) 601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_LENGTH_BIT (16) 611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT) 621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_IOE (1<<8) 631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_DZE (1<<9) 641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_OFE (1<<10) 651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_UFE (1<<11) 661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_IXE (1<<12) 671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_IDE (1<<15) 681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_IOC (1<<0) 691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_DZC (1<<1) 701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_OFC (1<<2) 711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_UFC (1<<3) 721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_IXC (1<<4) 731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FPSCR_IDC (1<<7) 741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7525ebee020bd34d1f4c5678538204f0b10bf9f6d5Catalin Marinas/* MVFR0 bits */ 7625ebee020bd34d1f4c5678538204f0b10bf9f6d5Catalin Marinas#define MVFR0_A_SIMD_BIT (0) 7725ebee020bd34d1f4c5678538204f0b10bf9f6d5Catalin Marinas#define MVFR0_A_SIMD_MASK (0xf << MVFR0_A_SIMD_BIT) 7825ebee020bd34d1f4c5678538204f0b10bf9f6d5Catalin Marinas 791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Bit patterns for decoding the packaged operation descriptors */ 801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define VFPOPDESC_LENGTH_BIT (9) 811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define VFPOPDESC_LENGTH_MASK (0x07 << VFPOPDESC_LENGTH_BIT) 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define VFPOPDESC_UNUSED_BIT (24) 831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define VFPOPDESC_UNUSED_MASK (0xFF << VFPOPDESC_UNUSED_BIT) 841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define VFPOPDESC_OPDESC_MASK (~(VFPOPDESC_LENGTH_MASK | VFPOPDESC_UNUSED_MASK)) 85