1/* 2 * arch/arm/mach-dove/addr-map.c 3 * 4 * Address map functions for Marvell Dove 88AP510 SoC 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11#include <linux/kernel.h> 12#include <linux/init.h> 13#include <linux/mbus.h> 14#include <linux/io.h> 15#include <asm/mach/arch.h> 16#include <asm/setup.h> 17#include <mach/dove.h> 18#include <plat/addr-map.h> 19#include "common.h" 20 21/* 22 * Generic Address Decode Windows bit settings 23 */ 24#define TARGET_DDR 0x0 25#define TARGET_BOOTROM 0x1 26#define TARGET_CESA 0x3 27#define TARGET_PCIE0 0x4 28#define TARGET_PCIE1 0x8 29#define TARGET_SCRATCHPAD 0xd 30 31#define ATTR_CESA 0x01 32#define ATTR_BOOTROM 0xfd 33#define ATTR_DEV_SPI0_ROM 0xfe 34#define ATTR_DEV_SPI1_ROM 0xfb 35#define ATTR_PCIE_IO 0xe0 36#define ATTR_PCIE_MEM 0xe8 37#define ATTR_SCRATCHPAD 0x0 38 39static inline void __iomem *ddr_map_sc(int i) 40{ 41 return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4)); 42} 43 44/* 45 * Description of the windows needed by the platform code 46 */ 47static struct __initdata orion_addr_map_cfg addr_map_cfg = { 48 .num_wins = 8, 49 .remappable_wins = 4, 50 .bridge_virt_base = BRIDGE_VIRT_BASE, 51}; 52 53static const struct __initdata orion_addr_map_info addr_map_info[] = { 54 /* 55 * Windows for PCIe IO+MEM space. 56 */ 57 { 0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE, 58 TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE 59 }, 60 { 1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE, 61 TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE 62 }, 63 { 2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE, 64 TARGET_PCIE0, ATTR_PCIE_MEM, -1 65 }, 66 { 3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE, 67 TARGET_PCIE1, ATTR_PCIE_MEM, -1 68 }, 69 /* 70 * Window for CESA engine. 71 */ 72 { 4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE, 73 TARGET_CESA, ATTR_CESA, -1 74 }, 75 /* 76 * Window to the BootROM for Standby and Sleep Resume 77 */ 78 { 5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE, 79 TARGET_BOOTROM, ATTR_BOOTROM, -1 80 }, 81 /* 82 * Window to the PMU Scratch Pad space 83 */ 84 { 6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE, 85 TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1 86 }, 87 /* End marker */ 88 { -1, 0, 0, 0, 0, 0 } 89}; 90 91void __init dove_setup_cpu_mbus(void) 92{ 93 int i; 94 int cs; 95 96 /* 97 * Disable, clear and configure windows. 98 */ 99 orion_config_wins(&addr_map_cfg, addr_map_info); 100 101 /* 102 * Setup MBUS dram target info. 103 */ 104 orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; 105 106 for (i = 0, cs = 0; i < 2; i++) { 107 u32 map = readl(ddr_map_sc(i)); 108 109 /* 110 * Chip select enabled? 111 */ 112 if (map & 1) { 113 struct mbus_dram_window *w; 114 115 w = &orion_mbus_dram_info.cs[cs++]; 116 w->cs_index = i; 117 w->mbus_attr = 0; /* CS address decoding done inside */ 118 /* the DDR controller, no need to */ 119 /* provide attributes */ 120 w->base = map & 0xff800000; 121 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); 122 } 123 } 124 orion_mbus_dram_info.num_cs = cs; 125} 126