1c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells/* 2c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * arch/arm/mach-lpc32xx/irq.c 3c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * 4c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * Author: Kevin Wells <kevin.wells@nxp.com> 5c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * 6c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * Copyright (C) 2010 NXP Semiconductors 7c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * 8c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * This program is free software; you can redistribute it and/or modify 9c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * it under the terms of the GNU General Public License as published by 10c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * the Free Software Foundation; either version 2 of the License, or 11c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * (at your option) any later version. 12c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * 13c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * This program is distributed in the hope that it will be useful, 14c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * but WITHOUT ANY WARRANTY; without even the implied warranty of 15c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * GNU General Public License for more details. 17c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells */ 18c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 19c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells#include <linux/kernel.h> 20c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells#include <linux/types.h> 21c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells#include <linux/interrupt.h> 22c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells#include <linux/irq.h> 23c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells#include <linux/err.h> 24c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells#include <linux/io.h> 25c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 26c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells#include <mach/irqs.h> 27c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells#include <mach/hardware.h> 28c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells#include <mach/platform.h> 29c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells#include "common.h" 30c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 31c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells/* 32c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * Default value representing the Activation polarity of all internal 33c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * interrupt sources 34c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells */ 35c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells#define MIC_APR_DEFAULT 0x3FF0EFE0 36c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells#define SIC1_APR_DEFAULT 0xFBD27186 37c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells#define SIC2_APR_DEFAULT 0x801810C0 38c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 39c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells/* 40c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * Default value representing the Activation Type of all internal 41c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * interrupt sources. All are level sensitive. 42c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells */ 43c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells#define MIC_ATR_DEFAULT 0x00000000 44c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells#define SIC1_ATR_DEFAULT 0x00026000 45c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells#define SIC2_ATR_DEFAULT 0x00000000 46c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 47c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wellsstruct lpc32xx_event_group_regs { 48c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells void __iomem *enab_reg; 49c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells void __iomem *edge_reg; 50c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells void __iomem *maskstat_reg; 51c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells void __iomem *rawstat_reg; 52c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells}; 53c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 54c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wellsstatic const struct lpc32xx_event_group_regs lpc32xx_event_int_regs = { 55c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .enab_reg = LPC32XX_CLKPWR_INT_ER, 56c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .edge_reg = LPC32XX_CLKPWR_INT_AP, 57c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .maskstat_reg = LPC32XX_CLKPWR_INT_SR, 58c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .rawstat_reg = LPC32XX_CLKPWR_INT_RS, 59c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells}; 60c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 61c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wellsstatic const struct lpc32xx_event_group_regs lpc32xx_event_pin_regs = { 62c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .enab_reg = LPC32XX_CLKPWR_PIN_ER, 63c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .edge_reg = LPC32XX_CLKPWR_PIN_AP, 64c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .maskstat_reg = LPC32XX_CLKPWR_PIN_SR, 65c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .rawstat_reg = LPC32XX_CLKPWR_PIN_RS, 66c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells}; 67c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 68c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wellsstruct lpc32xx_event_info { 69c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells const struct lpc32xx_event_group_regs *event_group; 70c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells u32 mask; 71c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells}; 72c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 73c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells/* 74c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * Maps an IRQ number to and event mask and register 75c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells */ 76c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wellsstatic const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = { 77c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_GPI_08] = { 78c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_pin_regs, 79c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT, 80c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 81c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_GPI_09] = { 82c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_pin_regs, 83c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT, 84c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 85c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_GPI_19] = { 86c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_pin_regs, 87c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT, 88c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 89c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_GPI_07] = { 90c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_pin_regs, 91c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT, 92c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 93c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_GPI_00] = { 94c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_pin_regs, 95c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT, 96c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 97c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_GPI_01] = { 98c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_pin_regs, 99c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT, 100c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 101c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_GPI_02] = { 102c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_pin_regs, 103c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT, 104c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 105c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_GPI_03] = { 106c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_pin_regs, 107c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT, 108c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 109c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_GPI_04] = { 110c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_pin_regs, 111c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT, 112c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 113c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_GPI_05] = { 114c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_pin_regs, 115c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT, 116c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 117c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_GPI_06] = { 118c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_pin_regs, 119c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT, 120c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 121f6737055c1c432a9628a9a731f9881ad8e0a9eeeRoland Stigge [IRQ_LPC32XX_GPI_28] = { 122f6737055c1c432a9628a9a731f9881ad8e0a9eeeRoland Stigge .event_group = &lpc32xx_event_pin_regs, 123f6737055c1c432a9628a9a731f9881ad8e0a9eeeRoland Stigge .mask = LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT, 124f6737055c1c432a9628a9a731f9881ad8e0a9eeeRoland Stigge }, 125c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_GPIO_00] = { 126c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_int_regs, 127c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT, 128c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 129c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_GPIO_01] = { 130c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_int_regs, 131c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT, 132c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 133c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_GPIO_02] = { 134c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_int_regs, 135c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT, 136c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 137c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_GPIO_03] = { 138c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_int_regs, 139c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT, 140c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 141c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_GPIO_04] = { 142c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_int_regs, 143c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT, 144c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 145c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_GPIO_05] = { 146c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_int_regs, 147c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT, 148c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 149c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_KEY] = { 150c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_int_regs, 151c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_INTSRC_KEY_BIT, 152c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 153c20b909be9ba27173294a52d08cab293ec030a2cRoland Stigge [IRQ_LPC32XX_ETHERNET] = { 154c20b909be9ba27173294a52d08cab293ec030a2cRoland Stigge .event_group = &lpc32xx_event_int_regs, 155c20b909be9ba27173294a52d08cab293ec030a2cRoland Stigge .mask = LPC32XX_CLKPWR_INTSRC_MAC_BIT, 156c20b909be9ba27173294a52d08cab293ec030a2cRoland Stigge }, 157c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_USB_OTG_ATX] = { 158c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_int_regs, 159c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT, 160c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 161c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_USB_HOST] = { 162c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_int_regs, 163c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_INTSRC_USB_BIT, 164c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 165c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_RTC] = { 166c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_int_regs, 167c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_INTSRC_RTC_BIT, 168c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 169c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_MSTIMER] = { 170c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_int_regs, 171c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT, 172c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 173c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_TS_AUX] = { 174c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_int_regs, 175c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT, 176c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 177c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_TS_P] = { 178c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_int_regs, 179c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_INTSRC_TS_P_BIT, 180c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 181c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells [IRQ_LPC32XX_TS_IRQ] = { 182c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .event_group = &lpc32xx_event_int_regs, 183c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells .mask = LPC32XX_CLKPWR_INTSRC_ADC_BIT, 184c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells }, 185c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells}; 186c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 187c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wellsstatic void get_controller(unsigned int irq, unsigned int *base, 188c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells unsigned int *irqbit) 189c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells{ 190c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells if (irq < 32) { 191c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells *base = LPC32XX_MIC_BASE; 192c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells *irqbit = 1 << irq; 193c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells } else if (irq < 64) { 194c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells *base = LPC32XX_SIC1_BASE; 195c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells *irqbit = 1 << (irq - 32); 196c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells } else { 197c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells *base = LPC32XX_SIC2_BASE; 198c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells *irqbit = 1 << (irq - 64); 199c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells } 200c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells} 201c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 2025638538117ea81063b0611a7374c0d65133860ecLennert Buytenhekstatic void lpc32xx_mask_irq(struct irq_data *d) 203c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells{ 204c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells unsigned int reg, ctrl, mask; 205c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 2065638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek get_controller(d->irq, &ctrl, &mask); 207c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 208c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask; 209c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); 210c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells} 211c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 2125638538117ea81063b0611a7374c0d65133860ecLennert Buytenhekstatic void lpc32xx_unmask_irq(struct irq_data *d) 213c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells{ 214c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells unsigned int reg, ctrl, mask; 215c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 2165638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek get_controller(d->irq, &ctrl, &mask); 217c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 218c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask; 219c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); 220c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells} 221c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 2225638538117ea81063b0611a7374c0d65133860ecLennert Buytenhekstatic void lpc32xx_ack_irq(struct irq_data *d) 223c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells{ 224c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells unsigned int ctrl, mask; 225c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 2265638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek get_controller(d->irq, &ctrl, &mask); 227c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 228c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl)); 229c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 230c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* Also need to clear pending wake event */ 2315638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek if (lpc32xx_events[d->irq].mask != 0) 2325638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek __raw_writel(lpc32xx_events[d->irq].mask, 2335638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek lpc32xx_events[d->irq].event_group->rawstat_reg); 234c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells} 235c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 236c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wellsstatic void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level, 237c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells int use_edge) 238c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells{ 239c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells unsigned int reg, ctrl, mask; 240c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 241c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells get_controller(irq, &ctrl, &mask); 242c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 243c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* Activation level, high or low */ 244c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells reg = __raw_readl(LPC32XX_INTC_POLAR(ctrl)); 245c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells if (use_high_level) 246c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells reg |= mask; 247c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells else 248c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells reg &= ~mask; 249c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(reg, LPC32XX_INTC_POLAR(ctrl)); 250c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 251c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* Activation type, edge or level */ 252c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells reg = __raw_readl(LPC32XX_INTC_ACT_TYPE(ctrl)); 253c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells if (use_edge) 254c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells reg |= mask; 255c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells else 256c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells reg &= ~mask; 257c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl)); 258c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 259c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* Use same polarity for the wake events */ 260c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells if (lpc32xx_events[irq].mask != 0) { 261c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells reg = __raw_readl(lpc32xx_events[irq].event_group->edge_reg); 262c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 263c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells if (use_high_level) 264c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells reg |= lpc32xx_events[irq].mask; 265c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells else 266c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells reg &= ~lpc32xx_events[irq].mask; 267c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 268c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(reg, lpc32xx_events[irq].event_group->edge_reg); 269c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells } 270c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells} 271c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 2725638538117ea81063b0611a7374c0d65133860ecLennert Buytenhekstatic int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type) 273c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells{ 274c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells switch (type) { 275c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells case IRQ_TYPE_EDGE_RISING: 276c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* Rising edge sensitive */ 2775638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek __lpc32xx_set_irq_type(d->irq, 1, 1); 278c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells break; 279c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 280c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells case IRQ_TYPE_EDGE_FALLING: 281c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* Falling edge sensitive */ 2825638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek __lpc32xx_set_irq_type(d->irq, 0, 1); 283c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells break; 284c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 285c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells case IRQ_TYPE_LEVEL_LOW: 286c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* Low level sensitive */ 2875638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek __lpc32xx_set_irq_type(d->irq, 0, 0); 288c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells break; 289c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 290c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells case IRQ_TYPE_LEVEL_HIGH: 291c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* High level sensitive */ 2925638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek __lpc32xx_set_irq_type(d->irq, 1, 0); 293c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells break; 294c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 295c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* Other modes are not supported */ 296c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells default: 297c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells return -EINVAL; 298c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells } 299c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 300c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* Ok to use the level handler for all types */ 3016845664a6a7d443f03883db59d10749d38d98b8eThomas Gleixner irq_set_handler(d->irq, handle_level_irq); 302c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 303c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells return 0; 304c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells} 305c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 3065638538117ea81063b0611a7374c0d65133860ecLennert Buytenhekstatic int lpc32xx_irq_wake(struct irq_data *d, unsigned int state) 307c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells{ 308c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells unsigned long eventreg; 309c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 3105638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek if (lpc32xx_events[d->irq].mask != 0) { 3115638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek eventreg = __raw_readl(lpc32xx_events[d->irq]. 312c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells event_group->enab_reg); 313c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 314c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells if (state) 3155638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek eventreg |= lpc32xx_events[d->irq].mask; 31694ed7830cba4dce57b18a2926b5d826bfd184bd6Roland Stigge else { 3175638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek eventreg &= ~lpc32xx_events[d->irq].mask; 318c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 31994ed7830cba4dce57b18a2926b5d826bfd184bd6Roland Stigge /* 32094ed7830cba4dce57b18a2926b5d826bfd184bd6Roland Stigge * When disabling the wakeup, clear the latched 32194ed7830cba4dce57b18a2926b5d826bfd184bd6Roland Stigge * event 32294ed7830cba4dce57b18a2926b5d826bfd184bd6Roland Stigge */ 32394ed7830cba4dce57b18a2926b5d826bfd184bd6Roland Stigge __raw_writel(lpc32xx_events[d->irq].mask, 32494ed7830cba4dce57b18a2926b5d826bfd184bd6Roland Stigge lpc32xx_events[d->irq]. 32594ed7830cba4dce57b18a2926b5d826bfd184bd6Roland Stigge event_group->rawstat_reg); 32694ed7830cba4dce57b18a2926b5d826bfd184bd6Roland Stigge } 32794ed7830cba4dce57b18a2926b5d826bfd184bd6Roland Stigge 328c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(eventreg, 3295638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek lpc32xx_events[d->irq].event_group->enab_reg); 330c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 331c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells return 0; 332c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells } 333c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 334c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* Clear event */ 3355638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek __raw_writel(lpc32xx_events[d->irq].mask, 3365638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek lpc32xx_events[d->irq].event_group->rawstat_reg); 337c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 338c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells return -ENODEV; 339c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells} 340c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 341c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wellsstatic void __init lpc32xx_set_default_mappings(unsigned int apr, 342c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells unsigned int atr, unsigned int offset) 343c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells{ 344c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells unsigned int i; 345c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 346c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* Set activation levels for each interrupt */ 347c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells i = 0; 348c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells while (i < 32) { 349c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __lpc32xx_set_irq_type(offset + i, ((apr >> i) & 0x1), 350c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells ((atr >> i) & 0x1)); 351c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells i++; 352c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells } 353c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells} 354c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 355c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wellsstatic struct irq_chip lpc32xx_irq_chip = { 3565638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek .irq_ack = lpc32xx_ack_irq, 3575638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek .irq_mask = lpc32xx_mask_irq, 3585638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek .irq_unmask = lpc32xx_unmask_irq, 3595638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek .irq_set_type = lpc32xx_set_irq_type, 3605638538117ea81063b0611a7374c0d65133860ecLennert Buytenhek .irq_set_wake = lpc32xx_irq_wake 361c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells}; 362c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 363c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wellsstatic void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc) 364c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells{ 365c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC1_BASE)); 366c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 367c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells while (ints != 0) { 368c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells int irqno = fls(ints) - 1; 369c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 370c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells ints &= ~(1 << irqno); 371c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 372c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells generic_handle_irq(LPC32XX_SIC1_IRQ(irqno)); 373c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells } 374c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells} 375c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 376c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wellsstatic void lpc32xx_sic2_handler(unsigned int irq, struct irq_desc *desc) 377c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells{ 378c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC2_BASE)); 379c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 380c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells while (ints != 0) { 381c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells int irqno = fls(ints) - 1; 382c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 383c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells ints &= ~(1 << irqno); 384c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 385c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells generic_handle_irq(LPC32XX_SIC2_IRQ(irqno)); 386c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells } 387c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells} 388c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 389c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wellsvoid __init lpc32xx_init_irq(void) 390c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells{ 391c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells unsigned int i; 392c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 393c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* Setup MIC */ 394c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE)); 395c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_MIC_BASE)); 396c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_MIC_BASE)); 397c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 398c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* Setup SIC1 */ 399c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE)); 40035dd0a75d4a382e7f769dd0277732e7aa5235718Roland Stigge __raw_writel(SIC1_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE)); 40135dd0a75d4a382e7f769dd0277732e7aa5235718Roland Stigge __raw_writel(SIC1_ATR_DEFAULT, 40235dd0a75d4a382e7f769dd0277732e7aa5235718Roland Stigge LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE)); 403c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 404c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* Setup SIC2 */ 405c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); 40635dd0a75d4a382e7f769dd0277732e7aa5235718Roland Stigge __raw_writel(SIC2_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE)); 40735dd0a75d4a382e7f769dd0277732e7aa5235718Roland Stigge __raw_writel(SIC2_ATR_DEFAULT, 40835dd0a75d4a382e7f769dd0277732e7aa5235718Roland Stigge LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE)); 409c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 410c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* Configure supported IRQ's */ 411c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells for (i = 0; i < NR_IRQS; i++) { 412f38c02f3b338651e145aac2889ba976baf6b28b3Thomas Gleixner irq_set_chip_and_handler(i, &lpc32xx_irq_chip, 413f38c02f3b338651e145aac2889ba976baf6b28b3Thomas Gleixner handle_level_irq); 414c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells set_irq_flags(i, IRQF_VALID); 415c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells } 416c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 417c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* Set default mappings */ 418c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells lpc32xx_set_default_mappings(MIC_APR_DEFAULT, MIC_ATR_DEFAULT, 0); 419c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells lpc32xx_set_default_mappings(SIC1_APR_DEFAULT, SIC1_ATR_DEFAULT, 32); 420c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells lpc32xx_set_default_mappings(SIC2_APR_DEFAULT, SIC2_ATR_DEFAULT, 64); 421c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 422c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* mask all interrupts except SUBIRQ */ 423c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE)); 424c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE)); 425c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); 426c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 427c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* MIC SUBIRQx interrupts will route handling to the chain handlers */ 4286845664a6a7d443f03883db59d10749d38d98b8eThomas Gleixner irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler); 4296845664a6a7d443f03883db59d10749d38d98b8eThomas Gleixner irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler); 430c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 431c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* Initially disable all wake events */ 432c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(0, LPC32XX_CLKPWR_P01_ER); 433c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(0, LPC32XX_CLKPWR_INT_ER); 434c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(0, LPC32XX_CLKPWR_PIN_ER); 435c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 436c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* 437c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * Default wake activation polarities, all pin sources are low edge 438c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells * triggered 439c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells */ 440c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(LPC32XX_CLKPWR_INTSRC_TS_P_BIT | 441c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT | 442c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells LPC32XX_CLKPWR_INTSRC_RTC_BIT, 443c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells LPC32XX_CLKPWR_INT_AP); 444c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(0, LPC32XX_CLKPWR_PIN_AP); 445c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells 446c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells /* Clear latched wake event states */ 447c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(__raw_readl(LPC32XX_CLKPWR_PIN_RS), 448c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells LPC32XX_CLKPWR_PIN_RS); 449c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells __raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS), 450c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells LPC32XX_CLKPWR_INT_RS); 451c4a0208fff6cba5c7e22166ad7209322eab16bb3Kevin Wells} 452