18f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean/* 28f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean * Copyright (C) 2007 Google, Inc. 38f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean * Copyright (c) 2009, Code Aurora Forum. All rights reserved. 48f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean * Author: Brian Swetland <swetland@google.com> 58f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean */ 68f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean 78f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#ifndef __ASM_ARCH_MSM_IRQS_7X00_H 88f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define __ASM_ARCH_MSM_IRQS_7X00_H 98f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean 108f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean/* MSM ARM11 Interrupt Numbers */ 118f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean/* See 80-VE113-1 A, pp219-221 */ 128f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean 138f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_A9_M2A_0 0 148f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_A9_M2A_1 1 158f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_A9_M2A_2 2 168f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_A9_M2A_3 3 178f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_A9_M2A_4 4 188f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_A9_M2A_5 5 198f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_A9_M2A_6 6 208f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_GP_TIMER_EXP 7 218f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_DEBUG_TIMER_EXP 8 228f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_UART1 9 238f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_UART2 10 248f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_UART3 11 258f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_UART1_RX 12 268f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_UART2_RX 13 278f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_UART3_RX 14 288f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_USB_OTG 15 298f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_MDDI_PRI 16 308f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_MDDI_EXT 17 318f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_MDDI_CLIENT 18 328f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_MDP 19 338f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_GRAPHICS 20 348f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_ADM_AARM 21 358f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_ADSP_A11 22 368f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_ADSP_A9_A11 23 378f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_SDC1_0 24 388f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_SDC1_1 25 398f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_SDC2_0 26 408f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_SDC2_1 27 418f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_KEYSENSE 28 428f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_TCHSCRN_SSBI 29 438f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_TCHSCRN1 30 448f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_TCHSCRN2 31 458f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean 468f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_GPIO_GROUP1 (32 + 0) 478f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_GPIO_GROUP2 (32 + 1) 488f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_PWB_I2C (32 + 2) 498f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_SOFTRESET (32 + 3) 508f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_NAND_WR_ER_DONE (32 + 4) 518f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_NAND_OP_DONE (32 + 5) 528f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_PBUS_ARM11 (32 + 6) 538f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_AXI_MPU_SMI (32 + 7) 548f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_AXI_MPU_EBI1 (32 + 8) 558f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_AD_HSSD (32 + 9) 568f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_ARM11_PMU (32 + 10) 578f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_ARM11_DMA (32 + 11) 588f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_TSIF_IRQ (32 + 12) 598f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_UART1DM_IRQ (32 + 13) 608f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_UART1DM_RX (32 + 14) 618f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_USB_HS (32 + 15) 628f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_SDC3_0 (32 + 16) 638f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_SDC3_1 (32 + 17) 648f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_SDC4_0 (32 + 18) 658f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_SDC4_1 (32 + 19) 668f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_UART2DM_RX (32 + 20) 678f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define INT_UART2DM_IRQ (32 + 21) 688f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean 698f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean/* 22-31 are reserved */ 708f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean 718f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define NR_MSM_IRQS 64 728f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define NR_GPIO_IRQS 122 738f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#define NR_BOARD_IRQS 64 748f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean 758f90c7b60d487866841bfa2fd51792873e54a3a5Gregory Bean#endif 76