1e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. 2e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker * 33162aa2f1b55849651a05052d3e5f5e640ea44faDavid Brown * This program is free software; you can redistribute it and/or modify 43162aa2f1b55849651a05052d3e5f5e640ea44faDavid Brown * it under the terms of the GNU General Public License version 2 and 53162aa2f1b55849651a05052d3e5f5e640ea44faDavid Brown * only version 2 as published by the Free Software Foundation. 6e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker * 73162aa2f1b55849651a05052d3e5f5e640ea44faDavid Brown * This program is distributed in the hope that it will be useful, 83162aa2f1b55849651a05052d3e5f5e640ea44faDavid Brown * but WITHOUT ANY WARRANTY; without even the implied warranty of 93162aa2f1b55849651a05052d3e5f5e640ea44faDavid Brown * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 103162aa2f1b55849651a05052d3e5f5e640ea44faDavid Brown * GNU General Public License for more details. 11e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker */ 12e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker 13e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#ifndef __ASM_ARCH_MSM_IRQS_8XXX_H 14e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define __ASM_ARCH_MSM_IRQS_8XXX_H 15e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker 16e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker/* MSM ACPU Interrupt Numbers */ 17e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker 18e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_A9_M2A_0 0 19e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_A9_M2A_1 1 20e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_A9_M2A_2 2 21e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_A9_M2A_3 3 22e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_A9_M2A_4 4 23e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_A9_M2A_5 5 24e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_A9_M2A_6 6 25e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_GP_TIMER_EXP 7 26e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_DEBUG_TIMER_EXP 8 27e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_SIRC_0 9 28e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_SDC3_0 10 29e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_SDC3_1 11 30e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_SDC4_0 12 31e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_SDC4_1 13 32e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_AD6_EXT_VFR 14 33e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_USB_OTG 15 34e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_MDDI_PRI 16 35e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_MDDI_EXT 17 36e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_MDDI_CLIENT 18 37e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_MDP 19 38e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_GRAPHICS 20 39e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_ADM_AARM 21 40e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_ADSP_A11 22 41e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_ADSP_A9_A11 23 42e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_SDC1_0 24 43e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_SDC1_1 25 44e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_SDC2_0 26 45e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_SDC2_1 27 46e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_KEYSENSE 28 47e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_TCHSCRN_SSBI 29 48e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_TCHSCRN1 30 49e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_TCHSCRN2 31 50e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker 51e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_TCSR_MPRPH_SC1 (32 + 0) 52e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_USB_FS2 (32 + 1) 53e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_PWB_I2C (32 + 2) 54e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_SOFTRESET (32 + 3) 55e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_NAND_WR_ER_DONE (32 + 4) 56e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_NAND_OP_DONE (32 + 5) 57e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_TCSR_MPRPH_SC2 (32 + 6) 58e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_OP_PEN (32 + 7) 59e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_AD_HSSD (32 + 8) 60e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_ARM11_PM (32 + 9) 61e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_SDMA_NON_SECURE (32 + 10) 62e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_TSIF_IRQ (32 + 11) 63e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_UART1DM_IRQ (32 + 12) 64e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_UART1DM_RX (32 + 13) 65e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_SDMA_SECURE (32 + 14) 66e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_SI2S_SLAVE (32 + 15) 67e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_SC_I2CPU (32 + 16) 68e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_SC_DBG_RDTRFULL (32 + 17) 69e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_SC_DBG_WDTRFULL (32 + 18) 70e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_SCPLL_CTL_DONE (32 + 19) 71e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_UART2DM_IRQ (32 + 20) 72e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_UART2DM_RX (32 + 21) 73e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_VDC_MEC (32 + 22) 74e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_VDC_DB (32 + 23) 75e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_VDC_AXI (32 + 24) 76e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_VFE (32 + 25) 77e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_USB_HS (32 + 26) 78e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_AUDIO_OUT0 (32 + 27) 79e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_AUDIO_OUT1 (32 + 28) 80e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_CRYPTO (32 + 29) 81e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_AD6M_IDLE (32 + 30) 82e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define INT_SIRC_1 (32 + 31) 83e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker 84e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define NR_GPIO_IRQS 165 85e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define NR_MSM_IRQS 64 86e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#define NR_BOARD_IRQS 64 87e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker 88e502c3777fb97453fb95c1479cac20ef58f53709Daniel Walker#endif 89