1/* 2 * OMAP4 CPU idle Routines 3 * 4 * Copyright (C) 2011 Texas Instruments, Inc. 5 * Santosh Shilimkar <santosh.shilimkar@ti.com> 6 * Rajendra Nayak <rnayak@ti.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13#include <linux/sched.h> 14#include <linux/cpuidle.h> 15#include <linux/cpu_pm.h> 16#include <linux/export.h> 17#include <linux/clockchips.h> 18 19#include <asm/proc-fns.h> 20 21#include "common.h" 22#include "pm.h" 23#include "prm.h" 24 25#ifdef CONFIG_CPU_IDLE 26 27/* Machine specific information to be recorded in the C-state driver_data */ 28struct omap4_idle_statedata { 29 u32 cpu_state; 30 u32 mpu_logic_state; 31 u32 mpu_state; 32 u8 valid; 33}; 34 35static struct cpuidle_params cpuidle_params_table[] = { 36 /* C1 - CPU0 ON + CPU1 ON + MPU ON */ 37 {.exit_latency = 2 + 2 , .target_residency = 5, .valid = 1}, 38 /* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */ 39 {.exit_latency = 328 + 440 , .target_residency = 960, .valid = 1}, 40 /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */ 41 {.exit_latency = 460 + 518 , .target_residency = 1100, .valid = 1}, 42}; 43 44#define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table) 45 46struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES]; 47static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd; 48 49/** 50 * omap4_enter_idle - Programs OMAP4 to enter the specified state 51 * @dev: cpuidle device 52 * @drv: cpuidle driver 53 * @index: the index of state to be entered 54 * 55 * Called from the CPUidle framework to program the device to the 56 * specified low power state selected by the governor. 57 * Returns the amount of time spent in the low power state. 58 */ 59static int omap4_enter_idle(struct cpuidle_device *dev, 60 struct cpuidle_driver *drv, 61 int index) 62{ 63 struct omap4_idle_statedata *cx = 64 cpuidle_get_statedata(&dev->states_usage[index]); 65 u32 cpu1_state; 66 int cpu_id = smp_processor_id(); 67 68 local_fiq_disable(); 69 70 /* 71 * CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state. 72 * This is necessary to honour hardware recommondation 73 * of triggeing all the possible low power modes once CPU1 is 74 * out of coherency and in OFF mode. 75 * Update dev->last_state so that governor stats reflects right 76 * data. 77 */ 78 cpu1_state = pwrdm_read_pwrst(cpu1_pd); 79 if (cpu1_state != PWRDM_POWER_OFF) { 80 index = drv->safe_state_index; 81 cx = cpuidle_get_statedata(&dev->states_usage[index]); 82 } 83 84 if (index > 0) 85 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id); 86 87 /* 88 * Call idle CPU PM enter notifier chain so that 89 * VFP and per CPU interrupt context is saved. 90 */ 91 if (cx->cpu_state == PWRDM_POWER_OFF) 92 cpu_pm_enter(); 93 94 pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state); 95 omap_set_pwrdm_state(mpu_pd, cx->mpu_state); 96 97 /* 98 * Call idle CPU cluster PM enter notifier chain 99 * to save GIC and wakeupgen context. 100 */ 101 if ((cx->mpu_state == PWRDM_POWER_RET) && 102 (cx->mpu_logic_state == PWRDM_POWER_OFF)) 103 cpu_cluster_pm_enter(); 104 105 omap4_enter_lowpower(dev->cpu, cx->cpu_state); 106 107 /* 108 * Call idle CPU PM exit notifier chain to restore 109 * VFP and per CPU IRQ context. Only CPU0 state is 110 * considered since CPU1 is managed by CPU hotplug. 111 */ 112 if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF) 113 cpu_pm_exit(); 114 115 /* 116 * Call idle CPU cluster PM exit notifier chain 117 * to restore GIC and wakeupgen context. 118 */ 119 if (omap4_mpuss_read_prev_context_state()) 120 cpu_cluster_pm_exit(); 121 122 if (index > 0) 123 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id); 124 125 local_fiq_enable(); 126 127 return index; 128} 129 130DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev); 131 132struct cpuidle_driver omap4_idle_driver = { 133 .name = "omap4_idle", 134 .owner = THIS_MODULE, 135 .en_core_tk_irqen = 1, 136}; 137 138static inline void _fill_cstate(struct cpuidle_driver *drv, 139 int idx, const char *descr) 140{ 141 struct cpuidle_state *state = &drv->states[idx]; 142 143 state->exit_latency = cpuidle_params_table[idx].exit_latency; 144 state->target_residency = cpuidle_params_table[idx].target_residency; 145 state->flags = CPUIDLE_FLAG_TIME_VALID; 146 state->enter = omap4_enter_idle; 147 sprintf(state->name, "C%d", idx + 1); 148 strncpy(state->desc, descr, CPUIDLE_DESC_LEN); 149} 150 151static inline struct omap4_idle_statedata *_fill_cstate_usage( 152 struct cpuidle_device *dev, 153 int idx) 154{ 155 struct omap4_idle_statedata *cx = &omap4_idle_data[idx]; 156 struct cpuidle_state_usage *state_usage = &dev->states_usage[idx]; 157 158 cx->valid = cpuidle_params_table[idx].valid; 159 cpuidle_set_statedata(state_usage, cx); 160 161 return cx; 162} 163 164 165 166/** 167 * omap4_idle_init - Init routine for OMAP4 idle 168 * 169 * Registers the OMAP4 specific cpuidle driver to the cpuidle 170 * framework with the valid set of states. 171 */ 172int __init omap4_idle_init(void) 173{ 174 struct omap4_idle_statedata *cx; 175 struct cpuidle_device *dev; 176 struct cpuidle_driver *drv = &omap4_idle_driver; 177 unsigned int cpu_id = 0; 178 179 mpu_pd = pwrdm_lookup("mpu_pwrdm"); 180 cpu0_pd = pwrdm_lookup("cpu0_pwrdm"); 181 cpu1_pd = pwrdm_lookup("cpu1_pwrdm"); 182 if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd)) 183 return -ENODEV; 184 185 186 drv->safe_state_index = -1; 187 dev = &per_cpu(omap4_idle_dev, cpu_id); 188 dev->cpu = cpu_id; 189 190 /* C1 - CPU0 ON + CPU1 ON + MPU ON */ 191 _fill_cstate(drv, 0, "MPUSS ON"); 192 drv->safe_state_index = 0; 193 cx = _fill_cstate_usage(dev, 0); 194 cx->valid = 1; /* C1 is always valid */ 195 cx->cpu_state = PWRDM_POWER_ON; 196 cx->mpu_state = PWRDM_POWER_ON; 197 cx->mpu_logic_state = PWRDM_POWER_RET; 198 199 /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */ 200 _fill_cstate(drv, 1, "MPUSS CSWR"); 201 cx = _fill_cstate_usage(dev, 1); 202 cx->cpu_state = PWRDM_POWER_OFF; 203 cx->mpu_state = PWRDM_POWER_RET; 204 cx->mpu_logic_state = PWRDM_POWER_RET; 205 206 /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */ 207 _fill_cstate(drv, 2, "MPUSS OSWR"); 208 cx = _fill_cstate_usage(dev, 2); 209 cx->cpu_state = PWRDM_POWER_OFF; 210 cx->mpu_state = PWRDM_POWER_RET; 211 cx->mpu_logic_state = PWRDM_POWER_OFF; 212 213 drv->state_count = OMAP4_NUM_STATES; 214 cpuidle_register_driver(&omap4_idle_driver); 215 216 dev->state_count = OMAP4_NUM_STATES; 217 if (cpuidle_register_device(dev)) { 218 pr_err("%s: CPUidle register device failed\n", __func__); 219 return -EIO; 220 } 221 222 return 0; 223} 224#else 225int __init omap4_idle_init(void) 226{ 227 return 0; 228} 229#endif /* CONFIG_CPU_IDLE */ 230