mach-smdk6410.c revision 001ca74f185f32bd8383146f9ffedd2de9b882ed 
1/* linux/arch/arm/mach-s3c64xx/mach-smdk6410.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 *	Ben Dooks <ben@simtec.co.uk>
6 *	http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/timer.h>
19#include <linux/init.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22#include <linux/io.h>
23#include <linux/i2c.h>
24#include <linux/leds.h>
25#include <linux/fb.h>
26#include <linux/gpio.h>
27#include <linux/delay.h>
28#include <linux/smsc911x.h>
29#include <linux/regulator/fixed.h>
30
31#ifdef CONFIG_SMDK6410_WM1190_EV1
32#include <linux/mfd/wm8350/core.h>
33#include <linux/mfd/wm8350/pmic.h>
34#endif
35
36#ifdef CONFIG_SMDK6410_WM1192_EV1
37#include <linux/mfd/wm831x/core.h>
38#include <linux/mfd/wm831x/pdata.h>
39#endif
40
41#include <video/platform_lcd.h>
42
43#include <asm/mach/arch.h>
44#include <asm/mach/map.h>
45#include <asm/mach/irq.h>
46
47#include <mach/hardware.h>
48#include <mach/regs-fb.h>
49#include <mach/map.h>
50
51#include <asm/irq.h>
52#include <asm/mach-types.h>
53
54#include <plat/regs-serial.h>
55#include <mach/regs-modem.h>
56#include <mach/regs-gpio.h>
57#include <mach/regs-sys.h>
58#include <mach/regs-srom.h>
59#include <plat/iic.h>
60#include <plat/fb.h>
61#include <plat/gpio-cfg.h>
62
63#include <mach/s3c6410.h>
64#include <plat/clock.h>
65#include <plat/devs.h>
66#include <plat/cpu.h>
67#include <plat/adc.h>
68#include <plat/ts.h>
69
70#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
71#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
72#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
73
74static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
75	[0] = {
76		.hwport	     = 0,
77		.flags	     = 0,
78		.ucon	     = UCON,
79		.ulcon	     = ULCON,
80		.ufcon	     = UFCON,
81	},
82	[1] = {
83		.hwport	     = 1,
84		.flags	     = 0,
85		.ucon	     = UCON,
86		.ulcon	     = ULCON,
87		.ufcon	     = UFCON,
88	},
89	[2] = {
90		.hwport	     = 2,
91		.flags	     = 0,
92		.ucon	     = UCON,
93		.ulcon	     = ULCON,
94		.ufcon	     = UFCON,
95	},
96	[3] = {
97		.hwport	     = 3,
98		.flags	     = 0,
99		.ucon	     = UCON,
100		.ulcon	     = ULCON,
101		.ufcon	     = UFCON,
102	},
103};
104
105/* framebuffer and LCD setup. */
106
107/* GPF15 = LCD backlight control
108 * GPF13 => Panel power
109 * GPN5 = LCD nRESET signal
110 * PWM_TOUT1 => backlight brightness
111 */
112
113static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
114				   unsigned int power)
115{
116	if (power) {
117		gpio_direction_output(S3C64XX_GPF(13), 1);
118		gpio_direction_output(S3C64XX_GPF(15), 1);
119
120		/* fire nRESET on power up */
121		gpio_direction_output(S3C64XX_GPN(5), 0);
122		msleep(10);
123		gpio_direction_output(S3C64XX_GPN(5), 1);
124		msleep(1);
125	} else {
126		gpio_direction_output(S3C64XX_GPF(15), 0);
127		gpio_direction_output(S3C64XX_GPF(13), 0);
128	}
129}
130
131static struct plat_lcd_data smdk6410_lcd_power_data = {
132	.set_power	= smdk6410_lcd_power_set,
133};
134
135static struct platform_device smdk6410_lcd_powerdev = {
136	.name			= "platform-lcd",
137	.dev.parent		= &s3c_device_fb.dev,
138	.dev.platform_data	= &smdk6410_lcd_power_data,
139};
140
141static struct s3c_fb_pd_win smdk6410_fb_win0 = {
142	/* this is to ensure we use win0 */
143	.win_mode	= {
144		.pixclock	= 41094,
145		.left_margin	= 8,
146		.right_margin	= 13,
147		.upper_margin	= 7,
148		.lower_margin	= 5,
149		.hsync_len	= 3,
150		.vsync_len	= 1,
151		.xres		= 800,
152		.yres		= 480,
153	},
154	.max_bpp	= 32,
155	.default_bpp	= 16,
156	.virtual_y	= 480 * 2,
157	.virtual_x	= 800,
158};
159
160/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
161static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
162	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
163	.win[0]		= &smdk6410_fb_win0,
164	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
165	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
166};
167
168/*
169 * Configuring Ethernet on SMDK6410
170 *
171 * Both CS8900A and LAN9115 chips share one chip select mediated by CFG6.
172 * The constant address below corresponds to nCS1
173 *
174 *  1) Set CFGB2 p3 ON others off, no other CFGB selects "ethernet"
175 *  2) CFG6 needs to be switched to "LAN9115" side
176 */
177
178static struct resource smdk6410_smsc911x_resources[] = {
179	[0] = {
180		.start = S3C64XX_PA_XM0CSN1,
181		.end   = S3C64XX_PA_XM0CSN1 + SZ_64K - 1,
182		.flags = IORESOURCE_MEM,
183	},
184	[1] = {
185		.start = S3C_EINT(10),
186		.end   = S3C_EINT(10),
187		.flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW,
188	},
189};
190
191static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
192	.irq_polarity  = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
193	.irq_type      = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
194	.flags         = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
195	.phy_interface = PHY_INTERFACE_MODE_MII,
196};
197
198
199static struct platform_device smdk6410_smsc911x = {
200	.name          = "smsc911x",
201	.id            = -1,
202	.num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
203	.resource      = &smdk6410_smsc911x_resources[0],
204	.dev = {
205		.platform_data = &smdk6410_smsc911x_pdata,
206	},
207};
208
209#ifdef CONFIG_REGULATOR
210static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
211	{
212		/* WM8580 */
213		.supply = "PVDD",
214		.dev_name = "0-001b",
215	},
216	{
217		/* WM8580 */
218		.supply = "AVDD",
219		.dev_name = "0-001b",
220	},
221};
222
223static struct regulator_init_data smdk6410_b_pwr_5v_data = {
224	.constraints = {
225		.always_on = 1,
226	},
227	.num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
228	.consumer_supplies = smdk6410_b_pwr_5v_consumers,
229};
230
231static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
232	.supply_name = "B_PWR_5V",
233	.microvolts = 5000000,
234	.init_data = &smdk6410_b_pwr_5v_data,
235	.gpio = -EINVAL,
236};
237
238static struct platform_device smdk6410_b_pwr_5v = {
239	.name          = "reg-fixed-voltage",
240	.id            = -1,
241	.dev = {
242		.platform_data = &smdk6410_b_pwr_5v_pdata,
243	},
244};
245#endif
246
247static struct map_desc smdk6410_iodesc[] = {};
248
249static struct platform_device *smdk6410_devices[] __initdata = {
250#ifdef CONFIG_SMDK6410_SD_CH0
251	&s3c_device_hsmmc0,
252#endif
253#ifdef CONFIG_SMDK6410_SD_CH1
254	&s3c_device_hsmmc1,
255#endif
256	&s3c_device_i2c0,
257	&s3c_device_i2c1,
258	&s3c_device_fb,
259	&s3c_device_ohci,
260	&s3c_device_usb_hsotg,
261	&s3c64xx_device_iisv4,
262
263#ifdef CONFIG_REGULATOR
264	&smdk6410_b_pwr_5v,
265#endif
266	&smdk6410_lcd_powerdev,
267
268	&smdk6410_smsc911x,
269	&s3c_device_adc,
270	&s3c_device_ts,
271	&s3c_device_wdt,
272};
273
274#ifdef CONFIG_REGULATOR
275/* ARM core */
276static struct regulator_consumer_supply smdk6410_vddarm_consumers[] = {
277	{
278		.supply = "vddarm",
279	}
280};
281
282/* VDDARM, BUCK1 on J5 */
283static struct regulator_init_data smdk6410_vddarm = {
284	.constraints = {
285		.name = "PVDD_ARM",
286		.min_uV = 1000000,
287		.max_uV = 1300000,
288		.always_on = 1,
289		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
290	},
291	.num_consumer_supplies = ARRAY_SIZE(smdk6410_vddarm_consumers),
292	.consumer_supplies = smdk6410_vddarm_consumers,
293};
294
295/* VDD_INT, BUCK2 on J5 */
296static struct regulator_init_data smdk6410_vddint = {
297	.constraints = {
298		.name = "PVDD_INT",
299		.min_uV = 1000000,
300		.max_uV = 1200000,
301		.always_on = 1,
302		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
303	},
304};
305
306/* VDD_HI, LDO3 on J5 */
307static struct regulator_init_data smdk6410_vddhi = {
308	.constraints = {
309		.name = "PVDD_HI",
310		.always_on = 1,
311	},
312};
313
314/* VDD_PLL, LDO2 on J5 */
315static struct regulator_init_data smdk6410_vddpll = {
316	.constraints = {
317		.name = "PVDD_PLL",
318		.always_on = 1,
319	},
320};
321
322/* VDD_UH_MMC, LDO5 on J5 */
323static struct regulator_init_data smdk6410_vdduh_mmc = {
324	.constraints = {
325		.name = "PVDD_UH/PVDD_MMC",
326		.always_on = 1,
327	},
328};
329
330/* VCCM3BT, LDO8 on J5 */
331static struct regulator_init_data smdk6410_vccmc3bt = {
332	.constraints = {
333		.name = "PVCCM3BT",
334		.always_on = 1,
335	},
336};
337
338/* VCCM2MTV, LDO11 on J5 */
339static struct regulator_init_data smdk6410_vccm2mtv = {
340	.constraints = {
341		.name = "PVCCM2MTV",
342		.always_on = 1,
343	},
344};
345
346/* VDD_LCD, LDO12 on J5 */
347static struct regulator_init_data smdk6410_vddlcd = {
348	.constraints = {
349		.name = "PVDD_LCD",
350		.always_on = 1,
351	},
352};
353
354/* VDD_OTGI, LDO9 on J5 */
355static struct regulator_init_data smdk6410_vddotgi = {
356	.constraints = {
357		.name = "PVDD_OTGI",
358		.always_on = 1,
359	},
360};
361
362/* VDD_OTG, LDO14 on J5 */
363static struct regulator_init_data smdk6410_vddotg = {
364	.constraints = {
365		.name = "PVDD_OTG",
366		.always_on = 1,
367	},
368};
369
370/* VDD_ALIVE, LDO15 on J5 */
371static struct regulator_init_data smdk6410_vddalive = {
372	.constraints = {
373		.name = "PVDD_ALIVE",
374		.always_on = 1,
375	},
376};
377
378/* VDD_AUDIO, VLDO_AUDIO on J5 */
379static struct regulator_init_data smdk6410_vddaudio = {
380	.constraints = {
381		.name = "PVDD_AUDIO",
382		.always_on = 1,
383	},
384};
385#endif
386
387#ifdef CONFIG_SMDK6410_WM1190_EV1
388/* S3C64xx internal logic & PLL */
389static struct regulator_init_data wm8350_dcdc1_data = {
390	.constraints = {
391		.name = "PVDD_INT/PVDD_PLL",
392		.min_uV = 1200000,
393		.max_uV = 1200000,
394		.always_on = 1,
395		.apply_uV = 1,
396	},
397};
398
399/* Memory */
400static struct regulator_init_data wm8350_dcdc3_data = {
401	.constraints = {
402		.name = "PVDD_MEM",
403		.min_uV = 1800000,
404		.max_uV = 1800000,
405		.always_on = 1,
406		.state_mem = {
407			 .uV = 1800000,
408			 .mode = REGULATOR_MODE_NORMAL,
409			 .enabled = 1,
410		},
411		.initial_state = PM_SUSPEND_MEM,
412	},
413};
414
415/* USB, EXT, PCM, ADC/DAC, USB, MMC */
416static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
417	{
418		/* WM8580 */
419		.supply = "DVDD",
420		.dev_name = "0-001b",
421	},
422};
423
424static struct regulator_init_data wm8350_dcdc4_data = {
425	.constraints = {
426		.name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
427		.min_uV = 3000000,
428		.max_uV = 3000000,
429		.always_on = 1,
430	},
431	.num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
432	.consumer_supplies = wm8350_dcdc4_consumers,
433};
434
435/* OTGi/1190-EV1 HPVDD & AVDD */
436static struct regulator_init_data wm8350_ldo4_data = {
437	.constraints = {
438		.name = "PVDD_OTGI/HPVDD/AVDD",
439		.min_uV = 1200000,
440		.max_uV = 1200000,
441		.apply_uV = 1,
442		.always_on = 1,
443	},
444};
445
446static struct {
447	int regulator;
448	struct regulator_init_data *initdata;
449} wm1190_regulators[] = {
450	{ WM8350_DCDC_1, &wm8350_dcdc1_data },
451	{ WM8350_DCDC_3, &wm8350_dcdc3_data },
452	{ WM8350_DCDC_4, &wm8350_dcdc4_data },
453	{ WM8350_DCDC_6, &smdk6410_vddarm },
454	{ WM8350_LDO_1, &smdk6410_vddalive },
455	{ WM8350_LDO_2, &smdk6410_vddotg },
456	{ WM8350_LDO_3, &smdk6410_vddlcd },
457	{ WM8350_LDO_4, &wm8350_ldo4_data },
458};
459
460static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
461{
462	int i;
463
464	/* Configure the IRQ line */
465	s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
466
467	/* Instantiate the regulators */
468	for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
469		wm8350_register_regulator(wm8350,
470					  wm1190_regulators[i].regulator,
471					  wm1190_regulators[i].initdata);
472
473	return 0;
474}
475
476static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
477	.init = smdk6410_wm8350_init,
478	.irq_high = 1,
479	.irq_base = IRQ_BOARD_START,
480};
481#endif
482
483#ifdef CONFIG_SMDK6410_WM1192_EV1
484static struct gpio_led wm1192_pmic_leds[] = {
485	{
486		.name = "PMIC:red:power",
487		.gpio = GPIO_BOARD_START + 3,
488		.default_state = LEDS_GPIO_DEFSTATE_ON,
489	},
490};
491
492static struct gpio_led_platform_data wm1192_pmic_led = {
493	.num_leds = ARRAY_SIZE(wm1192_pmic_leds),
494	.leds = wm1192_pmic_leds,
495};
496
497static struct platform_device wm1192_pmic_led_dev = {
498	.name          = "leds-gpio",
499	.id            = -1,
500	.dev = {
501		.platform_data = &wm1192_pmic_led,
502	},
503};
504
505static int wm1192_pre_init(struct wm831x *wm831x)
506{
507	int ret;
508
509	/* Configure the IRQ line */
510	s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
511
512	ret = platform_device_register(&wm1192_pmic_led_dev);
513	if (ret != 0)
514		dev_err(wm831x->dev, "Failed to add PMIC LED: %d\n", ret);
515
516	return 0;
517}
518
519static struct wm831x_backlight_pdata wm1192_backlight_pdata = {
520	.isink = 1,
521	.max_uA = 27554,
522};
523
524static struct regulator_init_data wm1192_dcdc3 = {
525	.constraints = {
526		.name = "PVDD_MEM/PVDD_GPS",
527		.always_on = 1,
528	},
529};
530
531static struct regulator_consumer_supply wm1192_ldo1_consumers[] = {
532	{ .supply = "DVDD", .dev_name = "0-001b", },   /* WM8580 */
533};
534
535static struct regulator_init_data wm1192_ldo1 = {
536	.constraints = {
537		.name = "PVDD_LCD/PVDD_EXT",
538		.always_on = 1,
539	},
540	.consumer_supplies = wm1192_ldo1_consumers,
541	.num_consumer_supplies = ARRAY_SIZE(wm1192_ldo1_consumers),
542};
543
544static struct wm831x_status_pdata wm1192_led7_pdata = {
545	.name = "LED7:green:",
546};
547
548static struct wm831x_status_pdata wm1192_led8_pdata = {
549	.name = "LED8:green:",
550};
551
552static struct wm831x_pdata smdk6410_wm1192_pdata = {
553	.pre_init = wm1192_pre_init,
554	.irq_base = IRQ_BOARD_START,
555
556	.backlight = &wm1192_backlight_pdata,
557	.dcdc = {
558		&smdk6410_vddarm,  /* DCDC1 */
559		&smdk6410_vddint,  /* DCDC2 */
560		&wm1192_dcdc3,
561	},
562	.gpio_base = GPIO_BOARD_START,
563	.ldo = {
564		 &wm1192_ldo1,        /* LDO1 */
565		 &smdk6410_vdduh_mmc, /* LDO2 */
566		 NULL,                /* LDO3 NC */
567		 &smdk6410_vddotgi,   /* LDO4 */
568		 &smdk6410_vddotg,    /* LDO5 */
569		 &smdk6410_vddhi,     /* LDO6 */
570		 &smdk6410_vddaudio,  /* LDO7 */
571		 &smdk6410_vccm2mtv,  /* LDO8 */
572		 &smdk6410_vddpll,    /* LDO9 */
573		 &smdk6410_vccmc3bt,  /* LDO10 */
574		 &smdk6410_vddalive,  /* LDO11 */
575	},
576	.status = {
577		&wm1192_led7_pdata,
578		&wm1192_led8_pdata,
579	},
580};
581#endif
582
583static struct i2c_board_info i2c_devs0[] __initdata = {
584	{ I2C_BOARD_INFO("24c08", 0x50), },
585	{ I2C_BOARD_INFO("wm8580", 0x1b), },
586
587#ifdef CONFIG_SMDK6410_WM1192_EV1
588	{ I2C_BOARD_INFO("wm8312", 0x34),
589	  .platform_data = &smdk6410_wm1192_pdata,
590	  .irq = S3C_EINT(12),
591	},
592#endif
593
594#ifdef CONFIG_SMDK6410_WM1190_EV1
595	{ I2C_BOARD_INFO("wm8350", 0x1a),
596	  .platform_data = &smdk6410_wm8350_pdata,
597	  .irq = S3C_EINT(12),
598	},
599#endif
600};
601
602static struct i2c_board_info i2c_devs1[] __initdata = {
603	{ I2C_BOARD_INFO("24c128", 0x57), },	/* Samsung S524AD0XD1 */
604};
605
606static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
607	.delay			= 10000,
608	.presc			= 49,
609	.oversampling_shift	= 2,
610};
611
612static void __init smdk6410_map_io(void)
613{
614	u32 tmp;
615
616	s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
617	s3c24xx_init_clocks(12000000);
618	s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
619
620	/* set the LCD type */
621
622	tmp = __raw_readl(S3C64XX_SPCON);
623	tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
624	tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
625	__raw_writel(tmp, S3C64XX_SPCON);
626
627	/* remove the lcd bypass */
628	tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
629	tmp &= ~MIFPCON_LCD_BYPASS;
630	__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
631}
632
633static void __init smdk6410_machine_init(void)
634{
635	u32 cs1;
636
637	s3c_i2c0_set_platdata(NULL);
638	s3c_i2c1_set_platdata(NULL);
639	s3c_fb_set_platdata(&smdk6410_lcd_pdata);
640
641	s3c24xx_ts_set_platdata(&s3c_ts_platform);
642
643	/* configure nCS1 width to 16 bits */
644
645	cs1 = __raw_readl(S3C64XX_SROM_BW) &
646		    ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
647	cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
648		(1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
649		(1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
650						   S3C64XX_SROM_BW__NCS1__SHIFT;
651	__raw_writel(cs1, S3C64XX_SROM_BW);
652
653	/* set timing for nCS1 suitable for ethernet chip */
654
655	__raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
656		     (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
657		     (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
658		     (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
659		     (0xe << S3C64XX_SROM_BCX__TACC__SHIFT) |
660		     (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
661		     (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
662
663	gpio_request(S3C64XX_GPN(5), "LCD power");
664	gpio_request(S3C64XX_GPF(13), "LCD power");
665	gpio_request(S3C64XX_GPF(15), "LCD power");
666
667	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
668	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
669
670	platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
671}
672
673MACHINE_START(SMDK6410, "SMDK6410")
674	/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
675	.phys_io	= S3C_PA_UART & 0xfff00000,
676	.io_pg_offst	= (((u32)S3C_VA_UART) >> 18) & 0xfffc,
677	.boot_params	= S3C64XX_PA_SDRAM + 0x100,
678
679	.init_irq	= s3c6410_init_irq,
680	.map_io		= smdk6410_map_io,
681	.init_machine	= smdk6410_machine_init,
682	.timer		= &s3c24xx_timer,
683MACHINE_END
684