mach-smdk6410.c revision f0fba2ad1b6b53d5360125c41953b7afcd6deff0 
1/* linux/arch/arm/mach-s3c64xx/mach-smdk6410.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 *	Ben Dooks <ben@simtec.co.uk>
6 *	http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/timer.h>
19#include <linux/init.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22#include <linux/io.h>
23#include <linux/i2c.h>
24#include <linux/leds.h>
25#include <linux/fb.h>
26#include <linux/gpio.h>
27#include <linux/delay.h>
28#include <linux/smsc911x.h>
29#include <linux/regulator/fixed.h>
30
31#ifdef CONFIG_SMDK6410_WM1190_EV1
32#include <linux/mfd/wm8350/core.h>
33#include <linux/mfd/wm8350/pmic.h>
34#endif
35
36#ifdef CONFIG_SMDK6410_WM1192_EV1
37#include <linux/mfd/wm831x/core.h>
38#include <linux/mfd/wm831x/pdata.h>
39#endif
40
41#include <video/platform_lcd.h>
42
43#include <asm/mach/arch.h>
44#include <asm/mach/map.h>
45#include <asm/mach/irq.h>
46
47#include <mach/hardware.h>
48#include <mach/regs-fb.h>
49#include <mach/map.h>
50
51#include <asm/irq.h>
52#include <asm/mach-types.h>
53
54#include <plat/regs-serial.h>
55#include <mach/regs-modem.h>
56#include <mach/regs-gpio.h>
57#include <mach/regs-sys.h>
58#include <mach/regs-srom.h>
59#include <plat/iic.h>
60#include <plat/fb.h>
61#include <plat/gpio-cfg.h>
62
63#include <mach/s3c6410.h>
64#include <plat/clock.h>
65#include <plat/devs.h>
66#include <plat/cpu.h>
67#include <plat/adc.h>
68#include <plat/ts.h>
69
70#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
71#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
72#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
73
74static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
75	[0] = {
76		.hwport	     = 0,
77		.flags	     = 0,
78		.ucon	     = UCON,
79		.ulcon	     = ULCON,
80		.ufcon	     = UFCON,
81	},
82	[1] = {
83		.hwport	     = 1,
84		.flags	     = 0,
85		.ucon	     = UCON,
86		.ulcon	     = ULCON,
87		.ufcon	     = UFCON,
88	},
89	[2] = {
90		.hwport	     = 2,
91		.flags	     = 0,
92		.ucon	     = UCON,
93		.ulcon	     = ULCON,
94		.ufcon	     = UFCON,
95	},
96	[3] = {
97		.hwport	     = 3,
98		.flags	     = 0,
99		.ucon	     = UCON,
100		.ulcon	     = ULCON,
101		.ufcon	     = UFCON,
102	},
103};
104
105/* framebuffer and LCD setup. */
106
107/* GPF15 = LCD backlight control
108 * GPF13 => Panel power
109 * GPN5 = LCD nRESET signal
110 * PWM_TOUT1 => backlight brightness
111 */
112
113static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
114				   unsigned int power)
115{
116	if (power) {
117		gpio_direction_output(S3C64XX_GPF(13), 1);
118		gpio_direction_output(S3C64XX_GPF(15), 1);
119
120		/* fire nRESET on power up */
121		gpio_direction_output(S3C64XX_GPN(5), 0);
122		msleep(10);
123		gpio_direction_output(S3C64XX_GPN(5), 1);
124		msleep(1);
125	} else {
126		gpio_direction_output(S3C64XX_GPF(15), 0);
127		gpio_direction_output(S3C64XX_GPF(13), 0);
128	}
129}
130
131static struct plat_lcd_data smdk6410_lcd_power_data = {
132	.set_power	= smdk6410_lcd_power_set,
133};
134
135static struct platform_device smdk6410_lcd_powerdev = {
136	.name			= "platform-lcd",
137	.dev.parent		= &s3c_device_fb.dev,
138	.dev.platform_data	= &smdk6410_lcd_power_data,
139};
140
141static struct s3c_fb_pd_win smdk6410_fb_win0 = {
142	/* this is to ensure we use win0 */
143	.win_mode	= {
144		.pixclock	= 41094,
145		.left_margin	= 8,
146		.right_margin	= 13,
147		.upper_margin	= 7,
148		.lower_margin	= 5,
149		.hsync_len	= 3,
150		.vsync_len	= 1,
151		.xres		= 800,
152		.yres		= 480,
153	},
154	.max_bpp	= 32,
155	.default_bpp	= 16,
156};
157
158/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
159static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
160	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
161	.win[0]		= &smdk6410_fb_win0,
162	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
163	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
164};
165
166/*
167 * Configuring Ethernet on SMDK6410
168 *
169 * Both CS8900A and LAN9115 chips share one chip select mediated by CFG6.
170 * The constant address below corresponds to nCS1
171 *
172 *  1) Set CFGB2 p3 ON others off, no other CFGB selects "ethernet"
173 *  2) CFG6 needs to be switched to "LAN9115" side
174 */
175
176static struct resource smdk6410_smsc911x_resources[] = {
177	[0] = {
178		.start = S3C64XX_PA_XM0CSN1,
179		.end   = S3C64XX_PA_XM0CSN1 + SZ_64K - 1,
180		.flags = IORESOURCE_MEM,
181	},
182	[1] = {
183		.start = S3C_EINT(10),
184		.end   = S3C_EINT(10),
185		.flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW,
186	},
187};
188
189static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
190	.irq_polarity  = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
191	.irq_type      = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
192	.flags         = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
193	.phy_interface = PHY_INTERFACE_MODE_MII,
194};
195
196
197static struct platform_device smdk6410_smsc911x = {
198	.name          = "smsc911x",
199	.id            = -1,
200	.num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
201	.resource      = &smdk6410_smsc911x_resources[0],
202	.dev = {
203		.platform_data = &smdk6410_smsc911x_pdata,
204	},
205};
206
207#ifdef CONFIG_REGULATOR
208static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
209	{
210		/* WM8580 */
211		.supply = "PVDD",
212		.dev_name = "0-001b",
213	},
214	{
215		/* WM8580 */
216		.supply = "AVDD",
217		.dev_name = "0-001b",
218	},
219};
220
221static struct regulator_init_data smdk6410_b_pwr_5v_data = {
222	.constraints = {
223		.always_on = 1,
224	},
225	.num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
226	.consumer_supplies = smdk6410_b_pwr_5v_consumers,
227};
228
229static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
230	.supply_name = "B_PWR_5V",
231	.microvolts = 5000000,
232	.init_data = &smdk6410_b_pwr_5v_data,
233	.gpio = -EINVAL,
234};
235
236static struct platform_device smdk6410_b_pwr_5v = {
237	.name          = "reg-fixed-voltage",
238	.id            = -1,
239	.dev = {
240		.platform_data = &smdk6410_b_pwr_5v_pdata,
241	},
242};
243#endif
244
245static struct map_desc smdk6410_iodesc[] = {};
246
247static struct platform_device *smdk6410_devices[] __initdata = {
248#ifdef CONFIG_SMDK6410_SD_CH0
249	&s3c_device_hsmmc0,
250#endif
251#ifdef CONFIG_SMDK6410_SD_CH1
252	&s3c_device_hsmmc1,
253#endif
254	&s3c_device_i2c0,
255	&s3c_device_i2c1,
256	&s3c_device_fb,
257	&s3c_device_ohci,
258	&s3c_device_usb_hsotg,
259	&s3c_device_pcm,
260	&s3c64xx_device_iisv4,
261
262#ifdef CONFIG_REGULATOR
263	&smdk6410_b_pwr_5v,
264#endif
265	&smdk6410_lcd_powerdev,
266
267	&smdk6410_smsc911x,
268	&s3c_device_adc,
269	&s3c_device_ts,
270	&s3c_device_wdt,
271};
272
273#ifdef CONFIG_REGULATOR
274/* ARM core */
275static struct regulator_consumer_supply smdk6410_vddarm_consumers[] = {
276	{
277		.supply = "vddarm",
278	}
279};
280
281/* VDDARM, BUCK1 on J5 */
282static struct regulator_init_data smdk6410_vddarm = {
283	.constraints = {
284		.name = "PVDD_ARM",
285		.min_uV = 1000000,
286		.max_uV = 1300000,
287		.always_on = 1,
288		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
289	},
290	.num_consumer_supplies = ARRAY_SIZE(smdk6410_vddarm_consumers),
291	.consumer_supplies = smdk6410_vddarm_consumers,
292};
293
294/* VDD_INT, BUCK2 on J5 */
295static struct regulator_init_data smdk6410_vddint = {
296	.constraints = {
297		.name = "PVDD_INT",
298		.min_uV = 1000000,
299		.max_uV = 1200000,
300		.always_on = 1,
301		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
302	},
303};
304
305/* VDD_HI, LDO3 on J5 */
306static struct regulator_init_data smdk6410_vddhi = {
307	.constraints = {
308		.name = "PVDD_HI",
309		.always_on = 1,
310	},
311};
312
313/* VDD_PLL, LDO2 on J5 */
314static struct regulator_init_data smdk6410_vddpll = {
315	.constraints = {
316		.name = "PVDD_PLL",
317		.always_on = 1,
318	},
319};
320
321/* VDD_UH_MMC, LDO5 on J5 */
322static struct regulator_init_data smdk6410_vdduh_mmc = {
323	.constraints = {
324		.name = "PVDD_UH/PVDD_MMC",
325		.always_on = 1,
326	},
327};
328
329/* VCCM3BT, LDO8 on J5 */
330static struct regulator_init_data smdk6410_vccmc3bt = {
331	.constraints = {
332		.name = "PVCCM3BT",
333		.always_on = 1,
334	},
335};
336
337/* VCCM2MTV, LDO11 on J5 */
338static struct regulator_init_data smdk6410_vccm2mtv = {
339	.constraints = {
340		.name = "PVCCM2MTV",
341		.always_on = 1,
342	},
343};
344
345/* VDD_LCD, LDO12 on J5 */
346static struct regulator_init_data smdk6410_vddlcd = {
347	.constraints = {
348		.name = "PVDD_LCD",
349		.always_on = 1,
350	},
351};
352
353/* VDD_OTGI, LDO9 on J5 */
354static struct regulator_init_data smdk6410_vddotgi = {
355	.constraints = {
356		.name = "PVDD_OTGI",
357		.always_on = 1,
358	},
359};
360
361/* VDD_OTG, LDO14 on J5 */
362static struct regulator_init_data smdk6410_vddotg = {
363	.constraints = {
364		.name = "PVDD_OTG",
365		.always_on = 1,
366	},
367};
368
369/* VDD_ALIVE, LDO15 on J5 */
370static struct regulator_init_data smdk6410_vddalive = {
371	.constraints = {
372		.name = "PVDD_ALIVE",
373		.always_on = 1,
374	},
375};
376
377/* VDD_AUDIO, VLDO_AUDIO on J5 */
378static struct regulator_init_data smdk6410_vddaudio = {
379	.constraints = {
380		.name = "PVDD_AUDIO",
381		.always_on = 1,
382	},
383};
384#endif
385
386#ifdef CONFIG_SMDK6410_WM1190_EV1
387/* S3C64xx internal logic & PLL */
388static struct regulator_init_data wm8350_dcdc1_data = {
389	.constraints = {
390		.name = "PVDD_INT/PVDD_PLL",
391		.min_uV = 1200000,
392		.max_uV = 1200000,
393		.always_on = 1,
394		.apply_uV = 1,
395	},
396};
397
398/* Memory */
399static struct regulator_init_data wm8350_dcdc3_data = {
400	.constraints = {
401		.name = "PVDD_MEM",
402		.min_uV = 1800000,
403		.max_uV = 1800000,
404		.always_on = 1,
405		.state_mem = {
406			 .uV = 1800000,
407			 .mode = REGULATOR_MODE_NORMAL,
408			 .enabled = 1,
409		},
410		.initial_state = PM_SUSPEND_MEM,
411	},
412};
413
414/* USB, EXT, PCM, ADC/DAC, USB, MMC */
415static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
416	{
417		/* WM8580 */
418		.supply = "DVDD",
419		.dev_name = "0-001b",
420	},
421};
422
423static struct regulator_init_data wm8350_dcdc4_data = {
424	.constraints = {
425		.name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
426		.min_uV = 3000000,
427		.max_uV = 3000000,
428		.always_on = 1,
429	},
430	.num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
431	.consumer_supplies = wm8350_dcdc4_consumers,
432};
433
434/* OTGi/1190-EV1 HPVDD & AVDD */
435static struct regulator_init_data wm8350_ldo4_data = {
436	.constraints = {
437		.name = "PVDD_OTGI/HPVDD/AVDD",
438		.min_uV = 1200000,
439		.max_uV = 1200000,
440		.apply_uV = 1,
441		.always_on = 1,
442	},
443};
444
445static struct {
446	int regulator;
447	struct regulator_init_data *initdata;
448} wm1190_regulators[] = {
449	{ WM8350_DCDC_1, &wm8350_dcdc1_data },
450	{ WM8350_DCDC_3, &wm8350_dcdc3_data },
451	{ WM8350_DCDC_4, &wm8350_dcdc4_data },
452	{ WM8350_DCDC_6, &smdk6410_vddarm },
453	{ WM8350_LDO_1, &smdk6410_vddalive },
454	{ WM8350_LDO_2, &smdk6410_vddotg },
455	{ WM8350_LDO_3, &smdk6410_vddlcd },
456	{ WM8350_LDO_4, &wm8350_ldo4_data },
457};
458
459static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
460{
461	int i;
462
463	/* Configure the IRQ line */
464	s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
465
466	/* Instantiate the regulators */
467	for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
468		wm8350_register_regulator(wm8350,
469					  wm1190_regulators[i].regulator,
470					  wm1190_regulators[i].initdata);
471
472	return 0;
473}
474
475static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
476	.init = smdk6410_wm8350_init,
477	.irq_high = 1,
478	.irq_base = IRQ_BOARD_START,
479};
480#endif
481
482#ifdef CONFIG_SMDK6410_WM1192_EV1
483static struct gpio_led wm1192_pmic_leds[] = {
484	{
485		.name = "PMIC:red:power",
486		.gpio = GPIO_BOARD_START + 3,
487		.default_state = LEDS_GPIO_DEFSTATE_ON,
488	},
489};
490
491static struct gpio_led_platform_data wm1192_pmic_led = {
492	.num_leds = ARRAY_SIZE(wm1192_pmic_leds),
493	.leds = wm1192_pmic_leds,
494};
495
496static struct platform_device wm1192_pmic_led_dev = {
497	.name          = "leds-gpio",
498	.id            = -1,
499	.dev = {
500		.platform_data = &wm1192_pmic_led,
501	},
502};
503
504static int wm1192_pre_init(struct wm831x *wm831x)
505{
506	int ret;
507
508	/* Configure the IRQ line */
509	s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
510
511	ret = platform_device_register(&wm1192_pmic_led_dev);
512	if (ret != 0)
513		dev_err(wm831x->dev, "Failed to add PMIC LED: %d\n", ret);
514
515	return 0;
516}
517
518static struct wm831x_backlight_pdata wm1192_backlight_pdata = {
519	.isink = 1,
520	.max_uA = 27554,
521};
522
523static struct regulator_init_data wm1192_dcdc3 = {
524	.constraints = {
525		.name = "PVDD_MEM/PVDD_GPS",
526		.always_on = 1,
527	},
528};
529
530static struct regulator_consumer_supply wm1192_ldo1_consumers[] = {
531	{ .supply = "DVDD", .dev_name = "0-001b", },   /* WM8580 */
532};
533
534static struct regulator_init_data wm1192_ldo1 = {
535	.constraints = {
536		.name = "PVDD_LCD/PVDD_EXT",
537		.always_on = 1,
538	},
539	.consumer_supplies = wm1192_ldo1_consumers,
540	.num_consumer_supplies = ARRAY_SIZE(wm1192_ldo1_consumers),
541};
542
543static struct wm831x_status_pdata wm1192_led7_pdata = {
544	.name = "LED7:green:",
545};
546
547static struct wm831x_status_pdata wm1192_led8_pdata = {
548	.name = "LED8:green:",
549};
550
551static struct wm831x_pdata smdk6410_wm1192_pdata = {
552	.pre_init = wm1192_pre_init,
553	.irq_base = IRQ_BOARD_START,
554
555	.backlight = &wm1192_backlight_pdata,
556	.dcdc = {
557		&smdk6410_vddarm,  /* DCDC1 */
558		&smdk6410_vddint,  /* DCDC2 */
559		&wm1192_dcdc3,
560	},
561	.gpio_base = GPIO_BOARD_START,
562	.ldo = {
563		 &wm1192_ldo1,        /* LDO1 */
564		 &smdk6410_vdduh_mmc, /* LDO2 */
565		 NULL,                /* LDO3 NC */
566		 &smdk6410_vddotgi,   /* LDO4 */
567		 &smdk6410_vddotg,    /* LDO5 */
568		 &smdk6410_vddhi,     /* LDO6 */
569		 &smdk6410_vddaudio,  /* LDO7 */
570		 &smdk6410_vccm2mtv,  /* LDO8 */
571		 &smdk6410_vddpll,    /* LDO9 */
572		 &smdk6410_vccmc3bt,  /* LDO10 */
573		 &smdk6410_vddalive,  /* LDO11 */
574	},
575	.status = {
576		&wm1192_led7_pdata,
577		&wm1192_led8_pdata,
578	},
579};
580#endif
581
582static struct i2c_board_info i2c_devs0[] __initdata = {
583	{ I2C_BOARD_INFO("24c08", 0x50), },
584	{ I2C_BOARD_INFO("wm8580", 0x1b), },
585
586#ifdef CONFIG_SMDK6410_WM1192_EV1
587	{ I2C_BOARD_INFO("wm8312", 0x34),
588	  .platform_data = &smdk6410_wm1192_pdata,
589	  .irq = S3C_EINT(12),
590	},
591#endif
592
593#ifdef CONFIG_SMDK6410_WM1190_EV1
594	{ I2C_BOARD_INFO("wm8350", 0x1a),
595	  .platform_data = &smdk6410_wm8350_pdata,
596	  .irq = S3C_EINT(12),
597	},
598#endif
599};
600
601static struct i2c_board_info i2c_devs1[] __initdata = {
602	{ I2C_BOARD_INFO("24c128", 0x57), },	/* Samsung S524AD0XD1 */
603};
604
605static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
606	.delay			= 10000,
607	.presc			= 49,
608	.oversampling_shift	= 2,
609};
610
611static void __init smdk6410_map_io(void)
612{
613	u32 tmp;
614
615	s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
616	s3c24xx_init_clocks(12000000);
617	s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
618
619	/* set the LCD type */
620
621	tmp = __raw_readl(S3C64XX_SPCON);
622	tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
623	tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
624	__raw_writel(tmp, S3C64XX_SPCON);
625
626	/* remove the lcd bypass */
627	tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
628	tmp &= ~MIFPCON_LCD_BYPASS;
629	__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
630}
631
632static void __init smdk6410_machine_init(void)
633{
634	u32 cs1;
635
636	s3c_i2c0_set_platdata(NULL);
637	s3c_i2c1_set_platdata(NULL);
638	s3c_fb_set_platdata(&smdk6410_lcd_pdata);
639
640	s3c24xx_ts_set_platdata(&s3c_ts_platform);
641
642	/* configure nCS1 width to 16 bits */
643
644	cs1 = __raw_readl(S3C64XX_SROM_BW) &
645		    ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
646	cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
647		(1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
648		(1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
649						   S3C64XX_SROM_BW__NCS1__SHIFT;
650	__raw_writel(cs1, S3C64XX_SROM_BW);
651
652	/* set timing for nCS1 suitable for ethernet chip */
653
654	__raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
655		     (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
656		     (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
657		     (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
658		     (0xe << S3C64XX_SROM_BCX__TACC__SHIFT) |
659		     (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
660		     (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
661
662	gpio_request(S3C64XX_GPN(5), "LCD power");
663	gpio_request(S3C64XX_GPF(13), "LCD power");
664	gpio_request(S3C64XX_GPF(15), "LCD power");
665
666	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
667	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
668
669	platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
670}
671
672MACHINE_START(SMDK6410, "SMDK6410")
673	/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
674	.phys_io	= S3C_PA_UART & 0xfff00000,
675	.io_pg_offst	= (((u32)S3C_VA_UART) >> 18) & 0xfffc,
676	.boot_params	= S3C64XX_PA_SDRAM + 0x100,
677
678	.init_irq	= s3c6410_init_irq,
679	.map_io		= smdk6410_map_io,
680	.init_machine	= smdk6410_machine_init,
681	.timer		= &s3c24xx_timer,
682MACHINE_END
683