1/*
2 *  linux/arch/arm/mm/proc-arm6,7.S
3 *
4 *  Copyright (C) 1997-2000 Russell King
5 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 *  These are the low level assembler for performing cache and TLB
12 *  functions on the ARM610 & ARM710.
13 */
14#include <linux/linkage.h>
15#include <linux/init.h>
16#include <asm/assembler.h>
17#include <asm/asm-offsets.h>
18#include <asm/hwcap.h>
19#include <asm/pgtable-hwdef.h>
20#include <asm/pgtable.h>
21#include <asm/ptrace.h>
22
23#include "proc-macros.S"
24
25ENTRY(cpu_arm6_dcache_clean_area)
26ENTRY(cpu_arm7_dcache_clean_area)
27		mov	pc, lr
28
29/*
30 * Function: arm6_7_data_abort ()
31 *
32 * Params  : r2 = pt_regs
33 *	   : r4 = aborted context pc
34 *	   : r5 = aborted context psr
35 *
36 * Purpose : obtain information about current aborted instruction
37 *
38 * Returns : r4-r5, r10-r11, r13 preserved
39 */
40
41ENTRY(cpu_arm7_data_abort)
42	mrc	p15, 0, r1, c5, c0, 0		@ get FSR
43	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
44	ldr	r8, [r4]			@ read arm instruction
45	tst	r8, #1 << 20			@ L = 0 -> write?
46	orreq	r1, r1, #1 << 11		@ yes.
47	and	r7, r8, #15 << 24
48	add	pc, pc, r7, lsr #22		@ Now branch to the relevant processing routine
49	nop
50
51/* 0 */	b	.data_unknown
52/* 1 */	b	do_DataAbort			@ swp
53/* 2 */	b	.data_unknown
54/* 3 */	b	.data_unknown
55/* 4 */	b	.data_arm_lateldrpostconst	@ ldr	rd, [rn], #m
56/* 5 */	b	.data_arm_lateldrpreconst	@ ldr	rd, [rn, #m]
57/* 6 */	b	.data_arm_lateldrpostreg	@ ldr	rd, [rn], rm
58/* 7 */	b	.data_arm_lateldrprereg		@ ldr	rd, [rn, rm]
59/* 8 */	b	.data_arm_ldmstm		@ ldm*a	rn, <rlist>
60/* 9 */	b	.data_arm_ldmstm		@ ldm*b	rn, <rlist>
61/* a */	b	.data_unknown
62/* b */	b	.data_unknown
63/* c */	b	do_DataAbort			@ ldc	rd, [rn], #m	@ Same as ldr	rd, [rn], #m
64/* d */	b	do_DataAbort			@ ldc	rd, [rn, #m]
65/* e */	b	.data_unknown
66/* f */
67.data_unknown:	@ Part of jumptable
68	mov	r0, r4
69	mov	r1, r8
70	b	baddataabort
71
72ENTRY(cpu_arm6_data_abort)
73	mrc	p15, 0, r1, c5, c0, 0		@ get FSR
74	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
75	ldr	r8, [r4]			@ read arm instruction
76	tst	r8, #1 << 20			@ L = 0 -> write?
77	orreq	r1, r1, #1 << 11		@ yes.
78	and	r7, r8, #14 << 24
79	teq	r7, #8 << 24			@ was it ldm/stm
80	bne	do_DataAbort
81
82.data_arm_ldmstm:
83	tst	r8, #1 << 21			@ check writeback bit
84	beq	do_DataAbort			@ no writeback -> no fixup
85	mov	r7, #0x11
86	orr	r7, r7, #0x1100
87	and	r6, r8, r7
88	and	r9, r8, r7, lsl #1
89	add	r6, r6, r9, lsr #1
90	and	r9, r8, r7, lsl #2
91	add	r6, r6, r9, lsr #2
92	and	r9, r8, r7, lsl #3
93	add	r6, r6, r9, lsr #3
94	add	r6, r6, r6, lsr #8
95	add	r6, r6, r6, lsr #4
96	and	r6, r6, #15			@ r6 = no. of registers to transfer.
97	and	r9, r8, #15 << 16		@ Extract 'n' from instruction
98	ldr	r7, [r2, r9, lsr #14]		@ Get register 'Rn'
99	tst	r8, #1 << 23			@ Check U bit
100	subne	r7, r7, r6, lsl #2		@ Undo increment
101	addeq	r7, r7, r6, lsl #2		@ Undo decrement
102	str	r7, [r2, r9, lsr #14]		@ Put register 'Rn'
103	b	do_DataAbort
104
105.data_arm_apply_r6_and_rn:
106	and	r9, r8, #15 << 16		@ Extract 'n' from instruction
107	ldr	r7, [r2, r9, lsr #14]		@ Get register 'Rn'
108	tst	r8, #1 << 23			@ Check U bit
109	subne	r7, r7, r6			@ Undo incrmenet
110	addeq	r7, r7, r6			@ Undo decrement
111	str	r7, [r2, r9, lsr #14]		@ Put register 'Rn'
112	b	do_DataAbort
113
114.data_arm_lateldrpreconst:
115	tst	r8, #1 << 21			@ check writeback bit
116	beq	do_DataAbort			@ no writeback -> no fixup
117.data_arm_lateldrpostconst:
118	movs	r6, r8, lsl #20			@ Get offset
119	beq	do_DataAbort			@ zero -> no fixup
120	and	r9, r8, #15 << 16		@ Extract 'n' from instruction
121	ldr	r7, [r2, r9, lsr #14]		@ Get register 'Rn'
122	tst	r8, #1 << 23			@ Check U bit
123	subne	r7, r7, r6, lsr #20		@ Undo increment
124	addeq	r7, r7, r6, lsr #20		@ Undo decrement
125	str	r7, [r2, r9, lsr #14]		@ Put register 'Rn'
126	b	do_DataAbort
127
128.data_arm_lateldrprereg:
129	tst	r8, #1 << 21			@ check writeback bit
130	beq	do_DataAbort			@ no writeback -> no fixup
131.data_arm_lateldrpostreg:
132	and	r7, r8, #15			@ Extract 'm' from instruction
133	ldr	r6, [r2, r7, lsl #2]		@ Get register 'Rm'
134	mov	r9, r8, lsr #7			@ get shift count
135	ands	r9, r9, #31
136	and	r7, r8, #0x70			@ get shift type
137	orreq	r7, r7, #8			@ shift count = 0
138	add	pc, pc, r7
139	nop
140
141	mov	r6, r6, lsl r9			@ 0: LSL #!0
142	b	.data_arm_apply_r6_and_rn
143	b	.data_arm_apply_r6_and_rn	@ 1: LSL #0
144	nop
145	b	.data_unknown			@ 2: MUL?
146	nop
147	b	.data_unknown			@ 3: MUL?
148	nop
149	mov	r6, r6, lsr r9			@ 4: LSR #!0
150	b	.data_arm_apply_r6_and_rn
151	mov	r6, r6, lsr #32			@ 5: LSR #32
152	b	.data_arm_apply_r6_and_rn
153	b	.data_unknown			@ 6: MUL?
154	nop
155	b	.data_unknown			@ 7: MUL?
156	nop
157	mov	r6, r6, asr r9			@ 8: ASR #!0
158	b	.data_arm_apply_r6_and_rn
159	mov	r6, r6, asr #32			@ 9: ASR #32
160	b	.data_arm_apply_r6_and_rn
161	b	.data_unknown			@ A: MUL?
162	nop
163	b	.data_unknown			@ B: MUL?
164	nop
165	mov	r6, r6, ror r9			@ C: ROR #!0
166	b	.data_arm_apply_r6_and_rn
167	mov	r6, r6, rrx			@ D: RRX
168	b	.data_arm_apply_r6_and_rn
169	b	.data_unknown			@ E: MUL?
170	nop
171	b	.data_unknown			@ F: MUL?
172
173/*
174 * Function: arm6_7_proc_init (void)
175 *	   : arm6_7_proc_fin (void)
176 *
177 * Notes   : This processor does not require these
178 */
179ENTRY(cpu_arm6_proc_init)
180ENTRY(cpu_arm7_proc_init)
181		mov	pc, lr
182
183ENTRY(cpu_arm6_proc_fin)
184ENTRY(cpu_arm7_proc_fin)
185		mov	r0, #0x31			@ ....S..DP...M
186		mcr	p15, 0, r0, c1, c0, 0		@ disable caches
187		mov	pc, lr
188
189ENTRY(cpu_arm6_do_idle)
190ENTRY(cpu_arm7_do_idle)
191		mov	pc, lr
192
193/*
194 * Function: arm6_7_switch_mm(unsigned long pgd_phys)
195 * Params  : pgd_phys	Physical address of page table
196 * Purpose : Perform a task switch, saving the old processes state, and restoring
197 *	     the new.
198 */
199ENTRY(cpu_arm6_switch_mm)
200ENTRY(cpu_arm7_switch_mm)
201#ifdef CONFIG_MMU
202		mov	r1, #0
203		mcr	p15, 0, r1, c7, c0, 0		@ flush cache
204		mcr	p15, 0, r0, c2, c0, 0		@ update page table ptr
205		mcr	p15, 0, r1, c5, c0, 0		@ flush TLBs
206#endif
207		mov	pc, lr
208
209/*
210 * Function: arm6_7_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
211 * Params  : r0 = Address to set
212 *	   : r1 = value to set
213 * Purpose : Set a PTE and flush it out of any WB cache
214 */
215	.align	5
216ENTRY(cpu_arm6_set_pte_ext)
217ENTRY(cpu_arm7_set_pte_ext)
218#ifdef CONFIG_MMU
219	armv3_set_pte_ext wc_disable=0
220#endif /* CONFIG_MMU */
221	mov	pc, lr
222
223/*
224 * Function: _arm6_7_reset
225 * Params  : r0 = address to jump to
226 * Notes   : This sets up everything for a reset
227 */
228		.pushsection	.idmap.text, "ax"
229ENTRY(cpu_arm6_reset)
230ENTRY(cpu_arm7_reset)
231		mov	r1, #0
232		mcr	p15, 0, r1, c7, c0, 0		@ flush cache
233#ifdef CONFIG_MMU
234		mcr	p15, 0, r1, c5, c0, 0		@ flush TLB
235#endif
236		mov	r1, #0x30
237		mcr	p15, 0, r1, c1, c0, 0		@ turn off MMU etc
238		mov	pc, r0
239ENDPROC(cpu_arm6_reset)
240ENDPROC(cpu_arm7_reset)
241		.popsection
242
243		__CPUINIT
244
245		.type	__arm6_setup, #function
246__arm6_setup:	mov	r0, #0
247		mcr	p15, 0, r0, c7, c0		@ flush caches on v3
248#ifdef CONFIG_MMU
249		mcr	p15, 0, r0, c5, c0		@ flush TLBs on v3
250		mov	r0, #0x3d			@ . ..RS BLDP WCAM
251		orr	r0, r0, #0x100			@ . ..01 0011 1101
252#else
253		mov	r0, #0x3c			@ . ..RS BLDP WCA.
254#endif
255		mov	pc, lr
256		.size	__arm6_setup, . - __arm6_setup
257
258		.type	__arm7_setup, #function
259__arm7_setup:	mov	r0, #0
260		mcr	p15, 0, r0, c7, c0		@ flush caches on v3
261#ifdef CONFIG_MMU
262		mcr	p15, 0, r0, c5, c0		@ flush TLBs on v3
263		mcr	p15, 0, r0, c3, c0		@ load domain access register
264		mov	r0, #0x7d			@ . ..RS BLDP WCAM
265		orr	r0, r0, #0x100			@ . ..01 0111 1101
266#else
267		mov	r0, #0x7c			@ . ..RS BLDP WCA.
268#endif
269		mov	pc, lr
270		.size	__arm7_setup, . - __arm7_setup
271
272		__INITDATA
273
274		@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
275		define_processor_functions arm6, dabort=cpu_arm6_data_abort, pabort=legacy_pabort
276		define_processor_functions arm7, dabort=cpu_arm7_data_abort, pabort=legacy_pabort
277
278		.section ".rodata"
279
280		string	cpu_arch_name, "armv3"
281		string	cpu_elf_name, "v3"
282		string	cpu_arm6_name, "ARM6"
283		string	cpu_arm610_name, "ARM610"
284		string	cpu_arm7_name, "ARM7"
285		string	cpu_arm710_name, "ARM710"
286
287		.align
288
289		.section ".proc.info.init", #alloc, #execinstr
290
291.macro arm67_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \
292	cpu_mm_mmu_flags:req, cpu_flush:req, cpu_proc_funcs:req
293		.type	__\name\()_proc_info, #object
294__\name\()_proc_info:
295		.long	\cpu_val
296		.long	\cpu_mask
297		.long	\cpu_mm_mmu_flags
298		.long   PMD_TYPE_SECT | \
299			PMD_BIT4 | \
300			PMD_SECT_AP_WRITE | \
301			PMD_SECT_AP_READ
302		b	\cpu_flush
303		.long	cpu_arch_name
304		.long	cpu_elf_name
305		.long	HWCAP_SWP | HWCAP_26BIT
306		.long	\cpu_name
307		.long	\cpu_proc_funcs
308		.long	v3_tlb_fns
309		.long	v3_user_fns
310		.long	v3_cache_fns
311		.size	__\name\()_proc_info, . - __\name\()_proc_info
312.endm
313
314	arm67_proc_info	arm6,	0x41560600, 0xfffffff0, cpu_arm6_name, \
315		0x00000c1e, __arm6_setup, arm6_processor_functions
316	arm67_proc_info	arm610,	0x41560610, 0xfffffff0, cpu_arm610_name, \
317		0x00000c1e, __arm6_setup, arm6_processor_functions
318	arm67_proc_info	arm7,	0x41007000, 0xffffff00, cpu_arm7_name, \
319		0x00000c1e, __arm7_setup, arm7_processor_functions
320	arm67_proc_info	arm710,	0x41007100, 0xfff8ff00, cpu_arm710_name, \
321			PMD_TYPE_SECT | \
322			PMD_SECT_BUFFERABLE | \
323			PMD_SECT_CACHEABLE | \
324			PMD_BIT4 | \
325			PMD_SECT_AP_WRITE | \
326			PMD_SECT_AP_READ, \
327		__arm7_setup, arm7_processor_functions
328