11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * linux/arch/arm/mm/proc-xscale.S 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Author: Nicolas Pitre 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Created: November 2000 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright: (C) 2000, 2001 MontaVista Software Inc. 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This program is free software; you can redistribute it and/or modify 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * it under the terms of the GNU General Public License version 2 as 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * published by the Free Software Foundation. 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * MMU functions for the Intel XScale CPUs 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2001 Aug 21: 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * some contributions by Brett Gaines <brett.w.gaines@intel.com> 161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright 2001 by Intel Corp. 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2001 Sep 08: 191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Completely revisited, many important fixes 202f82af08fcc7dc01a7e98a49a5995a77e32a2925Nicolas Pitre * Nicolas Pitre <nico@fluxnic.net> 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/linkage.h> 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/init.h> 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/assembler.h> 265ec9407dd1196daaf12b427b351e2cd62d2a16a7Russell King#include <asm/hwcap.h> 271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/pgtable.h> 280003cedfc577be9d679c16531f8720739e9637edRussell King#include <asm/pgtable-hwdef.h> 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/page.h> 301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/ptrace.h> 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include "proc-macros.S" 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This is the maximum size of an area which will be flushed. If the area 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * is larger than this, then we flush the whole cache 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAX_AREA_SIZE 32768 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the cache line size of the I and D cache 411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CACHELINESIZE 32 431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the size of the data cache 461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CACHESIZE 32768 481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Virtual address used to allocate the cache when flushed 511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This must be an address range which is _never_ used. It should 531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * apparently have a mapping in the corresponding page table for 541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * compatibility with future CPUs that _could_ require it. For instance we 551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * don't care. 561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This must be aligned on a 2*CACHESIZE boundary. The code selects one of 581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the 2 areas in alternance each time the clean_d_cache macro is used. 591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Without this the XScale core exhibits cache eviction problems and no one 601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * knows why. 611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Reminder: the vector table is located at 0xffff0000-0xffff0fff. 631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CLEAN_ADDR 0xfffe0000 651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This macro is used to wait for a CP15 write and is needed 681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * when we have to ensure that the last operation to the co-pro 691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * was completed before continuing with operation. 701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .macro cpwait, rd 721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov \rd, \rd @ wait for completion 741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds sub pc, pc, #4 @ flush instruction pipeline 751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .endm 761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .macro cpwait_ret, lr, rd 781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds sub pc, \lr, \rd, LSR #32 @ wait for completion and 801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ flush instruction pipeline 811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .endm 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This macro cleans the entire dcache using line allocate. 851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * The main loop has been unrolled to reduce loop overhead. 861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * rd and rs are two scratch registers. 871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .macro clean_d_cache, rd, rs 891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ldr \rs, =clean_addr 901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ldr \rd, [\rs] 911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds eor \rd, \rd, #CACHESIZE 921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds str \rd, [\rs] 931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rs, \rd, #CACHESIZE 941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rd, \rd, #CACHELINESIZE 961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rd, \rd, #CACHELINESIZE 981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rd, \rd, #CACHELINESIZE 1001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 1011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rd, \rd, #CACHELINESIZE 1021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds teq \rd, \rs 1031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bne 1b 1041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .endm 1051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .data 1071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsclean_addr: .word CLEAN_ADDR 1081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .text 1101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_proc_init() 1131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Nothing too exciting at the moment 1151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_proc_init) 117391c569daa6e4e999592966e29c146dfc4de9a9cArnaud Patard @ enable write buffer coalescing. Some bootloader disable it 118391c569daa6e4e999592966e29c146dfc4de9a9cArnaud Patard mrc p15, 0, r1, c1, c0, 1 119391c569daa6e4e999592966e29c146dfc4de9a9cArnaud Patard bic r1, r1, #1 120391c569daa6e4e999592966e29c146dfc4de9a9cArnaud Patard mcr p15, 0, r1, c1, c0, 1 1211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 1221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_proc_fin() 1251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_proc_fin) 1271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, r0, c1, c0, 0 @ ctrl register 1281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #0x1800 @ ...IZ........... 1291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #0x0006 @ .............CA. 1301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c1, c0, 0 @ disable caches 1319ca03a21e320a6bf44559323527aba704bcc8772Russell King mov pc, lr 1321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_reset(loc) 1351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Perform a soft reset of the system. Put the CPU into the 1371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * same state as it would be if it had been reset, and branch 1381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * to what would be the reset vector. 1391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * loc: location to jump to for soft reset 1412dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre * 1422dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre * Beware PXA270 erratum E7. 1431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 1451a4baafa7d203da1cceb302c2df38f0fea1c17a1Will Deacon .pushsection .idmap.text, "ax" 1461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_reset) 1471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE 1481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds msr cpsr_c, r1 @ reset CPSR 1492dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB 1502dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB 1511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, r1, c1, c0, 0 @ ctrl register 1521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r1, r1, #0x0086 @ ........B....CA. 1531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r1, r1, #0x3900 @ ..VIZ..S........ 1542dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre sub pc, pc, #4 @ flush pipeline 1552dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre @ *** cache line aligned *** 1561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r1, c1, c0, 0 @ ctrl register 1571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r1, r1, #0x0001 @ ...............M 1582dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB 1591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r1, c1, c0, 0 @ ctrl register 1601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ CAUTION: MMU turned off from this point. We count on the pipeline 1611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ already containing those two last instructions to survive. 1621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 1631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, r0 1641a4baafa7d203da1cceb302c2df38f0fea1c17a1Will DeaconENDPROC(cpu_xscale_reset) 1651a4baafa7d203da1cceb302c2df38f0fea1c17a1Will Deacon .popsection 1661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_do_idle() 1691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Cause the processor to idle 1711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * For now we do nothing but go to idle mode for every case 1731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * XScale supports clock switching, but using idle mode support 1751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * allows external hardware to react to system state changes. 1761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 1781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_do_idle) 1801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #1 1811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE 1821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 1831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* ================================= CACHE ================================ */ 1851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 187c8c90860cd3592fac83a349f84a20360a6498727Mika Westerberg * flush_icache_all() 188c8c90860cd3592fac83a349f84a20360a6498727Mika Westerberg * 189c8c90860cd3592fac83a349f84a20360a6498727Mika Westerberg * Unconditionally clean and invalidate the entire icache. 190c8c90860cd3592fac83a349f84a20360a6498727Mika Westerberg */ 191c8c90860cd3592fac83a349f84a20360a6498727Mika WesterbergENTRY(xscale_flush_icache_all) 192c8c90860cd3592fac83a349f84a20360a6498727Mika Westerberg mov r0, #0 193c8c90860cd3592fac83a349f84a20360a6498727Mika Westerberg mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 194c8c90860cd3592fac83a349f84a20360a6498727Mika Westerberg mov pc, lr 195c8c90860cd3592fac83a349f84a20360a6498727Mika WesterbergENDPROC(xscale_flush_icache_all) 196c8c90860cd3592fac83a349f84a20360a6498727Mika Westerberg 197c8c90860cd3592fac83a349f84a20360a6498727Mika Westerberg/* 1981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * flush_user_cache_all() 1991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Invalidate all cache entries in a particular address 2011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * space. 2021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_flush_user_cache_all) 2041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* FALLTHROUGH */ 2051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * flush_kern_cache_all() 2081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Clean and invalidate the entire cache. 2101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_flush_kern_cache_all) 2121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r2, #VM_EXEC 2131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov ip, #0 2141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__flush_whole_cache: 2151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds clean_d_cache r0, r1 2161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r2, #VM_EXEC 2171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB 2181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 2191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 2201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * flush_user_cache_range(start, end, vm_flags) 2231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Invalidate a range of cache entries in the specified 2251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * address space. 2261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - start address (may not be aligned) 2281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - end address (exclusive, may not be aligned) 2291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - vma - vma_area_struct describing address space 2301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 2321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_flush_user_cache_range) 2331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov ip, #0 2341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds sub r3, r1, r0 @ calculate total size 2351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r3, #MAX_AREA_SIZE 2361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bhs __flush_whole_cache 2371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: tst r2, #VM_EXEC 2391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line 2401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line 2411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line 2421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 2431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 2441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 2451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r2, #VM_EXEC 2461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB 2471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 2481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 2491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * coherent_kern_range(start, end) 2521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Ensure coherency between the Icache and the Dcache in the 2541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * region described by start. If you have non-snooping 2551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Harvard caches, you need to implement this function. 2561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 2581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 2591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Note: single I-cache line invalidation isn't used here since 2611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * it also trashes the mini I-cache used by JTAG debuggers. 2621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_coherent_kern_range) 2648a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre bic r0, r0, #CACHELINESIZE - 1 2658a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2668a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre add r0, r0, #CACHELINESIZE 2678a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre cmp r0, r1 2688a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre blo 1b 2698a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mov r0, #0 2708a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB 2718a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 2728a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mov pc, lr 2731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * coherent_user_range(start, end) 2761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Ensure coherency between the Icache and the Dcache in the 2781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * region described by start. If you have non-snooping 2791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Harvard caches, you need to implement this function. 2801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 2821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 2831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_coherent_user_range) 2851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #CACHELINESIZE - 1 2861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2878a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry 2881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 2891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 2901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 2911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #0 2928a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB 2931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 2941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 2951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2972c9b9c8490b60428fa2d1c64042f7c7caed93940Russell King * flush_kern_dcache_area(void *addr, size_t size) 2981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Ensure no D cache aliasing occurs, either with itself or 3001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the I cache 3011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3022c9b9c8490b60428fa2d1c64042f7c7caed93940Russell King * - addr - kernel address 3032c9b9c8490b60428fa2d1c64042f7c7caed93940Russell King * - size - region size 3041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3052c9b9c8490b60428fa2d1c64042f7c7caed93940Russell KingENTRY(xscale_flush_kern_dcache_area) 3062c9b9c8490b60428fa2d1c64042f7c7caed93940Russell King add r1, r0, r1 3071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 3091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 3101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 3111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 3121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #0 3131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB 3141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 3151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 3161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 3181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * dma_inv_range(start, end) 3191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Invalidate (discard) the specified virtual address range. 3211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * May not write back any entries. If 'start' or 'end' 3221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * are not cache line aligned, those lines must be written 3231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * back. 3241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 3261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 3271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 328702b94bff3c50542a6e4ab9a4f4cef093262fe65Russell Kingxscale_dma_inv_range: 3291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r0, #CACHELINESIZE - 1 3301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #CACHELINESIZE - 1 3311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 3321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r1, #CACHELINESIZE - 1 3331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 3341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 3351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 3361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 3371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 3381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 3391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 3401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 3421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * dma_clean_range(start, end) 3431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Clean the specified virtual address range. 3451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 3471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 3481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 349702b94bff3c50542a6e4ab9a4f4cef093262fe65Russell Kingxscale_dma_clean_range: 3501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #CACHELINESIZE - 1 3511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 3531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 3541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 3551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 3561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 3571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 3591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * dma_flush_range(start, end) 3601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Clean and invalidate the specified virtual address range. 3621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 3641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 3651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_dma_flush_range) 3671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #CACHELINESIZE - 1 3681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 3701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 3711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 3721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 3731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 3741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 3751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 376a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King/* 377a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * dma_map_area(start, size, dir) 378a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * - start - kernel virtual start address 379a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * - size - size of region 380a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * - dir - DMA direction 381a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King */ 382a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell KingENTRY(xscale_dma_map_area) 383a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King add r1, r1, r0 384a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King cmp r2, #DMA_TO_DEVICE 385a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King beq xscale_dma_clean_range 386a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King bcs xscale_dma_inv_range 387a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King b xscale_dma_flush_range 388a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell KingENDPROC(xscale_dma_map_area) 389a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King 390a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King/* 391a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * dma_map_area(start, size, dir) 392a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * - start - kernel virtual start address 393a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * - size - size of region 394a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * - dir - DMA direction 395a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King */ 396ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave MartinENTRY(xscale_80200_A0_A1_dma_map_area) 397a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King add r1, r1, r0 398a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King teq r2, #DMA_TO_DEVICE 399a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King beq xscale_dma_clean_range 400a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King b xscale_dma_flush_range 401ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave MartinENDPROC(xscale_80200_A0_A1_dma_map_area) 402a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King 403a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King/* 404a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * dma_unmap_area(start, size, dir) 405a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * - start - kernel virtual start address 406a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * - size - size of region 407a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * - dir - DMA direction 408a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King */ 409a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell KingENTRY(xscale_dma_unmap_area) 410a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King mov pc, lr 411a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell KingENDPROC(xscale_dma_unmap_area) 412a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King 413ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) 414ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin define_cache_functions xscale 4151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 416197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek/* 417197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't 418197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * clear the dirty bits, which means that if we invalidate a dirty line, 419197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * the dirty data can still be written back to external memory later on. 420197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * 421197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * The recommended workaround is to always do a clean D-cache line before 422197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * doing an invalidate D-cache line, so on the affected processors, 423197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * dma_inv_range() is implemented as dma_flush_range(). 424197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * 425197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * See erratum #25 of "Intel 80200 Processor Specification Update", 426197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * revision January 22, 2003, available at: 427197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * http://www.intel.com/design/iio/specupdt/273415.htm 428197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek */ 429ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin.macro a0_alias basename 430ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin .globl xscale_80200_A0_A1_\basename 431ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin .type xscale_80200_A0_A1_\basename , %function 432ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin .equ xscale_80200_A0_A1_\basename , xscale_\basename 433ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin.endm 434ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin 435ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin/* 436ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin * Most of the cache functions are unchanged for these processor revisions. 437ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin * Export suitable alias symbols for the unchanged functions: 438ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin */ 439ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin a0_alias flush_icache_all 440ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin a0_alias flush_user_cache_all 441ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin a0_alias flush_kern_cache_all 442ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin a0_alias flush_user_cache_range 443ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin a0_alias coherent_kern_range 444ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin a0_alias coherent_user_range 445ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin a0_alias flush_kern_dcache_area 446ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin a0_alias dma_flush_range 447ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin a0_alias dma_unmap_area 448ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin 449ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) 450ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin define_cache_functions xscale_80200_A0_A1 451197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek 4521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_dcache_clean_area) 4531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 4541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 4551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds subs r1, r1, #CACHELINESIZE 4561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bhi 1b 4571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 4581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* =============================== PageTable ============================== */ 4601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 4621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_switch_mm(pgd) 4631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Set the translation base pointer to be as described by pgd. 4651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * pgd: new page tables 4671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 4691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_switch_mm) 4701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds clean_d_cache r1, r2 4711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB 4721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 4731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 4741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 4751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cpwait_ret lr, ip 4761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 478ad1ae2fe7fe68414ef29eab3c87b48841f8b72f2Russell King * cpu_xscale_set_pte_ext(ptep, pte, ext) 4791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Set a PTE and flush it out 4811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Errata 40: must set memory to write-through for user read-only pages. 4831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4849e8b5199a753a2583a8ef8360e6428304a242283Russell Kingcpu_xscale_mt_table: 4859e8b5199a753a2583a8ef8360e6428304a242283Russell King .long 0x00 @ L_PTE_MT_UNCACHED 4869e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_BUFFERABLE @ L_PTE_MT_BUFFERABLE 4879e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH 4889e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK 48940df2d1d8538865341a4cb9d4b7a375296517ad2Russell King .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED 490639b0ae7f5bcd645862a9c3ea2d4321475c71d7aRussell King .long 0x00 @ unused 4919e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_EXT_TEX(1) | PTE_CACHEABLE @ L_PTE_MT_MINICACHE 4929e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC 493639b0ae7f5bcd645862a9c3ea2d4321475c71d7aRussell King .long 0x00 @ unused 4949e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_BUFFERABLE @ L_PTE_MT_DEV_WC 4959e8b5199a753a2583a8ef8360e6428304a242283Russell King .long 0x00 @ unused 4969e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED 4979e8b5199a753a2583a8ef8360e6428304a242283Russell King .long 0x00 @ L_PTE_MT_DEV_NONSHARED 498db5b7169474882fabbd811a4cf5c1bae3157e677Russell King .long 0x00 @ unused 4999e8b5199a753a2583a8ef8360e6428304a242283Russell King .long 0x00 @ unused 5009e8b5199a753a2583a8ef8360e6428304a242283Russell King .long 0x00 @ unused 5019e8b5199a753a2583a8ef8360e6428304a242283Russell King 5021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 503ad1ae2fe7fe68414ef29eab3c87b48841f8b72f2Russell KingENTRY(cpu_xscale_set_pte_ext) 504da0916539d20f257dfa46784357300e49d6bfd00Russell King xscale_set_pte_ext_prologue 5051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ 5079e8b5199a753a2583a8ef8360e6428304a242283Russell King @ Erratum 40: must set memory to write-through for user read-only pages 5081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ 50936bb94ba36f332de767cfaa3af6a5136435a3a9cRussell King and ip, r1, #(L_PTE_MT_MASK | L_PTE_USER | L_PTE_RDONLY) & ~(4 << 2) 51036bb94ba36f332de767cfaa3af6a5136435a3a9cRussell King teq ip, #L_PTE_MT_WRITEBACK | L_PTE_USER | L_PTE_RDONLY 5119e8b5199a753a2583a8ef8360e6428304a242283Russell King 5129e8b5199a753a2583a8ef8360e6428304a242283Russell King moveq r1, #L_PTE_MT_WRITETHROUGH 5139e8b5199a753a2583a8ef8360e6428304a242283Russell King and r1, r1, #L_PTE_MT_MASK 5149e8b5199a753a2583a8ef8360e6428304a242283Russell King adr ip, cpu_xscale_mt_table 5159e8b5199a753a2583a8ef8360e6428304a242283Russell King ldr ip, [ip, r1] 5169e8b5199a753a2583a8ef8360e6428304a242283Russell King bic r2, r2, #0x0c 5179e8b5199a753a2583a8ef8360e6428304a242283Russell King orr r2, r2, ip 5181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 519da0916539d20f257dfa46784357300e49d6bfd00Russell King xscale_set_pte_ext_epilogue 5201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 5211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .ltorg 5231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 525f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King.globl cpu_xscale_suspend_size 526de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King.equ cpu_xscale_suspend_size, 4 * 6 52729ea23ff905d07d8559bac69cca46f4bbf20038cRussell King#ifdef CONFIG_PM_SLEEP 528f6b0fa02e8b0708d17d631afce456524eadf87ffRussell KingENTRY(cpu_xscale_do_suspend) 529de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King stmfd sp!, {r4 - r9, lr} 530f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode 531f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mrc p15, 0, r5, c15, c1, 0 @ CP access reg 532f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mrc p15, 0, r6, c13, c0, 0 @ PID 533f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mrc p15, 0, r7, c3, c0, 0 @ domain ID 534de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mrc p15, 0, r8, c1, c1, 0 @ auxiliary control reg 535de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mrc p15, 0, r9, c1, c0, 0 @ control reg 536f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King bic r4, r4, #2 @ clear frequency change bit 537de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King stmia r0, {r4 - r9} @ store cp regs 538de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King ldmfd sp!, {r4 - r9, pc} 539f6b0fa02e8b0708d17d631afce456524eadf87ffRussell KingENDPROC(cpu_xscale_do_suspend) 540f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King 541f6b0fa02e8b0708d17d631afce456524eadf87ffRussell KingENTRY(cpu_xscale_do_resume) 542de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King ldmia r0, {r4 - r9} @ load cp regs 543f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mov ip, #0 544f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 545f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB 546f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode. 547f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, r5, c15, c1, 0 @ CP access reg 548f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, r6, c13, c0, 0 @ PID 549f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, r7, c3, c0, 0 @ domain ID 550de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mcr p15, 0, r1, c2, c0, 0 @ translation table base addr 551de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mcr p15, 0, r8, c1, c1, 0 @ auxiliary control reg 552de8e71ca4f2e17329f6718ae88d5c8336cb249eeRussell King mov r0, r9 @ control register 553f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King b cpu_resume_mmu 554f6b0fa02e8b0708d17d631afce456524eadf87ffRussell KingENDPROC(cpu_xscale_do_resume) 555f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King#endif 556f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King 5575085f3ff458521045f7e43da62b8c30ea7df2e82Russell King __CPUINIT 5581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __xscale_setup, #function 5601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__xscale_setup: 5611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB 5621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 5631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs 564afe4b25e7d9260d85fccb2d13c9933a987bdfc8aLennert Buytenhek mov r0, #1 << 6 @ cp6 for IOP3xx and Bulverde 5651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds orr r0, r0, #1 << 13 @ Its undefined whether this 5661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes 56722b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King 56822b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King adr r5, xscale_crval 56922b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King ldmia r5, {r5, r6} 5701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, r0, c1, c0, 0 @ get control register 5711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, r5 57222b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King orr r0, r0, r6 5731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 5741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __xscale_setup, . - __xscale_setup 5751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 5771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * R 5781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * .RVI ZFRS BLDP WCAM 5791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * ..11 1.01 .... .101 5801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 58222b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King .type xscale_crval, #object 58322b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell Kingxscale_crval: 58422b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900 5851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __INITDATA 5871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 588ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) 589ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin define_processor_functions xscale, dabort=v5t_early_abort, pabort=legacy_pabort, suspend=1 5901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .section ".rodata" 5921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 593ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin string cpu_arch_name, "armv5te" 594ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin string cpu_elf_name, "v5" 595ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin 596ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin string cpu_80200_A0_A1_name, "XScale-80200 A0/A1" 597ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin string cpu_80200_name, "XScale-80200" 598ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin string cpu_80219_name, "XScale-80219" 599ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin string cpu_8032x_name, "XScale-IOP8032x Family" 600ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin string cpu_8033x_name, "XScale-IOP8033x Family" 601ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin string cpu_pxa250_name, "XScale-PXA250" 602ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin string cpu_pxa210_name, "XScale-PXA210" 603ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin string cpu_ixp42x_name, "XScale-IXP42x Family" 604ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin string cpu_ixp43x_name, "XScale-IXP43x Family" 605ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin string cpu_ixp46x_name, "XScale-IXP46x Family" 606ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin string cpu_ixp2400_name, "XScale-IXP2400" 607ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin string cpu_ixp2800_name, "XScale-IXP2800" 608ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin string cpu_pxa255_name, "XScale-PXA255" 609ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin string cpu_pxa270_name, "XScale-PXA270" 6101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 6121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 61302b7dd1244aab9267ae4078e1ad6a2fdaabeb6edBen Dooks .section ".proc.info.init", #alloc, #execinstr 6141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 615ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin.macro xscale_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache 616ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin .type __\name\()_proc_info,#object 617ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin__\name\()_proc_info: 618ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin .long \cpu_val 619ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin .long \cpu_mask 620ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin .long PMD_TYPE_SECT | \ 6211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 6221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 6231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 6241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 625ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin .long PMD_TYPE_SECT | \ 6268799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 6278799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 6281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 6291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 6301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 6311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 632ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin .long \cpu_name 6331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 6341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 6351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 636ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin .ifb \cache 637ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin .long xscale_cache_fns 638ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin .else 639ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin .long \cache 640ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin .endif 641ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin .size __\name\()_proc_info, . - __\name\()_proc_info 642ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin.endm 643ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin 644ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin xscale_proc_info 80200_A0_A1, 0x69052000, 0xfffffffe, cpu_80200_name, \ 645ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin cache=xscale_80200_A0_A1_cache_fns 646ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin xscale_proc_info 80200, 0x69052000, 0xfffffff0, cpu_80200_name 647ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin xscale_proc_info 80219, 0x69052e20, 0xffffffe0, cpu_80219_name 648ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin xscale_proc_info 8032x, 0x69052420, 0xfffff7e0, cpu_8032x_name 649ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin xscale_proc_info 8033x, 0x69054010, 0xfffffd30, cpu_8033x_name 650ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin xscale_proc_info pxa250, 0x69052100, 0xfffff7f0, cpu_pxa250_name 651ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin xscale_proc_info pxa210, 0x69052120, 0xfffff3f0, cpu_pxa210_name 652ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin xscale_proc_info ixp2400, 0x69054190, 0xfffffff0, cpu_ixp2400_name 653ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin xscale_proc_info ixp2800, 0x690541a0, 0xfffffff0, cpu_ixp2800_name 654ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin xscale_proc_info ixp42x, 0x690541c0, 0xffffffc0, cpu_ixp42x_name 655ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin xscale_proc_info ixp43x, 0x69054040, 0xfffffff0, cpu_ixp43x_name 656ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin xscale_proc_info ixp46x, 0x69054200, 0xffffff00, cpu_ixp46x_name 657ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin xscale_proc_info pxa255, 0x69052d00, 0xfffffff0, cpu_pxa255_name 658ab1a746da9dd19e30a98d9744d5c7dc6df597fb0Dave Martin xscale_proc_info pxa270, 0x69054110, 0xfffffff0, cpu_pxa270_name 659