proc-xscale.S revision 1da177e4c3f41524e886b7f1b8a0c1fc7321cac
11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * linux/arch/arm/mm/proc-xscale.S 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Author: Nicolas Pitre 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Created: November 2000 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright: (C) 2000, 2001 MontaVista Software Inc. 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This program is free software; you can redistribute it and/or modify 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * it under the terms of the GNU General Public License version 2 as 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * published by the Free Software Foundation. 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * MMU functions for the Intel XScale CPUs 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2001 Aug 21: 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * some contributions by Brett Gaines <brett.w.gaines@intel.com> 161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright 2001 by Intel Corp. 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2001 Sep 08: 191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Completely revisited, many important fixes 201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Nicolas Pitre <nico@cam.org> 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/linkage.h> 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/init.h> 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/assembler.h> 261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/procinfo.h> 271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/hardware.h> 281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/pgtable.h> 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/page.h> 301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/ptrace.h> 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include "proc-macros.S" 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This is the maximum size of an area which will be flushed. If the area 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * is larger than this, then we flush the whole cache 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAX_AREA_SIZE 32768 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the cache line size of the I and D cache 411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CACHELINESIZE 32 431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the size of the data cache 461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CACHESIZE 32768 481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Virtual address used to allocate the cache when flushed 511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This must be an address range which is _never_ used. It should 531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * apparently have a mapping in the corresponding page table for 541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * compatibility with future CPUs that _could_ require it. For instance we 551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * don't care. 561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This must be aligned on a 2*CACHESIZE boundary. The code selects one of 581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the 2 areas in alternance each time the clean_d_cache macro is used. 591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Without this the XScale core exhibits cache eviction problems and no one 601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * knows why. 611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Reminder: the vector table is located at 0xffff0000-0xffff0fff. 631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CLEAN_ADDR 0xfffe0000 651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This macro is used to wait for a CP15 write and is needed 681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * when we have to ensure that the last operation to the co-pro 691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * was completed before continuing with operation. 701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .macro cpwait, rd 721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov \rd, \rd @ wait for completion 741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds sub pc, pc, #4 @ flush instruction pipeline 751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .endm 761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .macro cpwait_ret, lr, rd 781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds sub pc, \lr, \rd, LSR #32 @ wait for completion and 801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ flush instruction pipeline 811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .endm 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This macro cleans the entire dcache using line allocate. 851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * The main loop has been unrolled to reduce loop overhead. 861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * rd and rs are two scratch registers. 871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .macro clean_d_cache, rd, rs 891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ldr \rs, =clean_addr 901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ldr \rd, [\rs] 911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds eor \rd, \rd, #CACHESIZE 921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds str \rd, [\rs] 931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rs, \rd, #CACHESIZE 941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rd, \rd, #CACHELINESIZE 961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rd, \rd, #CACHELINESIZE 981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rd, \rd, #CACHELINESIZE 1001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 1011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rd, \rd, #CACHELINESIZE 1021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds teq \rd, \rs 1031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bne 1b 1041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .endm 1051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .data 1071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsclean_addr: .word CLEAN_ADDR 1081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .text 1101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_proc_init() 1131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Nothing too exciting at the moment 1151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_proc_init) 1171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 1181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_proc_fin() 1211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_proc_fin) 1231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds str lr, [sp, #-4]! 1241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE 1251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds msr cpsr_c, r0 1261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bl xscale_flush_kern_cache_all @ clean caches 1271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, r0, c1, c0, 0 @ ctrl register 1281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #0x1800 @ ...IZ........... 1291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #0x0006 @ .............CA. 1301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c1, c0, 0 @ disable caches 1311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ldr pc, [sp], #4 1321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_reset(loc) 1351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Perform a soft reset of the system. Put the CPU into the 1371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * same state as it would be if it had been reset, and branch 1381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * to what would be the reset vector. 1391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * loc: location to jump to for soft reset 1411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 1431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_reset) 1441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE 1451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds msr cpsr_c, r1 @ reset CPSR 1461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, r1, c1, c0, 0 @ ctrl register 1471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r1, r1, #0x0086 @ ........B....CA. 1481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r1, r1, #0x3900 @ ..VIZ..S........ 1491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r1, c1, c0, 0 @ ctrl register 1501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB 1511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r1, r1, #0x0001 @ ...............M 1521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r1, c1, c0, 0 @ ctrl register 1531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ CAUTION: MMU turned off from this point. We count on the pipeline 1541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ already containing those two last instructions to survive. 1551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 1561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, r0 1571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_do_idle() 1601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Cause the processor to idle 1621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * For now we do nothing but go to idle mode for every case 1641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * XScale supports clock switching, but using idle mode support 1661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * allows external hardware to react to system state changes. 1671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 1691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_do_idle) 1711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #1 1721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE 1731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 1741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* ================================= CACHE ================================ */ 1761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * flush_user_cache_all() 1791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Invalidate all cache entries in a particular address 1811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * space. 1821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_flush_user_cache_all) 1841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* FALLTHROUGH */ 1851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * flush_kern_cache_all() 1881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Clean and invalidate the entire cache. 1901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_flush_kern_cache_all) 1921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r2, #VM_EXEC 1931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov ip, #0 1941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__flush_whole_cache: 1951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds clean_d_cache r0, r1 1961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r2, #VM_EXEC 1971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB 1981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 1991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 2001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * flush_user_cache_range(start, end, vm_flags) 2031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Invalidate a range of cache entries in the specified 2051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * address space. 2061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - start address (may not be aligned) 2081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - end address (exclusive, may not be aligned) 2091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - vma - vma_area_struct describing address space 2101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 2121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_flush_user_cache_range) 2131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov ip, #0 2141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds sub r3, r1, r0 @ calculate total size 2151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r3, #MAX_AREA_SIZE 2161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bhs __flush_whole_cache 2171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: tst r2, #VM_EXEC 2191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line 2201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line 2211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line 2221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 2231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 2241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 2251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r2, #VM_EXEC 2261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB 2271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 2281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 2291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * coherent_kern_range(start, end) 2321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Ensure coherency between the Icache and the Dcache in the 2341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * region described by start. If you have non-snooping 2351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Harvard caches, you need to implement this function. 2361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 2381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 2391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Note: single I-cache line invalidation isn't used here since 2411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * it also trashes the mini I-cache used by JTAG debuggers. 2421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_coherent_kern_range) 2441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* FALLTHROUGH */ 2451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * coherent_user_range(start, end) 2481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Ensure coherency between the Icache and the Dcache in the 2501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * region described by start. If you have non-snooping 2511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Harvard caches, you need to implement this function. 2521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 2541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 2551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Note: single I-cache line invalidation isn't used here since 2571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * it also trashes the mini I-cache used by JTAG debuggers. 2581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_coherent_user_range) 2601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #CACHELINESIZE - 1 2611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 2631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 2641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 2651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #0 2661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB 2671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 2681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 2691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * flush_kern_dcache_page(void *page) 2721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Ensure no D cache aliasing occurs, either with itself or 2741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the I cache 2751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - addr - page aligned address 2771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_flush_kern_dcache_page) 2791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r1, r0, #PAGE_SZ 2801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 2821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 2831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 2841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 2851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #0 2861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB 2871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 2881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 2891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * dma_inv_range(start, end) 2921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Invalidate (discard) the specified virtual address range. 2941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * May not write back any entries. If 'start' or 'end' 2951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * are not cache line aligned, those lines must be written 2961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * back. 2971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 2991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 3001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_dma_inv_range) 3021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, r2, c0, c0, 0 @ read ID 3031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds eor r2, r2, #0x69000000 3041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds eor r2, r2, #0x00052000 3051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bics r2, r2, #1 3061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds beq xscale_dma_flush_range 3071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r0, #CACHELINESIZE - 1 3091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #CACHELINESIZE - 1 3101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 3111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r1, #CACHELINESIZE - 1 3121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 3131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 3141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 3151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 3161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 3171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 3181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 3191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 3211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * dma_clean_range(start, end) 3221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Clean the specified virtual address range. 3241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 3261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 3271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_dma_clean_range) 3291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #CACHELINESIZE - 1 3301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 3321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 3331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 3341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 3351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 3361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 3381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * dma_flush_range(start, end) 3391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Clean and invalidate the specified virtual address range. 3411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 3431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 3441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_dma_flush_range) 3461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #CACHELINESIZE - 1 3471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 3491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 3501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 3511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 3521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 3531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 3541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_cache_fns) 3561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_flush_kern_cache_all 3571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_flush_user_cache_all 3581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_flush_user_cache_range 3591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_coherent_kern_range 3601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_coherent_user_range 3611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_flush_kern_dcache_page 3621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_dma_inv_range 3631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_dma_clean_range 3641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_dma_flush_range 3651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_dcache_clean_area) 3671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 3691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds subs r1, r1, #CACHELINESIZE 3701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bhi 1b 3711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 3721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* ================================ CACHE LOCKING============================ 3741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * The XScale MicroArchitecture implements support for locking entries into 3761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the data and instruction cache. The following functions implement the core 3771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * low level instructions needed to accomplish the locking. The developer's 3781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * manual states that the code that performs the locking must be in non-cached 3791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * memory. To accomplish this, the code in xscale-cache-lock.c copies the 3801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * following functions from the cache into a non-cached memory region that 3811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * is allocated through consistent_alloc(). 3821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 3851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 3861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * xscale_icache_lock 3871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * r0: starting address to lock 3891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * r1: end address to lock 3901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_icache_lock) 3921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsiLockLoop: 3941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #CACHELINESIZE - 1 3951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c9, c1, 0 @ lock into cache 3961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 @ are we done? 3971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE @ advance to next cache line 3981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bls iLockLoop 3991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 4001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 4021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * xscale_icache_unlock 4031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_icache_unlock) 4051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c9, c1, 1 @ Unlock icache 4061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 4071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 4091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * xscale_dcache_lock 4101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * r0: starting address to lock 4121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * r1: end address to lock 4131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_dcache_lock) 4151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 4161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r2, #1 4171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r2, c9, c2, 0 @ Put dcache in lock mode 4181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cpwait ip @ Wait for completion 4191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrs r2, cpsr 4211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds orr r3, r2, #PSR_F_BIT | PSR_I_BIT 4221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsdLockLoop: 4231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds msr cpsr_c, r3 4241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 1 @ Write back line if it is dirty 4251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c6, 1 @ Flush/invalidate line 4261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds msr cpsr_c, r2 4271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ldr ip, [r0], #CACHELINESIZE @ Preload 32 bytes into cache from 4281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ location [r0]. Post-increment 4291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ r3 to next cache line 4301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 @ Are we done? 4311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bls dLockLoop 4321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 4341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r2, #0 4351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r2, c9, c2, 0 @ Get out of lock mode 4361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cpwait_ret lr, ip 4371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 4391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * xscale_dcache_unlock 4401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_dcache_unlock) 4421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 4431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c9, c2, 1 @ Unlock cache 4441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 4451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 4471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Needed to determine the length of the code that needs to be copied. 4481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 4501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_cache_dummy) 4511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 4521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* ================================ TLB LOCKING============================== 4541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * The XScale MicroArchitecture implements support for locking entries into 4561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the Instruction and Data TLBs. The following functions provide the 4571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * low level support for supporting these under Linux. xscale-lock.c 4581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * implements some higher level management code. Most of the following 4591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * is taken straight out of the Developer's Manual. 4601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 4631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Lock I-TLB entry 4641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * r0: Virtual address to translate and lock 4661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 4681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_itlb_lock) 4691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrs r2, cpsr 4701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds orr r3, r2, #PSR_F_BIT | PSR_I_BIT 4711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds msr cpsr_c, r3 @ Disable interrupts 4721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c8, c5, 1 @ Invalidate I-TLB entry 4731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c10, c4, 0 @ Translate and lock 4741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds msr cpsr_c, r2 @ Restore interrupts 4751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cpwait_ret lr, ip 4761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 4781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Lock D-TLB entry 4791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * r0: Virtual address to translate and lock 4811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 4831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_dtlb_lock) 4841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrs r2, cpsr 4851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds orr r3, r2, #PSR_F_BIT | PSR_I_BIT 4861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds msr cpsr_c, r3 @ Disable interrupts 4871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c8, c6, 1 @ Invalidate D-TLB entry 4881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c10, c8, 0 @ Translate and lock 4891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds msr cpsr_c, r2 @ Restore interrupts 4901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cpwait_ret lr, ip 4911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 4931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Unlock all I-TLB entries 4941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 4961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_itlb_unlock) 4971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c10, c4, 1 @ Unlock I-TLB 4981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c8, c5, 0 @ Invalidate I-TLB 4991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cpwait_ret lr, ip 5001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 5021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Unlock all D-TLB entries 5031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 5041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_dtlb_unlock) 5051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c10, c8, 1 @ Unlock D-TBL 5061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c8, c6, 0 @ Invalidate D-TLB 5071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cpwait_ret lr, ip 5081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* =============================== PageTable ============================== */ 5101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PTE_CACHE_WRITE_ALLOCATE 0 5121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 5141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_switch_mm(pgd) 5151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Set the translation base pointer to be as described by pgd. 5171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * pgd: new page tables 5191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 5201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 5211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_switch_mm) 5221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds clean_d_cache r1, r2 5231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB 5241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 5251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 5261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 5271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cpwait_ret lr, ip 5281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 5301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_set_pte(ptep, pte) 5311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Set a PTE and flush it out 5331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Errata 40: must set memory to write-through for user read-only pages. 5351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 5361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 5371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_set_pte) 5381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds str r1, [r0], #-2048 @ linux version 5391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r2, r1, #0xff0 5411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds orr r2, r2, #PTE_TYPE_EXT @ extended page 5421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 5441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r3, #L_PTE_USER @ User? 5461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w 5471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty? 5491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w 5501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ combined with user -> user r/w 5511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ 5531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ Handle the X bit. We want to set this bit for the minicache 5541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ (U = E = B = W = 0, C = 1) or when write allocate is enabled, 5551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ and we have a writeable, cacheable region. If we ignore the 5561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ U and E bits, we can allow user space to use the minicache as 5571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ well. 5581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ 5591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ X = (C & ~W & ~B) | (C & W & B & write_allocate) 5601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ 5611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds eor ip, r1, #L_PTE_CACHEABLE 5621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE 5631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#if PTE_CACHE_WRITE_ALLOCATE 5641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds eorne ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE 5651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tstne ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE 5661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 5671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds orreq r2, r2, #PTE_EXT_TEX(1) 5681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ 5701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ Erratum 40: The B bit must be cleared for a user read-only 5711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ cacheable page. 5721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ 5731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ B = B & ~(U & C & ~W) 5741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ 5751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds and ip, r1, #L_PTE_USER | L_PTE_WRITE | L_PTE_CACHEABLE 5761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds teq ip, #L_PTE_USER | L_PTE_CACHEABLE 5771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds biceq r2, r2, #PTE_BUFFERABLE 5781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? 5801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds movne r2, #0 @ no -> fault 5811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds str r2, [r0] @ hardware version 5831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov ip, #0 5841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line 5851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 5861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 5871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .ltorg 5901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __INIT 5941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __xscale_setup, #function 5961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__xscale_setup: 5971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB 5981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 5991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs 6001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CONFIG_IWMMXT 6011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #0 @ initially disallow access to CP0/CP1 6021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#else 6031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #1 @ Allow access to CP0 6041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 6051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde 6061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds orr r0, r0, #1 << 13 @ Its undefined whether this 6071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes 6081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, r0, c1, c0, 0 @ get control register 6091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ldr r5, xscale_cr1_clear 6101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, r5 6111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ldr r5, xscale_cr1_set 6121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds orr r0, r0, r5 6131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 6141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __xscale_setup, . - __xscale_setup 6151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 6171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * R 6181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * .RVI ZFRS BLDP WCAM 6191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * ..11 1.01 .... .101 6201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 6211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 6221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type xscale_cr1_clear, #object 6231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type xscale_cr1_set, #object 6241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsxscale_cr1_clear: 6251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word 0x3b07 6261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsxscale_cr1_set: 6271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word 0x3905 6281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __INITDATA 6301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 6321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Purpose : Function pointers used to access above functions - all calls 6331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * come through these 6341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 6351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type xscale_processor_functions, #object 6371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_processor_functions) 6381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word v5t_early_abort 6391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_proc_init 6401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_proc_fin 6411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_reset 6421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_do_idle 6431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_dcache_clean_area 6441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_switch_mm 6451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_set_pte 6461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size xscale_processor_functions, . - xscale_processor_functions 6471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .section ".rodata" 6491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_arch_name, #object 6511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_arch_name: 6521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "armv5te" 6531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_arch_name, . - cpu_arch_name 6541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_elf_name, #object 6561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_elf_name: 6571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "v5" 6581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_elf_name, . - cpu_elf_name 6591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_80200_name, #object 6611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_80200_name: 6621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-80200" 6631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_80200_name, . - cpu_80200_name 6641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_8032x_name, #object 6661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_8032x_name: 6671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IOP8032x Family" 6681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_8032x_name, . - cpu_8032x_name 6691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_8033x_name, #object 6711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_8033x_name: 6721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IOP8033x Family" 6731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_8033x_name, . - cpu_8033x_name 6741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_pxa250_name, #object 6761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_pxa250_name: 6771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-PXA250" 6781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_pxa250_name, . - cpu_pxa250_name 6791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_pxa210_name, #object 6811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_pxa210_name: 6821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-PXA210" 6831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_pxa210_name, . - cpu_pxa210_name 6841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_ixp42x_name, #object 6861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_ixp42x_name: 6871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IXP42x Family" 6881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_ixp42x_name, . - cpu_ixp42x_name 6891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_ixp46x_name, #object 6911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_ixp46x_name: 6921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IXP46x Family" 6931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_ixp46x_name, . - cpu_ixp46x_name 6941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_ixp2400_name, #object 6961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_ixp2400_name: 6971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IXP2400" 6981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_ixp2400_name, . - cpu_ixp2400_name 6991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_ixp2800_name, #object 7011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_ixp2800_name: 7021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IXP2800" 7031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_ixp2800_name, . - cpu_ixp2800_name 7041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_pxa255_name, #object 7061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_pxa255_name: 7071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-PXA255" 7081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_pxa255_name, . - cpu_pxa255_name 7091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_pxa270_name, #object 7111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_pxa270_name: 7121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-PXA270" 7131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_pxa270_name, . - cpu_pxa270_name 7141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 7161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .section ".proc.info", #alloc, #execinstr 7181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __80200_proc_info,#object 7201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__80200_proc_info: 7211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69052000 7221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffffff0 7231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 7241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 7251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 7261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 7271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 7281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 7291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 7301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 7311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 7321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_80200_name 7331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 7341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 7351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 7361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 7371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __80200_proc_info, . - __80200_proc_info 7381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __8032x_proc_info,#object 7401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__8032x_proc_info: 7411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69052420 7421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffff5e0 @ mask should accomodate IOP80219 also 7431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 7441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 7451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 7461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 7471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 7481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 7491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 7501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 7511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 7521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_8032x_name 7531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 7541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 7551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 7561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 7571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __8032x_proc_info, . - __8032x_proc_info 7581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __8033x_proc_info,#object 7601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__8033x_proc_info: 7611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69054010 7621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xffffff30 7631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 7641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 7651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 7661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 7671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 7681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 7691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 7701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 7711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 7721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_8033x_name 7731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 7741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 7751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 7761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 7771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __8033x_proc_info, . - __8033x_proc_info 7781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __pxa250_proc_info,#object 7801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__pxa250_proc_info: 7811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69052100 7821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffff7f0 7831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 7841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 7851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 7861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 7871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 7881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 7891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 7901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 7911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 7921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_pxa250_name 7931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 7941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 7951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 7961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 7971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __pxa250_proc_info, . - __pxa250_proc_info 7981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __pxa210_proc_info,#object 8001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__pxa210_proc_info: 8011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69052120 8021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffff3f0 8031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 8041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 8051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 8061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 8071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 8081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 8091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 8101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 8111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 8121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_pxa210_name 8131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 8141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 8151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 8161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 8171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __pxa210_proc_info, . - __pxa210_proc_info 8181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __ixp2400_proc_info, #object 8201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__ixp2400_proc_info: 8211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69054190 8221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffffff0 8231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 8241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 8251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 8261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 8271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 8281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 8291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 8301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 8311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 8321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_ixp2400_name 8331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 8341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 8351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 8361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 8371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __ixp2400_proc_info, . - __ixp2400_proc_info 8381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __ixp2800_proc_info, #object 8401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__ixp2800_proc_info: 8411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x690541a0 8421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffffff0 8431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 8441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 8451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 8461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 8471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 8481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 8491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 8501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 8511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 8521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_ixp2800_name 8531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 8541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 8551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 8561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 8571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __ixp2800_proc_info, . - __ixp2800_proc_info 8581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __ixp42x_proc_info, #object 8601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__ixp42x_proc_info: 8611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x690541c0 8621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xffffffc0 8631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 8641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 8651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 8661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 8671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 8681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 8691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 8701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 8711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 8721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_ixp42x_name 8731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 8741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 8751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 8761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 8771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __ixp42x_proc_info, . - __ixp42x_proc_info 8781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __ixp46x_proc_info, #object 8801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__ixp46x_proc_info: 8811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69054200 8821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xffffff00 8831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x00000c0e 8841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 8851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 8861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 8871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 8881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_ixp46x_name 8891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 8901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 8911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 8921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 8931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __ixp46x_proc_info, . - __ixp46x_proc_info 8941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __pxa255_proc_info,#object 8961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__pxa255_proc_info: 8971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69052d00 8981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffffff0 8991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 9001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 9011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 9021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 9031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 9041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 9051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 9061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 9071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 9081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_pxa255_name 9091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 9101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 9111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 9121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 9131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __pxa255_proc_info, . - __pxa255_proc_info 9141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __pxa270_proc_info,#object 9161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__pxa270_proc_info: 9171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69054110 9181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffffff0 9191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 9201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 9211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 9221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 9231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 9241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 9251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 9261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 9271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 9281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_pxa270_name 9291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 9301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 9311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 9321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 9331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __pxa270_proc_info, . - __pxa270_proc_info 9341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 935