proc-xscale.S revision 40df2d1d8538865341a4cb9d4b7a375296517ad2
11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * linux/arch/arm/mm/proc-xscale.S 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Author: Nicolas Pitre 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Created: November 2000 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright: (C) 2000, 2001 MontaVista Software Inc. 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This program is free software; you can redistribute it and/or modify 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * it under the terms of the GNU General Public License version 2 as 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * published by the Free Software Foundation. 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * MMU functions for the Intel XScale CPUs 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2001 Aug 21: 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * some contributions by Brett Gaines <brett.w.gaines@intel.com> 161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright 2001 by Intel Corp. 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2001 Sep 08: 191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Completely revisited, many important fixes 201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Nicolas Pitre <nico@cam.org> 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/linkage.h> 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/init.h> 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/assembler.h> 26ee90dabcadd053d5dd69f3a7f8161afa2c751aceRussell King#include <asm/elf.h> 271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/pgtable.h> 280003cedfc577be9d679c16531f8720739e9637edRussell King#include <asm/pgtable-hwdef.h> 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/page.h> 301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/ptrace.h> 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include "proc-macros.S" 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This is the maximum size of an area which will be flushed. If the area 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * is larger than this, then we flush the whole cache 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAX_AREA_SIZE 32768 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the cache line size of the I and D cache 411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CACHELINESIZE 32 431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the size of the data cache 461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CACHESIZE 32768 481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Virtual address used to allocate the cache when flushed 511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This must be an address range which is _never_ used. It should 531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * apparently have a mapping in the corresponding page table for 541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * compatibility with future CPUs that _could_ require it. For instance we 551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * don't care. 561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This must be aligned on a 2*CACHESIZE boundary. The code selects one of 581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the 2 areas in alternance each time the clean_d_cache macro is used. 591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Without this the XScale core exhibits cache eviction problems and no one 601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * knows why. 611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Reminder: the vector table is located at 0xffff0000-0xffff0fff. 631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CLEAN_ADDR 0xfffe0000 651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This macro is used to wait for a CP15 write and is needed 681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * when we have to ensure that the last operation to the co-pro 691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * was completed before continuing with operation. 701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .macro cpwait, rd 721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov \rd, \rd @ wait for completion 741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds sub pc, pc, #4 @ flush instruction pipeline 751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .endm 761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .macro cpwait_ret, lr, rd 781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds sub pc, \lr, \rd, LSR #32 @ wait for completion and 801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ flush instruction pipeline 811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .endm 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This macro cleans the entire dcache using line allocate. 851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * The main loop has been unrolled to reduce loop overhead. 861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * rd and rs are two scratch registers. 871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .macro clean_d_cache, rd, rs 891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ldr \rs, =clean_addr 901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ldr \rd, [\rs] 911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds eor \rd, \rd, #CACHESIZE 921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds str \rd, [\rs] 931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rs, \rd, #CACHESIZE 941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rd, \rd, #CACHELINESIZE 961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rd, \rd, #CACHELINESIZE 981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rd, \rd, #CACHELINESIZE 1001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 1011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rd, \rd, #CACHELINESIZE 1021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds teq \rd, \rs 1031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bne 1b 1041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .endm 1051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .data 1071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsclean_addr: .word CLEAN_ADDR 1081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .text 1101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_proc_init() 1131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Nothing too exciting at the moment 1151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_proc_init) 117391c569daa6e4e999592966e29c146dfc4de9a9cArnaud Patard @ enable write buffer coalescing. Some bootloader disable it 118391c569daa6e4e999592966e29c146dfc4de9a9cArnaud Patard mrc p15, 0, r1, c1, c0, 1 119391c569daa6e4e999592966e29c146dfc4de9a9cArnaud Patard bic r1, r1, #1 120391c569daa6e4e999592966e29c146dfc4de9a9cArnaud Patard mcr p15, 0, r1, c1, c0, 1 1211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 1221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_proc_fin() 1251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_proc_fin) 1271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds str lr, [sp, #-4]! 1281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE 1291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds msr cpsr_c, r0 1301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bl xscale_flush_kern_cache_all @ clean caches 1311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, r0, c1, c0, 0 @ ctrl register 1321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #0x1800 @ ...IZ........... 1331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #0x0006 @ .............CA. 1341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c1, c0, 0 @ disable caches 1351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ldr pc, [sp], #4 1361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_reset(loc) 1391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Perform a soft reset of the system. Put the CPU into the 1411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * same state as it would be if it had been reset, and branch 1421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * to what would be the reset vector. 1431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * loc: location to jump to for soft reset 1452dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre * 1462dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre * Beware PXA270 erratum E7. 1471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 1491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_reset) 1501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE 1511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds msr cpsr_c, r1 @ reset CPSR 1522dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB 1532dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB 1541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, r1, c1, c0, 0 @ ctrl register 1551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r1, r1, #0x0086 @ ........B....CA. 1561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r1, r1, #0x3900 @ ..VIZ..S........ 1572dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre sub pc, pc, #4 @ flush pipeline 1582dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre @ *** cache line aligned *** 1591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r1, c1, c0, 0 @ ctrl register 1601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r1, r1, #0x0001 @ ...............M 1612dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB 1621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r1, c1, c0, 0 @ ctrl register 1631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ CAUTION: MMU turned off from this point. We count on the pipeline 1641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ already containing those two last instructions to survive. 1651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 1661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, r0 1671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_do_idle() 1701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Cause the processor to idle 1721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * For now we do nothing but go to idle mode for every case 1741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * XScale supports clock switching, but using idle mode support 1761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * allows external hardware to react to system state changes. 1771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 1791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_do_idle) 1811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #1 1821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE 1831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 1841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* ================================= CACHE ================================ */ 1861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * flush_user_cache_all() 1891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Invalidate all cache entries in a particular address 1911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * space. 1921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_flush_user_cache_all) 1941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* FALLTHROUGH */ 1951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * flush_kern_cache_all() 1981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Clean and invalidate the entire cache. 2001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_flush_kern_cache_all) 2021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r2, #VM_EXEC 2031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov ip, #0 2041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__flush_whole_cache: 2051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds clean_d_cache r0, r1 2061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r2, #VM_EXEC 2071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB 2081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 2091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 2101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * flush_user_cache_range(start, end, vm_flags) 2131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Invalidate a range of cache entries in the specified 2151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * address space. 2161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - start address (may not be aligned) 2181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - end address (exclusive, may not be aligned) 2191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - vma - vma_area_struct describing address space 2201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 2221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_flush_user_cache_range) 2231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov ip, #0 2241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds sub r3, r1, r0 @ calculate total size 2251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r3, #MAX_AREA_SIZE 2261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bhs __flush_whole_cache 2271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: tst r2, #VM_EXEC 2291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line 2301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line 2311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line 2321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 2331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 2341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 2351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r2, #VM_EXEC 2361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB 2371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 2381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 2391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * coherent_kern_range(start, end) 2421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Ensure coherency between the Icache and the Dcache in the 2441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * region described by start. If you have non-snooping 2451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Harvard caches, you need to implement this function. 2461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 2481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 2491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Note: single I-cache line invalidation isn't used here since 2511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * it also trashes the mini I-cache used by JTAG debuggers. 2521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_coherent_kern_range) 2548a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre bic r0, r0, #CACHELINESIZE - 1 2558a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2568a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre add r0, r0, #CACHELINESIZE 2578a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre cmp r0, r1 2588a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre blo 1b 2598a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mov r0, #0 2608a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB 2618a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 2628a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mov pc, lr 2631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * coherent_user_range(start, end) 2661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Ensure coherency between the Icache and the Dcache in the 2681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * region described by start. If you have non-snooping 2691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Harvard caches, you need to implement this function. 2701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 2721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 2731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_coherent_user_range) 2751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #CACHELINESIZE - 1 2761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2778a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry 2781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 2791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 2801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 2811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #0 2828a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB 2831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 2841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 2851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * flush_kern_dcache_page(void *page) 2881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Ensure no D cache aliasing occurs, either with itself or 2901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the I cache 2911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - addr - page aligned address 2931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_flush_kern_dcache_page) 2951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r1, r0, #PAGE_SZ 2961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 2981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 2991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 3001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 3011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #0 3021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB 3031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 3041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 3051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 3071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * dma_inv_range(start, end) 3081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Invalidate (discard) the specified virtual address range. 3101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * May not write back any entries. If 'start' or 'end' 3111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * are not cache line aligned, those lines must be written 3121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * back. 3131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 3151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 3161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_dma_inv_range) 3181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r0, #CACHELINESIZE - 1 3191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #CACHELINESIZE - 1 3201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 3211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r1, #CACHELINESIZE - 1 3221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 3231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 3241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 3251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 3261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 3271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 3281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 3291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 3311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * dma_clean_range(start, end) 3321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Clean the specified virtual address range. 3341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 3361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 3371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_dma_clean_range) 3391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #CACHELINESIZE - 1 3401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 3421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 3431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 3441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 3451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 3461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 3481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * dma_flush_range(start, end) 3491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Clean and invalidate the specified virtual address range. 3511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 3531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 3541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_dma_flush_range) 3561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #CACHELINESIZE - 1 3571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 3591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 3601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 3611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 3621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 3631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 3641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_cache_fns) 3661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_flush_kern_cache_all 3671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_flush_user_cache_all 3681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_flush_user_cache_range 3691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_coherent_kern_range 3701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_coherent_user_range 3711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_flush_kern_dcache_page 3721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_dma_inv_range 3731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_dma_clean_range 3741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_dma_flush_range 3751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 376197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek/* 377197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't 378197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * clear the dirty bits, which means that if we invalidate a dirty line, 379197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * the dirty data can still be written back to external memory later on. 380197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * 381197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * The recommended workaround is to always do a clean D-cache line before 382197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * doing an invalidate D-cache line, so on the affected processors, 383197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * dma_inv_range() is implemented as dma_flush_range(). 384197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * 385197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * See erratum #25 of "Intel 80200 Processor Specification Update", 386197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * revision January 22, 2003, available at: 387197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * http://www.intel.com/design/iio/specupdt/273415.htm 388197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek */ 389197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert BuytenhekENTRY(xscale_80200_A0_A1_cache_fns) 390197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_flush_kern_cache_all 391197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_flush_user_cache_all 392197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_flush_user_cache_range 393197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_coherent_kern_range 394197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_coherent_user_range 395197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_flush_kern_dcache_page 396197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_dma_flush_range 397197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_dma_clean_range 398197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_dma_flush_range 399197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek 4001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_dcache_clean_area) 4011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 4021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 4031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds subs r1, r1, #CACHELINESIZE 4041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bhi 1b 4051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 4061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* =============================== PageTable ============================== */ 4081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 4101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_switch_mm(pgd) 4111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Set the translation base pointer to be as described by pgd. 4131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * pgd: new page tables 4151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 4171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_switch_mm) 4181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds clean_d_cache r1, r2 4191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB 4201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 4211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 4221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 4231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cpwait_ret lr, ip 4241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 426ad1ae2fe7fe68414ef29eab3c87b48841f8b72f2Russell King * cpu_xscale_set_pte_ext(ptep, pte, ext) 4271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Set a PTE and flush it out 4291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Errata 40: must set memory to write-through for user read-only pages. 4311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4329e8b5199a753a2583a8ef8360e6428304a242283Russell Kingcpu_xscale_mt_table: 4339e8b5199a753a2583a8ef8360e6428304a242283Russell King .long 0x00 @ L_PTE_MT_UNCACHED 4349e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_BUFFERABLE @ L_PTE_MT_BUFFERABLE 4359e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH 4369e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK 43740df2d1d8538865341a4cb9d4b7a375296517ad2Russell King .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED 438639b0ae7f5bcd645862a9c3ea2d4321475c71d7aRussell King .long 0x00 @ unused 4399e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_EXT_TEX(1) | PTE_CACHEABLE @ L_PTE_MT_MINICACHE 4409e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC 441639b0ae7f5bcd645862a9c3ea2d4321475c71d7aRussell King .long 0x00 @ unused 4429e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_BUFFERABLE @ L_PTE_MT_DEV_WC 4439e8b5199a753a2583a8ef8360e6428304a242283Russell King .long 0x00 @ unused 4449e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED 4459e8b5199a753a2583a8ef8360e6428304a242283Russell King .long 0x00 @ L_PTE_MT_DEV_NONSHARED 4469e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_IXP2000 4479e8b5199a753a2583a8ef8360e6428304a242283Russell King .long 0x00 @ unused 4489e8b5199a753a2583a8ef8360e6428304a242283Russell King .long 0x00 @ unused 4499e8b5199a753a2583a8ef8360e6428304a242283Russell King 4501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 451ad1ae2fe7fe68414ef29eab3c87b48841f8b72f2Russell KingENTRY(cpu_xscale_set_pte_ext) 452da0916539d20f257dfa46784357300e49d6bfd00Russell King xscale_set_pte_ext_prologue 4531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ 4559e8b5199a753a2583a8ef8360e6428304a242283Russell King @ Erratum 40: must set memory to write-through for user read-only pages 4561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ 4579e8b5199a753a2583a8ef8360e6428304a242283Russell King and ip, r1, #(L_PTE_MT_MASK | L_PTE_USER | L_PTE_WRITE) & ~(4 << 2) 4589e8b5199a753a2583a8ef8360e6428304a242283Russell King teq ip, #L_PTE_MT_WRITEBACK | L_PTE_USER 4599e8b5199a753a2583a8ef8360e6428304a242283Russell King 4609e8b5199a753a2583a8ef8360e6428304a242283Russell King moveq r1, #L_PTE_MT_WRITETHROUGH 4619e8b5199a753a2583a8ef8360e6428304a242283Russell King and r1, r1, #L_PTE_MT_MASK 4629e8b5199a753a2583a8ef8360e6428304a242283Russell King adr ip, cpu_xscale_mt_table 4639e8b5199a753a2583a8ef8360e6428304a242283Russell King ldr ip, [ip, r1] 4649e8b5199a753a2583a8ef8360e6428304a242283Russell King bic r2, r2, #0x0c 4659e8b5199a753a2583a8ef8360e6428304a242283Russell King orr r2, r2, ip 4661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 467da0916539d20f257dfa46784357300e49d6bfd00Russell King xscale_set_pte_ext_epilogue 4681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 4691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .ltorg 4721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 4741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __INIT 4761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __xscale_setup, #function 4781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__xscale_setup: 4791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB 4801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 4811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs 482afe4b25e7d9260d85fccb2d13c9933a987bdfc8aLennert Buytenhek mov r0, #1 << 6 @ cp6 for IOP3xx and Bulverde 4831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds orr r0, r0, #1 << 13 @ Its undefined whether this 4841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes 48522b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King 48622b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King adr r5, xscale_crval 48722b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King ldmia r5, {r5, r6} 4881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, r0, c1, c0, 0 @ get control register 4891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, r5 49022b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King orr r0, r0, r6 4911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 4921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __xscale_setup, . - __xscale_setup 4931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 4951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * R 4961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * .RVI ZFRS BLDP WCAM 4971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * ..11 1.01 .... .101 4981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 50022b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King .type xscale_crval, #object 50122b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell Kingxscale_crval: 50222b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900 5031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __INITDATA 5051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 5071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Purpose : Function pointers used to access above functions - all calls 5081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * come through these 5091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 5101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type xscale_processor_functions, #object 5121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_processor_functions) 5131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word v5t_early_abort 5144a1fd556c1f1fbd6d9d6739efec042324732b697Catalin Marinas .word pabort_noifar 5151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_proc_init 5161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_proc_fin 5171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_reset 5181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_do_idle 5191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_dcache_clean_area 5201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_switch_mm 521ad1ae2fe7fe68414ef29eab3c87b48841f8b72f2Russell King .word cpu_xscale_set_pte_ext 5221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size xscale_processor_functions, . - xscale_processor_functions 5231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .section ".rodata" 5251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_arch_name, #object 5271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_arch_name: 5281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "armv5te" 5291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_arch_name, . - cpu_arch_name 5301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_elf_name, #object 5321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_elf_name: 5331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "v5" 5341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_elf_name, . - cpu_elf_name 5351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 536197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .type cpu_80200_A0_A1_name, #object 537197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhekcpu_80200_A0_A1_name: 538197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .asciz "XScale-80200 A0/A1" 539197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .size cpu_80200_A0_A1_name, . - cpu_80200_A0_A1_name 540197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek 5411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_80200_name, #object 5421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_80200_name: 5431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-80200" 5441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_80200_name, . - cpu_80200_name 5451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 546a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .type cpu_80219_name, #object 547a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhekcpu_80219_name: 548a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .asciz "XScale-80219" 549a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .size cpu_80219_name, . - cpu_80219_name 550a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek 5511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_8032x_name, #object 5521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_8032x_name: 5531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IOP8032x Family" 5541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_8032x_name, . - cpu_8032x_name 5551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_8033x_name, #object 5571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_8033x_name: 5581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IOP8033x Family" 5591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_8033x_name, . - cpu_8033x_name 5601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_pxa250_name, #object 5621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_pxa250_name: 5631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-PXA250" 5641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_pxa250_name, . - cpu_pxa250_name 5651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_pxa210_name, #object 5671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_pxa210_name: 5681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-PXA210" 5691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_pxa210_name, . - cpu_pxa210_name 5701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_ixp42x_name, #object 5721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_ixp42x_name: 5731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IXP42x Family" 5741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_ixp42x_name, . - cpu_ixp42x_name 5751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 57645fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .type cpu_ixp43x_name, #object 57745fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushkocpu_ixp43x_name: 57845fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .asciz "XScale-IXP43x Family" 57945fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .size cpu_ixp43x_name, . - cpu_ixp43x_name 58045fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko 5811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_ixp46x_name, #object 5821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_ixp46x_name: 5831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IXP46x Family" 5841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_ixp46x_name, . - cpu_ixp46x_name 5851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_ixp2400_name, #object 5871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_ixp2400_name: 5881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IXP2400" 5891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_ixp2400_name, . - cpu_ixp2400_name 5901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_ixp2800_name, #object 5921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_ixp2800_name: 5931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IXP2800" 5941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_ixp2800_name, . - cpu_ixp2800_name 5951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_pxa255_name, #object 5971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_pxa255_name: 5981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-PXA255" 5991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_pxa255_name, . - cpu_pxa255_name 6001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_pxa270_name, #object 6021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_pxa270_name: 6031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-PXA270" 6041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_pxa270_name, . - cpu_pxa270_name 6051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 6071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 60802b7dd1244aab9267ae4078e1ad6a2fdaabeb6edBen Dooks .section ".proc.info.init", #alloc, #execinstr 6091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 610197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .type __80200_A0_A1_proc_info,#object 611197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek__80200_A0_A1_proc_info: 612197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long 0x69052000 613197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long 0xfffffffe 614197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long PMD_TYPE_SECT | \ 615197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek PMD_SECT_BUFFERABLE | \ 616197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek PMD_SECT_CACHEABLE | \ 617197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek PMD_SECT_AP_WRITE | \ 618197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek PMD_SECT_AP_READ 619197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long PMD_TYPE_SECT | \ 620197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek PMD_SECT_AP_WRITE | \ 621197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek PMD_SECT_AP_READ 622197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek b __xscale_setup 623197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long cpu_arch_name 624197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long cpu_elf_name 625197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 626197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long cpu_80200_name 627197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_processor_functions 628197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long v4wbi_tlb_fns 629197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_mc_user_fns 630197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_80200_A0_A1_cache_fns 631197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .size __80200_A0_A1_proc_info, . - __80200_A0_A1_proc_info 632197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek 6331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __80200_proc_info,#object 6341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__80200_proc_info: 6351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69052000 6361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffffff0 6371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 6381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 6391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 6401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 6411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 6428799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 6438799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 6448799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 6451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 6461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 6471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 6481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 6491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_80200_name 6501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 6511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 6521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 6531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 6541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __80200_proc_info, . - __80200_proc_info 6551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 656a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .type __80219_proc_info,#object 657a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek__80219_proc_info: 658a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long 0x69052e20 659a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long 0xffffffe0 660a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long PMD_TYPE_SECT | \ 661a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek PMD_SECT_BUFFERABLE | \ 662a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek PMD_SECT_CACHEABLE | \ 663a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek PMD_SECT_AP_WRITE | \ 664a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek PMD_SECT_AP_READ 665a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long PMD_TYPE_SECT | \ 666a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek PMD_SECT_AP_WRITE | \ 667a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek PMD_SECT_AP_READ 668a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek b __xscale_setup 669a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long cpu_arch_name 670a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long cpu_elf_name 671a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 672a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long cpu_80219_name 673a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long xscale_processor_functions 674a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long v4wbi_tlb_fns 675a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long xscale_mc_user_fns 676a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long xscale_cache_fns 677a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .size __80219_proc_info, . - __80219_proc_info 678a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek 6791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __8032x_proc_info,#object 6801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__8032x_proc_info: 6811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69052420 68236694a4c22767ee09c91ccda63810086c65c810bDan Williams .long 0xfffff7e0 6831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 6841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 6851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 6861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 6871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 6888799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 6898799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 6908799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 6911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 6921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 6931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 6941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 6951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_8032x_name 6961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 6971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 6981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 6991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 7001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __8032x_proc_info, . - __8032x_proc_info 7011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __8033x_proc_info,#object 7031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__8033x_proc_info: 7041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69054010 7057f215abc69302dc027f024fe656e4841063e8fe8Dan Williams .long 0xfffffd30 7061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 7071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 7081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 7091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 7101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 7118799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 7128799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 7138799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 7141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 7151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 7161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 7171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 7181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_8033x_name 7191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 7201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 7211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 7221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 7231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __8033x_proc_info, . - __8033x_proc_info 7241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __pxa250_proc_info,#object 7261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__pxa250_proc_info: 7271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69052100 7281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffff7f0 7291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 7301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 7311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 7321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 7331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 7348799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 7358799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 7368799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 7371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 7381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 7391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 7401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 7411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_pxa250_name 7421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 7431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 7441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 7451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 7461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __pxa250_proc_info, . - __pxa250_proc_info 7471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __pxa210_proc_info,#object 7491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__pxa210_proc_info: 7501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69052120 7511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffff3f0 7521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 7531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 7541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 7551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 7561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 7578799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 7588799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 7598799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 7601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 7611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 7621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 7631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 7641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_pxa210_name 7651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 7661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 7671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 7681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 7691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __pxa210_proc_info, . - __pxa210_proc_info 7701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __ixp2400_proc_info, #object 7721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__ixp2400_proc_info: 7731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69054190 7741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffffff0 7751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 7761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 7771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 7781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 7791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 7808799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 7818799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 7828799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 7831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 7841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 7851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 7861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 7871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_ixp2400_name 7881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 7891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 7901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 7911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 7921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __ixp2400_proc_info, . - __ixp2400_proc_info 7931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __ixp2800_proc_info, #object 7951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__ixp2800_proc_info: 7961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x690541a0 7971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffffff0 7981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 7991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 8001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 8011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 8021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 8038799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 8048799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 8058799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 8061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 8071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 8081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 8091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 8101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_ixp2800_name 8111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 8121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 8131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 8141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 8151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __ixp2800_proc_info, . - __ixp2800_proc_info 8161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __ixp42x_proc_info, #object 8181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__ixp42x_proc_info: 8191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x690541c0 8201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xffffffc0 8211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 8221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 8231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 8241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 8251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 8268799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 8278799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 8288799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 8291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 8301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 8311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 8321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 8331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_ixp42x_name 8341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 8351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 8361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 8371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 8381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __ixp42x_proc_info, . - __ixp42x_proc_info 8391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 84045fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .type __ixp43x_proc_info, #object 84145fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko__ixp43x_proc_info: 84245fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long 0x69054040 84345fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long 0xfffffff0 84445fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long PMD_TYPE_SECT | \ 84545fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko PMD_SECT_BUFFERABLE | \ 84645fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko PMD_SECT_CACHEABLE | \ 84745fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko PMD_SECT_AP_WRITE | \ 84845fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko PMD_SECT_AP_READ 84945fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long PMD_TYPE_SECT | \ 85045fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko PMD_SECT_AP_WRITE | \ 85145fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko PMD_SECT_AP_READ 85245fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko b __xscale_setup 85345fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long cpu_arch_name 85445fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long cpu_elf_name 85545fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 85645fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long cpu_ixp43x_name 85745fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long xscale_processor_functions 85845fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long v4wbi_tlb_fns 85945fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long xscale_mc_user_fns 86045fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long xscale_cache_fns 86145fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .size __ixp43x_proc_info, . - __ixp43x_proc_info 86245fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko 8631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __ixp46x_proc_info, #object 8641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__ixp46x_proc_info: 8651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69054200 8661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xffffff00 8678799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 8688799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_BUFFERABLE | \ 8698799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_CACHEABLE | \ 8708799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 8718799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 8728799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 8738799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 8748799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 8751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 8761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 8771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 8781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 8791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_ixp46x_name 8801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 8811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 8821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 8831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 8841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __ixp46x_proc_info, . - __ixp46x_proc_info 8851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __pxa255_proc_info,#object 8871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__pxa255_proc_info: 8881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69052d00 8891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffffff0 8901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 8911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 8921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 8931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 8941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 8958799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 8968799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 8978799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 8981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 8991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 9001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 9011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 9021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_pxa255_name 9031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 9041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 9051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 9061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 9071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __pxa255_proc_info, . - __pxa255_proc_info 9081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __pxa270_proc_info,#object 9101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__pxa270_proc_info: 9111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69054110 9121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffffff0 9131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 9141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 9151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 9161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 9171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 9188799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 9198799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 9208799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 9211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 9221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 9231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 924afe4b25e7d9260d85fccb2d13c9933a987bdfc8aLennert Buytenhek .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 9251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_pxa270_name 9261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 9271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 9281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 9291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 9301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __pxa270_proc_info, . - __pxa270_proc_info 9311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 932