proc-xscale.S revision ee90dabcadd053d5dd69f3a7f8161afa2c751ace
11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * linux/arch/arm/mm/proc-xscale.S 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Author: Nicolas Pitre 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Created: November 2000 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright: (C) 2000, 2001 MontaVista Software Inc. 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This program is free software; you can redistribute it and/or modify 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * it under the terms of the GNU General Public License version 2 as 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * published by the Free Software Foundation. 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * MMU functions for the Intel XScale CPUs 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2001 Aug 21: 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * some contributions by Brett Gaines <brett.w.gaines@intel.com> 161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright 2001 by Intel Corp. 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2001 Sep 08: 191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Completely revisited, many important fixes 201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Nicolas Pitre <nico@cam.org> 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/linkage.h> 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/init.h> 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/assembler.h> 26ee90dabcadd053d5dd69f3a7f8161afa2c751aceRussell King#include <asm/elf.h> 271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/pgtable.h> 280003cedfc577be9d679c16531f8720739e9637edRussell King#include <asm/pgtable-hwdef.h> 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/page.h> 301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/ptrace.h> 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include "proc-macros.S" 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This is the maximum size of an area which will be flushed. If the area 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * is larger than this, then we flush the whole cache 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAX_AREA_SIZE 32768 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the cache line size of the I and D cache 411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CACHELINESIZE 32 431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the size of the data cache 461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CACHESIZE 32768 481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Virtual address used to allocate the cache when flushed 511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This must be an address range which is _never_ used. It should 531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * apparently have a mapping in the corresponding page table for 541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * compatibility with future CPUs that _could_ require it. For instance we 551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * don't care. 561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This must be aligned on a 2*CACHESIZE boundary. The code selects one of 581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the 2 areas in alternance each time the clean_d_cache macro is used. 591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Without this the XScale core exhibits cache eviction problems and no one 601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * knows why. 611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Reminder: the vector table is located at 0xffff0000-0xffff0fff. 631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CLEAN_ADDR 0xfffe0000 651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This macro is used to wait for a CP15 write and is needed 681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * when we have to ensure that the last operation to the co-pro 691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * was completed before continuing with operation. 701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .macro cpwait, rd 721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov \rd, \rd @ wait for completion 741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds sub pc, pc, #4 @ flush instruction pipeline 751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .endm 761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .macro cpwait_ret, lr, rd 781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds sub pc, \lr, \rd, LSR #32 @ wait for completion and 801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ flush instruction pipeline 811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .endm 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This macro cleans the entire dcache using line allocate. 851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * The main loop has been unrolled to reduce loop overhead. 861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * rd and rs are two scratch registers. 871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .macro clean_d_cache, rd, rs 891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ldr \rs, =clean_addr 901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ldr \rd, [\rs] 911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds eor \rd, \rd, #CACHESIZE 921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds str \rd, [\rs] 931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rs, \rd, #CACHESIZE 941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rd, \rd, #CACHELINESIZE 961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rd, \rd, #CACHELINESIZE 981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rd, \rd, #CACHELINESIZE 1001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 1011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rd, \rd, #CACHELINESIZE 1021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds teq \rd, \rs 1031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bne 1b 1041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .endm 1051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .data 1071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsclean_addr: .word CLEAN_ADDR 1081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .text 1101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_proc_init() 1131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Nothing too exciting at the moment 1151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_proc_init) 1171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 1181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_proc_fin() 1211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_proc_fin) 1231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds str lr, [sp, #-4]! 1241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE 1251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds msr cpsr_c, r0 1261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bl xscale_flush_kern_cache_all @ clean caches 1271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, r0, c1, c0, 0 @ ctrl register 1281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #0x1800 @ ...IZ........... 1291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #0x0006 @ .............CA. 1301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c1, c0, 0 @ disable caches 1311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ldr pc, [sp], #4 1321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_reset(loc) 1351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Perform a soft reset of the system. Put the CPU into the 1371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * same state as it would be if it had been reset, and branch 1381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * to what would be the reset vector. 1391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * loc: location to jump to for soft reset 1412dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre * 1422dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre * Beware PXA270 erratum E7. 1431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 1451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_reset) 1461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE 1471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds msr cpsr_c, r1 @ reset CPSR 1482dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB 1492dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB 1501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, r1, c1, c0, 0 @ ctrl register 1511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r1, r1, #0x0086 @ ........B....CA. 1521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r1, r1, #0x3900 @ ..VIZ..S........ 1532dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre sub pc, pc, #4 @ flush pipeline 1542dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre @ *** cache line aligned *** 1551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r1, c1, c0, 0 @ ctrl register 1561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r1, r1, #0x0001 @ ...............M 1572dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB 1581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r1, c1, c0, 0 @ ctrl register 1591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ CAUTION: MMU turned off from this point. We count on the pipeline 1601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ already containing those two last instructions to survive. 1611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 1621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, r0 1631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_do_idle() 1661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Cause the processor to idle 1681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * For now we do nothing but go to idle mode for every case 1701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * XScale supports clock switching, but using idle mode support 1721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * allows external hardware to react to system state changes. 1731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 1751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_do_idle) 1771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #1 1781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE 1791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 1801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* ================================= CACHE ================================ */ 1821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * flush_user_cache_all() 1851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Invalidate all cache entries in a particular address 1871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * space. 1881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_flush_user_cache_all) 1901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* FALLTHROUGH */ 1911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * flush_kern_cache_all() 1941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Clean and invalidate the entire cache. 1961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_flush_kern_cache_all) 1981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r2, #VM_EXEC 1991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov ip, #0 2001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__flush_whole_cache: 2011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds clean_d_cache r0, r1 2021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r2, #VM_EXEC 2031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB 2041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 2051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 2061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * flush_user_cache_range(start, end, vm_flags) 2091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Invalidate a range of cache entries in the specified 2111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * address space. 2121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - start address (may not be aligned) 2141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - end address (exclusive, may not be aligned) 2151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - vma - vma_area_struct describing address space 2161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 2181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_flush_user_cache_range) 2191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov ip, #0 2201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds sub r3, r1, r0 @ calculate total size 2211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r3, #MAX_AREA_SIZE 2221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bhs __flush_whole_cache 2231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: tst r2, #VM_EXEC 2251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line 2261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line 2271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line 2281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 2291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 2301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 2311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r2, #VM_EXEC 2321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB 2331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 2341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 2351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * coherent_kern_range(start, end) 2381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Ensure coherency between the Icache and the Dcache in the 2401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * region described by start. If you have non-snooping 2411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Harvard caches, you need to implement this function. 2421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 2441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 2451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Note: single I-cache line invalidation isn't used here since 2471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * it also trashes the mini I-cache used by JTAG debuggers. 2481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_coherent_kern_range) 2508a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre bic r0, r0, #CACHELINESIZE - 1 2518a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2528a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre add r0, r0, #CACHELINESIZE 2538a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre cmp r0, r1 2548a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre blo 1b 2558a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mov r0, #0 2568a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB 2578a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 2588a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mov pc, lr 2591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * coherent_user_range(start, end) 2621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Ensure coherency between the Icache and the Dcache in the 2641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * region described by start. If you have non-snooping 2651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Harvard caches, you need to implement this function. 2661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 2681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 2691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_coherent_user_range) 2711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #CACHELINESIZE - 1 2721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2738a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry 2741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 2751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 2761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 2771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #0 2788a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB 2791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 2801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 2811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * flush_kern_dcache_page(void *page) 2841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Ensure no D cache aliasing occurs, either with itself or 2861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the I cache 2871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - addr - page aligned address 2891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_flush_kern_dcache_page) 2911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r1, r0, #PAGE_SZ 2921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 2941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 2951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 2961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 2971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #0 2981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB 2991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 3001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 3011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 3031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * dma_inv_range(start, end) 3041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Invalidate (discard) the specified virtual address range. 3061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * May not write back any entries. If 'start' or 'end' 3071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * are not cache line aligned, those lines must be written 3081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * back. 3091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 3111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 3121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_dma_inv_range) 3141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r0, #CACHELINESIZE - 1 3151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #CACHELINESIZE - 1 3161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 3171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r1, #CACHELINESIZE - 1 3181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 3191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 3201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 3211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 3221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 3231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 3241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 3251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 3271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * dma_clean_range(start, end) 3281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Clean the specified virtual address range. 3301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 3321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 3331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_dma_clean_range) 3351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #CACHELINESIZE - 1 3361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 3381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 3391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 3401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 3411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 3421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 3441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * dma_flush_range(start, end) 3451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Clean and invalidate the specified virtual address range. 3471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 3491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 3501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_dma_flush_range) 3521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #CACHELINESIZE - 1 3531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 3551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 3561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 3571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 3581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 3591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 3601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_cache_fns) 3621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_flush_kern_cache_all 3631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_flush_user_cache_all 3641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_flush_user_cache_range 3651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_coherent_kern_range 3661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_coherent_user_range 3671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_flush_kern_dcache_page 3681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_dma_inv_range 3691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_dma_clean_range 3701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_dma_flush_range 3711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 372197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek/* 373197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't 374197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * clear the dirty bits, which means that if we invalidate a dirty line, 375197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * the dirty data can still be written back to external memory later on. 376197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * 377197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * The recommended workaround is to always do a clean D-cache line before 378197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * doing an invalidate D-cache line, so on the affected processors, 379197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * dma_inv_range() is implemented as dma_flush_range(). 380197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * 381197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * See erratum #25 of "Intel 80200 Processor Specification Update", 382197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * revision January 22, 2003, available at: 383197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * http://www.intel.com/design/iio/specupdt/273415.htm 384197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek */ 385197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert BuytenhekENTRY(xscale_80200_A0_A1_cache_fns) 386197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_flush_kern_cache_all 387197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_flush_user_cache_all 388197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_flush_user_cache_range 389197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_coherent_kern_range 390197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_coherent_user_range 391197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_flush_kern_dcache_page 392197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_dma_flush_range 393197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_dma_clean_range 394197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_dma_flush_range 395197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek 3961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_dcache_clean_area) 3971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 3991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds subs r1, r1, #CACHELINESIZE 4001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bhi 1b 4011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 4021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* =============================== PageTable ============================== */ 4041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PTE_CACHE_WRITE_ALLOCATE 0 4061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 4081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_switch_mm(pgd) 4091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Set the translation base pointer to be as described by pgd. 4111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * pgd: new page tables 4131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 4151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_switch_mm) 4161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds clean_d_cache r1, r2 4171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB 4181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 4191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 4201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 4211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cpwait_ret lr, ip 4221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 4241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_set_pte(ptep, pte) 4251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Set a PTE and flush it out 4271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Errata 40: must set memory to write-through for user read-only pages. 4291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 4311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_set_pte) 4321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds str r1, [r0], #-2048 @ linux version 4331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r2, r1, #0xff0 4351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds orr r2, r2, #PTE_TYPE_EXT @ extended page 4361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 4381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r3, #L_PTE_USER @ User? 4401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w 4411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty? 4431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w 4441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ combined with user -> user r/w 4451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ 4471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ Handle the X bit. We want to set this bit for the minicache 4481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ (U = E = B = W = 0, C = 1) or when write allocate is enabled, 4491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ and we have a writeable, cacheable region. If we ignore the 4501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ U and E bits, we can allow user space to use the minicache as 4511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ well. 4521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ 4531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ X = (C & ~W & ~B) | (C & W & B & write_allocate) 4541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ 4551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds eor ip, r1, #L_PTE_CACHEABLE 4561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE 4571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#if PTE_CACHE_WRITE_ALLOCATE 4581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds eorne ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE 4591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tstne ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE 4601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 4611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds orreq r2, r2, #PTE_EXT_TEX(1) 4621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ 4641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ Erratum 40: The B bit must be cleared for a user read-only 4651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ cacheable page. 4661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ 4671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ B = B & ~(U & C & ~W) 4681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ 4691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds and ip, r1, #L_PTE_USER | L_PTE_WRITE | L_PTE_CACHEABLE 4701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds teq ip, #L_PTE_USER | L_PTE_CACHEABLE 4711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds biceq r2, r2, #PTE_BUFFERABLE 4721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? 4741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds movne r2, #0 @ no -> fault 4751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds str r2, [r0] @ hardware version 4771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov ip, #0 4781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line 4791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 4801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 4811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .ltorg 4841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 4861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __INIT 4881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __xscale_setup, #function 4901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__xscale_setup: 4911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB 4921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 4931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs 4941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CONFIG_IWMMXT 4951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #0 @ initially disallow access to CP0/CP1 4961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#else 4971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #1 @ Allow access to CP0 4981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 4991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde 5001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds orr r0, r0, #1 << 13 @ Its undefined whether this 5011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes 50222b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King 50322b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King adr r5, xscale_crval 50422b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King ldmia r5, {r5, r6} 5051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, r0, c1, c0, 0 @ get control register 5061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, r5 50722b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King orr r0, r0, r6 5081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 5091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __xscale_setup, . - __xscale_setup 5101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 5121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * R 5131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * .RVI ZFRS BLDP WCAM 5141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * ..11 1.01 .... .101 5151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 51722b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King .type xscale_crval, #object 51822b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell Kingxscale_crval: 51922b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900 5201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __INITDATA 5221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 5241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Purpose : Function pointers used to access above functions - all calls 5251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * come through these 5261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 5271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type xscale_processor_functions, #object 5291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_processor_functions) 5301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word v5t_early_abort 5311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_proc_init 5321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_proc_fin 5331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_reset 5341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_do_idle 5351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_dcache_clean_area 5361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_switch_mm 5371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_set_pte 5381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size xscale_processor_functions, . - xscale_processor_functions 5391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .section ".rodata" 5411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_arch_name, #object 5431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_arch_name: 5441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "armv5te" 5451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_arch_name, . - cpu_arch_name 5461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_elf_name, #object 5481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_elf_name: 5491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "v5" 5501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_elf_name, . - cpu_elf_name 5511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 552197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .type cpu_80200_A0_A1_name, #object 553197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhekcpu_80200_A0_A1_name: 554197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .asciz "XScale-80200 A0/A1" 555197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .size cpu_80200_A0_A1_name, . - cpu_80200_A0_A1_name 556197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek 5571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_80200_name, #object 5581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_80200_name: 5591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-80200" 5601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_80200_name, . - cpu_80200_name 5611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 562a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .type cpu_80219_name, #object 563a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhekcpu_80219_name: 564a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .asciz "XScale-80219" 565a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .size cpu_80219_name, . - cpu_80219_name 566a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek 5671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_8032x_name, #object 5681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_8032x_name: 5691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IOP8032x Family" 5701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_8032x_name, . - cpu_8032x_name 5711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_8033x_name, #object 5731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_8033x_name: 5741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IOP8033x Family" 5751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_8033x_name, . - cpu_8033x_name 5761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_pxa250_name, #object 5781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_pxa250_name: 5791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-PXA250" 5801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_pxa250_name, . - cpu_pxa250_name 5811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_pxa210_name, #object 5831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_pxa210_name: 5841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-PXA210" 5851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_pxa210_name, . - cpu_pxa210_name 5861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_ixp42x_name, #object 5881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_ixp42x_name: 5891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IXP42x Family" 5901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_ixp42x_name, . - cpu_ixp42x_name 5911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_ixp46x_name, #object 5931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_ixp46x_name: 5941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IXP46x Family" 5951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_ixp46x_name, . - cpu_ixp46x_name 5961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_ixp2400_name, #object 5981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_ixp2400_name: 5991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IXP2400" 6001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_ixp2400_name, . - cpu_ixp2400_name 6011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_ixp2800_name, #object 6031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_ixp2800_name: 6041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IXP2800" 6051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_ixp2800_name, . - cpu_ixp2800_name 6061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_pxa255_name, #object 6081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_pxa255_name: 6091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-PXA255" 6101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_pxa255_name, . - cpu_pxa255_name 6111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_pxa270_name, #object 6131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_pxa270_name: 6141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-PXA270" 6151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_pxa270_name, . - cpu_pxa270_name 6161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 6181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 61902b7dd1244aab9267ae4078e1ad6a2fdaabeb6edBen Dooks .section ".proc.info.init", #alloc, #execinstr 6201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 621197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .type __80200_A0_A1_proc_info,#object 622197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek__80200_A0_A1_proc_info: 623197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long 0x69052000 624197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long 0xfffffffe 625197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long PMD_TYPE_SECT | \ 626197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek PMD_SECT_BUFFERABLE | \ 627197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek PMD_SECT_CACHEABLE | \ 628197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek PMD_SECT_AP_WRITE | \ 629197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek PMD_SECT_AP_READ 630197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long PMD_TYPE_SECT | \ 631197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek PMD_SECT_AP_WRITE | \ 632197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek PMD_SECT_AP_READ 633197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek b __xscale_setup 634197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long cpu_arch_name 635197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long cpu_elf_name 636197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 637197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long cpu_80200_name 638197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_processor_functions 639197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long v4wbi_tlb_fns 640197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_mc_user_fns 641197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_80200_A0_A1_cache_fns 642197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .size __80200_A0_A1_proc_info, . - __80200_A0_A1_proc_info 643197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek 6441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __80200_proc_info,#object 6451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__80200_proc_info: 6461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69052000 6471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffffff0 6481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 6491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 6501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 6511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 6521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 6538799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 6548799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 6558799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 6561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 6571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 6581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 6591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 6601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_80200_name 6611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 6621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 6631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 6641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 6651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __80200_proc_info, . - __80200_proc_info 6661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 667a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .type __80219_proc_info,#object 668a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek__80219_proc_info: 669a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long 0x69052e20 670a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long 0xffffffe0 671a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long PMD_TYPE_SECT | \ 672a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek PMD_SECT_BUFFERABLE | \ 673a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek PMD_SECT_CACHEABLE | \ 674a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek PMD_SECT_AP_WRITE | \ 675a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek PMD_SECT_AP_READ 676a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long PMD_TYPE_SECT | \ 677a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek PMD_SECT_AP_WRITE | \ 678a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek PMD_SECT_AP_READ 679a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek b __xscale_setup 680a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long cpu_arch_name 681a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long cpu_elf_name 682a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 683a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long cpu_80219_name 684a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long xscale_processor_functions 685a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long v4wbi_tlb_fns 686a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long xscale_mc_user_fns 687a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long xscale_cache_fns 688a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .size __80219_proc_info, . - __80219_proc_info 689a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek 6901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __8032x_proc_info,#object 6911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__8032x_proc_info: 6921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69052420 69336694a4c22767ee09c91ccda63810086c65c810bDan Williams .long 0xfffff7e0 6941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 6951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 6961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 6971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 6981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 6998799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 7008799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 7018799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 7021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 7031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 7041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 7051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 7061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_8032x_name 7071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 7081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 7091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 7101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 7111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __8032x_proc_info, . - __8032x_proc_info 7121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __8033x_proc_info,#object 7141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__8033x_proc_info: 7151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69054010 7161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xffffff30 7171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 7181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 7191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 7201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 7211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 7228799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 7238799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 7248799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 7251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 7261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 7271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 7281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 7291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_8033x_name 7301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 7311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 7321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 7331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 7341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __8033x_proc_info, . - __8033x_proc_info 7351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __pxa250_proc_info,#object 7371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__pxa250_proc_info: 7381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69052100 7391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffff7f0 7401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 7411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 7421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 7431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 7441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 7458799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 7468799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 7478799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 7481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 7491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 7501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 7511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 7521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_pxa250_name 7531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 7541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 7551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 7561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 7571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __pxa250_proc_info, . - __pxa250_proc_info 7581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __pxa210_proc_info,#object 7601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__pxa210_proc_info: 7611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69052120 7621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffff3f0 7631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 7641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 7651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 7661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 7671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 7688799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 7698799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 7708799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 7711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 7721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 7731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 7741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 7751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_pxa210_name 7761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 7771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 7781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 7791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 7801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __pxa210_proc_info, . - __pxa210_proc_info 7811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __ixp2400_proc_info, #object 7831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__ixp2400_proc_info: 7841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69054190 7851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffffff0 7861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 7871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 7881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 7891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 7901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 7918799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 7928799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 7938799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 7941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 7951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 7961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 7971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 7981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_ixp2400_name 7991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 8001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 8011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 8021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 8031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __ixp2400_proc_info, . - __ixp2400_proc_info 8041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __ixp2800_proc_info, #object 8061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__ixp2800_proc_info: 8071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x690541a0 8081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffffff0 8091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 8101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 8111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 8121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 8131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 8148799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 8158799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 8168799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 8171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 8181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 8191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 8201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 8211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_ixp2800_name 8221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 8231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 8241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 8251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 8261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __ixp2800_proc_info, . - __ixp2800_proc_info 8271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __ixp42x_proc_info, #object 8291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__ixp42x_proc_info: 8301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x690541c0 8311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xffffffc0 8321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 8331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 8341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 8351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 8361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 8378799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 8388799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 8398799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 8401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 8411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 8421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 8431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 8441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_ixp42x_name 8451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 8461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 8471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 8481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 8491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __ixp42x_proc_info, . - __ixp42x_proc_info 8501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __ixp46x_proc_info, #object 8521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__ixp46x_proc_info: 8531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69054200 8541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xffffff00 8558799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 8568799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_BUFFERABLE | \ 8578799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_CACHEABLE | \ 8588799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 8598799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 8608799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 8618799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 8628799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 8631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 8641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 8651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 8661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 8671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_ixp46x_name 8681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 8691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 8701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 8711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 8721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __ixp46x_proc_info, . - __ixp46x_proc_info 8731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __pxa255_proc_info,#object 8751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__pxa255_proc_info: 8761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69052d00 8771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffffff0 8781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 8791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 8801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 8811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 8821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 8838799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 8848799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 8858799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 8861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 8871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 8881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 8891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 8901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_pxa255_name 8911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 8921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 8931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 8941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 8951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __pxa255_proc_info, . - __pxa255_proc_info 8961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __pxa270_proc_info,#object 8981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__pxa270_proc_info: 8991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69054110 9001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffffff0 9011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 9021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 9031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 9041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 9051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 9068799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 9078799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 9088799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 9091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 9101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 9111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 9128f7f9435e6df0985c877d10259393bdfaac3655fPaul Gortmaker .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_IWMMXT 9131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_pxa270_name 9141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 9151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 9161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 9171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 9181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __pxa270_proc_info, . - __pxa270_proc_info 9191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 920