proc-xscale.S revision f6b0fa02e8b0708d17d631afce456524eadf87ff
11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * linux/arch/arm/mm/proc-xscale.S 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Author: Nicolas Pitre 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Created: November 2000 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright: (C) 2000, 2001 MontaVista Software Inc. 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This program is free software; you can redistribute it and/or modify 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * it under the terms of the GNU General Public License version 2 as 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * published by the Free Software Foundation. 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * MMU functions for the Intel XScale CPUs 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2001 Aug 21: 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * some contributions by Brett Gaines <brett.w.gaines@intel.com> 161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright 2001 by Intel Corp. 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2001 Sep 08: 191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Completely revisited, many important fixes 202f82af08fcc7dc01a7e98a49a5995a77e32a2925Nicolas Pitre * Nicolas Pitre <nico@fluxnic.net> 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/linkage.h> 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/init.h> 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/assembler.h> 265ec9407dd1196daaf12b427b351e2cd62d2a16a7Russell King#include <asm/hwcap.h> 271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/pgtable.h> 280003cedfc577be9d679c16531f8720739e9637edRussell King#include <asm/pgtable-hwdef.h> 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/page.h> 301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/ptrace.h> 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include "proc-macros.S" 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This is the maximum size of an area which will be flushed. If the area 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * is larger than this, then we flush the whole cache 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAX_AREA_SIZE 32768 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the cache line size of the I and D cache 411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CACHELINESIZE 32 431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the size of the data cache 461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CACHESIZE 32768 481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Virtual address used to allocate the cache when flushed 511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This must be an address range which is _never_ used. It should 531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * apparently have a mapping in the corresponding page table for 541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * compatibility with future CPUs that _could_ require it. For instance we 551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * don't care. 561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This must be aligned on a 2*CACHESIZE boundary. The code selects one of 581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the 2 areas in alternance each time the clean_d_cache macro is used. 591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Without this the XScale core exhibits cache eviction problems and no one 601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * knows why. 611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Reminder: the vector table is located at 0xffff0000-0xffff0fff. 631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CLEAN_ADDR 0xfffe0000 651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This macro is used to wait for a CP15 write and is needed 681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * when we have to ensure that the last operation to the co-pro 691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * was completed before continuing with operation. 701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .macro cpwait, rd 721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov \rd, \rd @ wait for completion 741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds sub pc, pc, #4 @ flush instruction pipeline 751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .endm 761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .macro cpwait_ret, lr, rd 781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds sub pc, \lr, \rd, LSR #32 @ wait for completion and 801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ flush instruction pipeline 811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .endm 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This macro cleans the entire dcache using line allocate. 851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * The main loop has been unrolled to reduce loop overhead. 861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * rd and rs are two scratch registers. 871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .macro clean_d_cache, rd, rs 891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ldr \rs, =clean_addr 901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ldr \rd, [\rs] 911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds eor \rd, \rd, #CACHESIZE 921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds str \rd, [\rs] 931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rs, \rd, #CACHESIZE 941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rd, \rd, #CACHELINESIZE 961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rd, \rd, #CACHELINESIZE 981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rd, \rd, #CACHELINESIZE 1001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 1011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add \rd, \rd, #CACHELINESIZE 1021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds teq \rd, \rs 1031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bne 1b 1041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .endm 1051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .data 1071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsclean_addr: .word CLEAN_ADDR 1081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .text 1101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_proc_init() 1131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Nothing too exciting at the moment 1151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_proc_init) 117391c569daa6e4e999592966e29c146dfc4de9a9cArnaud Patard @ enable write buffer coalescing. Some bootloader disable it 118391c569daa6e4e999592966e29c146dfc4de9a9cArnaud Patard mrc p15, 0, r1, c1, c0, 1 119391c569daa6e4e999592966e29c146dfc4de9a9cArnaud Patard bic r1, r1, #1 120391c569daa6e4e999592966e29c146dfc4de9a9cArnaud Patard mcr p15, 0, r1, c1, c0, 1 1211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 1221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_proc_fin() 1251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_proc_fin) 1271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, r0, c1, c0, 0 @ ctrl register 1281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #0x1800 @ ...IZ........... 1291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #0x0006 @ .............CA. 1301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c1, c0, 0 @ disable caches 1319ca03a21e320a6bf44559323527aba704bcc8772Russell King mov pc, lr 1321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_reset(loc) 1351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Perform a soft reset of the system. Put the CPU into the 1371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * same state as it would be if it had been reset, and branch 1381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * to what would be the reset vector. 1391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * loc: location to jump to for soft reset 1412dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre * 1422dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre * Beware PXA270 erratum E7. 1431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 1451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_reset) 1461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE 1471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds msr cpsr_c, r1 @ reset CPSR 1482dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB 1492dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB 1501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, r1, c1, c0, 0 @ ctrl register 1511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r1, r1, #0x0086 @ ........B....CA. 1521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r1, r1, #0x3900 @ ..VIZ..S........ 1532dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre sub pc, pc, #4 @ flush pipeline 1542dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre @ *** cache line aligned *** 1551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r1, c1, c0, 0 @ ctrl register 1561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r1, r1, #0x0001 @ ...............M 1572dc7667b9d0674db6572723356fe3857031101a4Nicolas Pitre mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB 1581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r1, c1, c0, 0 @ ctrl register 1591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ CAUTION: MMU turned off from this point. We count on the pipeline 1601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ already containing those two last instructions to survive. 1611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 1621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, r0 1631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_do_idle() 1661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Cause the processor to idle 1681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * For now we do nothing but go to idle mode for every case 1701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * XScale supports clock switching, but using idle mode support 1721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * allows external hardware to react to system state changes. 1731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 1751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_do_idle) 1771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #1 1781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE 1791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 1801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* ================================= CACHE ================================ */ 1821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 184c8c90860cd3592fac83a349f84a20360a6498727Mika Westerberg * flush_icache_all() 185c8c90860cd3592fac83a349f84a20360a6498727Mika Westerberg * 186c8c90860cd3592fac83a349f84a20360a6498727Mika Westerberg * Unconditionally clean and invalidate the entire icache. 187c8c90860cd3592fac83a349f84a20360a6498727Mika Westerberg */ 188c8c90860cd3592fac83a349f84a20360a6498727Mika WesterbergENTRY(xscale_flush_icache_all) 189c8c90860cd3592fac83a349f84a20360a6498727Mika Westerberg mov r0, #0 190c8c90860cd3592fac83a349f84a20360a6498727Mika Westerberg mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 191c8c90860cd3592fac83a349f84a20360a6498727Mika Westerberg mov pc, lr 192c8c90860cd3592fac83a349f84a20360a6498727Mika WesterbergENDPROC(xscale_flush_icache_all) 193c8c90860cd3592fac83a349f84a20360a6498727Mika Westerberg 194c8c90860cd3592fac83a349f84a20360a6498727Mika Westerberg/* 1951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * flush_user_cache_all() 1961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Invalidate all cache entries in a particular address 1981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * space. 1991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_flush_user_cache_all) 2011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* FALLTHROUGH */ 2021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * flush_kern_cache_all() 2051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Clean and invalidate the entire cache. 2071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_flush_kern_cache_all) 2091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r2, #VM_EXEC 2101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov ip, #0 2111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__flush_whole_cache: 2121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds clean_d_cache r0, r1 2131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r2, #VM_EXEC 2141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB 2151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 2161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 2171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * flush_user_cache_range(start, end, vm_flags) 2201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Invalidate a range of cache entries in the specified 2221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * address space. 2231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - start address (may not be aligned) 2251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - end address (exclusive, may not be aligned) 2261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - vma - vma_area_struct describing address space 2271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 2291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_flush_user_cache_range) 2301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov ip, #0 2311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds sub r3, r1, r0 @ calculate total size 2321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r3, #MAX_AREA_SIZE 2331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bhs __flush_whole_cache 2341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: tst r2, #VM_EXEC 2361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line 2371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line 2381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line 2391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 2401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 2411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 2421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r2, #VM_EXEC 2431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB 2441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 2451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 2461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * coherent_kern_range(start, end) 2491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Ensure coherency between the Icache and the Dcache in the 2511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * region described by start. If you have non-snooping 2521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Harvard caches, you need to implement this function. 2531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 2551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 2561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Note: single I-cache line invalidation isn't used here since 2581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * it also trashes the mini I-cache used by JTAG debuggers. 2591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_coherent_kern_range) 2618a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre bic r0, r0, #CACHELINESIZE - 1 2628a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2638a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre add r0, r0, #CACHELINESIZE 2648a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre cmp r0, r1 2658a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre blo 1b 2668a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mov r0, #0 2678a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB 2688a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 2698a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mov pc, lr 2701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * coherent_user_range(start, end) 2731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Ensure coherency between the Icache and the Dcache in the 2751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * region described by start. If you have non-snooping 2761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Harvard caches, you need to implement this function. 2771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 2791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 2801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_coherent_user_range) 2821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #CACHELINESIZE - 1 2831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2848a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry 2851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 2861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 2871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 2881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #0 2898a052e0bc25ff52f17b3dff150846ca9eb969162Nicolas Pitre mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB 2901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 2911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 2921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2942c9b9c8490b60428fa2d1c64042f7c7caed93940Russell King * flush_kern_dcache_area(void *addr, size_t size) 2951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Ensure no D cache aliasing occurs, either with itself or 2971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the I cache 2981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2992c9b9c8490b60428fa2d1c64042f7c7caed93940Russell King * - addr - kernel address 3002c9b9c8490b60428fa2d1c64042f7c7caed93940Russell King * - size - region size 3011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3022c9b9c8490b60428fa2d1c64042f7c7caed93940Russell KingENTRY(xscale_flush_kern_dcache_area) 3032c9b9c8490b60428fa2d1c64042f7c7caed93940Russell King add r1, r0, r1 3041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 3061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 3071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 3081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 3091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov r0, #0 3101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB 3111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 3121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 3131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 3151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * dma_inv_range(start, end) 3161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Invalidate (discard) the specified virtual address range. 3181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * May not write back any entries. If 'start' or 'end' 3191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * are not cache line aligned, those lines must be written 3201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * back. 3211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 3231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 3241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 325702b94bff3c50542a6e4ab9a4f4cef093262fe65Russell Kingxscale_dma_inv_range: 3261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r0, #CACHELINESIZE - 1 3271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #CACHELINESIZE - 1 3281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 3291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tst r1, #CACHELINESIZE - 1 3301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 3311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 3321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 3331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 3341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 3351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 3361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 3371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 3391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * dma_clean_range(start, end) 3401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Clean the specified virtual address range. 3421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 3441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 3451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 346702b94bff3c50542a6e4ab9a4f4cef093262fe65Russell Kingxscale_dma_clean_range: 3471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #CACHELINESIZE - 1 3481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 3501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 3511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 3521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 3531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 3541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 3561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * dma_flush_range(start, end) 3571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Clean and invalidate the specified virtual address range. 3591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - start - virtual start address 3611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - end - virtual end address 3621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 3631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_dma_flush_range) 3641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, #CACHELINESIZE - 1 3651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 3671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 3681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cmp r0, r1 3691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blo 1b 3701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 3711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 3721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 373a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King/* 374a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * dma_map_area(start, size, dir) 375a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * - start - kernel virtual start address 376a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * - size - size of region 377a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * - dir - DMA direction 378a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King */ 379a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell KingENTRY(xscale_dma_map_area) 380a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King add r1, r1, r0 381a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King cmp r2, #DMA_TO_DEVICE 382a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King beq xscale_dma_clean_range 383a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King bcs xscale_dma_inv_range 384a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King b xscale_dma_flush_range 385a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell KingENDPROC(xscale_dma_map_area) 386a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King 387a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King/* 388a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * dma_map_area(start, size, dir) 389a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * - start - kernel virtual start address 390a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * - size - size of region 391a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * - dir - DMA direction 392a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King */ 393a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell KingENTRY(xscale_dma_a0_map_area) 394a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King add r1, r1, r0 395a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King teq r2, #DMA_TO_DEVICE 396a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King beq xscale_dma_clean_range 397a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King b xscale_dma_flush_range 398a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell KingENDPROC(xscsale_dma_a0_map_area) 399a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King 400a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King/* 401a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * dma_unmap_area(start, size, dir) 402a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * - start - kernel virtual start address 403a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * - size - size of region 404a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King * - dir - DMA direction 405a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King */ 406a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell KingENTRY(xscale_dma_unmap_area) 407a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King mov pc, lr 408a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell KingENDPROC(xscale_dma_unmap_area) 409a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King 4101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_cache_fns) 411c8c90860cd3592fac83a349f84a20360a6498727Mika Westerberg .long xscale_flush_icache_all 4121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_flush_kern_cache_all 4131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_flush_user_cache_all 4141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_flush_user_cache_range 4151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_coherent_kern_range 4161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_coherent_user_range 4172c9b9c8490b60428fa2d1c64042f7c7caed93940Russell King .long xscale_flush_kern_dcache_area 418a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King .long xscale_dma_map_area 419a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King .long xscale_dma_unmap_area 4201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_dma_flush_range 4211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 422197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek/* 423197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't 424197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * clear the dirty bits, which means that if we invalidate a dirty line, 425197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * the dirty data can still be written back to external memory later on. 426197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * 427197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * The recommended workaround is to always do a clean D-cache line before 428197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * doing an invalidate D-cache line, so on the affected processors, 429197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * dma_inv_range() is implemented as dma_flush_range(). 430197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * 431197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * See erratum #25 of "Intel 80200 Processor Specification Update", 432197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * revision January 22, 2003, available at: 433197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek * http://www.intel.com/design/iio/specupdt/273415.htm 434197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek */ 435197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert BuytenhekENTRY(xscale_80200_A0_A1_cache_fns) 436197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_flush_kern_cache_all 437197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_flush_user_cache_all 438197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_flush_user_cache_range 439197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_coherent_kern_range 440197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_coherent_user_range 4412c9b9c8490b60428fa2d1c64042f7c7caed93940Russell King .long xscale_flush_kern_dcache_area 442a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King .long xscale_dma_a0_map_area 443a9c9147eb9b1dba0ce567a41897c7773b4d1b0bcRussell King .long xscale_dma_unmap_area 444197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_dma_flush_range 445197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek 4461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_dcache_clean_area) 4471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 4481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds add r0, r0, #CACHELINESIZE 4491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds subs r1, r1, #CACHELINESIZE 4501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bhi 1b 4511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 4521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* =============================== PageTable ============================== */ 4541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 4561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cpu_xscale_switch_mm(pgd) 4571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Set the translation base pointer to be as described by pgd. 4591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * pgd: new page tables 4611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 4631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(cpu_xscale_switch_mm) 4641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds clean_d_cache r1, r2 4651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB 4661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 4671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 4681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 4691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cpwait_ret lr, ip 4701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 472ad1ae2fe7fe68414ef29eab3c87b48841f8b72f2Russell King * cpu_xscale_set_pte_ext(ptep, pte, ext) 4731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Set a PTE and flush it out 4751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 4761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Errata 40: must set memory to write-through for user read-only pages. 4771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 4789e8b5199a753a2583a8ef8360e6428304a242283Russell Kingcpu_xscale_mt_table: 4799e8b5199a753a2583a8ef8360e6428304a242283Russell King .long 0x00 @ L_PTE_MT_UNCACHED 4809e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_BUFFERABLE @ L_PTE_MT_BUFFERABLE 4819e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH 4829e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK 48340df2d1d8538865341a4cb9d4b7a375296517ad2Russell King .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED 484639b0ae7f5bcd645862a9c3ea2d4321475c71d7aRussell King .long 0x00 @ unused 4859e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_EXT_TEX(1) | PTE_CACHEABLE @ L_PTE_MT_MINICACHE 4869e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC 487639b0ae7f5bcd645862a9c3ea2d4321475c71d7aRussell King .long 0x00 @ unused 4889e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_BUFFERABLE @ L_PTE_MT_DEV_WC 4899e8b5199a753a2583a8ef8360e6428304a242283Russell King .long 0x00 @ unused 4909e8b5199a753a2583a8ef8360e6428304a242283Russell King .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED 4919e8b5199a753a2583a8ef8360e6428304a242283Russell King .long 0x00 @ L_PTE_MT_DEV_NONSHARED 492db5b7169474882fabbd811a4cf5c1bae3157e677Russell King .long 0x00 @ unused 4939e8b5199a753a2583a8ef8360e6428304a242283Russell King .long 0x00 @ unused 4949e8b5199a753a2583a8ef8360e6428304a242283Russell King .long 0x00 @ unused 4959e8b5199a753a2583a8ef8360e6428304a242283Russell King 4961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5 497ad1ae2fe7fe68414ef29eab3c87b48841f8b72f2Russell KingENTRY(cpu_xscale_set_pte_ext) 498da0916539d20f257dfa46784357300e49d6bfd00Russell King xscale_set_pte_ext_prologue 4991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ 5019e8b5199a753a2583a8ef8360e6428304a242283Russell King @ Erratum 40: must set memory to write-through for user read-only pages 5021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds @ 50336bb94ba36f332de767cfaa3af6a5136435a3a9cRussell King and ip, r1, #(L_PTE_MT_MASK | L_PTE_USER | L_PTE_RDONLY) & ~(4 << 2) 50436bb94ba36f332de767cfaa3af6a5136435a3a9cRussell King teq ip, #L_PTE_MT_WRITEBACK | L_PTE_USER | L_PTE_RDONLY 5059e8b5199a753a2583a8ef8360e6428304a242283Russell King 5069e8b5199a753a2583a8ef8360e6428304a242283Russell King moveq r1, #L_PTE_MT_WRITETHROUGH 5079e8b5199a753a2583a8ef8360e6428304a242283Russell King and r1, r1, #L_PTE_MT_MASK 5089e8b5199a753a2583a8ef8360e6428304a242283Russell King adr ip, cpu_xscale_mt_table 5099e8b5199a753a2583a8ef8360e6428304a242283Russell King ldr ip, [ip, r1] 5109e8b5199a753a2583a8ef8360e6428304a242283Russell King bic r2, r2, #0x0c 5119e8b5199a753a2583a8ef8360e6428304a242283Russell King orr r2, r2, ip 5121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 513da0916539d20f257dfa46784357300e49d6bfd00Russell King xscale_set_pte_ext_epilogue 5141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 5151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .ltorg 5171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 5181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 519f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King.globl cpu_xscale_suspend_size 520f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King.equ cpu_xscale_suspend_size, 4 * 7 521f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King#ifdef CONFIG_PM 522f6b0fa02e8b0708d17d631afce456524eadf87ffRussell KingENTRY(cpu_xscale_do_suspend) 523f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King stmfd sp!, {r4 - r10, lr} 524f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode 525f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mrc p15, 0, r5, c15, c1, 0 @ CP access reg 526f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mrc p15, 0, r6, c13, c0, 0 @ PID 527f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mrc p15, 0, r7, c3, c0, 0 @ domain ID 528f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mrc p15, 0, r8, c2, c0, 0 @ translation table base addr 529f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mrc p15, 0, r9, c1, c1, 0 @ auxiliary control reg 530f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mrc p15, 0, r10, c1, c0, 0 @ control reg 531f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King bic r4, r4, #2 @ clear frequency change bit 532f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King stmia r0, {r4 - r10} @ store cp regs 533f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King ldmfd sp!, {r4 - r10, pc} 534f6b0fa02e8b0708d17d631afce456524eadf87ffRussell KingENDPROC(cpu_xscale_do_suspend) 535f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King 536f6b0fa02e8b0708d17d631afce456524eadf87ffRussell KingENTRY(cpu_xscale_do_resume) 537f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King ldmia r0, {r4 - r10} @ load cp regs 538f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mov ip, #0 539f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 540f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB 541f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode. 542f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, r5, c15, c1, 0 @ CP access reg 543f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, r6, c13, c0, 0 @ PID 544f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, r7, c3, c0, 0 @ domain ID 545f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, r8, c2, c0, 0 @ translation table base addr 546f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mcr p15, 0, r9, c1, c1, 0 @ auxiliary control reg 547f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mov r0, r10 @ control register 548f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mov r2, r8, lsr #14 @ get TTB0 base 549f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King mov r2, r2, lsl #14 550f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \ 551f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE 552f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King b cpu_resume_mmu 553f6b0fa02e8b0708d17d631afce456524eadf87ffRussell KingENDPROC(cpu_xscale_do_resume) 554f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King#else 555f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King#define cpu_xscale_do_suspend 0 556f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King#define cpu_xscale_do_resume 0 557f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King#endif 558f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King 5595085f3ff458521045f7e43da62b8c30ea7df2e82Russell King __CPUINIT 5601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __xscale_setup, #function 5621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__xscale_setup: 5631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB 5641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 5651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs 566afe4b25e7d9260d85fccb2d13c9933a987bdfc8aLennert Buytenhek mov r0, #1 << 6 @ cp6 for IOP3xx and Bulverde 5671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds orr r0, r0, #1 << 13 @ Its undefined whether this 5681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes 56922b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King 57022b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King adr r5, xscale_crval 57122b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King ldmia r5, {r5, r6} 5721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mrc p15, 0, r0, c1, c0, 0 @ get control register 5731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bic r0, r0, r5 57422b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King orr r0, r0, r6 5751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds mov pc, lr 5761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __xscale_setup, . - __xscale_setup 5771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 5791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * R 5801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * .RVI ZFRS BLDP WCAM 5811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * ..11 1.01 .... .101 5821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 5831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 58422b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King .type xscale_crval, #object 58522b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell Kingxscale_crval: 58622b1908610dd7ff68471cd4fbd383dbdfe5e0ecdRussell King crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900 5871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __INITDATA 5891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 5911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Purpose : Function pointers used to access above functions - all calls 5921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * come through these 5931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 5941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type xscale_processor_functions, #object 5961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsENTRY(xscale_processor_functions) 5971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word v5t_early_abort 5984fb2847437d871fe579f820ceb18031db3359901Kirill A. Shutemov .word legacy_pabort 5991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_proc_init 6001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_proc_fin 6011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_reset 6021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_do_idle 6031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_dcache_clean_area 6041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .word cpu_xscale_switch_mm 605ad1ae2fe7fe68414ef29eab3c87b48841f8b72f2Russell King .word cpu_xscale_set_pte_ext 606f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King .word cpu_xscale_suspend_size 607f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King .word cpu_xscale_do_suspend 608f6b0fa02e8b0708d17d631afce456524eadf87ffRussell King .word cpu_xscale_do_resume 6091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size xscale_processor_functions, . - xscale_processor_functions 6101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .section ".rodata" 6121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_arch_name, #object 6141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_arch_name: 6151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "armv5te" 6161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_arch_name, . - cpu_arch_name 6171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_elf_name, #object 6191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_elf_name: 6201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "v5" 6211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_elf_name, . - cpu_elf_name 6221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 623197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .type cpu_80200_A0_A1_name, #object 624197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhekcpu_80200_A0_A1_name: 625197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .asciz "XScale-80200 A0/A1" 626197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .size cpu_80200_A0_A1_name, . - cpu_80200_A0_A1_name 627197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek 6281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_80200_name, #object 6291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_80200_name: 6301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-80200" 6311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_80200_name, . - cpu_80200_name 6321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 633a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .type cpu_80219_name, #object 634a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhekcpu_80219_name: 635a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .asciz "XScale-80219" 636a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .size cpu_80219_name, . - cpu_80219_name 637a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek 6381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_8032x_name, #object 6391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_8032x_name: 6401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IOP8032x Family" 6411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_8032x_name, . - cpu_8032x_name 6421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_8033x_name, #object 6441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_8033x_name: 6451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IOP8033x Family" 6461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_8033x_name, . - cpu_8033x_name 6471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_pxa250_name, #object 6491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_pxa250_name: 6501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-PXA250" 6511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_pxa250_name, . - cpu_pxa250_name 6521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_pxa210_name, #object 6541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_pxa210_name: 6551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-PXA210" 6561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_pxa210_name, . - cpu_pxa210_name 6571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_ixp42x_name, #object 6591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_ixp42x_name: 6601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IXP42x Family" 6611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_ixp42x_name, . - cpu_ixp42x_name 6621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 66345fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .type cpu_ixp43x_name, #object 66445fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushkocpu_ixp43x_name: 66545fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .asciz "XScale-IXP43x Family" 66645fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .size cpu_ixp43x_name, . - cpu_ixp43x_name 66745fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko 6681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_ixp46x_name, #object 6691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_ixp46x_name: 6701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IXP46x Family" 6711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_ixp46x_name, . - cpu_ixp46x_name 6721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_ixp2400_name, #object 6741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_ixp2400_name: 6751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IXP2400" 6761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_ixp2400_name, . - cpu_ixp2400_name 6771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_ixp2800_name, #object 6791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_ixp2800_name: 6801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-IXP2800" 6811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_ixp2800_name, . - cpu_ixp2800_name 6821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_pxa255_name, #object 6841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_pxa255_name: 6851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-PXA255" 6861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_pxa255_name, . - cpu_pxa255_name 6871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type cpu_pxa270_name, #object 6891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldscpu_pxa270_name: 6901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .asciz "XScale-PXA270" 6911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size cpu_pxa270_name, . - cpu_pxa270_name 6921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .align 6941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 69502b7dd1244aab9267ae4078e1ad6a2fdaabeb6edBen Dooks .section ".proc.info.init", #alloc, #execinstr 6961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 697197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .type __80200_A0_A1_proc_info,#object 698197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek__80200_A0_A1_proc_info: 699197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long 0x69052000 700197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long 0xfffffffe 701197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long PMD_TYPE_SECT | \ 702197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek PMD_SECT_BUFFERABLE | \ 703197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek PMD_SECT_CACHEABLE | \ 704197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek PMD_SECT_AP_WRITE | \ 705197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek PMD_SECT_AP_READ 706197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long PMD_TYPE_SECT | \ 707197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek PMD_SECT_AP_WRITE | \ 708197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek PMD_SECT_AP_READ 709197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek b __xscale_setup 710197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long cpu_arch_name 711197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long cpu_elf_name 712197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 713197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long cpu_80200_name 714197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_processor_functions 715197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long v4wbi_tlb_fns 716197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_mc_user_fns 717197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .long xscale_80200_A0_A1_cache_fns 718197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek .size __80200_A0_A1_proc_info, . - __80200_A0_A1_proc_info 719197c9444d6093b70c8faa24e7ab04a2423c9d14dLennert Buytenhek 7201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __80200_proc_info,#object 7211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__80200_proc_info: 7221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69052000 7231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffffff0 7241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 7251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 7261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 7271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 7281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 7298799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 7308799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 7318799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 7321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 7331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 7341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 7351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 7361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_80200_name 7371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 7381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 7391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 7401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 7411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __80200_proc_info, . - __80200_proc_info 7421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 743a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .type __80219_proc_info,#object 744a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek__80219_proc_info: 745a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long 0x69052e20 746a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long 0xffffffe0 747a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long PMD_TYPE_SECT | \ 748a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek PMD_SECT_BUFFERABLE | \ 749a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek PMD_SECT_CACHEABLE | \ 750a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek PMD_SECT_AP_WRITE | \ 751a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek PMD_SECT_AP_READ 752a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long PMD_TYPE_SECT | \ 753a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek PMD_SECT_AP_WRITE | \ 754a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek PMD_SECT_AP_READ 755a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek b __xscale_setup 756a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long cpu_arch_name 757a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long cpu_elf_name 758a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 759a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long cpu_80219_name 760a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long xscale_processor_functions 761a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long v4wbi_tlb_fns 762a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long xscale_mc_user_fns 763a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .long xscale_cache_fns 764a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek .size __80219_proc_info, . - __80219_proc_info 765a6a38a66224c7c578cfed2f584b440c81af0c3aeLennert Buytenhek 7661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __8032x_proc_info,#object 7671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__8032x_proc_info: 7681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69052420 76936694a4c22767ee09c91ccda63810086c65c810bDan Williams .long 0xfffff7e0 7701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 7711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 7721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 7731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 7741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 7758799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 7768799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 7778799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 7781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 7791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 7801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 7811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 7821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_8032x_name 7831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 7841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 7851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 7861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 7871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __8032x_proc_info, . - __8032x_proc_info 7881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __8033x_proc_info,#object 7901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__8033x_proc_info: 7911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69054010 7927f215abc69302dc027f024fe656e4841063e8fe8Dan Williams .long 0xfffffd30 7931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 7941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 7951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 7961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 7971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 7988799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 7998799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 8008799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 8011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 8021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 8031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 8041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 8051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_8033x_name 8061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 8071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 8081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 8091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 8101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __8033x_proc_info, . - __8033x_proc_info 8111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __pxa250_proc_info,#object 8131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__pxa250_proc_info: 8141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69052100 8151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffff7f0 8161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 8171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 8181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 8191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 8201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 8218799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 8228799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 8238799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 8241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 8251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 8261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 8271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 8281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_pxa250_name 8291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 8301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 8311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 8321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 8331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __pxa250_proc_info, . - __pxa250_proc_info 8341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __pxa210_proc_info,#object 8361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__pxa210_proc_info: 8371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69052120 8381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffff3f0 8391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 8401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 8411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 8421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 8431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 8448799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 8458799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 8468799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 8471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 8481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 8491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 8501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 8511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_pxa210_name 8521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 8531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 8541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 8551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 8561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __pxa210_proc_info, . - __pxa210_proc_info 8571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __ixp2400_proc_info, #object 8591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__ixp2400_proc_info: 8601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69054190 8611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffffff0 8621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 8631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 8641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 8651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 8661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 8678799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 8688799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 8698799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 8701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 8711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 8721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 8731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 8741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_ixp2400_name 8751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 8761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 8771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 8781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 8791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __ixp2400_proc_info, . - __ixp2400_proc_info 8801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __ixp2800_proc_info, #object 8821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__ixp2800_proc_info: 8831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x690541a0 8841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffffff0 8851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 8861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 8871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 8881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 8891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 8908799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 8918799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 8928799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 8931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 8941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 8951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 8961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 8971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_ixp2800_name 8981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 8991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 9001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 9011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 9021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __ixp2800_proc_info, . - __ixp2800_proc_info 9031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __ixp42x_proc_info, #object 9051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__ixp42x_proc_info: 9061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x690541c0 9071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xffffffc0 9081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 9091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 9101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 9111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 9121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 9138799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 9148799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 9158799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 9161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 9171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 9181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 9191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 9201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_ixp42x_name 9211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 9221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 9231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 9241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 9251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __ixp42x_proc_info, . - __ixp42x_proc_info 9261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 92745fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .type __ixp43x_proc_info, #object 92845fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko__ixp43x_proc_info: 92945fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long 0x69054040 93045fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long 0xfffffff0 93145fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long PMD_TYPE_SECT | \ 93245fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko PMD_SECT_BUFFERABLE | \ 93345fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko PMD_SECT_CACHEABLE | \ 93445fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko PMD_SECT_AP_WRITE | \ 93545fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko PMD_SECT_AP_READ 93645fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long PMD_TYPE_SECT | \ 93745fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko PMD_SECT_AP_WRITE | \ 93845fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko PMD_SECT_AP_READ 93945fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko b __xscale_setup 94045fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long cpu_arch_name 94145fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long cpu_elf_name 94245fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 94345fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long cpu_ixp43x_name 94445fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long xscale_processor_functions 94545fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long v4wbi_tlb_fns 94645fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long xscale_mc_user_fns 94745fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .long xscale_cache_fns 94845fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko .size __ixp43x_proc_info, . - __ixp43x_proc_info 94945fba0846f5a5a48ed3c394aa4f8ca93699e7655Ruslan V. Sushko 9501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __ixp46x_proc_info, #object 9511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__ixp46x_proc_info: 9521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69054200 9531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xffffff00 9548799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 9558799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_BUFFERABLE | \ 9568799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_CACHEABLE | \ 9578799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 9588799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 9598799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 9608799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 9618799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 9621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 9631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 9641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 9651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 9661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_ixp46x_name 9671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 9681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 9691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 9701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 9711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __ixp46x_proc_info, . - __ixp46x_proc_info 9721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __pxa255_proc_info,#object 9741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__pxa255_proc_info: 9751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69052d00 9761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffffff0 9771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 9781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 9791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 9801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 9811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 9828799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 9838799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 9848799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 9851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 9861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 9871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 9881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 9891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_pxa255_name 9901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 9911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 9921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 9931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 9941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __pxa255_proc_info, . - __pxa255_proc_info 9951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .type __pxa270_proc_info,#object 9971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds__pxa270_proc_info: 9981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0x69054110 9991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long 0xfffffff0 10001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long PMD_TYPE_SECT | \ 10011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_BUFFERABLE | \ 10021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_CACHEABLE | \ 10031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_WRITE | \ 10041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMD_SECT_AP_READ 10058799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King .long PMD_TYPE_SECT | \ 10068799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_WRITE | \ 10078799ee9f49f6171fd58f4d64f8c067ca49006a5dRussell King PMD_SECT_AP_READ 10081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds b __xscale_setup 10091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_arch_name 10101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_elf_name 1011afe4b25e7d9260d85fccb2d13c9933a987bdfc8aLennert Buytenhek .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 10121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long cpu_pxa270_name 10131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_processor_functions 10141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long v4wbi_tlb_fns 10151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_mc_user_fns 10161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .long xscale_cache_fns 10171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .size __pxa270_proc_info, . - __pxa270_proc_info 10181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1019