1/* linux/arch/arm/plat-s5p/sleep.S 2 * 3 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 4 * http://www.samsung.com 5 * 6 * Common S5P Sleep Code 7 * Based on S3C64XX sleep code by: 8 * Ben Dooks, (c) 2008 Simtec Electronics 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23*/ 24 25#include <linux/linkage.h> 26#include <asm/asm-offsets.h> 27#include <asm/hardware/cache-l2x0.h> 28 29/* 30 * The following code is located into the .data section. This is to 31 * allow l2x0_regs_phys to be accessed with a relative load while we 32 * can't rely on any MMU translation. We could have put l2x0_regs_phys 33 * in the .text section as well, but some setups might insist on it to 34 * be truly read-only. (Reference from: arch/arm/kernel/sleep.S) 35 */ 36 .data 37 .align 38 39 /* 40 * sleep magic, to allow the bootloader to check for an valid 41 * image to resume to. Must be the first word before the 42 * s3c_cpu_resume entry. 43 */ 44 45 .word 0x2bedf00d 46 47 /* 48 * s3c_cpu_resume 49 * 50 * resume code entry for bootloader to call 51 */ 52 53ENTRY(s3c_cpu_resume) 54#ifdef CONFIG_CACHE_L2X0 55 adr r0, l2x0_regs_phys 56 ldr r0, [r0] 57 ldr r1, [r0, #L2X0_R_PHY_BASE] 58 ldr r2, [r1, #L2X0_CTRL] 59 tst r2, #0x1 60 bne resume_l2on 61 ldr r2, [r0, #L2X0_R_AUX_CTRL] 62 str r2, [r1, #L2X0_AUX_CTRL] 63 ldr r2, [r0, #L2X0_R_TAG_LATENCY] 64 str r2, [r1, #L2X0_TAG_LATENCY_CTRL] 65 ldr r2, [r0, #L2X0_R_DATA_LATENCY] 66 str r2, [r1, #L2X0_DATA_LATENCY_CTRL] 67 ldr r2, [r0, #L2X0_R_PREFETCH_CTRL] 68 str r2, [r1, #L2X0_PREFETCH_CTRL] 69 ldr r2, [r0, #L2X0_R_PWR_CTRL] 70 str r2, [r1, #L2X0_POWER_CTRL] 71 mov r2, #1 72 str r2, [r1, #L2X0_CTRL] 73resume_l2on: 74#endif 75 b cpu_resume 76ENDPROC(s3c_cpu_resume) 77#ifdef CONFIG_CACHE_L2X0 78 .globl l2x0_regs_phys 79l2x0_regs_phys: 80 .long 0 81#endif 82