170f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar/* 270f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * arch/arm/plat-spear/include/plat/padmux.h 370f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * 470f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * SPEAr platform specific gpio pads muxing file 570f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * 670f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * Copyright (C) 2009 ST Microelectronics 770f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * Viresh Kumar<viresh.kumar@st.com> 870f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * 970f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * This file is licensed under the terms of the GNU General Public 1070f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * License version 2. This program is licensed "as is" without any 1170f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * warranty of any kind, whether express or implied. 1270f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar */ 1370f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar 1470f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar#ifndef __PLAT_PADMUX_H 1570f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar#define __PLAT_PADMUX_H 1670f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar 1770f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar#include <linux/types.h> 1870f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar 1970f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar/* 2070f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * struct pmx_reg: configuration structure for mode reg and mux reg 2170f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * 2270f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * offset: offset of mode reg 2370f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * mask: mask of mode reg 2470f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar */ 2570f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumarstruct pmx_reg { 2670f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar u32 offset; 2770f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar u32 mask; 2870f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar}; 2970f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar 3070f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar/* 3170f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * struct pmx_dev_mode: configuration structure every group of modes of a device 3270f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * 3370f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * ids: all modes for this configuration 3470f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * mask: mask for supported mode 3570f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar */ 3670f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumarstruct pmx_dev_mode { 3770f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar u32 ids; 3870f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar u32 mask; 3970f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar}; 4070f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar 4170f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar/* 4270f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * struct pmx_mode: mode definition structure 4370f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * 4470f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * name: mode name 4570f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * mask: mode mask 4670f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar */ 4770f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumarstruct pmx_mode { 4870f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar char *name; 4970f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar u32 id; 5070f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar u32 mask; 5170f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar}; 5270f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar 5370f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar/* 5470f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * struct pmx_dev: device definition structure 5570f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * 5670f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * name: device name 5770f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * modes: device configuration array for different modes supported 5870f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * mode_count: size of modes array 5970f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * is_active: is peripheral active/enabled 6070f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg 6170f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar */ 6270f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumarstruct pmx_dev { 6370f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar char *name; 6470f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar struct pmx_dev_mode *modes; 6570f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar u8 mode_count; 6670f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar bool is_active; 6770f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar bool enb_on_reset; 6870f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar}; 6970f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar 7070f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar/* 7170f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * struct pmx_driver: driver definition structure 7270f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * 7370f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * mode: mode to be set 7470f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * devs: array of pointer to pmx devices 7570f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * devs_count: ARRAY_SIZE of devs 7670f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * base: base address of soc config registers 7770f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * mode_reg: structure of mode config register 7870f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar * mux_reg: structure of device mux config register 7970f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar */ 8070f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumarstruct pmx_driver { 8170f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar struct pmx_mode *mode; 8270f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar struct pmx_dev **devs; 8370f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar u8 devs_count; 8470f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar u32 *base; 8570f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar struct pmx_reg mode_reg; 8670f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar struct pmx_reg mux_reg; 8770f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar}; 8870f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar 8970f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar/* pmx functions */ 9070f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumarint pmx_register(struct pmx_driver *driver); 9170f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar 9270f4c0bf9e4d067744ee453bc37c0c4adcea6e53viresh kumar#endif /* __PLAT_PADMUX_H */ 93