1e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta/* File:	arch/blackfin/mach-bf527/boards/tll6527m.c
2e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta * Based on:	arch/blackfin/mach-bf527/boards/ezkit.c
3e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta * Author:	Ashish Gupta
4e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta *
5e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta * Copyright: 2010 - The Learning Labs Inc.
6e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta *
7e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta * Licensed under the GPL-2 or later.
8e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta */
9e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
10e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <linux/device.h>
118dc7a9c84fbeb8825d19c18e9d8c6fce416c473fPaul Gortmaker#include <linux/export.h>
12e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <linux/platform_device.h>
13e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <linux/mtd/mtd.h>
14e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <linux/mtd/partitions.h>
15e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <linux/mtd/physmap.h>
16e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <linux/spi/spi.h>
17e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <linux/spi/flash.h>
18e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <linux/i2c.h>
19e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <linux/irq.h>
20e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <linux/interrupt.h>
21e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <linux/usb/musb.h>
22e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <linux/leds.h>
23e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <linux/input.h>
24e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <asm/dma.h>
25e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <asm/bfin5xx_spi.h>
26e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <asm/reboot.h>
27e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <asm/nand.h>
28e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <asm/portmux.h>
29e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <asm/dpmc.h>
30e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
31e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_TOUCHSCREEN_AD7879) \
32e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	|| defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
33e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <linux/spi/ad7879.h>
34e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#define LCD_BACKLIGHT_GPIO 0x40
35e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta/* TLL6527M uses TLL7UIQ35 / ADI LCD EZ Extender. AD7879 AUX GPIO is used for
36e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta * LCD Backlight Enable
37e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta */
38e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
39e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
40e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta/*
41e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta * Name the Board for the /proc/cpuinfo
42e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta */
43e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptaconst char bfin_board_name[] = "TLL6527M";
44e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta/*
45e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta *  Driver needs to know address, irq and flag pin.
46e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta */
47e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
48e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
49e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct resource musb_resources[] = {
50e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	[0] = {
51e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start	= 0xffc03800,
52e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end	= 0xffc03cff,
53e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags	= IORESOURCE_MEM,
54e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
55e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	[1] = {	/* general IRQ */
56e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start	= IRQ_USB_INT0,
57e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end	= IRQ_USB_INT0,
58e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
59e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
60e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	[2] = {	/* DMA IRQ */
61e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start	= IRQ_USB_DMA,
62e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end	= IRQ_USB_DMA,
63e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
64e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
65e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
66e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
67e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct musb_hdrc_config musb_config = {
68e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.multipoint	= 0,
69e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.dyn_fifo	= 0,
70e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.soft_con	= 1,
71e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.dma		= 1,
72e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.num_eps	= 8,
73e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.dma_channels	= 8,
74e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	/*.gpio_vrsel	= GPIO_PG13,*/
75e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	/* Some custom boards need to be active low, just set it to "0"
76e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	 * if it is the case.
77e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	 */
78e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.gpio_vrsel_active	= 1,
79e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
80e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
81e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct musb_hdrc_platform_data musb_plat = {
82e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_USB_MUSB_OTG)
83e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.mode		= MUSB_OTG,
84e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
85e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.mode		= MUSB_HOST,
86e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
87e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.mode		= MUSB_PERIPHERAL,
88e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
89e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.config		= &musb_config,
90e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
91e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
92e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic u64 musb_dmamask = ~(u32)0;
93e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
94e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct platform_device musb_device = {
959cb0308eec7a965136fe9fc6d1be3548c01a4a1eFelipe Balbi	.name		= "musb-blackfin",
96e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.id		= 0,
97e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.dev = {
98e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.dma_mask		= &musb_dmamask,
99e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.coherent_dma_mask	= 0xffffffff,
100e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.platform_data		= &musb_plat,
101e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
102e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.num_resources	= ARRAY_SIZE(musb_resources),
103e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.resource	= musb_resources,
104e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
105e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
106e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
107e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
108e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <asm/bfin-lq035q1.h>
109e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
110e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
111e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
112e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.ppi_mode = USE_RGB565_16_BIT_PPI,
113e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.use_bl = 1,
114e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.gpio_bl = LCD_BACKLIGHT_GPIO,
115e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
116e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
117e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct resource bfin_lq035q1_resources[] = {
118e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
119e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = IRQ_PPI_ERROR,
120e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = IRQ_PPI_ERROR,
121e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_IRQ,
122e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
123e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
124e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
125e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct platform_device bfin_lq035q1_device = {
126e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.name		= "bfin-lq035q1",
127e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.id		= -1,
128e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.num_resources	= ARRAY_SIZE(bfin_lq035q1_resources),
129e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.resource	= bfin_lq035q1_resources,
130e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.dev		= {
131e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.platform_data = &bfin_lq035q1_data,
132e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
133e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
134e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
135e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
136e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
137e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct mtd_partition tll6527m_partitions[] = {
138e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
139e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.name       = "bootloader(nor)",
140e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.size       = 0xA0000,
141e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.offset     = 0,
142e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	}, {
143e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.name       = "linux kernel(nor)",
144e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.size       = 0xD00000,
145e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.offset     = MTDPART_OFS_APPEND,
146e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	}, {
147e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.name       = "file system(nor)",
148e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.size       = MTDPART_SIZ_FULL,
149e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.offset     = MTDPART_OFS_APPEND,
150e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	}
151e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
152e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
153e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct physmap_flash_data tll6527m_flash_data = {
154e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.width      = 2,
155e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.parts      = tll6527m_partitions,
156e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.nr_parts   = ARRAY_SIZE(tll6527m_partitions),
157e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
158e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
159e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic unsigned tll6527m_flash_gpios[] = { GPIO_PG11, GPIO_PH11, GPIO_PH12 };
160e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
161e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct resource tll6527m_flash_resource[] = {
162e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
163e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.name  = "cfi_probe",
164e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = 0x20000000,
165e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end   = 0x201fffff,
166e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_MEM,
167e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	}, {
168e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = (unsigned long)tll6527m_flash_gpios,
169e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end   = ARRAY_SIZE(tll6527m_flash_gpios),
170e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_IRQ,
171e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	}
172e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
173e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
174e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct platform_device tll6527m_flash_device = {
175e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.name          = "gpio-addr-flash",
176e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.id            = 0,
177e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.dev = {
178e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.platform_data = &tll6527m_flash_data,
179e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
180e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.num_resources = ARRAY_SIZE(tll6527m_flash_resource),
181e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.resource      = tll6527m_flash_resource,
182e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
183e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
184e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
185e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_GPIO_DECODER) || defined(CONFIG_GPIO_DECODER_MODULE)
186e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta/* An SN74LVC138A 3:8 decoder chip has been used to generate 7 augmented
187e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta * outputs used as SPI CS lines for all SPI SLAVE devices on TLL6527v1-0.
188e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta * EXP_GPIO_SPISEL_BASE is the base number for the expanded outputs being
189e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta * used as SPI CS lines, this should be > MAX_BLACKFIN_GPIOS
190e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta */
191e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <linux/gpio-decoder.h>
192e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#define EXP_GPIO_SPISEL_BASE 0x64
193e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic unsigned gpio_addr_inputs[] = {
194e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	GPIO_PG1, GPIO_PH9, GPIO_PH10
195e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
196e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
197e01b5b129661ee1eaddd4f2a0d8df6cb170339a5Stefan Weilstatic struct gpio_decoder_platform_data spi_decoded_cs = {
198e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.base		= EXP_GPIO_SPISEL_BASE,
199e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.input_addrs	= gpio_addr_inputs,
200e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.nr_input_addrs = ARRAY_SIZE(gpio_addr_inputs),
201e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.default_output	= 0,
202e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta/*	.default_output = (1 << ARRAY_SIZE(gpio_addr_inputs)) - 1 */
203e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
204e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
205e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct platform_device spi_decoded_gpio = {
206e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.name	= "gpio-decoder",
207e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.id	= 0,
208e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.dev	= {
209e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.platform_data = &spi_decoded_cs,
210e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
211e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
212e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
213e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#else
214e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#define EXP_GPIO_SPISEL_BASE 0x0
215e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
216e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
217e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
218e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
219e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <linux/input/adxl34x.h>
220e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic const struct adxl34x_platform_data adxl345_info = {
221e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.x_axis_offset = 0,
222e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.y_axis_offset = 0,
223e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.z_axis_offset = 0,
224e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.tap_threshold = 0x31,
225e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.tap_duration = 0x10,
226e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.tap_latency = 0x60,
227e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.tap_window = 0xF0,
228e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
229e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.act_axis_control = 0xFF,
230e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.activity_threshold = 5,
231e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.inactivity_threshold = 2,
232e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.inactivity_time = 2,
233e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.free_fall_threshold = 0x7,
234e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.free_fall_time = 0x20,
235e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.data_rate = 0x8,
236e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.data_range = ADXL_FULL_RES,
237e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
238e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.ev_type = EV_ABS,
239e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.ev_code_x = ABS_X,		/* EV_REL */
240e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.ev_code_y = ABS_Y,		/* EV_REL */
241e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.ev_code_z = ABS_Z,		/* EV_REL */
242e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
243e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
244e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
245e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta/*	.ev_code_ff = KEY_F,*/		/* EV_KEY */
246e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.ev_code_act_inactivity = KEY_A,	/* EV_KEY */
247e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.use_int2 = 1,
248e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
249e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.fifo_mode = ADXL_FIFO_STREAM,
250e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
251e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
252e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
253e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
254e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct platform_device rtc_device = {
255e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.name = "rtc-bfin",
256e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.id   = -1,
257e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
258e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
259e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
260e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
26102460d08930656b3a50381cfb119864efcd4eef9Sonic Zhang#include <linux/bfin_mac.h>
26202460d08930656b3a50381cfb119864efcd4eef9Sonic Zhangstatic const unsigned short bfin_mac_peripherals[] = P_RMII0;
26302460d08930656b3a50381cfb119864efcd4eef9Sonic Zhang
26402460d08930656b3a50381cfb119864efcd4eef9Sonic Zhangstatic struct bfin_phydev_platform_data bfin_phydev_data[] = {
26502460d08930656b3a50381cfb119864efcd4eef9Sonic Zhang	{
26602460d08930656b3a50381cfb119864efcd4eef9Sonic Zhang		.addr = 1,
26702460d08930656b3a50381cfb119864efcd4eef9Sonic Zhang		.irq = IRQ_MAC_PHYINT,
26802460d08930656b3a50381cfb119864efcd4eef9Sonic Zhang	},
26902460d08930656b3a50381cfb119864efcd4eef9Sonic Zhang};
27002460d08930656b3a50381cfb119864efcd4eef9Sonic Zhang
27102460d08930656b3a50381cfb119864efcd4eef9Sonic Zhangstatic struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
27202460d08930656b3a50381cfb119864efcd4eef9Sonic Zhang	.phydev_number = 1,
27302460d08930656b3a50381cfb119864efcd4eef9Sonic Zhang	.phydev_data = bfin_phydev_data,
27402460d08930656b3a50381cfb119864efcd4eef9Sonic Zhang	.phy_mode = PHY_INTERFACE_MODE_RMII,
27502460d08930656b3a50381cfb119864efcd4eef9Sonic Zhang	.mac_peripherals = bfin_mac_peripherals,
27602460d08930656b3a50381cfb119864efcd4eef9Sonic Zhang};
27702460d08930656b3a50381cfb119864efcd4eef9Sonic Zhang
278e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct platform_device bfin_mii_bus = {
279e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.name = "bfin_mii_bus",
28002460d08930656b3a50381cfb119864efcd4eef9Sonic Zhang	.dev = {
28102460d08930656b3a50381cfb119864efcd4eef9Sonic Zhang		.platform_data = &bfin_mii_bus_data,
28202460d08930656b3a50381cfb119864efcd4eef9Sonic Zhang	}
283e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
284e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
285e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct platform_device bfin_mac_device = {
286e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.name = "bfin_mac",
28702460d08930656b3a50381cfb119864efcd4eef9Sonic Zhang	.dev = {
28802460d08930656b3a50381cfb119864efcd4eef9Sonic Zhang		.platform_data = &bfin_mii_bus,
28902460d08930656b3a50381cfb119864efcd4eef9Sonic Zhang	}
290e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
291e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
292e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
293e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_MTD_M25P80) \
294e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	|| defined(CONFIG_MTD_M25P80_MODULE)
295e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct mtd_partition bfin_spi_flash_partitions[] = {
296e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
297e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.name = "bootloader(spi)",
298e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.size = 0x00040000,
299e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.offset = 0,
300e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.mask_flags = MTD_CAP_ROM
301e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	}, {
302e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.name = "linux kernel(spi)",
303e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.size = MTDPART_SIZ_FULL,
304e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.offset = MTDPART_OFS_APPEND,
305e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	}
306e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
307e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
308e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct flash_platform_data bfin_spi_flash_data = {
309e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.name = "m25p80",
310e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.parts = bfin_spi_flash_partitions,
311e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
312e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.type = "m25p16",
313e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
314e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
315e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta/* SPI flash chip (m25p64) */
316e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct bfin5xx_spi_chip spi_flash_chip_info = {
317e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.enable_dma = 0,         /* use dma transfer with this chip*/
318e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
319e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
320e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
321e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
322e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct bfin5xx_spi_chip  mmc_spi_chip_info = {
323e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.enable_dma = 0,
324e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
325e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
326e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
327e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_TOUCHSCREEN_AD7879) \
328e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	|| defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
329e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic const struct ad7879_platform_data bfin_ad7879_ts_info = {
330e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.model			= 7879,	/* Model = AD7879 */
331e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.x_plate_ohms		= 620,	/* 620 Ohm from the touch datasheet */
332e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.pressure_max		= 10000,
333e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.pressure_min		= 0,
334e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.first_conversion_delay = 3,
335e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta				/* wait 512us before do a first conversion */
336e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.acquisition_time	= 1,	/* 4us acquisition time per sample */
337e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.median			= 2,	/* do 8 measurements */
338e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.averaging		= 1,
339e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta				/* take the average of 4 middle samples */
340e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.pen_down_acc_interval	= 255,	/* 9.4 ms */
341e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.gpio_export		= 1,	/* configure AUX as GPIO output*/
342e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.gpio_base		= LCD_BACKLIGHT_GPIO,
343e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
344e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
345e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
346e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
347e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct platform_device bfin_i2s = {
348e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.name = "bfin-i2s",
349e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.id = CONFIG_SND_BF5XX_SPORT_NUM,
350e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	/* TODO: add platform data here */
351e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
352e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
353e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
354e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE)
355e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#include <linux/spi/mcp23s08.h>
356e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = {
357e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.chip[0].is_present = true,
358e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.base = 0x30,
359e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
360e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic const struct mcp23s08_platform_data bfin_mcp23s08_usr_gpio_info = {
361e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.chip[2].is_present = true,
362e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.base = 0x38,
363e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
364e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
365e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
366e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct spi_board_info bfin_spi_board_info[] __initdata = {
367e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_MTD_M25P80) \
368e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	|| defined(CONFIG_MTD_M25P80_MODULE)
369e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
370e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		/* the modalias must be the same as spi device driver name */
371e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.modalias = "m25p80", /* Name of spi_driver for this device */
372e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.max_speed_hz = 25000000,
373e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta				/* max spi clock (SCK) speed in HZ */
374e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.bus_num = 0, /* Framework bus number */
375e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS,
376e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		/* Can be connected to TLL6527M GPIO connector */
377e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		/* Either SPI_ADC or M25P80 FLASH can be installed at a time */
378e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.platform_data = &bfin_spi_flash_data,
379e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.controller_data = &spi_flash_chip_info,
380e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.mode = SPI_MODE_3,
381e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
382e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
383e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
384e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
385e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
386e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.modalias = "mmc_spi",
387e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta/*
388e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta * TLL6527M V1.0 does not support SD Card at SPI Clock > 10 MHz due to
389e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta * SPI buffer limitations
390e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta */
391e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.max_speed_hz = 10000000,
392e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta					/* max spi clock (SCK) speed in HZ */
393e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.bus_num = 0,
394e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.chip_select = EXP_GPIO_SPISEL_BASE + 0x05 + MAX_CTRL_CS,
395e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.controller_data = &mmc_spi_chip_info,
396e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.mode = SPI_MODE_0,
397e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
398e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
399e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) \
400e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	|| defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
401e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
402e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.modalias = "ad7879",
403e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.platform_data = &bfin_ad7879_ts_info,
404e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.irq = IRQ_PH14,
405e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.max_speed_hz = 5000000,
406e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta					/* max spi clock (SCK) speed in HZ */
407e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.bus_num = 0,
408e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.chip_select = EXP_GPIO_SPISEL_BASE + 0x07 + MAX_CTRL_CS,
409e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.mode = SPI_CPHA | SPI_CPOL,
410e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
411e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
412e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
413e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
414e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.modalias = "spidev",
415e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.max_speed_hz = 10000000,
416e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		/* TLL6527Mv1-0 supports max spi clock (SCK) speed = 10 MHz */
417e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.bus_num = 0,
418e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.chip_select = EXP_GPIO_SPISEL_BASE + 0x03 + MAX_CTRL_CS,
419e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.mode = SPI_CPHA | SPI_CPOL,
420e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
421e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
422e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
423e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
424e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.modalias = "bfin-lq035q1-spi",
425e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.max_speed_hz = 20000000,
426e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.bus_num = 0,
427e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.chip_select = EXP_GPIO_SPISEL_BASE + 0x06 + MAX_CTRL_CS,
428e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.mode = SPI_CPHA | SPI_CPOL,
429e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
430e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
431e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE)
432e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
433e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.modalias = "mcp23s08",
434e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.platform_data = &bfin_mcp23s08_sys_gpio_info,
435e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
436e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.bus_num = 0,
437e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.chip_select = EXP_GPIO_SPISEL_BASE + 0x01 + MAX_CTRL_CS,
438e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.mode = SPI_CPHA | SPI_CPOL,
439e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
440e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
441e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.modalias = "mcp23s08",
442e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.platform_data = &bfin_mcp23s08_usr_gpio_info,
443e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
444e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.bus_num = 0,
445e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.chip_select = EXP_GPIO_SPISEL_BASE + 0x02 + MAX_CTRL_CS,
446e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.mode = SPI_CPHA | SPI_CPOL,
447e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
448e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
449e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
450e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
4517d157fb02bc3f4dc74e6830725864ba501d92da7Sonic Zhang#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
452e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta/* SPI controller data */
453e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct bfin5xx_spi_master bfin_spi0_info = {
454e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.num_chipselect = EXP_GPIO_SPISEL_BASE + 8 + MAX_CTRL_CS,
455e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	/* EXP_GPIO_SPISEL_BASE will be > MAX_BLACKFIN_GPIOS */
456e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.enable_dma = 1,  /* master has the ability to do dma transfer */
457e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
458e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
459e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
460e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta/* SPI (0) */
461e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct resource bfin_spi0_resource[] = {
462e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	[0] = {
463e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = SPI0_REGBASE,
464e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end   = SPI0_REGBASE + 0xFF,
465e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_MEM,
466e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		},
467e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	[1] = {
468e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = CH_SPI,
469e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end   = CH_SPI,
470e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_DMA,
471e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
472e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	[2] = {
473e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = IRQ_SPI,
474e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end   = IRQ_SPI,
475e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_IRQ,
476e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
477e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
478e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
479e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct platform_device bfin_spi0_device = {
480e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.name = "bfin-spi",
481e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.id = 0, /* Bus number */
482e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.num_resources = ARRAY_SIZE(bfin_spi0_resource),
483e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.resource = bfin_spi0_resource,
484e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.dev = {
485e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.platform_data = &bfin_spi0_info, /* Passed to driver */
486e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
487e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
488e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif  /* spi master and devices */
489e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
490e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
491e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#ifdef CONFIG_SERIAL_BFIN_UART0
492e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct resource bfin_uart0_resources[] = {
493e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
494e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = UART0_THR,
495e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = UART0_GCTL+2,
496e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_MEM,
497e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
498e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
499edb0a6408a84b4f14647770d8a6796afff3e93a9Sonic Zhang		.start = IRQ_UART0_TX,
500edb0a6408a84b4f14647770d8a6796afff3e93a9Sonic Zhang		.end = IRQ_UART0_TX,
501edb0a6408a84b4f14647770d8a6796afff3e93a9Sonic Zhang		.flags = IORESOURCE_IRQ,
502edb0a6408a84b4f14647770d8a6796afff3e93a9Sonic Zhang	},
503edb0a6408a84b4f14647770d8a6796afff3e93a9Sonic Zhang	{
504e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = IRQ_UART0_RX,
505edb0a6408a84b4f14647770d8a6796afff3e93a9Sonic Zhang		.end = IRQ_UART0_RX,
506e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_IRQ,
507e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
508e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
509e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = IRQ_UART0_ERROR,
510e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = IRQ_UART0_ERROR,
511e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_IRQ,
512e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
513e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
514e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = CH_UART0_TX,
515e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = CH_UART0_TX,
516e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_DMA,
517e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
518e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
519e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = CH_UART0_RX,
520e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = CH_UART0_RX,
521e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_DMA,
522e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
523e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
524e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
525a8b19886097032df38bd521cece4bc538fee2266Mike Frysingerstatic unsigned short bfin_uart0_peripherals[] = {
526e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	P_UART0_TX, P_UART0_RX, 0
527e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
528e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
529e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct platform_device bfin_uart0_device = {
530e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.name = "bfin-uart",
531e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.id = 0,
532e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.num_resources = ARRAY_SIZE(bfin_uart0_resources),
533e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.resource = bfin_uart0_resources,
534e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.dev = {
535e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.platform_data = &bfin_uart0_peripherals,
536e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta					/* Passed to driver */
537e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
538e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
539e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
540e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#ifdef CONFIG_SERIAL_BFIN_UART1
541e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct resource bfin_uart1_resources[] = {
542e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
543e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = UART1_THR,
544e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = UART1_GCTL+2,
545e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_MEM,
546e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
547e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
548edb0a6408a84b4f14647770d8a6796afff3e93a9Sonic Zhang		.start = IRQ_UART1_TX,
549edb0a6408a84b4f14647770d8a6796afff3e93a9Sonic Zhang		.end = IRQ_UART1_TX,
550edb0a6408a84b4f14647770d8a6796afff3e93a9Sonic Zhang		.flags = IORESOURCE_IRQ,
551edb0a6408a84b4f14647770d8a6796afff3e93a9Sonic Zhang	},
552edb0a6408a84b4f14647770d8a6796afff3e93a9Sonic Zhang	{
553e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = IRQ_UART1_RX,
554edb0a6408a84b4f14647770d8a6796afff3e93a9Sonic Zhang		.end = IRQ_UART1_RX,
555e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_IRQ,
556e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
557e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
558e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = IRQ_UART1_ERROR,
559e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = IRQ_UART1_ERROR,
560e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_IRQ,
561e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
562e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
563e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = CH_UART1_TX,
564e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = CH_UART1_TX,
565e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_DMA,
566e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
567e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
568e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = CH_UART1_RX,
569e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = CH_UART1_RX,
570e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_DMA,
571e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
572e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#ifdef CONFIG_BFIN_UART1_CTSRTS
573e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{	/* CTS pin */
574e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = GPIO_PF9,
575e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = GPIO_PF9,
576e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_IO,
577e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
578e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{	/* RTS pin */
579e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = GPIO_PF10,
580e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = GPIO_PF10,
581e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_IO,
582e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
583e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
584e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
585e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
586a8b19886097032df38bd521cece4bc538fee2266Mike Frysingerstatic unsigned short bfin_uart1_peripherals[] = {
587e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	P_UART1_TX, P_UART1_RX, 0
588e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
589e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
590e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct platform_device bfin_uart1_device = {
591e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.name = "bfin-uart",
592e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.id = 1,
593e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.num_resources = ARRAY_SIZE(bfin_uart1_resources),
594e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.resource = bfin_uart1_resources,
595e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.dev = {
596e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.platform_data = &bfin_uart1_peripherals,
597e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta						/* Passed to driver */
598e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
599e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
600e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
601e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
602e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
603e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
604e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#ifdef CONFIG_BFIN_SIR0
605e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct resource bfin_sir0_resources[] = {
606e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
607e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = 0xFFC00400,
608e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = 0xFFC004FF,
609e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_MEM,
610e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
611e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
612e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = IRQ_UART0_RX,
613e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = IRQ_UART0_RX+1,
614e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_IRQ,
615e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
616e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
617e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = CH_UART0_RX,
618e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = CH_UART0_RX+1,
619e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_DMA,
620e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
621e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
622e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
623e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct platform_device bfin_sir0_device = {
624e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.name = "bfin_sir",
625e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.id = 0,
626e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.num_resources = ARRAY_SIZE(bfin_sir0_resources),
627e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.resource = bfin_sir0_resources,
628e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
629e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
630e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#ifdef CONFIG_BFIN_SIR1
631e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct resource bfin_sir1_resources[] = {
632e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
633e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = 0xFFC02000,
634e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = 0xFFC020FF,
635e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_MEM,
636e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
637e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
638e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = IRQ_UART1_RX,
639e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = IRQ_UART1_RX+1,
640e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_IRQ,
641e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
642e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
643e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = CH_UART1_RX,
644e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = CH_UART1_RX+1,
645e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_DMA,
646e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
647e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
648e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
649e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct platform_device bfin_sir1_device = {
650e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.name = "bfin_sir",
651e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.id = 1,
652e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.num_resources = ARRAY_SIZE(bfin_sir1_resources),
653e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.resource = bfin_sir1_resources,
654e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
655e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
656e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
657e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
658e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
659e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct resource bfin_twi0_resource[] = {
660e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	[0] = {
661e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = TWI0_REGBASE,
662e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end   = TWI0_REGBASE,
663e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_MEM,
664e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
665e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	[1] = {
666e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = IRQ_TWI,
667e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end   = IRQ_TWI,
668e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_IRQ,
669e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
670e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
671e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
672e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct platform_device i2c_bfin_twi_device = {
673e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.name = "i2c-bfin-twi",
674e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.id = 0,
675e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.num_resources = ARRAY_SIZE(bfin_twi0_resource),
676e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.resource = bfin_twi0_resource,
677e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
678e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
679e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
680e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct i2c_board_info __initdata bfin_i2c_board_info[] = {
681e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
682e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
683e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		I2C_BOARD_INFO("pcf8574_lcd", 0x22),
684e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
685e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
686e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
687e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
688e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
689e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		I2C_BOARD_INFO("bfin-adv7393", 0x2B),
690e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
691e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
692e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_TOUCHSCREEN_AD7879_I2C) \
693e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	|| defined(CONFIG_TOUCHSCREEN_AD7879_I2C_MODULE)
694e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
695e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		I2C_BOARD_INFO("ad7879", 0x2C),
696e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.irq = IRQ_PH14,
697e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.platform_data = (void *)&bfin_ad7879_ts_info,
698e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
699e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
700e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
701e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
702e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		I2C_BOARD_INFO("ssm2602", 0x1b),
703e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
704e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
705e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
706e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		I2C_BOARD_INFO("adm1192", 0x2e),
707e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
708e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
709e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
710e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		I2C_BOARD_INFO("ltc3576", 0x09),
711e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
712e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_INPUT_ADXL34X_I2C) \
713e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	|| defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
714e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
715e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		I2C_BOARD_INFO("adxl34x", 0x53),
716e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.irq = IRQ_PH13,
717e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.platform_data = (void *)&adxl345_info,
718e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
719e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
720e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
721e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
722e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_SERIAL_BFIN_SPORT) \
723e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	|| defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
724e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
725e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct resource bfin_sport0_uart_resources[] = {
726e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
727e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = SPORT0_TCR1,
728e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = SPORT0_MRCS3+4,
729e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_MEM,
730e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
731e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
732e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = IRQ_SPORT0_RX,
733e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = IRQ_SPORT0_RX+1,
734e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_IRQ,
735e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
736e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
737e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = IRQ_SPORT0_ERROR,
738e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = IRQ_SPORT0_ERROR,
739e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_IRQ,
740e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
741e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
742e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
743a8b19886097032df38bd521cece4bc538fee2266Mike Frysingerstatic unsigned short bfin_sport0_peripherals[] = {
744e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
745e54b673081d12c46b47fdfe1772656cb2b43721dSonic Zhang	P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
746e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
747e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
748e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct platform_device bfin_sport0_uart_device = {
749e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.name = "bfin-sport-uart",
750e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.id = 0,
751e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
752e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.resource = bfin_sport0_uart_resources,
753e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.dev = {
754e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.platform_data = &bfin_sport0_peripherals,
755e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		/* Passed to driver */
756e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
757e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
758e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
759e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
760e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct resource bfin_sport1_uart_resources[] = {
761e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
762e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = SPORT1_TCR1,
763e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = SPORT1_MRCS3+4,
764e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_MEM,
765e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
766e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
767e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = IRQ_SPORT1_RX,
768e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = IRQ_SPORT1_RX+1,
769e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_IRQ,
770e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
771e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	{
772e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.start = IRQ_SPORT1_ERROR,
773e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.end = IRQ_SPORT1_ERROR,
774e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.flags = IORESOURCE_IRQ,
775e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
776e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
777e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
778a8b19886097032df38bd521cece4bc538fee2266Mike Frysingerstatic unsigned short bfin_sport1_peripherals[] = {
779e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
780e54b673081d12c46b47fdfe1772656cb2b43721dSonic Zhang	P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
781e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
782e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
783e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct platform_device bfin_sport1_uart_device = {
784e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.name = "bfin-sport-uart",
785e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.id = 1,
786e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
787e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.resource = bfin_sport1_uart_resources,
788e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.dev = {
789e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.platform_data = &bfin_sport1_peripherals,
790e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		/* Passed to driver */
791e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
792e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
793e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
794e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
795e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
796e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic const unsigned int cclk_vlev_datasheet[] = {
797e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	VRPAIR(VLEV_100, 400000000),
798e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	VRPAIR(VLEV_105, 426000000),
799e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	VRPAIR(VLEV_110, 500000000),
800e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	VRPAIR(VLEV_115, 533000000),
801e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	VRPAIR(VLEV_120, 600000000),
802e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
803e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
804e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
805e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.tuple_tab = cclk_vlev_datasheet,
806e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
807e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.vr_settling_time = 25 /* us */,
808e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
809e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
810e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct platform_device bfin_dpmc = {
811e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.name = "bfin dpmc",
812e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	.dev = {
813e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		.platform_data = &bfin_dmpc_vreg_data,
814e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	},
815e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
816e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
817e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct platform_device *tll6527m_devices[] __initdata = {
818e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
819e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	&bfin_dpmc,
820e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
821e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
822e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	&rtc_device,
823e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
824e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
825e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
826e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	&musb_device,
827e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
828e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
829e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
830e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	&bfin_mii_bus,
831e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	&bfin_mac_device,
832e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
833e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
8347d157fb02bc3f4dc74e6830725864ba501d92da7Sonic Zhang#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
835e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	&bfin_spi0_device,
836e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
837e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
838e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
839e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	&bfin_lq035q1_device,
840e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
841e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
842e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
843e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#ifdef CONFIG_SERIAL_BFIN_UART0
844e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	&bfin_uart0_device,
845e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
846e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#ifdef CONFIG_SERIAL_BFIN_UART1
847e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	&bfin_uart1_device,
848e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
849e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
850e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
851e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
852e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#ifdef CONFIG_BFIN_SIR0
853e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	&bfin_sir0_device,
854e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
855e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#ifdef CONFIG_BFIN_SIR1
856e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	&bfin_sir1_device,
857e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
858e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
859e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
860e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
861e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	&i2c_bfin_twi_device,
862e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
863e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
864e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_SERIAL_BFIN_SPORT) \
865e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	|| defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
866e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
867e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	&bfin_sport0_uart_device,
868e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
869e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
870e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	&bfin_sport1_uart_device,
871e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
872e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
873e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
874e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
875e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	&tll6527m_flash_device,
876e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
877e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
878e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
879e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	&bfin_i2s,
880e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
881e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
882e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_GPIO_DECODER) || defined(CONFIG_GPIO_DECODER_MODULE)
883e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	&spi_decoded_gpio,
884e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
885e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
886e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
887e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic int __init tll6527m_init(void)
888e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta{
889e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	printk(KERN_INFO "%s(): registering device resources\n", __func__);
890e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	i2c_register_board_info(0, bfin_i2c_board_info,
891e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta				ARRAY_SIZE(bfin_i2c_board_info));
892e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	platform_add_devices(tll6527m_devices, ARRAY_SIZE(tll6527m_devices));
893e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	spi_register_board_info(bfin_spi_board_info,
894e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta				ARRAY_SIZE(bfin_spi_board_info));
895e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	return 0;
896e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta}
897e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
898e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptaarch_initcall(tll6527m_init);
899e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
900e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptastatic struct platform_device *tll6527m_early_devices[] __initdata = {
901e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
902e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#ifdef CONFIG_SERIAL_BFIN_UART0
903e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	&bfin_uart0_device,
904e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
905e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#ifdef CONFIG_SERIAL_BFIN_UART1
906e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	&bfin_uart1_device,
907e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
908e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
909e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
910e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
911e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
912e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	&bfin_sport0_uart_device,
913e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
914e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
915e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	&bfin_sport1_uart_device,
916e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
917e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta#endif
918e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta};
919e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
920e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptavoid __init native_machine_early_platform_add_devices(void)
921e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta{
922e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	printk(KERN_INFO "register early platform devices\n");
923e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	early_platform_add_devices(tll6527m_early_devices,
924e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		ARRAY_SIZE(tll6527m_early_devices));
925e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta}
926e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
927e5c1721894415d00a55c2650ed6536b644799c50Ashish Guptavoid native_machine_restart(char *cmd)
928e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta{
929e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	/* workaround reboot hang when booting from SPI */
930e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	if ((bfin_read_SYSCR() & 0x7) == 0x3)
931e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
932e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta}
933e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
934fa63c6da22b4a6ea6e7d04e3dc9178dd72304903Danny Kukawkaint bfin_get_ether_addr(char *addr)
935e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta{
936e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	/* the MAC is stored in OTP memory page 0xDF */
937e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	u32 ret;
938e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	u64 otp_mac;
939e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	u32 (*otp_read)(u32 page, u32 flags,
940e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta			u64 *page_content) = (void *)0xEF00001A;
941e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta
942e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	ret = otp_read(0xDF, 0x00, &otp_mac);
943e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	if (!(ret & 0x1)) {
944e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		char *otp_mac_p = (char *)&otp_mac;
945e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta		for (ret = 0; ret < 6; ++ret)
946e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta			addr[ret] = otp_mac_p[5 - ret];
947e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta	}
948fa63c6da22b4a6ea6e7d04e3dc9178dd72304903Danny Kukawka	return 0;
949e5c1721894415d00a55c2650ed6536b644799c50Ashish Gupta}
950e5c1721894415d00a55c2650ed6536b644799c50Ashish GuptaEXPORT_SYMBOL(bfin_get_ether_addr);
951