124a07a124198153540f8f43d9e91d16227aba66eRoy Huang/* 296f1050d3df105c9ae6c6ac224f370199ea82fcdRobin Getz * simple DMA Implementation for Blackfin 324a07a124198153540f8f43d9e91d16227aba66eRoy Huang * 496f1050d3df105c9ae6c6ac224f370199ea82fcdRobin Getz * Copyright 2007-2009 Analog Devices Inc. 524a07a124198153540f8f43d9e91d16227aba66eRoy Huang * 696f1050d3df105c9ae6c6ac224f370199ea82fcdRobin Getz * Licensed under the GPL-2 or later. 724a07a124198153540f8f43d9e91d16227aba66eRoy Huang */ 896f1050d3df105c9ae6c6ac224f370199ea82fcdRobin Getz 9ac86a9785384843e8359c45a042cc4f87953d4c8Bernd Schmidt#include <linux/module.h> 10ac86a9785384843e8359c45a042cc4f87953d4c8Bernd Schmidt 1124a07a124198153540f8f43d9e91d16227aba66eRoy Huang#include <asm/blackfin.h> 1224a07a124198153540f8f43d9e91d16227aba66eRoy Huang#include <asm/dma.h> 1324a07a124198153540f8f43d9e91d16227aba66eRoy Huang 145e3bcf30d655c2e277c77b523347685d06bb9d31Mike Frysingerstruct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { 1524a07a124198153540f8f43d9e91d16227aba66eRoy Huang (struct dma_register *) DMA0_NEXT_DESC_PTR, 1624a07a124198153540f8f43d9e91d16227aba66eRoy Huang (struct dma_register *) DMA1_NEXT_DESC_PTR, 1724a07a124198153540f8f43d9e91d16227aba66eRoy Huang (struct dma_register *) DMA2_NEXT_DESC_PTR, 1824a07a124198153540f8f43d9e91d16227aba66eRoy Huang (struct dma_register *) DMA3_NEXT_DESC_PTR, 1924a07a124198153540f8f43d9e91d16227aba66eRoy Huang (struct dma_register *) DMA4_NEXT_DESC_PTR, 2024a07a124198153540f8f43d9e91d16227aba66eRoy Huang (struct dma_register *) DMA5_NEXT_DESC_PTR, 2124a07a124198153540f8f43d9e91d16227aba66eRoy Huang (struct dma_register *) DMA6_NEXT_DESC_PTR, 2224a07a124198153540f8f43d9e91d16227aba66eRoy Huang (struct dma_register *) DMA7_NEXT_DESC_PTR, 2324a07a124198153540f8f43d9e91d16227aba66eRoy Huang (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, 2424a07a124198153540f8f43d9e91d16227aba66eRoy Huang (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, 2524a07a124198153540f8f43d9e91d16227aba66eRoy Huang (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, 2624a07a124198153540f8f43d9e91d16227aba66eRoy Huang (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, 2724a07a124198153540f8f43d9e91d16227aba66eRoy Huang}; 287795566495ff90c541a4654d3c903ab277abadfdBernd SchmidtEXPORT_SYMBOL(dma_io_base_addr); 2924a07a124198153540f8f43d9e91d16227aba66eRoy Huang 30f8ffe652a01506e85e2dd579c58e50a3ba391921Mike Frysingerint channel2irq(unsigned int channel) 3124a07a124198153540f8f43d9e91d16227aba66eRoy Huang{ 3224a07a124198153540f8f43d9e91d16227aba66eRoy Huang int ret_irq = -1; 3324a07a124198153540f8f43d9e91d16227aba66eRoy Huang 3424a07a124198153540f8f43d9e91d16227aba66eRoy Huang switch (channel) { 3524a07a124198153540f8f43d9e91d16227aba66eRoy Huang case CH_PPI: 3624a07a124198153540f8f43d9e91d16227aba66eRoy Huang ret_irq = IRQ_PPI; 3724a07a124198153540f8f43d9e91d16227aba66eRoy Huang break; 3824a07a124198153540f8f43d9e91d16227aba66eRoy Huang 3924a07a124198153540f8f43d9e91d16227aba66eRoy Huang case CH_SPORT0_RX: 4024a07a124198153540f8f43d9e91d16227aba66eRoy Huang ret_irq = IRQ_SPORT0_RX; 4124a07a124198153540f8f43d9e91d16227aba66eRoy Huang break; 4224a07a124198153540f8f43d9e91d16227aba66eRoy Huang 4324a07a124198153540f8f43d9e91d16227aba66eRoy Huang case CH_SPORT0_TX: 4424a07a124198153540f8f43d9e91d16227aba66eRoy Huang ret_irq = IRQ_SPORT0_TX; 4524a07a124198153540f8f43d9e91d16227aba66eRoy Huang break; 4624a07a124198153540f8f43d9e91d16227aba66eRoy Huang 4724a07a124198153540f8f43d9e91d16227aba66eRoy Huang case CH_SPORT1_RX: 4824a07a124198153540f8f43d9e91d16227aba66eRoy Huang ret_irq = IRQ_SPORT1_RX; 4924a07a124198153540f8f43d9e91d16227aba66eRoy Huang break; 5024a07a124198153540f8f43d9e91d16227aba66eRoy Huang 5124a07a124198153540f8f43d9e91d16227aba66eRoy Huang case CH_SPORT1_TX: 5224a07a124198153540f8f43d9e91d16227aba66eRoy Huang ret_irq = IRQ_SPORT1_TX; 5324a07a124198153540f8f43d9e91d16227aba66eRoy Huang break; 5424a07a124198153540f8f43d9e91d16227aba66eRoy Huang 5524a07a124198153540f8f43d9e91d16227aba66eRoy Huang case CH_SPI: 5624a07a124198153540f8f43d9e91d16227aba66eRoy Huang ret_irq = IRQ_SPI; 5724a07a124198153540f8f43d9e91d16227aba66eRoy Huang break; 5824a07a124198153540f8f43d9e91d16227aba66eRoy Huang 598d71e075966e29232cd38d8ca6335047a164c1dcMike Frysinger case CH_UART0_RX: 608d71e075966e29232cd38d8ca6335047a164c1dcMike Frysinger ret_irq = IRQ_UART0_RX; 6124a07a124198153540f8f43d9e91d16227aba66eRoy Huang break; 6224a07a124198153540f8f43d9e91d16227aba66eRoy Huang 638d71e075966e29232cd38d8ca6335047a164c1dcMike Frysinger case CH_UART0_TX: 648d71e075966e29232cd38d8ca6335047a164c1dcMike Frysinger ret_irq = IRQ_UART0_TX; 6524a07a124198153540f8f43d9e91d16227aba66eRoy Huang break; 6624a07a124198153540f8f43d9e91d16227aba66eRoy Huang 6724a07a124198153540f8f43d9e91d16227aba66eRoy Huang case CH_MEM_STREAM0_SRC: 6824a07a124198153540f8f43d9e91d16227aba66eRoy Huang case CH_MEM_STREAM0_DEST: 6924a07a124198153540f8f43d9e91d16227aba66eRoy Huang ret_irq = IRQ_MEM_DMA0; 7024a07a124198153540f8f43d9e91d16227aba66eRoy Huang break; 7124a07a124198153540f8f43d9e91d16227aba66eRoy Huang 7224a07a124198153540f8f43d9e91d16227aba66eRoy Huang case CH_MEM_STREAM1_SRC: 7324a07a124198153540f8f43d9e91d16227aba66eRoy Huang case CH_MEM_STREAM1_DEST: 7424a07a124198153540f8f43d9e91d16227aba66eRoy Huang ret_irq = IRQ_MEM_DMA1; 7524a07a124198153540f8f43d9e91d16227aba66eRoy Huang break; 7624a07a124198153540f8f43d9e91d16227aba66eRoy Huang } 7724a07a124198153540f8f43d9e91d16227aba66eRoy Huang return ret_irq; 7824a07a124198153540f8f43d9e91d16227aba66eRoy Huang} 79