bf533.h revision 0c0497c257c12c9ecb8825490a339bfce8a0532f 
1/*
2 * File:         include/asm-blackfin/mach-bf533/bf533.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:  SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
8 *
9 * Modified:
10 *               Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
28 */
29
30#ifndef __MACH_BF533_H__
31#define __MACH_BF533_H__
32
33#define OFFSET_(x) ((x) & 0x0000FFFF)
34
35/*some misc defines*/
36#define IMASK_IVG15		0x8000
37#define IMASK_IVG14		0x4000
38#define IMASK_IVG13		0x2000
39#define IMASK_IVG12		0x1000
40
41#define IMASK_IVG11		0x0800
42#define IMASK_IVG10		0x0400
43#define IMASK_IVG9		0x0200
44#define IMASK_IVG8		0x0100
45
46#define IMASK_IVG7		0x0080
47#define IMASK_IVGTMR		0x0040
48#define IMASK_IVGHW		0x0020
49
50/***************************/
51
52
53#define BFIN_DSUBBANKS	4
54#define BFIN_DWAYS		2
55#define BFIN_DLINES		64
56#define BFIN_ISUBBANKS	4
57#define BFIN_IWAYS		4
58#define BFIN_ILINES		32
59
60#define WAY0_L			0x1
61#define WAY1_L			0x2
62#define WAY01_L			0x3
63#define WAY2_L			0x4
64#define WAY02_L			0x5
65#define	WAY12_L			0x6
66#define	WAY012_L		0x7
67
68#define	WAY3_L			0x8
69#define	WAY03_L			0x9
70#define	WAY13_L			0xA
71#define	WAY013_L		0xB
72
73#define	WAY32_L			0xC
74#define	WAY320_L		0xD
75#define	WAY321_L		0xE
76#define	WAYALL_L		0xF
77
78#define DMC_ENABLE (2<<2)	/*yes, 2, not 1 */
79
80/* IAR0 BIT FIELDS*/
81#define RTC_ERROR_BIT			0x0FFFFFFF
82#define UART_ERROR_BIT			0xF0FFFFFF
83#define SPORT1_ERROR_BIT		0xFF0FFFFF
84#define SPI_ERROR_BIT			0xFFF0FFFF
85#define SPORT0_ERROR_BIT		0xFFFF0FFF
86#define PPI_ERROR_BIT			0xFFFFF0FF
87#define DMA_ERROR_BIT			0xFFFFFF0F
88#define PLLWAKE_ERROR_BIT		0xFFFFFFFF
89
90/* IAR1 BIT FIELDS*/
91#define DMA7_UARTTX_BIT			0x0FFFFFFF
92#define DMA6_UARTRX_BIT			0xF0FFFFFF
93#define DMA5_SPI_BIT			0xFF0FFFFF
94#define DMA4_SPORT1TX_BIT		0xFFF0FFFF
95#define DMA3_SPORT1RX_BIT		0xFFFF0FFF
96#define DMA2_SPORT0TX_BIT		0xFFFFF0FF
97#define DMA1_SPORT0RX_BIT		0xFFFFFF0F
98#define DMA0_PPI_BIT			0xFFFFFFFF
99
100/* IAR2 BIT FIELDS*/
101#define WDTIMER_BIT			0x0FFFFFFF
102#define MEMDMA1_BIT			0xF0FFFFFF
103#define MEMDMA0_BIT			0xFF0FFFFF
104#define PFB_BIT				0xFFF0FFFF
105#define PFA_BIT				0xFFFF0FFF
106#define TIMER2_BIT			0xFFFFF0FF
107#define TIMER1_BIT			0xFFFFFF0F
108#define TIMER0_BIT		        0xFFFFFFFF
109
110/********************************* EBIU Settings ************************************/
111#define AMBCTL0VAL	((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
112#define AMBCTL1VAL	((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
113
114#ifdef CONFIG_C_AMBEN_ALL
115#define V_AMBEN AMBEN_ALL
116#endif
117#ifdef CONFIG_C_AMBEN
118#define V_AMBEN 0x0
119#endif
120#ifdef CONFIG_C_AMBEN_B0
121#define V_AMBEN AMBEN_B0
122#endif
123#ifdef CONFIG_C_AMBEN_B0_B1
124#define V_AMBEN AMBEN_B0_B1
125#endif
126#ifdef CONFIG_C_AMBEN_B0_B1_B2
127#define V_AMBEN AMBEN_B0_B1_B2
128#endif
129#ifdef CONFIG_C_AMCKEN
130#define V_AMCKEN AMCKEN
131#else
132#define V_AMCKEN 0x0
133#endif
134#ifdef CONFIG_C_CDPRIO
135#define V_CDPRIO 0x100
136#else
137#define V_CDPRIO 0x0
138#endif
139
140#define AMGCTLVAL	(V_AMBEN | V_AMCKEN | V_CDPRIO)
141
142#ifdef CONFIG_BF533
143#define CPU "BF533"
144#define CPUID 0x027a5000
145#endif
146#ifdef CONFIG_BF532
147#define CPU "BF532"
148#define CPUID 0x0275A000
149#endif
150#ifdef CONFIG_BF531
151#define CPU "BF531"
152#define CPUID 0x027a5000
153#endif
154#ifndef CPU
155#define	CPU "UNKNOWN"
156#define CPUID 0x0
157#endif
158
159#endif				/* __MACH_BF533_H__  */
160