1/* 2 * Copyright 2008-2010 Analog Devices Inc. 3 * 4 * Licensed under the ADI BSD license or the GPL-2 (or later) 5 */ 6 7#ifndef _DEF_BF538_H 8#define _DEF_BF538_H 9 10/* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */ 11#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ 12#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ 13#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ 14#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ 15#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ 16#define CHIPID 0xFFC00014 /* Chip ID Register */ 17 18/* CHIPID Masks */ 19#define CHIPID_VERSION 0xF0000000 20#define CHIPID_FAMILY 0x0FFFF000 21#define CHIPID_MANUFACTURE 0x00000FFE 22 23/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ 24#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ 25#define SYSCR 0xFFC00104 /* System Configuration registe */ 26#define SIC_RVECT 0xFFC00108 27#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ 28#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ 29#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ 30#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ 31#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ 32#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ 33#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ 34#define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */ 35#define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */ 36#define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */ 37#define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */ 38#define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */ 39#define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */ 40 41 42/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ 43#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ 44#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ 45#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ 46 47 48/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ 49#define RTC_STAT 0xFFC00300 /* RTC Status Register */ 50#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ 51#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ 52#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ 53#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ 54#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ 55#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ 56 57 58/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ 59#define UART0_THR 0xFFC00400 /* Transmit Holding register */ 60#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ 61#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ 62#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ 63#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ 64#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ 65#define UART0_LCR 0xFFC0040C /* Line Control Register */ 66#define UART0_MCR 0xFFC00410 /* Modem Control Register */ 67#define UART0_LSR 0xFFC00414 /* Line Status Register */ 68#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ 69#define UART0_GCTL 0xFFC00424 /* Global Control Register */ 70 71 72/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */ 73 74#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */ 75#define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */ 76#define SPI0_STAT 0xFFC00508 /* SPI0 Status register */ 77#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */ 78#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */ 79#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */ 80#define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */ 81#define SPI0_REGBASE SPI0_CTL 82 83 84/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */ 85#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ 86#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ 87#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ 88#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ 89 90#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ 91#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ 92#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ 93#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ 94 95#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ 96#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ 97#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ 98#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ 99 100#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ 101#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */ 102#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */ 103 104 105/* Programmable Flags (0xFFC00700 - 0xFFC007FF) */ 106#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */ 107#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */ 108#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */ 109#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */ 110#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */ 111#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */ 112#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */ 113#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */ 114#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */ 115#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */ 116#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */ 117#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */ 118#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */ 119#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */ 120#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */ 121#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */ 122#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */ 123 124 125/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ 126#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ 127#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ 128#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ 129#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ 130#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ 131#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ 132#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ 133#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ 134#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ 135#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ 136#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ 137#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ 138#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ 139#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ 140#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ 141#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ 142#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ 143#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ 144#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ 145#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ 146#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ 147#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ 148 149 150/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ 151#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ 152#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ 153#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ 154#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ 155#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ 156#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ 157#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ 158#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ 159#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ 160#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ 161#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ 162#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ 163#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ 164#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ 165#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ 166#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ 167#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ 168#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ 169#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ 170#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ 171#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ 172#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ 173 174 175/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ 176/* Asynchronous Memory Controller */ 177#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ 178#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ 179#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ 180 181/* SDRAM Controller */ 182#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ 183#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ 184#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ 185#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ 186 187 188 189/* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */ 190 191#define DMAC0_TC_PER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */ 192#define DMAC0_TC_CNT 0xFFC00B10 /* DMA Controller 0 Traffic Control Current Counts Register */ 193 194 195 196/* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF) */ 197 198#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ 199#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ 200#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ 201#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ 202#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ 203#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ 204#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ 205#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ 206#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ 207#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ 208#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ 209#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ 210#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ 211 212#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ 213#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ 214#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ 215#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ 216#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ 217#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ 218#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ 219#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ 220#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ 221#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ 222#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ 223#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ 224#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ 225 226#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ 227#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ 228#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ 229#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ 230#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ 231#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ 232#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ 233#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ 234#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ 235#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ 236#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ 237#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ 238#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ 239 240#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ 241#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ 242#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ 243#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ 244#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ 245#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ 246#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ 247#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ 248#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ 249#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ 250#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ 251#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ 252#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ 253 254#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ 255#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ 256#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ 257#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ 258#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ 259#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ 260#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ 261#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ 262#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ 263#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ 264#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ 265#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ 266#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ 267 268#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ 269#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ 270#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ 271#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ 272#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ 273#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ 274#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ 275#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ 276#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ 277#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ 278#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ 279#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ 280#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ 281 282#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ 283#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ 284#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ 285#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ 286#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ 287#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ 288#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ 289#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ 290#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ 291#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ 292#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ 293#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ 294#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ 295 296#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ 297#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ 298#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ 299#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ 300#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ 301#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ 302#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ 303#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ 304#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ 305#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ 306#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ 307#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ 308#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ 309 310#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */ 311#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA0 Stream 0 Destination Start Address Register */ 312#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA0 Stream 0 Destination Configuration Register */ 313#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA0 Stream 0 Destination X Count Register */ 314#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA0 Stream 0 Destination X Modify Register */ 315#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA0 Stream 0 Destination Y Count Register */ 316#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA0 Stream 0 Destination Y Modify Register */ 317#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */ 318#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA0 Stream 0 Destination Current Address Register */ 319#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA0 Stream 0 Destination Interrupt/Status Register */ 320#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA0 Stream 0 Destination Peripheral Map Register */ 321#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA0 Stream 0 Destination Current X Count Register */ 322#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA0 Stream 0 Destination Current Y Count Register */ 323 324#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */ 325#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA0 Stream 0 Source Start Address Register */ 326#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA0 Stream 0 Source Configuration Register */ 327#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA0 Stream 0 Source X Count Register */ 328#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA0 Stream 0 Source X Modify Register */ 329#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA0 Stream 0 Source Y Count Register */ 330#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA0 Stream 0 Source Y Modify Register */ 331#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */ 332#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA0 Stream 0 Source Current Address Register */ 333#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA0 Stream 0 Source Interrupt/Status Register */ 334#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA0 Stream 0 Source Peripheral Map Register */ 335#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA0 Stream 0 Source Current X Count Register */ 336#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA0 Stream 0 Source Current Y Count Register */ 337 338#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */ 339#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA0 Stream 1 Destination Start Address Register */ 340#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA0 Stream 1 Destination Configuration Register */ 341#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA0 Stream 1 Destination X Count Register */ 342#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA0 Stream 1 Destination X Modify Register */ 343#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA0 Stream 1 Destination Y Count Register */ 344#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA0 Stream 1 Destination Y Modify Register */ 345#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */ 346#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA0 Stream 1 Destination Current Address Register */ 347#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA0 Stream 1 Destination Interrupt/Status Register */ 348#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA0 Stream 1 Destination Peripheral Map Register */ 349#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA0 Stream 1 Destination Current X Count Register */ 350#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA0 Stream 1 Destination Current Y Count Register */ 351 352#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */ 353#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA0 Stream 1 Source Start Address Register */ 354#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA0 Stream 1 Source Configuration Register */ 355#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA0 Stream 1 Source X Count Register */ 356#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA0 Stream 1 Source X Modify Register */ 357#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA0 Stream 1 Source Y Count Register */ 358#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA0 Stream 1 Source Y Modify Register */ 359#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */ 360#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA0 Stream 1 Source Current Address Register */ 361#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA0 Stream 1 Source Interrupt/Status Register */ 362#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA0 Stream 1 Source Peripheral Map Register */ 363#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */ 364#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */ 365 366 367/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ 368#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ 369#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ 370#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ 371#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ 372#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ 373 374 375/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */ 376#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ 377#define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */ 378#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ 379#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ 380#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ 381#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ 382#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ 383#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ 384#define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */ 385#define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */ 386#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ 387#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ 388#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ 389#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ 390#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ 391#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ 392 393#define TWI0_REGBASE TWI0_CLKDIV 394 395/* the following are for backwards compatibility */ 396#define TWI0_PRESCALE TWI0_CONTROL 397#define TWI0_INT_SRC TWI0_INT_STAT 398#define TWI0_INT_ENABLE TWI0_INT_MASK 399 400 401/* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */ 402 403/* GPIO Port C Register Names */ 404#define PORTCIO_FER 0xFFC01500 /* GPIO Pin Port C Configuration Register */ 405#define PORTCIO 0xFFC01510 /* GPIO Pin Port C Data Register */ 406#define PORTCIO_CLEAR 0xFFC01520 /* Clear GPIO Pin Port C Register */ 407#define PORTCIO_SET 0xFFC01530 /* Set GPIO Pin Port C Register */ 408#define PORTCIO_TOGGLE 0xFFC01540 /* Toggle GPIO Pin Port C Register */ 409#define PORTCIO_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */ 410#define PORTCIO_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */ 411 412/* GPIO Port D Register Names */ 413#define PORTDIO_FER 0xFFC01504 /* GPIO Pin Port D Configuration Register */ 414#define PORTDIO 0xFFC01514 /* GPIO Pin Port D Data Register */ 415#define PORTDIO_CLEAR 0xFFC01524 /* Clear GPIO Pin Port D Register */ 416#define PORTDIO_SET 0xFFC01534 /* Set GPIO Pin Port D Register */ 417#define PORTDIO_TOGGLE 0xFFC01544 /* Toggle GPIO Pin Port D Register */ 418#define PORTDIO_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */ 419#define PORTDIO_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */ 420 421/* GPIO Port E Register Names */ 422#define PORTEIO_FER 0xFFC01508 /* GPIO Pin Port E Configuration Register */ 423#define PORTEIO 0xFFC01518 /* GPIO Pin Port E Data Register */ 424#define PORTEIO_CLEAR 0xFFC01528 /* Clear GPIO Pin Port E Register */ 425#define PORTEIO_SET 0xFFC01538 /* Set GPIO Pin Port E Register */ 426#define PORTEIO_TOGGLE 0xFFC01548 /* Toggle GPIO Pin Port E Register */ 427#define PORTEIO_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */ 428#define PORTEIO_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */ 429 430/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */ 431 432#define DMAC1_TC_PER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */ 433#define DMAC1_TC_CNT 0xFFC01B10 /* DMA Controller 1 Traffic Control Current Counts Register */ 434 435 436 437/* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF) */ 438#define DMA8_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 8 Next Descriptor Pointer Register */ 439#define DMA8_START_ADDR 0xFFC01C04 /* DMA Channel 8 Start Address Register */ 440#define DMA8_CONFIG 0xFFC01C08 /* DMA Channel 8 Configuration Register */ 441#define DMA8_X_COUNT 0xFFC01C10 /* DMA Channel 8 X Count Register */ 442#define DMA8_X_MODIFY 0xFFC01C14 /* DMA Channel 8 X Modify Register */ 443#define DMA8_Y_COUNT 0xFFC01C18 /* DMA Channel 8 Y Count Register */ 444#define DMA8_Y_MODIFY 0xFFC01C1C /* DMA Channel 8 Y Modify Register */ 445#define DMA8_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 8 Current Descriptor Pointer Register */ 446#define DMA8_CURR_ADDR 0xFFC01C24 /* DMA Channel 8 Current Address Register */ 447#define DMA8_IRQ_STATUS 0xFFC01C28 /* DMA Channel 8 Interrupt/Status Register */ 448#define DMA8_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 8 Peripheral Map Register */ 449#define DMA8_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 8 Current X Count Register */ 450#define DMA8_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 8 Current Y Count Register */ 451 452#define DMA9_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 9 Next Descriptor Pointer Register */ 453#define DMA9_START_ADDR 0xFFC01C44 /* DMA Channel 9 Start Address Register */ 454#define DMA9_CONFIG 0xFFC01C48 /* DMA Channel 9 Configuration Register */ 455#define DMA9_X_COUNT 0xFFC01C50 /* DMA Channel 9 X Count Register */ 456#define DMA9_X_MODIFY 0xFFC01C54 /* DMA Channel 9 X Modify Register */ 457#define DMA9_Y_COUNT 0xFFC01C58 /* DMA Channel 9 Y Count Register */ 458#define DMA9_Y_MODIFY 0xFFC01C5C /* DMA Channel 9 Y Modify Register */ 459#define DMA9_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 9 Current Descriptor Pointer Register */ 460#define DMA9_CURR_ADDR 0xFFC01C64 /* DMA Channel 9 Current Address Register */ 461#define DMA9_IRQ_STATUS 0xFFC01C68 /* DMA Channel 9 Interrupt/Status Register */ 462#define DMA9_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 9 Peripheral Map Register */ 463#define DMA9_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 9 Current X Count Register */ 464#define DMA9_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 9 Current Y Count Register */ 465 466#define DMA10_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 10 Next Descriptor Pointer Register */ 467#define DMA10_START_ADDR 0xFFC01C84 /* DMA Channel 10 Start Address Register */ 468#define DMA10_CONFIG 0xFFC01C88 /* DMA Channel 10 Configuration Register */ 469#define DMA10_X_COUNT 0xFFC01C90 /* DMA Channel 10 X Count Register */ 470#define DMA10_X_MODIFY 0xFFC01C94 /* DMA Channel 10 X Modify Register */ 471#define DMA10_Y_COUNT 0xFFC01C98 /* DMA Channel 10 Y Count Register */ 472#define DMA10_Y_MODIFY 0xFFC01C9C /* DMA Channel 10 Y Modify Register */ 473#define DMA10_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 10 Current Descriptor Pointer Register */ 474#define DMA10_CURR_ADDR 0xFFC01CA4 /* DMA Channel 10 Current Address Register */ 475#define DMA10_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 10 Interrupt/Status Register */ 476#define DMA10_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 10 Peripheral Map Register */ 477#define DMA10_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 10 Current X Count Register */ 478#define DMA10_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 10 Current Y Count Register */ 479 480#define DMA11_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 11 Next Descriptor Pointer Register */ 481#define DMA11_START_ADDR 0xFFC01CC4 /* DMA Channel 11 Start Address Register */ 482#define DMA11_CONFIG 0xFFC01CC8 /* DMA Channel 11 Configuration Register */ 483#define DMA11_X_COUNT 0xFFC01CD0 /* DMA Channel 11 X Count Register */ 484#define DMA11_X_MODIFY 0xFFC01CD4 /* DMA Channel 11 X Modify Register */ 485#define DMA11_Y_COUNT 0xFFC01CD8 /* DMA Channel 11 Y Count Register */ 486#define DMA11_Y_MODIFY 0xFFC01CDC /* DMA Channel 11 Y Modify Register */ 487#define DMA11_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 11 Current Descriptor Pointer Register */ 488#define DMA11_CURR_ADDR 0xFFC01CE4 /* DMA Channel 11 Current Address Register */ 489#define DMA11_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 11 Interrupt/Status Register */ 490#define DMA11_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 11 Peripheral Map Register */ 491#define DMA11_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 11 Current X Count Register */ 492#define DMA11_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 11 Current Y Count Register */ 493 494#define DMA12_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 12 Next Descriptor Pointer Register */ 495#define DMA12_START_ADDR 0xFFC01D04 /* DMA Channel 12 Start Address Register */ 496#define DMA12_CONFIG 0xFFC01D08 /* DMA Channel 12 Configuration Register */ 497#define DMA12_X_COUNT 0xFFC01D10 /* DMA Channel 12 X Count Register */ 498#define DMA12_X_MODIFY 0xFFC01D14 /* DMA Channel 12 X Modify Register */ 499#define DMA12_Y_COUNT 0xFFC01D18 /* DMA Channel 12 Y Count Register */ 500#define DMA12_Y_MODIFY 0xFFC01D1C /* DMA Channel 12 Y Modify Register */ 501#define DMA12_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 12 Current Descriptor Pointer Register */ 502#define DMA12_CURR_ADDR 0xFFC01D24 /* DMA Channel 12 Current Address Register */ 503#define DMA12_IRQ_STATUS 0xFFC01D28 /* DMA Channel 12 Interrupt/Status Register */ 504#define DMA12_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 12 Peripheral Map Register */ 505#define DMA12_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 12 Current X Count Register */ 506#define DMA12_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 12 Current Y Count Register */ 507 508#define DMA13_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 13 Next Descriptor Pointer Register */ 509#define DMA13_START_ADDR 0xFFC01D44 /* DMA Channel 13 Start Address Register */ 510#define DMA13_CONFIG 0xFFC01D48 /* DMA Channel 13 Configuration Register */ 511#define DMA13_X_COUNT 0xFFC01D50 /* DMA Channel 13 X Count Register */ 512#define DMA13_X_MODIFY 0xFFC01D54 /* DMA Channel 13 X Modify Register */ 513#define DMA13_Y_COUNT 0xFFC01D58 /* DMA Channel 13 Y Count Register */ 514#define DMA13_Y_MODIFY 0xFFC01D5C /* DMA Channel 13 Y Modify Register */ 515#define DMA13_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 13 Current Descriptor Pointer Register */ 516#define DMA13_CURR_ADDR 0xFFC01D64 /* DMA Channel 13 Current Address Register */ 517#define DMA13_IRQ_STATUS 0xFFC01D68 /* DMA Channel 13 Interrupt/Status Register */ 518#define DMA13_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 13 Peripheral Map Register */ 519#define DMA13_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 13 Current X Count Register */ 520#define DMA13_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 13 Current Y Count Register */ 521 522#define DMA14_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 14 Next Descriptor Pointer Register */ 523#define DMA14_START_ADDR 0xFFC01D84 /* DMA Channel 14 Start Address Register */ 524#define DMA14_CONFIG 0xFFC01D88 /* DMA Channel 14 Configuration Register */ 525#define DMA14_X_COUNT 0xFFC01D90 /* DMA Channel 14 X Count Register */ 526#define DMA14_X_MODIFY 0xFFC01D94 /* DMA Channel 14 X Modify Register */ 527#define DMA14_Y_COUNT 0xFFC01D98 /* DMA Channel 14 Y Count Register */ 528#define DMA14_Y_MODIFY 0xFFC01D9C /* DMA Channel 14 Y Modify Register */ 529#define DMA14_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 14 Current Descriptor Pointer Register */ 530#define DMA14_CURR_ADDR 0xFFC01DA4 /* DMA Channel 14 Current Address Register */ 531#define DMA14_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 14 Interrupt/Status Register */ 532#define DMA14_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 14 Peripheral Map Register */ 533#define DMA14_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 14 Current X Count Register */ 534#define DMA14_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 14 Current Y Count Register */ 535 536#define DMA15_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 15 Next Descriptor Pointer Register */ 537#define DMA15_START_ADDR 0xFFC01DC4 /* DMA Channel 15 Start Address Register */ 538#define DMA15_CONFIG 0xFFC01DC8 /* DMA Channel 15 Configuration Register */ 539#define DMA15_X_COUNT 0xFFC01DD0 /* DMA Channel 15 X Count Register */ 540#define DMA15_X_MODIFY 0xFFC01DD4 /* DMA Channel 15 X Modify Register */ 541#define DMA15_Y_COUNT 0xFFC01DD8 /* DMA Channel 15 Y Count Register */ 542#define DMA15_Y_MODIFY 0xFFC01DDC /* DMA Channel 15 Y Modify Register */ 543#define DMA15_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 15 Current Descriptor Pointer Register */ 544#define DMA15_CURR_ADDR 0xFFC01DE4 /* DMA Channel 15 Current Address Register */ 545#define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */ 546#define DMA15_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 15 Peripheral Map Register */ 547#define DMA15_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 15 Current X Count Register */ 548#define DMA15_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 15 Current Y Count Register */ 549 550#define DMA16_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 16 Next Descriptor Pointer Register */ 551#define DMA16_START_ADDR 0xFFC01E04 /* DMA Channel 16 Start Address Register */ 552#define DMA16_CONFIG 0xFFC01E08 /* DMA Channel 16 Configuration Register */ 553#define DMA16_X_COUNT 0xFFC01E10 /* DMA Channel 16 X Count Register */ 554#define DMA16_X_MODIFY 0xFFC01E14 /* DMA Channel 16 X Modify Register */ 555#define DMA16_Y_COUNT 0xFFC01E18 /* DMA Channel 16 Y Count Register */ 556#define DMA16_Y_MODIFY 0xFFC01E1C /* DMA Channel 16 Y Modify Register */ 557#define DMA16_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 16 Current Descriptor Pointer Register */ 558#define DMA16_CURR_ADDR 0xFFC01E24 /* DMA Channel 16 Current Address Register */ 559#define DMA16_IRQ_STATUS 0xFFC01E28 /* DMA Channel 16 Interrupt/Status Register */ 560#define DMA16_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 16 Peripheral Map Register */ 561#define DMA16_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 16 Current X Count Register */ 562#define DMA16_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 16 Current Y Count Register */ 563 564#define DMA17_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 17 Next Descriptor Pointer Register */ 565#define DMA17_START_ADDR 0xFFC01E44 /* DMA Channel 17 Start Address Register */ 566#define DMA17_CONFIG 0xFFC01E48 /* DMA Channel 17 Configuration Register */ 567#define DMA17_X_COUNT 0xFFC01E50 /* DMA Channel 17 X Count Register */ 568#define DMA17_X_MODIFY 0xFFC01E54 /* DMA Channel 17 X Modify Register */ 569#define DMA17_Y_COUNT 0xFFC01E58 /* DMA Channel 17 Y Count Register */ 570#define DMA17_Y_MODIFY 0xFFC01E5C /* DMA Channel 17 Y Modify Register */ 571#define DMA17_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 17 Current Descriptor Pointer Register */ 572#define DMA17_CURR_ADDR 0xFFC01E64 /* DMA Channel 17 Current Address Register */ 573#define DMA17_IRQ_STATUS 0xFFC01E68 /* DMA Channel 17 Interrupt/Status Register */ 574#define DMA17_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 17 Peripheral Map Register */ 575#define DMA17_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 17 Current X Count Register */ 576#define DMA17_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 17 Current Y Count Register */ 577 578#define DMA18_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 18 Next Descriptor Pointer Register */ 579#define DMA18_START_ADDR 0xFFC01E84 /* DMA Channel 18 Start Address Register */ 580#define DMA18_CONFIG 0xFFC01E88 /* DMA Channel 18 Configuration Register */ 581#define DMA18_X_COUNT 0xFFC01E90 /* DMA Channel 18 X Count Register */ 582#define DMA18_X_MODIFY 0xFFC01E94 /* DMA Channel 18 X Modify Register */ 583#define DMA18_Y_COUNT 0xFFC01E98 /* DMA Channel 18 Y Count Register */ 584#define DMA18_Y_MODIFY 0xFFC01E9C /* DMA Channel 18 Y Modify Register */ 585#define DMA18_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 18 Current Descriptor Pointer Register */ 586#define DMA18_CURR_ADDR 0xFFC01EA4 /* DMA Channel 18 Current Address Register */ 587#define DMA18_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 18 Interrupt/Status Register */ 588#define DMA18_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 18 Peripheral Map Register */ 589#define DMA18_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 18 Current X Count Register */ 590#define DMA18_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 18 Current Y Count Register */ 591 592#define DMA19_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 19 Next Descriptor Pointer Register */ 593#define DMA19_START_ADDR 0xFFC01EC4 /* DMA Channel 19 Start Address Register */ 594#define DMA19_CONFIG 0xFFC01EC8 /* DMA Channel 19 Configuration Register */ 595#define DMA19_X_COUNT 0xFFC01ED0 /* DMA Channel 19 X Count Register */ 596#define DMA19_X_MODIFY 0xFFC01ED4 /* DMA Channel 19 X Modify Register */ 597#define DMA19_Y_COUNT 0xFFC01ED8 /* DMA Channel 19 Y Count Register */ 598#define DMA19_Y_MODIFY 0xFFC01EDC /* DMA Channel 19 Y Modify Register */ 599#define DMA19_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 19 Current Descriptor Pointer Register */ 600#define DMA19_CURR_ADDR 0xFFC01EE4 /* DMA Channel 19 Current Address Register */ 601#define DMA19_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 19 Interrupt/Status Register */ 602#define DMA19_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 19 Peripheral Map Register */ 603#define DMA19_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 19 Current X Count Register */ 604#define DMA19_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 19 Current Y Count Register */ 605 606#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */ 607#define MDMA_D2_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address Register */ 608#define MDMA_D2_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration Register */ 609#define MDMA_D2_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination X Count Register */ 610#define MDMA_D2_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Destination X Modify Register */ 611#define MDMA_D2_Y_COUNT 0xFFC01F18 /* MemDMA1 Stream 0 Destination Y Count Register */ 612#define MDMA_D2_Y_MODIFY 0xFFC01F1C /* MemDMA1 Stream 0 Destination Y Modify Register */ 613#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */ 614#define MDMA_D2_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address Register */ 615#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register */ 616#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map Register */ 617#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Destination Current X Count Register */ 618#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Destination Current Y Count Register */ 619 620#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */ 621#define MDMA_S2_START_ADDR 0xFFC01F44 /* MemDMA1 Stream 0 Source Start Address Register */ 622#define MDMA_S2_CONFIG 0xFFC01F48 /* MemDMA1 Stream 0 Source Configuration Register */ 623#define MDMA_S2_X_COUNT 0xFFC01F50 /* MemDMA1 Stream 0 Source X Count Register */ 624#define MDMA_S2_X_MODIFY 0xFFC01F54 /* MemDMA1 Stream 0 Source X Modify Register */ 625#define MDMA_S2_Y_COUNT 0xFFC01F58 /* MemDMA1 Stream 0 Source Y Count Register */ 626#define MDMA_S2_Y_MODIFY 0xFFC01F5C /* MemDMA1 Stream 0 Source Y Modify Register */ 627#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */ 628#define MDMA_S2_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address Register */ 629#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status Register */ 630#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map Register */ 631#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current X Count Register */ 632#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Y Count Register */ 633 634#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */ 635#define MDMA_D3_START_ADDR 0xFFC01F84 /* MemDMA1 Stream 1 Destination Start Address Register */ 636#define MDMA_D3_CONFIG 0xFFC01F88 /* MemDMA1 Stream 1 Destination Configuration Register */ 637#define MDMA_D3_X_COUNT 0xFFC01F90 /* MemDMA1 Stream 1 Destination X Count Register */ 638#define MDMA_D3_X_MODIFY 0xFFC01F94 /* MemDMA1 Stream 1 Destination X Modify Register */ 639#define MDMA_D3_Y_COUNT 0xFFC01F98 /* MemDMA1 Stream 1 Destination Y Count Register */ 640#define MDMA_D3_Y_MODIFY 0xFFC01F9C /* MemDMA1 Stream 1 Destination Y Modify Register */ 641#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */ 642#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Destination Current Address Register */ 643#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Destination Interrupt/Status Register */ 644#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Destination Peripheral Map Register */ 645#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Destination Current X Count Register */ 646#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Destination Current Y Count Register */ 647 648#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */ 649#define MDMA_S3_START_ADDR 0xFFC01FC4 /* MemDMA1 Stream 1 Source Start Address Register */ 650#define MDMA_S3_CONFIG 0xFFC01FC8 /* MemDMA1 Stream 1 Source Configuration Register */ 651#define MDMA_S3_X_COUNT 0xFFC01FD0 /* MemDMA1 Stream 1 Source X Count Register */ 652#define MDMA_S3_X_MODIFY 0xFFC01FD4 /* MemDMA1 Stream 1 Source X Modify Register */ 653#define MDMA_S3_Y_COUNT 0xFFC01FD8 /* MemDMA1 Stream 1 Source Y Count Register */ 654#define MDMA_S3_Y_MODIFY 0xFFC01FDC /* MemDMA1 Stream 1 Source Y Modify Register */ 655#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */ 656#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address Register */ 657#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status Register */ 658#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map Register */ 659#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current X Count Register */ 660#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Y Count Register */ 661 662 663/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ 664#define UART1_THR 0xFFC02000 /* Transmit Holding register */ 665#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ 666#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ 667#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ 668#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ 669#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ 670#define UART1_LCR 0xFFC0200C /* Line Control Register */ 671#define UART1_MCR 0xFFC02010 /* Modem Control Register */ 672#define UART1_LSR 0xFFC02014 /* Line Status Register */ 673#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ 674#define UART1_GCTL 0xFFC02024 /* Global Control Register */ 675 676 677/* UART2 Controller (0xFFC02100 - 0xFFC021FF) */ 678#define UART2_THR 0xFFC02100 /* Transmit Holding register */ 679#define UART2_RBR 0xFFC02100 /* Receive Buffer register */ 680#define UART2_DLL 0xFFC02100 /* Divisor Latch (Low-Byte) */ 681#define UART2_IER 0xFFC02104 /* Interrupt Enable Register */ 682#define UART2_DLH 0xFFC02104 /* Divisor Latch (High-Byte) */ 683#define UART2_IIR 0xFFC02108 /* Interrupt Identification Register */ 684#define UART2_LCR 0xFFC0210C /* Line Control Register */ 685#define UART2_MCR 0xFFC02110 /* Modem Control Register */ 686#define UART2_LSR 0xFFC02114 /* Line Status Register */ 687#define UART2_SCR 0xFFC0211C /* SCR Scratch Register */ 688#define UART2_GCTL 0xFFC02124 /* Global Control Register */ 689 690 691/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */ 692#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */ 693#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */ 694#define TWI1_SLAVE_CTL 0xFFC02208 /* Slave Mode Control Register */ 695#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */ 696#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */ 697#define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */ 698#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */ 699#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */ 700#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */ 701#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */ 702#define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */ 703#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */ 704#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */ 705#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */ 706#define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */ 707#define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */ 708#define TWI1_REGBASE TWI1_CLKDIV 709 710 711/* the following are for backwards compatibility */ 712#define TWI1_PRESCALE TWI1_CONTROL 713#define TWI1_INT_SRC TWI1_INT_STAT 714#define TWI1_INT_ENABLE TWI1_INT_MASK 715 716 717/* SPI1 Controller (0xFFC02300 - 0xFFC023FF) */ 718#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */ 719#define SPI1_FLG 0xFFC02304 /* SPI1 Flag register */ 720#define SPI1_STAT 0xFFC02308 /* SPI1 Status register */ 721#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */ 722#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */ 723#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud rate Register */ 724#define SPI1_SHADOW 0xFFC02318 /* SPI1_RDBR Shadow Register */ 725#define SPI1_REGBASE SPI1_CTL 726 727/* SPI2 Controller (0xFFC02400 - 0xFFC024FF) */ 728#define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */ 729#define SPI2_FLG 0xFFC02404 /* SPI2 Flag register */ 730#define SPI2_STAT 0xFFC02408 /* SPI2 Status register */ 731#define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */ 732#define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */ 733#define SPI2_BAUD 0xFFC02414 /* SPI2 Baud rate Register */ 734#define SPI2_SHADOW 0xFFC02418 /* SPI2_RDBR Shadow Register */ 735#define SPI2_REGBASE SPI2_CTL 736 737/* SPORT2 Controller (0xFFC02500 - 0xFFC025FF) */ 738#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */ 739#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */ 740#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Clock Divider */ 741#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider */ 742#define SPORT2_TX 0xFFC02510 /* SPORT2 TX Data Register */ 743#define SPORT2_RX 0xFFC02518 /* SPORT2 RX Data Register */ 744#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Transmit Configuration 1 Register */ 745#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Transmit Configuration 2 Register */ 746#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Clock Divider */ 747#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider */ 748#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */ 749#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */ 750#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi-Channel Configuration Register 1 */ 751#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi-Channel Configuration Register 2 */ 752#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi-Channel Transmit Select Register 0 */ 753#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi-Channel Transmit Select Register 1 */ 754#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi-Channel Transmit Select Register 2 */ 755#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi-Channel Transmit Select Register 3 */ 756#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi-Channel Receive Select Register 0 */ 757#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi-Channel Receive Select Register 1 */ 758#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi-Channel Receive Select Register 2 */ 759#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi-Channel Receive Select Register 3 */ 760 761 762/* SPORT3 Controller (0xFFC02600 - 0xFFC026FF) */ 763#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */ 764#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */ 765#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Clock Divider */ 766#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider */ 767#define SPORT3_TX 0xFFC02610 /* SPORT3 TX Data Register */ 768#define SPORT3_RX 0xFFC02618 /* SPORT3 RX Data Register */ 769#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Transmit Configuration 1 Register */ 770#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Transmit Configuration 2 Register */ 771#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Clock Divider */ 772#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider */ 773#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */ 774#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */ 775#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi-Channel Configuration Register 1 */ 776#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi-Channel Configuration Register 2 */ 777#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi-Channel Transmit Select Register 0 */ 778#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi-Channel Transmit Select Register 1 */ 779#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi-Channel Transmit Select Register 2 */ 780#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi-Channel Transmit Select Register 3 */ 781#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi-Channel Receive Select Register 0 */ 782#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi-Channel Receive Select Register 1 */ 783#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi-Channel Receive Select Register 2 */ 784#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi-Channel Receive Select Register 3 */ 785 786 787/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */ 788/* For Mailboxes 0-15 */ 789#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */ 790#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */ 791#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */ 792#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */ 793#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */ 794#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */ 795#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */ 796#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */ 797#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */ 798#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */ 799#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */ 800#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */ 801#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */ 802 803/* For Mailboxes 16-31 */ 804#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */ 805#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */ 806#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */ 807#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */ 808#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */ 809#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */ 810#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */ 811#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */ 812#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */ 813#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */ 814#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */ 815#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */ 816#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */ 817 818#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */ 819#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */ 820 821#define CAN_DEBUG 0xFFC02A88 /* Debug Register */ 822/* the following is for backwards compatibility */ 823#define CAN_CNF CAN_DEBUG 824 825#define CAN_STATUS 0xFFC02A8C /* Global Status Register */ 826#define CAN_CEC 0xFFC02A90 /* Error Counter Register */ 827#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */ 828#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */ 829#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */ 830#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */ 831#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */ 832#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */ 833#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */ 834#define CAN_ESR 0xFFC02AB4 /* Error Status Register */ 835#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */ 836#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Reload/Capture Register */ 837#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */ 838 839/* Mailbox Acceptance Masks */ 840#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */ 841#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */ 842#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */ 843#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */ 844#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */ 845#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */ 846#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */ 847#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */ 848#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */ 849#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */ 850#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */ 851#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */ 852#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */ 853#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */ 854#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */ 855#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */ 856#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */ 857#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */ 858#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */ 859#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */ 860#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */ 861#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */ 862#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */ 863#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */ 864#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */ 865#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */ 866#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */ 867#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */ 868#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */ 869#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */ 870#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */ 871#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */ 872 873#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */ 874#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */ 875#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */ 876#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */ 877#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */ 878#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */ 879#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */ 880#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */ 881#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */ 882#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */ 883#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */ 884#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */ 885#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */ 886#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */ 887#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */ 888#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */ 889#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */ 890#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */ 891#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */ 892#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */ 893#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */ 894#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */ 895#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */ 896#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */ 897#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */ 898#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */ 899#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */ 900#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */ 901#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */ 902#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */ 903#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */ 904#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */ 905 906/* CAN Acceptance Mask Macros */ 907#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8)) 908#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8)) 909 910/* Mailbox Registers */ 911#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */ 912#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */ 913#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */ 914#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */ 915#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */ 916#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */ 917#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */ 918#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */ 919 920#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */ 921#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */ 922#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */ 923#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */ 924#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */ 925#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */ 926#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */ 927#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */ 928 929#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */ 930#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */ 931#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */ 932#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */ 933#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */ 934#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */ 935#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */ 936#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */ 937 938#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */ 939#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */ 940#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */ 941#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */ 942#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */ 943#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */ 944#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */ 945#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */ 946 947#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */ 948#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */ 949#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */ 950#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */ 951#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */ 952#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */ 953#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */ 954#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */ 955 956#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */ 957#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */ 958#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */ 959#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */ 960#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */ 961#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */ 962#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */ 963#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */ 964 965#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */ 966#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */ 967#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */ 968#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */ 969#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */ 970#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */ 971#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */ 972#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */ 973 974#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */ 975#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */ 976#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */ 977#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */ 978#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */ 979#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */ 980#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */ 981#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */ 982 983#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */ 984#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */ 985#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */ 986#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */ 987#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */ 988#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */ 989#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */ 990#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */ 991 992#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */ 993#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */ 994#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */ 995#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */ 996#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */ 997#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */ 998#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */ 999#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */ 1000 1001#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */ 1002#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */ 1003#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */ 1004#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */ 1005#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */ 1006#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */ 1007#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */ 1008#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */ 1009 1010#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */ 1011#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */ 1012#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */ 1013#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */ 1014#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */ 1015#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */ 1016#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */ 1017#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */ 1018 1019#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */ 1020#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */ 1021#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */ 1022#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */ 1023#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */ 1024#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */ 1025#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */ 1026#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */ 1027 1028#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */ 1029#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */ 1030#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */ 1031#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */ 1032#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */ 1033#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */ 1034#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */ 1035#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */ 1036 1037#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */ 1038#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */ 1039#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */ 1040#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */ 1041#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */ 1042#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */ 1043#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */ 1044#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */ 1045 1046#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */ 1047#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */ 1048#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */ 1049#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */ 1050#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */ 1051#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */ 1052#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */ 1053#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */ 1054 1055#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */ 1056#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */ 1057#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */ 1058#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */ 1059#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */ 1060#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */ 1061#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */ 1062#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */ 1063 1064#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */ 1065#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */ 1066#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */ 1067#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */ 1068#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */ 1069#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */ 1070#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */ 1071#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */ 1072 1073#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */ 1074#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */ 1075#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */ 1076#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */ 1077#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */ 1078#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */ 1079#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */ 1080#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */ 1081 1082#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */ 1083#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */ 1084#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */ 1085#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */ 1086#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */ 1087#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */ 1088#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */ 1089#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */ 1090 1091#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */ 1092#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */ 1093#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */ 1094#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */ 1095#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */ 1096#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */ 1097#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */ 1098#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */ 1099 1100#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */ 1101#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */ 1102#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */ 1103#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */ 1104#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */ 1105#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */ 1106#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */ 1107#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */ 1108 1109#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */ 1110#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */ 1111#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */ 1112#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */ 1113#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */ 1114#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */ 1115#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */ 1116#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */ 1117 1118#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */ 1119#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */ 1120#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */ 1121#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */ 1122#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */ 1123#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */ 1124#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */ 1125#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */ 1126 1127#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */ 1128#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */ 1129#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */ 1130#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */ 1131#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */ 1132#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */ 1133#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */ 1134#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */ 1135 1136#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */ 1137#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */ 1138#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */ 1139#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */ 1140#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */ 1141#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */ 1142#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */ 1143#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */ 1144 1145#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */ 1146#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */ 1147#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */ 1148#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */ 1149#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */ 1150#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */ 1151#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */ 1152#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */ 1153 1154#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */ 1155#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */ 1156#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */ 1157#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */ 1158#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */ 1159#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */ 1160#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */ 1161#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */ 1162 1163#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */ 1164#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */ 1165#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */ 1166#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */ 1167#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */ 1168#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */ 1169#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */ 1170#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */ 1171 1172#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */ 1173#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */ 1174#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */ 1175#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */ 1176#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */ 1177#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */ 1178#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */ 1179#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */ 1180 1181#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */ 1182#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */ 1183#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */ 1184#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */ 1185#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */ 1186#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */ 1187#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */ 1188#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */ 1189 1190#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */ 1191#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */ 1192#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */ 1193#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */ 1194#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */ 1195#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */ 1196#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */ 1197#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */ 1198 1199/* CAN Mailbox Area Macros */ 1200#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20)) 1201#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20)) 1202#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20)) 1203#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20)) 1204#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20)) 1205#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20)) 1206#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20)) 1207#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20)) 1208 1209 1210/*********************************************************************************** */ 1211/* System MMR Register Bits and Macros */ 1212/******************************************************************************* */ 1213 1214/* SWRST Mask */ 1215#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ 1216#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ 1217#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ 1218#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ 1219#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ 1220 1221/* SYSCR Masks */ 1222#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */ 1223#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ 1224 1225 1226/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ 1227 1228/* Peripheral Masks For SIC0_ISR, SIC0_IWR, SIC0_IMASK */ 1229#define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */ 1230#define DMAC0_ERR_IRQ 0x00000002 /* DMA Controller 0 Error Interrupt Request */ 1231#define PPI_ERR_IRQ 0x00000004 /* PPI Error Interrupt Request */ 1232#define SPORT0_ERR_IRQ 0x00000008 /* SPORT0 Error Interrupt Request */ 1233#define SPORT1_ERR_IRQ 0x00000010 /* SPORT1 Error Interrupt Request */ 1234#define SPI0_ERR_IRQ 0x00000020 /* SPI0 Error Interrupt Request */ 1235#define UART0_ERR_IRQ 0x00000040 /* UART0 Error Interrupt Request */ 1236#define RTC_IRQ 0x00000080 /* Real-Time Clock Interrupt Request */ 1237#define DMA0_IRQ 0x00000100 /* DMA Channel 0 (PPI) Interrupt Request */ 1238#define DMA1_IRQ 0x00000200 /* DMA Channel 1 (SPORT0 RX) Interrupt Request */ 1239#define DMA2_IRQ 0x00000400 /* DMA Channel 2 (SPORT0 TX) Interrupt Request */ 1240#define DMA3_IRQ 0x00000800 /* DMA Channel 3 (SPORT1 RX) Interrupt Request */ 1241#define DMA4_IRQ 0x00001000 /* DMA Channel 4 (SPORT1 TX) Interrupt Request */ 1242#define DMA5_IRQ 0x00002000 /* DMA Channel 5 (SPI) Interrupt Request */ 1243#define DMA6_IRQ 0x00004000 /* DMA Channel 6 (UART RX) Interrupt Request */ 1244#define DMA7_IRQ 0x00008000 /* DMA Channel 7 (UART TX) Interrupt Request */ 1245#define TIMER0_IRQ 0x00010000 /* Timer 0 Interrupt Request */ 1246#define TIMER1_IRQ 0x00020000 /* Timer 1 Interrupt Request */ 1247#define TIMER2_IRQ 0x00040000 /* Timer 2 Interrupt Request */ 1248#define PFA_IRQ 0x00080000 /* Programmable Flag Interrupt Request A */ 1249#define PFB_IRQ 0x00100000 /* Programmable Flag Interrupt Request B */ 1250#define MDMA0_0_IRQ 0x00200000 /* MemDMA0 Stream 0 Interrupt Request */ 1251#define MDMA0_1_IRQ 0x00400000 /* MemDMA0 Stream 1 Interrupt Request */ 1252#define WDOG_IRQ 0x00800000 /* Software Watchdog Timer Interrupt Request */ 1253#define DMAC1_ERR_IRQ 0x01000000 /* DMA Controller 1 Error Interrupt Request */ 1254#define SPORT2_ERR_IRQ 0x02000000 /* SPORT2 Error Interrupt Request */ 1255#define SPORT3_ERR_IRQ 0x04000000 /* SPORT3 Error Interrupt Request */ 1256#define MXVR_SD_IRQ 0x08000000 /* MXVR Synchronous Data Interrupt Request */ 1257#define SPI1_ERR_IRQ 0x10000000 /* SPI1 Error Interrupt Request */ 1258#define SPI2_ERR_IRQ 0x20000000 /* SPI2 Error Interrupt Request */ 1259#define UART1_ERR_IRQ 0x40000000 /* UART1 Error Interrupt Request */ 1260#define UART2_ERR_IRQ 0x80000000 /* UART2 Error Interrupt Request */ 1261 1262/* the following are for backwards compatibility */ 1263#define DMA0_ERR_IRQ DMAC0_ERR_IRQ 1264#define DMA1_ERR_IRQ DMAC1_ERR_IRQ 1265 1266 1267/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */ 1268#define CAN_ERR_IRQ 0x00000001 /* CAN Error Interrupt Request */ 1269#define DMA8_IRQ 0x00000002 /* DMA Channel 8 (SPORT2 RX) Interrupt Request */ 1270#define DMA9_IRQ 0x00000004 /* DMA Channel 9 (SPORT2 TX) Interrupt Request */ 1271#define DMA10_IRQ 0x00000008 /* DMA Channel 10 (SPORT3 RX) Interrupt Request */ 1272#define DMA11_IRQ 0x00000010 /* DMA Channel 11 (SPORT3 TX) Interrupt Request */ 1273#define DMA12_IRQ 0x00000020 /* DMA Channel 12 Interrupt Request */ 1274#define DMA13_IRQ 0x00000040 /* DMA Channel 13 Interrupt Request */ 1275#define DMA14_IRQ 0x00000080 /* DMA Channel 14 (SPI1) Interrupt Request */ 1276#define DMA15_IRQ 0x00000100 /* DMA Channel 15 (SPI2) Interrupt Request */ 1277#define DMA16_IRQ 0x00000200 /* DMA Channel 16 (UART1 RX) Interrupt Request */ 1278#define DMA17_IRQ 0x00000400 /* DMA Channel 17 (UART1 TX) Interrupt Request */ 1279#define DMA18_IRQ 0x00000800 /* DMA Channel 18 (UART2 RX) Interrupt Request */ 1280#define DMA19_IRQ 0x00001000 /* DMA Channel 19 (UART2 TX) Interrupt Request */ 1281#define TWI0_IRQ 0x00002000 /* TWI0 Interrupt Request */ 1282#define TWI1_IRQ 0x00004000 /* TWI1 Interrupt Request */ 1283#define CAN_RX_IRQ 0x00008000 /* CAN Receive Interrupt Request */ 1284#define CAN_TX_IRQ 0x00010000 /* CAN Transmit Interrupt Request */ 1285#define MDMA1_0_IRQ 0x00020000 /* MemDMA1 Stream 0 Interrupt Request */ 1286#define MDMA1_1_IRQ 0x00040000 /* MemDMA1 Stream 1 Interrupt Request */ 1287#define MXVR_STAT_IRQ 0x00080000 /* MXVR Status Interrupt Request */ 1288#define MXVR_CM_IRQ 0x00100000 /* MXVR Control Message Interrupt Request */ 1289#define MXVR_AP_IRQ 0x00200000 /* MXVR Asynchronous Packet Interrupt */ 1290 1291/* the following are for backwards compatibility */ 1292#define MDMA0_IRQ MDMA1_0_IRQ 1293#define MDMA1_IRQ MDMA1_1_IRQ 1294 1295#ifdef _MISRA_RULES 1296#define _MF15 0xFu 1297#define _MF7 7u 1298#else 1299#define _MF15 0xF 1300#define _MF7 7 1301#endif /* _MISRA_RULES */ 1302 1303/* SIC_IMASKx Masks */ 1304#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ 1305#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ 1306#ifdef _MISRA_RULES 1307#define SIC_MASK(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */ 1308#define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */ 1309#else 1310#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ 1311#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ 1312#endif /* _MISRA_RULES */ 1313 1314/* SIC_IWRx Masks */ 1315#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ 1316#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ 1317#ifdef _MISRA_RULES 1318#define IWR_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */ 1319#define IWR_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */ 1320#else 1321#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ 1322#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ 1323#endif /* _MISRA_RULES */ 1324 1325/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ 1326/* PPI_CONTROL Masks */ 1327#define PORT_EN 0x0001 /* PPI Port Enable */ 1328#define PORT_DIR 0x0002 /* PPI Port Direction */ 1329#define XFR_TYPE 0x000C /* PPI Transfer Type */ 1330#define PORT_CFG 0x0030 /* PPI Port Configuration */ 1331#define FLD_SEL 0x0040 /* PPI Active Field Select */ 1332#define PACK_EN 0x0080 /* PPI Packing Mode */ 1333/* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */ 1334#define SKIP_EN 0x0200 /* PPI Skip Element Enable */ 1335#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ 1336#define DLENGTH 0x3800 /* PPI Data Length */ 1337#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */ 1338#define DLEN_10 0x0800 /* Data Length = 10 Bits */ 1339#define DLEN_11 0x1000 /* Data Length = 11 Bits */ 1340#define DLEN_12 0x1800 /* Data Length = 12 Bits */ 1341#define DLEN_13 0x2000 /* Data Length = 13 Bits */ 1342#define DLEN_14 0x2800 /* Data Length = 14 Bits */ 1343#define DLEN_15 0x3000 /* Data Length = 15 Bits */ 1344#define DLEN_16 0x3800 /* Data Length = 16 Bits */ 1345#ifdef _MISRA_RULES 1346#define DLEN(x) ((((x)-9u) & 0x07u) << 11) /* PPI Data Length (only works for x=10-->x=16) */ 1347#else 1348#define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ 1349#endif /* _MISRA_RULES */ 1350#define POL 0xC000 /* PPI Signal Polarities */ 1351#define POLC 0x4000 /* PPI Clock Polarity */ 1352#define POLS 0x8000 /* PPI Frame Sync Polarity */ 1353 1354 1355/* PPI_STATUS Masks */ 1356#define FLD 0x0400 /* Field Indicator */ 1357#define FT_ERR 0x0800 /* Frame Track Error */ 1358#define OVR 0x1000 /* FIFO Overflow Error */ 1359#define UNDR 0x2000 /* FIFO Underrun Error */ 1360#define ERR_DET 0x4000 /* Error Detected Indicator */ 1361#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ 1362 1363 1364/* ********** DMA CONTROLLER MASKS ***********************/ 1365 1366/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ 1367 1368#define CTYPE 0x0040 /* DMA Channel Type Indicator */ 1369#define CTYPE_P 0x6 /* DMA Channel Type Indicator BIT POSITION */ 1370#define PCAP8 0x0080 /* DMA 8-bit Operation Indicator */ 1371#define PCAP16 0x0100 /* DMA 16-bit Operation Indicator */ 1372#define PCAP32 0x0200 /* DMA 32-bit Operation Indicator */ 1373#define PCAPWR 0x0400 /* DMA Write Operation Indicator */ 1374#define PCAPRD 0x0800 /* DMA Read Operation Indicator */ 1375#define PMAP 0xF000 /* DMA Peripheral Map Field */ 1376 1377/* PMAP Encodings For DMA Controller 0 */ 1378#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */ 1379#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */ 1380#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */ 1381#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */ 1382#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */ 1383#define PMAP_SPI0 0x5000 /* PMAP SPI DMA */ 1384#define PMAP_UART0RX 0x6000 /* PMAP UART Receive DMA */ 1385#define PMAP_UART0TX 0x7000 /* PMAP UART Transmit DMA */ 1386 1387/* PMAP Encodings For DMA Controller 1 */ 1388#define PMAP_SPORT2RX 0x0000 /* PMAP SPORT2 Receive DMA */ 1389#define PMAP_SPORT2TX 0x1000 /* PMAP SPORT2 Transmit DMA */ 1390#define PMAP_SPORT3RX 0x2000 /* PMAP SPORT3 Receive DMA */ 1391#define PMAP_SPORT3TX 0x3000 /* PMAP SPORT3 Transmit DMA */ 1392#define PMAP_SPI1 0x6000 /* PMAP SPI1 DMA */ 1393#define PMAP_SPI2 0x7000 /* PMAP SPI2 DMA */ 1394#define PMAP_UART1RX 0x8000 /* PMAP UART1 Receive DMA */ 1395#define PMAP_UART1TX 0x9000 /* PMAP UART1 Transmit DMA */ 1396#define PMAP_UART2RX 0xA000 /* PMAP UART2 Receive DMA */ 1397#define PMAP_UART2TX 0xB000 /* PMAP UART2 Transmit DMA */ 1398 1399 1400/* ************* GENERAL PURPOSE TIMER MASKS ******************** */ 1401/* PWM Timer bit definitions */ 1402/* TIMER_ENABLE Register */ 1403#define TIMEN0 0x0001 /* Enable Timer 0 */ 1404#define TIMEN1 0x0002 /* Enable Timer 1 */ 1405#define TIMEN2 0x0004 /* Enable Timer 2 */ 1406 1407#define TIMEN0_P 0x00 1408#define TIMEN1_P 0x01 1409#define TIMEN2_P 0x02 1410 1411/* TIMER_DISABLE Register */ 1412#define TIMDIS0 0x0001 /* Disable Timer 0 */ 1413#define TIMDIS1 0x0002 /* Disable Timer 1 */ 1414#define TIMDIS2 0x0004 /* Disable Timer 2 */ 1415 1416#define TIMDIS0_P 0x00 1417#define TIMDIS1_P 0x01 1418#define TIMDIS2_P 0x02 1419 1420/* TIMER_STATUS Register */ 1421#define TIMIL0 0x0001 /* Timer 0 Interrupt */ 1422#define TIMIL1 0x0002 /* Timer 1 Interrupt */ 1423#define TIMIL2 0x0004 /* Timer 2 Interrupt */ 1424#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */ 1425#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */ 1426#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */ 1427#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */ 1428#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */ 1429#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */ 1430 1431#define TIMIL0_P 0x00 1432#define TIMIL1_P 0x01 1433#define TIMIL2_P 0x02 1434#define TOVF_ERR0_P 0x04 1435#define TOVF_ERR1_P 0x05 1436#define TOVF_ERR2_P 0x06 1437#define TRUN0_P 0x0C 1438#define TRUN1_P 0x0D 1439#define TRUN2_P 0x0E 1440 1441/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ 1442#define TOVL_ERR0 TOVF_ERR0 1443#define TOVL_ERR1 TOVF_ERR1 1444#define TOVL_ERR2 TOVF_ERR2 1445#define TOVL_ERR0_P TOVF_ERR0_P 1446#define TOVL_ERR1_P TOVF_ERR1_P 1447#define TOVL_ERR2_P TOVF_ERR2_P 1448 1449/* TIMERx_CONFIG Registers */ 1450#define PWM_OUT 0x0001 1451#define WDTH_CAP 0x0002 1452#define EXT_CLK 0x0003 1453#define PULSE_HI 0x0004 1454#define PERIOD_CNT 0x0008 1455#define IRQ_ENA 0x0010 1456#define TIN_SEL 0x0020 1457#define OUT_DIS 0x0040 1458#define CLK_SEL 0x0080 1459#define TOGGLE_HI 0x0100 1460#define EMU_RUN 0x0200 1461#ifdef _MISRA_RULES 1462#define ERR_TYP(x) (((x) & 0x03u) << 14) 1463#else 1464#define ERR_TYP(x) (((x) & 0x03) << 14) 1465#endif /* _MISRA_RULES */ 1466 1467#define TMODE_P0 0x00 1468#define TMODE_P1 0x01 1469#define PULSE_HI_P 0x02 1470#define PERIOD_CNT_P 0x03 1471#define IRQ_ENA_P 0x04 1472#define TIN_SEL_P 0x05 1473#define OUT_DIS_P 0x06 1474#define CLK_SEL_P 0x07 1475#define TOGGLE_HI_P 0x08 1476#define EMU_RUN_P 0x09 1477#define ERR_TYP_P0 0x0E 1478#define ERR_TYP_P1 0x0F 1479 1480/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ 1481/* EBIU_AMGCTL Masks */ 1482#define AMCKEN 0x0001 /* Enable CLKOUT */ 1483#define AMBEN_NONE 0x0000 /* All Banks Disabled */ 1484#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */ 1485#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */ 1486#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ 1487#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ 1488#define CDPRIO 0x0100 /* DMA has priority over core for external accesses */ 1489 1490/* EBIU_AMGCTL Bit Positions */ 1491#define AMCKEN_P 0x0000 /* Enable CLKOUT */ 1492#define AMBEN_P0 0x0001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ 1493#define AMBEN_P1 0x0002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ 1494#define AMBEN_P2 0x0003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ 1495 1496/* EBIU_AMBCTL0 Masks */ 1497#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ 1498#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ 1499#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ 1500#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ 1501#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ 1502#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ 1503#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ 1504#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ 1505#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ 1506#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ 1507#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ 1508#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ 1509#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ 1510#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ 1511#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ 1512#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ 1513#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ 1514#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ 1515#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ 1516#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ 1517#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ 1518#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ 1519#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ 1520#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ 1521#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ 1522#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ 1523#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ 1524#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ 1525#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ 1526#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ 1527#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ 1528#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ 1529#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ 1530#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ 1531#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ 1532#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ 1533#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ 1534#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ 1535#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ 1536#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ 1537#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ 1538#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ 1539#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ 1540#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ 1541#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ 1542#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ 1543#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ 1544#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ 1545#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ 1546#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ 1547#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ 1548#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ 1549#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ 1550#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ 1551#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ 1552#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ 1553#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ 1554#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ 1555#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ 1556#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ 1557#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ 1558#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ 1559#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ 1560#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ 1561#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ 1562#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ 1563#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ 1564#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ 1565#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ 1566#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ 1567#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ 1568#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ 1569#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ 1570#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ 1571#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ 1572#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ 1573#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ 1574#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ 1575#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ 1576#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ 1577#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ 1578#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ 1579#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ 1580#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ 1581#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ 1582#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ 1583#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ 1584#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ 1585 1586/* EBIU_AMBCTL1 Masks */ 1587#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ 1588#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ 1589#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ 1590#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ 1591#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ 1592#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ 1593#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ 1594#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ 1595#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ 1596#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ 1597#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ 1598#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ 1599#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ 1600#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ 1601#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ 1602#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ 1603#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ 1604#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ 1605#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ 1606#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ 1607#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ 1608#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ 1609#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ 1610#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ 1611#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ 1612#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ 1613#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ 1614#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ 1615#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ 1616#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ 1617#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ 1618#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ 1619#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ 1620#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ 1621#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ 1622#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ 1623#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ 1624#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ 1625#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ 1626#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ 1627#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ 1628#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ 1629#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ 1630#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ 1631#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ 1632#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ 1633#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ 1634#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ 1635#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ 1636#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ 1637#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ 1638#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ 1639#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ 1640#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ 1641#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ 1642#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ 1643#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ 1644#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ 1645#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ 1646#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ 1647#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ 1648#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ 1649#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ 1650#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ 1651#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ 1652#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ 1653#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ 1654#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ 1655#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ 1656#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ 1657#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ 1658#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ 1659#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ 1660#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ 1661#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ 1662#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ 1663#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ 1664#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ 1665#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ 1666#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ 1667#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ 1668#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ 1669#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ 1670#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ 1671#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ 1672#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ 1673#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ 1674#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ 1675 1676/* ********************** SDRAM CONTROLLER MASKS *************************** */ 1677/* EBIU_SDGCTL Masks */ 1678#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ 1679#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ 1680#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ 1681#define PFE 0x00000010 /* Enable SDRAM prefetch */ 1682#define PFP 0x00000020 /* Prefetch has priority over AMC requests */ 1683#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ 1684#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ 1685#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ 1686#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ 1687#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ 1688#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ 1689#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ 1690#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ 1691#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ 1692#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ 1693#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ 1694#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ 1695#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ 1696#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ 1697#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ 1698#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ 1699#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ 1700#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ 1701#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ 1702#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ 1703#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ 1704#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ 1705#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ 1706#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ 1707#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ 1708#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ 1709#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ 1710#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ 1711#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ 1712#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ 1713#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ 1714#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ 1715#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ 1716#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ 1717#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ 1718#define PUPSD 0x00200000 /*Power-up start delay */ 1719#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ 1720#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ 1721#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ 1722#define EBUFE 0x02000000 /* Enable external buffering timing */ 1723#define FBBRW 0x04000000 /* Fast back-to-back read write enable */ 1724#define EMREN 0x10000000 /* Extended mode register enable */ 1725#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ 1726#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ 1727 1728/* EBIU_SDBCTL Masks */ 1729#define EBE 0x00000001 /* Enable SDRAM external bank */ 1730#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */ 1731#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */ 1732#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */ 1733#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */ 1734#define EBSZ_256 0x00000008 /* SDRAM External Bank Size = 256MB */ 1735#define EBSZ_512 0x0000000A /* SDRAM External Bank Size = 512MB */ 1736#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ 1737#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ 1738#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ 1739#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ 1740 1741/* EBIU_SDSTAT Masks */ 1742#define SDCI 0x00000001 /* SDRAM controller is idle */ 1743#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ 1744#define SDPUA 0x00000004 /* SDRAM power up active */ 1745#define SDRS 0x00000008 /* SDRAM is in reset state */ 1746#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ 1747#define BGSTAT 0x00000020 /* Bus granted */ 1748 1749 1750/* ******************** TWO-WIRE INTERFACE (TWIx) MASKS ***********************/ 1751/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ 1752#ifdef _MISRA_RULES 1753#define CLKLOW(x) ((x) & 0xFFu) /* Periods Clock Is Held Low */ 1754#define CLKHI(y) (((y)&0xFFu)<<0x8) /* Periods Before New Clock Low */ 1755#else 1756#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ 1757#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ 1758#endif /* _MISRA_RULES */ 1759 1760/* TWIx_PRESCALE Masks */ 1761#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ 1762#define TWI_ENA 0x0080 /* TWI Enable */ 1763#define SCCB 0x0200 /* SCCB Compatibility Enable */ 1764 1765/* TWIx_SLAVE_CTRL Masks */ 1766#define SEN 0x0001 /* Slave Enable */ 1767#define SADD_LEN 0x0002 /* Slave Address Length */ 1768#define STDVAL 0x0004 /* Slave Transmit Data Valid */ 1769#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ 1770#define GEN 0x0010 /* General Call Adrress Matching Enabled */ 1771 1772/* TWIx_SLAVE_STAT Masks */ 1773#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ 1774#define GCALL 0x0002 /* General Call Indicator */ 1775 1776/* TWIx_MASTER_CTRL Masks */ 1777#define MEN 0x0001 /* Master Mode Enable */ 1778#define MADD_LEN 0x0002 /* Master Address Length */ 1779#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ 1780#define FAST 0x0008 /* Use Fast Mode Timing Specs */ 1781#define STOP 0x0010 /* Issue Stop Condition */ 1782#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ 1783#define DCNT 0x3FC0 /* Data Bytes To Transfer */ 1784#define SDAOVR 0x4000 /* Serial Data Override */ 1785#define SCLOVR 0x8000 /* Serial Clock Override */ 1786 1787/* TWIx_MASTER_STAT Masks */ 1788#define MPROG 0x0001 /* Master Transfer In Progress */ 1789#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ 1790#define ANAK 0x0004 /* Address Not Acknowledged */ 1791#define DNAK 0x0008 /* Data Not Acknowledged */ 1792#define BUFRDERR 0x0010 /* Buffer Read Error */ 1793#define BUFWRERR 0x0020 /* Buffer Write Error */ 1794#define SDASEN 0x0040 /* Serial Data Sense */ 1795#define SCLSEN 0x0080 /* Serial Clock Sense */ 1796#define BUSBUSY 0x0100 /* Bus Busy Indicator */ 1797 1798/* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */ 1799#define SINIT 0x0001 /* Slave Transfer Initiated */ 1800#define SCOMP 0x0002 /* Slave Transfer Complete */ 1801#define SERR 0x0004 /* Slave Transfer Error */ 1802#define SOVF 0x0008 /* Slave Overflow */ 1803#define MCOMP 0x0010 /* Master Transfer Complete */ 1804#define MERR 0x0020 /* Master Transfer Error */ 1805#define XMTSERV 0x0040 /* Transmit FIFO Service */ 1806#define RCVSERV 0x0080 /* Receive FIFO Service */ 1807 1808/* TWIx_FIFO_CTL Masks */ 1809#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ 1810#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ 1811#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ 1812#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ 1813 1814/* TWIx_FIFO_STAT Masks */ 1815#define XMTSTAT 0x0003 /* Transmit FIFO Status */ 1816#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ 1817#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ 1818#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ 1819 1820#define RCVSTAT 0x000C /* Receive FIFO Status */ 1821#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ 1822#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ 1823#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ 1824 1825#endif 1826