1/* 2 * Simple synchronous serial port driver for ETRAX 100LX. 3 * 4 * Synchronous serial ports are used for continuous streamed data like audio. 5 * The default setting for this driver is compatible with the STA 013 MP3 6 * decoder. The driver can easily be tuned to fit other audio encoder/decoders 7 * and SPI 8 * 9 * Copyright (c) 2001-2008 Axis Communications AB 10 * 11 * Author: Mikael Starvik, Johan Adolfsson 12 * 13 */ 14#include <linux/module.h> 15#include <linux/kernel.h> 16#include <linux/types.h> 17#include <linux/errno.h> 18#include <linux/major.h> 19#include <linux/sched.h> 20#include <linux/interrupt.h> 21#include <linux/poll.h> 22#include <linux/init.h> 23#include <linux/mutex.h> 24#include <linux/timer.h> 25#include <asm/irq.h> 26#include <asm/dma.h> 27#include <asm/io.h> 28#include <arch/svinto.h> 29#include <asm/uaccess.h> 30#include <asm/sync_serial.h> 31#include <arch/io_interface_mux.h> 32 33/* The receiver is a bit tricky because of the continuous stream of data.*/ 34/* */ 35/* Three DMA descriptors are linked together. Each DMA descriptor is */ 36/* responsible for port->bufchunk of a common buffer. */ 37/* */ 38/* +---------------------------------------------+ */ 39/* | +----------+ +----------+ +----------+ | */ 40/* +-> | Descr[0] |-->| Descr[1] |-->| Descr[2] |-+ */ 41/* +----------+ +----------+ +----------+ */ 42/* | | | */ 43/* v v v */ 44/* +-------------------------------------+ */ 45/* | BUFFER | */ 46/* +-------------------------------------+ */ 47/* |<- data_avail ->| */ 48/* readp writep */ 49/* */ 50/* If the application keeps up the pace readp will be right after writep.*/ 51/* If the application can't keep the pace we have to throw away data. */ 52/* The idea is that readp should be ready with the data pointed out by */ 53/* Descr[i] when the DMA has filled in Descr[i+1]. */ 54/* Otherwise we will discard */ 55/* the rest of the data pointed out by Descr1 and set readp to the start */ 56/* of Descr2 */ 57 58#define SYNC_SERIAL_MAJOR 125 59 60/* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */ 61/* words can be handled */ 62#define IN_BUFFER_SIZE 12288 63#define IN_DESCR_SIZE 256 64#define NUM_IN_DESCR (IN_BUFFER_SIZE/IN_DESCR_SIZE) 65#define OUT_BUFFER_SIZE 4096 66 67#define DEFAULT_FRAME_RATE 0 68#define DEFAULT_WORD_RATE 7 69 70/* NOTE: Enabling some debug will likely cause overrun or underrun, 71 * especially if manual mode is use. 72 */ 73#define DEBUG(x) 74#define DEBUGREAD(x) 75#define DEBUGWRITE(x) 76#define DEBUGPOLL(x) 77#define DEBUGRXINT(x) 78#define DEBUGTXINT(x) 79 80/* Define some macros to access ETRAX 100 registers */ 81#define SETF(var, reg, field, val) \ 82 do { \ 83 var = (var & ~IO_MASK_(reg##_, field##_)) | \ 84 IO_FIELD_(reg##_, field##_, val); \ 85 } while (0) 86 87#define SETS(var, reg, field, val) \ 88 do { \ 89 var = (var & ~IO_MASK_(reg##_, field##_)) | \ 90 IO_STATE_(reg##_, field##_, _##val); \ 91 } while (0) 92 93struct sync_port { 94 /* Etrax registers and bits*/ 95 const volatile unsigned *const status; 96 volatile unsigned *const ctrl_data; 97 volatile unsigned *const output_dma_first; 98 volatile unsigned char *const output_dma_cmd; 99 volatile unsigned char *const output_dma_clr_irq; 100 volatile unsigned *const input_dma_first; 101 volatile unsigned char *const input_dma_cmd; 102 volatile unsigned *const input_dma_descr; 103 /* 8*4 */ 104 volatile unsigned char *const input_dma_clr_irq; 105 volatile unsigned *const data_out; 106 const volatile unsigned *const data_in; 107 char data_avail_bit; /* In R_IRQ_MASK1_RD/SET/CLR */ 108 char transmitter_ready_bit; /* In R_IRQ_MASK1_RD/SET/CLR */ 109 char input_dma_descr_bit; /* In R_IRQ_MASK2_RD */ 110 111 char output_dma_bit; /* In R_IRQ_MASK2_RD */ 112 /* End of fields initialised in array */ 113 char started; /* 1 if port has been started */ 114 char port_nbr; /* Port 0 or 1 */ 115 char busy; /* 1 if port is busy */ 116 117 char enabled; /* 1 if port is enabled */ 118 char use_dma; /* 1 if port uses dma */ 119 char tr_running; 120 121 char init_irqs; 122 123 /* Register shadow */ 124 unsigned int ctrl_data_shadow; 125 /* Remaining bytes for current transfer */ 126 volatile unsigned int out_count; 127 /* Current position in out_buffer */ 128 unsigned char *outp; 129 /* 16*4 */ 130 /* Next byte to be read by application */ 131 volatile unsigned char *volatile readp; 132 /* Next byte to be written by etrax */ 133 volatile unsigned char *volatile writep; 134 135 unsigned int in_buffer_size; 136 unsigned int inbufchunk; 137 struct etrax_dma_descr out_descr __attribute__ ((aligned(32))); 138 struct etrax_dma_descr in_descr[NUM_IN_DESCR] __attribute__ ((aligned(32))); 139 unsigned char out_buffer[OUT_BUFFER_SIZE] __attribute__ ((aligned(32))); 140 unsigned char in_buffer[IN_BUFFER_SIZE]__attribute__ ((aligned(32))); 141 unsigned char flip[IN_BUFFER_SIZE] __attribute__ ((aligned(32))); 142 struct etrax_dma_descr *next_rx_desc; 143 struct etrax_dma_descr *prev_rx_desc; 144 int full; 145 146 wait_queue_head_t out_wait_q; 147 wait_queue_head_t in_wait_q; 148}; 149 150 151static DEFINE_MUTEX(sync_serial_mutex); 152static int etrax_sync_serial_init(void); 153static void initialize_port(int portnbr); 154static inline int sync_data_avail(struct sync_port *port); 155 156static int sync_serial_open(struct inode *inode, struct file *file); 157static int sync_serial_release(struct inode *inode, struct file *file); 158static unsigned int sync_serial_poll(struct file *filp, poll_table *wait); 159 160static long sync_serial_ioctl(struct file *file, 161 unsigned int cmd, unsigned long arg); 162static ssize_t sync_serial_write(struct file *file, const char *buf, 163 size_t count, loff_t *ppos); 164static ssize_t sync_serial_read(struct file *file, char *buf, 165 size_t count, loff_t *ppos); 166 167#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \ 168 defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \ 169 (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \ 170 defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA))) 171#define SYNC_SER_DMA 172#endif 173 174static void send_word(struct sync_port *port); 175static void start_dma(struct sync_port *port, const char *data, int count); 176static void start_dma_in(struct sync_port *port); 177#ifdef SYNC_SER_DMA 178static irqreturn_t tr_interrupt(int irq, void *dev_id); 179static irqreturn_t rx_interrupt(int irq, void *dev_id); 180#endif 181#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \ 182 !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \ 183 (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \ 184 !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA))) 185#define SYNC_SER_MANUAL 186#endif 187#ifdef SYNC_SER_MANUAL 188static irqreturn_t manual_interrupt(int irq, void *dev_id); 189#endif 190 191/* The ports */ 192static struct sync_port ports[] = { 193 { 194 .status = R_SYNC_SERIAL1_STATUS, 195 .ctrl_data = R_SYNC_SERIAL1_CTRL, 196 .output_dma_first = R_DMA_CH8_FIRST, 197 .output_dma_cmd = R_DMA_CH8_CMD, 198 .output_dma_clr_irq = R_DMA_CH8_CLR_INTR, 199 .input_dma_first = R_DMA_CH9_FIRST, 200 .input_dma_cmd = R_DMA_CH9_CMD, 201 .input_dma_descr = R_DMA_CH9_DESCR, 202 .input_dma_clr_irq = R_DMA_CH9_CLR_INTR, 203 .data_out = R_SYNC_SERIAL1_TR_DATA, 204 .data_in = R_SYNC_SERIAL1_REC_DATA, 205 .data_avail_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_data), 206 .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_ready), 207 .input_dma_descr_bit = IO_BITNR(R_IRQ_MASK2_RD, dma9_descr), 208 .output_dma_bit = IO_BITNR(R_IRQ_MASK2_RD, dma8_eop), 209 .init_irqs = 1, 210#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA) 211 .use_dma = 1, 212#else 213 .use_dma = 0, 214#endif 215 }, 216 { 217 .status = R_SYNC_SERIAL3_STATUS, 218 .ctrl_data = R_SYNC_SERIAL3_CTRL, 219 .output_dma_first = R_DMA_CH4_FIRST, 220 .output_dma_cmd = R_DMA_CH4_CMD, 221 .output_dma_clr_irq = R_DMA_CH4_CLR_INTR, 222 .input_dma_first = R_DMA_CH5_FIRST, 223 .input_dma_cmd = R_DMA_CH5_CMD, 224 .input_dma_descr = R_DMA_CH5_DESCR, 225 .input_dma_clr_irq = R_DMA_CH5_CLR_INTR, 226 .data_out = R_SYNC_SERIAL3_TR_DATA, 227 .data_in = R_SYNC_SERIAL3_REC_DATA, 228 .data_avail_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_data), 229 .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_ready), 230 .input_dma_descr_bit = IO_BITNR(R_IRQ_MASK2_RD, dma5_descr), 231 .output_dma_bit = IO_BITNR(R_IRQ_MASK2_RD, dma4_eop), 232 .init_irqs = 1, 233#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA) 234 .use_dma = 1, 235#else 236 .use_dma = 0, 237#endif 238 } 239}; 240 241/* Register shadows */ 242static unsigned sync_serial_prescale_shadow; 243 244#define NUMBER_OF_PORTS 2 245 246static const struct file_operations sync_serial_fops = { 247 .owner = THIS_MODULE, 248 .write = sync_serial_write, 249 .read = sync_serial_read, 250 .poll = sync_serial_poll, 251 .unlocked_ioctl = sync_serial_ioctl, 252 .open = sync_serial_open, 253 .release = sync_serial_release, 254 .llseek = noop_llseek, 255}; 256 257static int __init etrax_sync_serial_init(void) 258{ 259 ports[0].enabled = 0; 260 ports[1].enabled = 0; 261 262#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) 263 if (cris_request_io_interface(if_sync_serial_1, "sync_ser1")) { 264 printk(KERN_CRIT "ETRAX100LX sync_serial: " 265 "Could not allocate IO group for port %d\n", 0); 266 return -EBUSY; 267 } 268#endif 269#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) 270 if (cris_request_io_interface(if_sync_serial_3, "sync_ser3")) { 271#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) 272 cris_free_io_interface(if_sync_serial_1); 273#endif 274 printk(KERN_CRIT "ETRAX100LX sync_serial: " 275 "Could not allocate IO group for port %d\n", 1); 276 return -EBUSY; 277 } 278#endif 279 280 if (register_chrdev(SYNC_SERIAL_MAJOR, "sync serial", 281 &sync_serial_fops) < 0) { 282#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) 283 cris_free_io_interface(if_sync_serial_3); 284#endif 285#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) 286 cris_free_io_interface(if_sync_serial_1); 287#endif 288 printk("unable to get major for synchronous serial port\n"); 289 return -EBUSY; 290 } 291 292 /* Deselect synchronous serial ports while configuring. */ 293 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async); 294 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async); 295 *R_GEN_CONFIG_II = gen_config_ii_shadow; 296 297 /* Initialize Ports */ 298#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) 299 ports[0].enabled = 1; 300 SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser1, ss1extra); 301 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync); 302#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA) 303 ports[0].use_dma = 1; 304#else 305 ports[0].use_dma = 0; 306#endif 307 initialize_port(0); 308#endif 309 310#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) 311 ports[1].enabled = 1; 312 SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser3, ss3extra); 313 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync); 314#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA) 315 ports[1].use_dma = 1; 316#else 317 ports[1].use_dma = 0; 318#endif 319 initialize_port(1); 320#endif 321 322 *R_PORT_PB_I2C = port_pb_i2c_shadow; /* Use PB4/PB7 */ 323 324 /* Set up timing */ 325 *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow = ( 326 IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u1, codec) | 327 IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u1, external) | 328 IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u3, codec) | 329 IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u3, external) | 330 IO_STATE(R_SYNC_SERIAL_PRESCALE, prescaler, div4) | 331 IO_FIELD(R_SYNC_SERIAL_PRESCALE, frame_rate, 332 DEFAULT_FRAME_RATE) | 333 IO_FIELD(R_SYNC_SERIAL_PRESCALE, word_rate, DEFAULT_WORD_RATE) | 334 IO_STATE(R_SYNC_SERIAL_PRESCALE, warp_mode, normal)); 335 336 /* Select synchronous ports */ 337 *R_GEN_CONFIG_II = gen_config_ii_shadow; 338 339 printk(KERN_INFO "ETRAX 100LX synchronous serial port driver\n"); 340 return 0; 341} 342 343static void __init initialize_port(int portnbr) 344{ 345 struct sync_port *port = &ports[portnbr]; 346 347 DEBUG(printk(KERN_DEBUG "Init sync serial port %d\n", portnbr)); 348 349 port->started = 0; 350 port->port_nbr = portnbr; 351 port->busy = 0; 352 port->tr_running = 0; 353 354 port->out_count = 0; 355 port->outp = port->out_buffer; 356 357 port->readp = port->flip; 358 port->writep = port->flip; 359 port->in_buffer_size = IN_BUFFER_SIZE; 360 port->inbufchunk = IN_DESCR_SIZE; 361 port->next_rx_desc = &port->in_descr[0]; 362 port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR-1]; 363 port->prev_rx_desc->ctrl = d_eol; 364 365 init_waitqueue_head(&port->out_wait_q); 366 init_waitqueue_head(&port->in_wait_q); 367 368 port->ctrl_data_shadow = 369 IO_STATE(R_SYNC_SERIAL1_CTRL, tr_baud, c115k2Hz) | 370 IO_STATE(R_SYNC_SERIAL1_CTRL, mode, master_output) | 371 IO_STATE(R_SYNC_SERIAL1_CTRL, error, ignore) | 372 IO_STATE(R_SYNC_SERIAL1_CTRL, rec_enable, disable) | 373 IO_STATE(R_SYNC_SERIAL1_CTRL, f_synctype, normal) | 374 IO_STATE(R_SYNC_SERIAL1_CTRL, f_syncsize, word) | 375 IO_STATE(R_SYNC_SERIAL1_CTRL, f_sync, on) | 376 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_mode, normal) | 377 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_halt, stopped) | 378 IO_STATE(R_SYNC_SERIAL1_CTRL, bitorder, msb) | 379 IO_STATE(R_SYNC_SERIAL1_CTRL, tr_enable, disable) | 380 IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit) | 381 IO_STATE(R_SYNC_SERIAL1_CTRL, buf_empty, lmt_8) | 382 IO_STATE(R_SYNC_SERIAL1_CTRL, buf_full, lmt_8) | 383 IO_STATE(R_SYNC_SERIAL1_CTRL, flow_ctrl, enabled) | 384 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_polarity, neg) | 385 IO_STATE(R_SYNC_SERIAL1_CTRL, frame_polarity, normal)| 386 IO_STATE(R_SYNC_SERIAL1_CTRL, status_polarity, inverted)| 387 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_driver, normal) | 388 IO_STATE(R_SYNC_SERIAL1_CTRL, frame_driver, normal) | 389 IO_STATE(R_SYNC_SERIAL1_CTRL, status_driver, normal)| 390 IO_STATE(R_SYNC_SERIAL1_CTRL, def_out0, high); 391 392 if (port->use_dma) 393 port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL, 394 dma_enable, on); 395 else 396 port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL, 397 dma_enable, off); 398 399 *port->ctrl_data = port->ctrl_data_shadow; 400} 401 402static inline int sync_data_avail(struct sync_port *port) 403{ 404 int avail; 405 unsigned char *start; 406 unsigned char *end; 407 408 start = (unsigned char *)port->readp; /* cast away volatile */ 409 end = (unsigned char *)port->writep; /* cast away volatile */ 410 /* 0123456789 0123456789 411 * ----- - ----- 412 * ^rp ^wp ^wp ^rp 413 */ 414 if (end >= start) 415 avail = end - start; 416 else 417 avail = port->in_buffer_size - (start - end); 418 return avail; 419} 420 421static inline int sync_data_avail_to_end(struct sync_port *port) 422{ 423 int avail; 424 unsigned char *start; 425 unsigned char *end; 426 427 start = (unsigned char *)port->readp; /* cast away volatile */ 428 end = (unsigned char *)port->writep; /* cast away volatile */ 429 /* 0123456789 0123456789 430 * ----- ----- 431 * ^rp ^wp ^wp ^rp 432 */ 433 434 if (end >= start) 435 avail = end - start; 436 else 437 avail = port->flip + port->in_buffer_size - start; 438 return avail; 439} 440 441 442static int sync_serial_open(struct inode *inode, struct file *file) 443{ 444 int dev = MINOR(inode->i_rdev); 445 struct sync_port *port; 446 int mode; 447 int err = -EBUSY; 448 449 mutex_lock(&sync_serial_mutex); 450 DEBUG(printk(KERN_DEBUG "Open sync serial port %d\n", dev)); 451 452 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { 453 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); 454 err = -ENODEV; 455 goto out; 456 } 457 port = &ports[dev]; 458 /* Allow open this device twice (assuming one reader and one writer) */ 459 if (port->busy == 2) { 460 DEBUG(printk(KERN_DEBUG "Device is busy.. \n")); 461 goto out; 462 } 463 if (port->init_irqs) { 464 if (port->use_dma) { 465 if (port == &ports[0]) { 466#ifdef SYNC_SER_DMA 467 if (request_irq(24, tr_interrupt, 0, 468 "synchronous serial 1 dma tr", 469 &ports[0])) { 470 printk(KERN_CRIT "Can't alloc " 471 "sync serial port 1 IRQ"); 472 goto out; 473 } else if (request_irq(25, rx_interrupt, 0, 474 "synchronous serial 1 dma rx", 475 &ports[0])) { 476 free_irq(24, &port[0]); 477 printk(KERN_CRIT "Can't alloc " 478 "sync serial port 1 IRQ"); 479 goto out; 480 } else if (cris_request_dma(8, 481 "synchronous serial 1 dma tr", 482 DMA_VERBOSE_ON_ERROR, 483 dma_ser1)) { 484 free_irq(24, &port[0]); 485 free_irq(25, &port[0]); 486 printk(KERN_CRIT "Can't alloc " 487 "sync serial port 1 " 488 "TX DMA channel"); 489 goto out; 490 } else if (cris_request_dma(9, 491 "synchronous serial 1 dma rec", 492 DMA_VERBOSE_ON_ERROR, 493 dma_ser1)) { 494 cris_free_dma(8, NULL); 495 free_irq(24, &port[0]); 496 free_irq(25, &port[0]); 497 printk(KERN_CRIT "Can't alloc " 498 "sync serial port 1 " 499 "RX DMA channel"); 500 goto out; 501 } 502#endif 503 RESET_DMA(8); WAIT_DMA(8); 504 RESET_DMA(9); WAIT_DMA(9); 505 *R_DMA_CH8_CLR_INTR = 506 IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, 507 do) | 508 IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, 509 do); 510 *R_DMA_CH9_CLR_INTR = 511 IO_STATE(R_DMA_CH9_CLR_INTR, clr_eop, 512 do) | 513 IO_STATE(R_DMA_CH9_CLR_INTR, clr_descr, 514 do); 515 *R_IRQ_MASK2_SET = 516 IO_STATE(R_IRQ_MASK2_SET, dma8_eop, 517 set) | 518 IO_STATE(R_IRQ_MASK2_SET, dma9_descr, 519 set); 520 } else if (port == &ports[1]) { 521#ifdef SYNC_SER_DMA 522 if (request_irq(20, tr_interrupt, 0, 523 "synchronous serial 3 dma tr", 524 &ports[1])) { 525 printk(KERN_CRIT "Can't alloc " 526 "sync serial port 3 IRQ"); 527 goto out; 528 } else if (request_irq(21, rx_interrupt, 0, 529 "synchronous serial 3 dma rx", 530 &ports[1])) { 531 free_irq(20, &ports[1]); 532 printk(KERN_CRIT "Can't alloc " 533 "sync serial port 3 IRQ"); 534 goto out; 535 } else if (cris_request_dma(4, 536 "synchronous serial 3 dma tr", 537 DMA_VERBOSE_ON_ERROR, 538 dma_ser3)) { 539 free_irq(21, &ports[1]); 540 free_irq(20, &ports[1]); 541 printk(KERN_CRIT "Can't alloc " 542 "sync serial port 3 " 543 "TX DMA channel"); 544 goto out; 545 } else if (cris_request_dma(5, 546 "synchronous serial 3 dma rec", 547 DMA_VERBOSE_ON_ERROR, 548 dma_ser3)) { 549 cris_free_dma(4, NULL); 550 free_irq(21, &ports[1]); 551 free_irq(20, &ports[1]); 552 printk(KERN_CRIT "Can't alloc " 553 "sync serial port 3 " 554 "RX DMA channel"); 555 goto out; 556 } 557#endif 558 RESET_DMA(4); WAIT_DMA(4); 559 RESET_DMA(5); WAIT_DMA(5); 560 *R_DMA_CH4_CLR_INTR = 561 IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, 562 do) | 563 IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, 564 do); 565 *R_DMA_CH5_CLR_INTR = 566 IO_STATE(R_DMA_CH5_CLR_INTR, clr_eop, 567 do) | 568 IO_STATE(R_DMA_CH5_CLR_INTR, clr_descr, 569 do); 570 *R_IRQ_MASK2_SET = 571 IO_STATE(R_IRQ_MASK2_SET, dma4_eop, 572 set) | 573 IO_STATE(R_IRQ_MASK2_SET, dma5_descr, 574 set); 575 } 576 start_dma_in(port); 577 port->init_irqs = 0; 578 } else { /* !port->use_dma */ 579#ifdef SYNC_SER_MANUAL 580 if (port == &ports[0]) { 581 if (request_irq(8, 582 manual_interrupt, 583 IRQF_SHARED | IRQF_DISABLED, 584 "synchronous serial manual irq", 585 &ports[0])) { 586 printk(KERN_CRIT "Can't alloc " 587 "sync serial manual irq"); 588 goto out; 589 } 590 } else if (port == &ports[1]) { 591 if (request_irq(8, 592 manual_interrupt, 593 IRQF_SHARED | IRQF_DISABLED, 594 "synchronous serial manual irq", 595 &ports[1])) { 596 printk(KERN_CRIT "Can't alloc " 597 "sync serial manual irq"); 598 goto out; 599 } 600 } 601 port->init_irqs = 0; 602#else 603 panic("sync_serial: Manual mode not supported.\n"); 604#endif /* SYNC_SER_MANUAL */ 605 } 606 } /* port->init_irqs */ 607 608 port->busy++; 609 /* Start port if we use it as input */ 610 mode = IO_EXTRACT(R_SYNC_SERIAL1_CTRL, mode, port->ctrl_data_shadow); 611 if (mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_input) || 612 mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_input) || 613 mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_bidir) || 614 mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_bidir)) { 615 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt, 616 running); 617 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable, 618 enable); 619 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable, 620 enable); 621 port->started = 1; 622 *port->ctrl_data = port->ctrl_data_shadow; 623 if (!port->use_dma) 624 *R_IRQ_MASK1_SET = 1 << port->data_avail_bit; 625 DEBUG(printk(KERN_DEBUG "sser%d rec started\n", dev)); 626 } 627 err = 0; 628 629out: 630 mutex_unlock(&sync_serial_mutex); 631 return err; 632} 633 634static int sync_serial_release(struct inode *inode, struct file *file) 635{ 636 int dev = MINOR(inode->i_rdev); 637 struct sync_port *port; 638 639 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { 640 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); 641 return -ENODEV; 642 } 643 port = &ports[dev]; 644 if (port->busy) 645 port->busy--; 646 if (!port->busy) 647 *R_IRQ_MASK1_CLR = ((1 << port->data_avail_bit) | 648 (1 << port->transmitter_ready_bit)); 649 650 return 0; 651} 652 653 654 655static unsigned int sync_serial_poll(struct file *file, poll_table *wait) 656{ 657 int dev = MINOR(file->f_dentry->d_inode->i_rdev); 658 unsigned int mask = 0; 659 struct sync_port *port; 660 DEBUGPOLL(static unsigned int prev_mask = 0); 661 662 port = &ports[dev]; 663 poll_wait(file, &port->out_wait_q, wait); 664 poll_wait(file, &port->in_wait_q, wait); 665 /* Some room to write */ 666 if (port->out_count < OUT_BUFFER_SIZE) 667 mask |= POLLOUT | POLLWRNORM; 668 /* At least an inbufchunk of data */ 669 if (sync_data_avail(port) >= port->inbufchunk) 670 mask |= POLLIN | POLLRDNORM; 671 672 DEBUGPOLL(if (mask != prev_mask) 673 printk(KERN_DEBUG "sync_serial_poll: mask 0x%08X %s %s\n", 674 mask, 675 mask & POLLOUT ? "POLLOUT" : "", 676 mask & POLLIN ? "POLLIN" : ""); 677 prev_mask = mask; 678 ); 679 return mask; 680} 681 682static int sync_serial_ioctl_unlocked(struct file *file, 683 unsigned int cmd, unsigned long arg) 684{ 685 int return_val = 0; 686 unsigned long flags; 687 688 int dev = MINOR(file->f_dentry->d_inode->i_rdev); 689 struct sync_port *port; 690 691 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { 692 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); 693 return -1; 694 } 695 port = &ports[dev]; 696 697 local_irq_save(flags); 698 /* Disable port while changing config */ 699 if (dev) { 700 if (port->use_dma) { 701 RESET_DMA(4); WAIT_DMA(4); 702 port->tr_running = 0; 703 port->out_count = 0; 704 port->outp = port->out_buffer; 705 *R_DMA_CH4_CLR_INTR = 706 IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, do) | 707 IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, do); 708 } 709 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async); 710 } else { 711 if (port->use_dma) { 712 RESET_DMA(8); WAIT_DMA(8); 713 port->tr_running = 0; 714 port->out_count = 0; 715 port->outp = port->out_buffer; 716 *R_DMA_CH8_CLR_INTR = 717 IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, do) | 718 IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, do); 719 } 720 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async); 721 } 722 *R_GEN_CONFIG_II = gen_config_ii_shadow; 723 local_irq_restore(flags); 724 725 switch (cmd) { 726 case SSP_SPEED: 727 if (GET_SPEED(arg) == CODEC) { 728 if (dev) 729 SETS(sync_serial_prescale_shadow, 730 R_SYNC_SERIAL_PRESCALE, clk_sel_u3, 731 codec); 732 else 733 SETS(sync_serial_prescale_shadow, 734 R_SYNC_SERIAL_PRESCALE, clk_sel_u1, 735 codec); 736 737 SETF(sync_serial_prescale_shadow, 738 R_SYNC_SERIAL_PRESCALE, prescaler, 739 GET_FREQ(arg)); 740 SETF(sync_serial_prescale_shadow, 741 R_SYNC_SERIAL_PRESCALE, frame_rate, 742 GET_FRAME_RATE(arg)); 743 SETF(sync_serial_prescale_shadow, 744 R_SYNC_SERIAL_PRESCALE, word_rate, 745 GET_WORD_RATE(arg)); 746 } else { 747 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 748 tr_baud, GET_SPEED(arg)); 749 if (dev) 750 SETS(sync_serial_prescale_shadow, 751 R_SYNC_SERIAL_PRESCALE, clk_sel_u3, 752 baudrate); 753 else 754 SETS(sync_serial_prescale_shadow, 755 R_SYNC_SERIAL_PRESCALE, clk_sel_u1, 756 baudrate); 757 } 758 break; 759 case SSP_MODE: 760 if (arg > 5) 761 return -EINVAL; 762 if (arg == MASTER_OUTPUT || arg == SLAVE_OUTPUT) 763 *R_IRQ_MASK1_CLR = 1 << port->data_avail_bit; 764 else if (!port->use_dma) 765 *R_IRQ_MASK1_SET = 1 << port->data_avail_bit; 766 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, mode, arg); 767 break; 768 case SSP_FRAME_SYNC: 769 if (arg & NORMAL_SYNC) 770 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 771 f_synctype, normal); 772 else if (arg & EARLY_SYNC) 773 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 774 f_synctype, early); 775 776 if (arg & BIT_SYNC) 777 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 778 f_syncsize, bit); 779 else if (arg & WORD_SYNC) 780 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 781 f_syncsize, word); 782 else if (arg & EXTENDED_SYNC) 783 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 784 f_syncsize, extended); 785 786 if (arg & SYNC_ON) 787 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 788 f_sync, on); 789 else if (arg & SYNC_OFF) 790 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 791 f_sync, off); 792 793 if (arg & WORD_SIZE_8) 794 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 795 wordsize, size8bit); 796 else if (arg & WORD_SIZE_12) 797 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 798 wordsize, size12bit); 799 else if (arg & WORD_SIZE_16) 800 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 801 wordsize, size16bit); 802 else if (arg & WORD_SIZE_24) 803 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 804 wordsize, size24bit); 805 else if (arg & WORD_SIZE_32) 806 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 807 wordsize, size32bit); 808 809 if (arg & BIT_ORDER_MSB) 810 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 811 bitorder, msb); 812 else if (arg & BIT_ORDER_LSB) 813 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 814 bitorder, lsb); 815 816 if (arg & FLOW_CONTROL_ENABLE) 817 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 818 flow_ctrl, enabled); 819 else if (arg & FLOW_CONTROL_DISABLE) 820 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 821 flow_ctrl, disabled); 822 823 if (arg & CLOCK_NOT_GATED) 824 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 825 clk_mode, normal); 826 else if (arg & CLOCK_GATED) 827 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 828 clk_mode, gated); 829 830 break; 831 case SSP_IPOLARITY: 832 /* NOTE!! negedge is considered NORMAL */ 833 if (arg & CLOCK_NORMAL) 834 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 835 clk_polarity, neg); 836 else if (arg & CLOCK_INVERT) 837 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 838 clk_polarity, pos); 839 840 if (arg & FRAME_NORMAL) 841 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 842 frame_polarity, normal); 843 else if (arg & FRAME_INVERT) 844 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 845 frame_polarity, inverted); 846 847 if (arg & STATUS_NORMAL) 848 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 849 status_polarity, normal); 850 else if (arg & STATUS_INVERT) 851 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 852 status_polarity, inverted); 853 break; 854 case SSP_OPOLARITY: 855 if (arg & CLOCK_NORMAL) 856 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 857 clk_driver, normal); 858 else if (arg & CLOCK_INVERT) 859 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 860 clk_driver, inverted); 861 862 if (arg & FRAME_NORMAL) 863 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 864 frame_driver, normal); 865 else if (arg & FRAME_INVERT) 866 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 867 frame_driver, inverted); 868 869 if (arg & STATUS_NORMAL) 870 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 871 status_driver, normal); 872 else if (arg & STATUS_INVERT) 873 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 874 status_driver, inverted); 875 break; 876 case SSP_SPI: 877 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, flow_ctrl, 878 disabled); 879 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, bitorder, 880 msb); 881 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize, 882 size8bit); 883 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_sync, on); 884 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_syncsize, 885 word); 886 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_synctype, 887 normal); 888 if (arg & SPI_SLAVE) { 889 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 890 frame_polarity, inverted); 891 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 892 clk_polarity, neg); 893 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 894 mode, SLAVE_INPUT); 895 } else { 896 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 897 frame_driver, inverted); 898 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 899 clk_driver, inverted); 900 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 901 mode, MASTER_OUTPUT); 902 } 903 break; 904 case SSP_INBUFCHUNK: 905#if 0 906 if (arg > port->in_buffer_size/NUM_IN_DESCR) 907 return -EINVAL; 908 port->inbufchunk = arg; 909 /* Make sure in_buffer_size is a multiple of inbufchunk */ 910 port->in_buffer_size = 911 (port->in_buffer_size/port->inbufchunk) * 912 port->inbufchunk; 913 DEBUG(printk(KERN_DEBUG "inbufchunk %i in_buffer_size: %i\n", 914 port->inbufchunk, port->in_buffer_size)); 915 if (port->use_dma) { 916 if (port->port_nbr == 0) { 917 RESET_DMA(9); 918 WAIT_DMA(9); 919 } else { 920 RESET_DMA(5); 921 WAIT_DMA(5); 922 } 923 start_dma_in(port); 924 } 925#endif 926 break; 927 default: 928 return_val = -1; 929 } 930 /* Make sure we write the config without interruption */ 931 local_irq_save(flags); 932 /* Set config and enable port */ 933 *port->ctrl_data = port->ctrl_data_shadow; 934 nop(); nop(); nop(); nop(); 935 *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow; 936 nop(); nop(); nop(); nop(); 937 if (dev) 938 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync); 939 else 940 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync); 941 942 *R_GEN_CONFIG_II = gen_config_ii_shadow; 943 /* Reset DMA. At readout from serial port the data could be shifted 944 * one byte if not resetting DMA. 945 */ 946 if (port->use_dma) { 947 if (port->port_nbr == 0) { 948 RESET_DMA(9); 949 WAIT_DMA(9); 950 } else { 951 RESET_DMA(5); 952 WAIT_DMA(5); 953 } 954 start_dma_in(port); 955 } 956 local_irq_restore(flags); 957 return return_val; 958} 959 960static long sync_serial_ioctl(struct file *file, 961 unsigned int cmd, unsigned long arg) 962{ 963 long ret; 964 965 mutex_lock(&sync_serial_mutex); 966 ret = sync_serial_ioctl_unlocked(file, cmd, arg); 967 mutex_unlock(&sync_serial_mutex); 968 969 return ret; 970} 971 972 973static ssize_t sync_serial_write(struct file *file, const char *buf, 974 size_t count, loff_t *ppos) 975{ 976 int dev = MINOR(file->f_dentry->d_inode->i_rdev); 977 DECLARE_WAITQUEUE(wait, current); 978 struct sync_port *port; 979 unsigned long flags; 980 unsigned long c, c1; 981 unsigned long free_outp; 982 unsigned long outp; 983 unsigned long out_buffer; 984 985 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { 986 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); 987 return -ENODEV; 988 } 989 port = &ports[dev]; 990 991 DEBUGWRITE(printk(KERN_DEBUG "W d%d c %lu (%d/%d)\n", 992 port->port_nbr, count, port->out_count, OUT_BUFFER_SIZE)); 993 /* Space to end of buffer */ 994 /* 995 * out_buffer <c1>012345<- c ->OUT_BUFFER_SIZE 996 * outp^ +out_count 997 * ^free_outp 998 * out_buffer 45<- c ->0123OUT_BUFFER_SIZE 999 * +out_count outp^ 1000 * free_outp 1001 * 1002 */ 1003 1004 /* Read variables that may be updated by interrupts */ 1005 local_irq_save(flags); 1006 if (count > OUT_BUFFER_SIZE - port->out_count) 1007 count = OUT_BUFFER_SIZE - port->out_count; 1008 1009 outp = (unsigned long)port->outp; 1010 free_outp = outp + port->out_count; 1011 local_irq_restore(flags); 1012 out_buffer = (unsigned long)port->out_buffer; 1013 1014 /* Find out where and how much to write */ 1015 if (free_outp >= out_buffer + OUT_BUFFER_SIZE) 1016 free_outp -= OUT_BUFFER_SIZE; 1017 if (free_outp >= outp) 1018 c = out_buffer + OUT_BUFFER_SIZE - free_outp; 1019 else 1020 c = outp - free_outp; 1021 if (c > count) 1022 c = count; 1023 1024 DEBUGWRITE(printk(KERN_DEBUG "w op %08lX fop %08lX c %lu\n", 1025 outp, free_outp, c)); 1026 if (copy_from_user((void *)free_outp, buf, c)) 1027 return -EFAULT; 1028 1029 if (c != count) { 1030 buf += c; 1031 c1 = count - c; 1032 DEBUGWRITE(printk(KERN_DEBUG "w2 fi %lu c %lu c1 %lu\n", 1033 free_outp-out_buffer, c, c1)); 1034 if (copy_from_user((void *)out_buffer, buf, c1)) 1035 return -EFAULT; 1036 } 1037 local_irq_save(flags); 1038 port->out_count += count; 1039 local_irq_restore(flags); 1040 1041 /* Make sure transmitter/receiver is running */ 1042 if (!port->started) { 1043 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt, 1044 running); 1045 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable, 1046 enable); 1047 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable, 1048 enable); 1049 port->started = 1; 1050 } 1051 1052 *port->ctrl_data = port->ctrl_data_shadow; 1053 1054 if (file->f_flags & O_NONBLOCK) { 1055 local_irq_save(flags); 1056 if (!port->tr_running) { 1057 if (!port->use_dma) { 1058 /* Start sender by writing data */ 1059 send_word(port); 1060 /* and enable transmitter ready IRQ */ 1061 *R_IRQ_MASK1_SET = 1 << 1062 port->transmitter_ready_bit; 1063 } else 1064 start_dma(port, 1065 (unsigned char *volatile)port->outp, c); 1066 } 1067 local_irq_restore(flags); 1068 DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu NB\n", 1069 port->port_nbr, count)); 1070 return count; 1071 } 1072 1073 /* Sleep until all sent */ 1074 add_wait_queue(&port->out_wait_q, &wait); 1075 set_current_state(TASK_INTERRUPTIBLE); 1076 local_irq_save(flags); 1077 if (!port->tr_running) { 1078 if (!port->use_dma) { 1079 /* Start sender by writing data */ 1080 send_word(port); 1081 /* and enable transmitter ready IRQ */ 1082 *R_IRQ_MASK1_SET = 1 << port->transmitter_ready_bit; 1083 } else 1084 start_dma(port, port->outp, c); 1085 } 1086 local_irq_restore(flags); 1087 schedule(); 1088 set_current_state(TASK_RUNNING); 1089 remove_wait_queue(&port->out_wait_q, &wait); 1090 if (signal_pending(current)) 1091 return -EINTR; 1092 1093 DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu\n", port->port_nbr, count)); 1094 return count; 1095} 1096 1097static ssize_t sync_serial_read(struct file *file, char *buf, 1098 size_t count, loff_t *ppos) 1099{ 1100 int dev = MINOR(file->f_dentry->d_inode->i_rdev); 1101 int avail; 1102 struct sync_port *port; 1103 unsigned char *start; 1104 unsigned char *end; 1105 unsigned long flags; 1106 1107 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { 1108 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); 1109 return -ENODEV; 1110 } 1111 port = &ports[dev]; 1112 1113 DEBUGREAD(printk(KERN_DEBUG "R%d c %d ri %lu wi %lu /%lu\n", 1114 dev, count, port->readp - port->flip, 1115 port->writep - port->flip, port->in_buffer_size)); 1116 1117 if (!port->started) { 1118 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt, 1119 running); 1120 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable, 1121 enable); 1122 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable, 1123 enable); 1124 port->started = 1; 1125 } 1126 *port->ctrl_data = port->ctrl_data_shadow; 1127 1128 /* Calculate number of available bytes */ 1129 /* Save pointers to avoid that they are modified by interrupt */ 1130 local_irq_save(flags); 1131 start = (unsigned char *)port->readp; /* cast away volatile */ 1132 end = (unsigned char *)port->writep; /* cast away volatile */ 1133 local_irq_restore(flags); 1134 while (start == end && !port->full) { 1135 /* No data */ 1136 if (file->f_flags & O_NONBLOCK) 1137 return -EAGAIN; 1138 1139 interruptible_sleep_on(&port->in_wait_q); 1140 if (signal_pending(current)) 1141 return -EINTR; 1142 1143 local_irq_save(flags); 1144 start = (unsigned char *)port->readp; /* cast away volatile */ 1145 end = (unsigned char *)port->writep; /* cast away volatile */ 1146 local_irq_restore(flags); 1147 } 1148 1149 /* Lazy read, never return wrapped data. */ 1150 if (port->full) 1151 avail = port->in_buffer_size; 1152 else if (end > start) 1153 avail = end - start; 1154 else 1155 avail = port->flip + port->in_buffer_size - start; 1156 1157 count = count > avail ? avail : count; 1158 if (copy_to_user(buf, start, count)) 1159 return -EFAULT; 1160 /* Disable interrupts while updating readp */ 1161 local_irq_save(flags); 1162 port->readp += count; 1163 if (port->readp >= port->flip + port->in_buffer_size) /* Wrap? */ 1164 port->readp = port->flip; 1165 port->full = 0; 1166 local_irq_restore(flags); 1167 DEBUGREAD(printk(KERN_DEBUG "r %d\n", count)); 1168 return count; 1169} 1170 1171static void send_word(struct sync_port *port) 1172{ 1173 switch (IO_EXTRACT(R_SYNC_SERIAL1_CTRL, wordsize, 1174 port->ctrl_data_shadow)) { 1175 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit): 1176 port->out_count--; 1177 *port->data_out = *port->outp++; 1178 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) 1179 port->outp = port->out_buffer; 1180 break; 1181 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit): 1182 { 1183 int data = (*port->outp++) << 8; 1184 data |= *port->outp++; 1185 port->out_count -= 2; 1186 *port->data_out = data; 1187 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) 1188 port->outp = port->out_buffer; 1189 break; 1190 } 1191 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit): 1192 port->out_count -= 2; 1193 *port->data_out = *(unsigned short *)port->outp; 1194 port->outp += 2; 1195 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) 1196 port->outp = port->out_buffer; 1197 break; 1198 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit): 1199 port->out_count -= 3; 1200 *port->data_out = *(unsigned int *)port->outp; 1201 port->outp += 3; 1202 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) 1203 port->outp = port->out_buffer; 1204 break; 1205 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit): 1206 port->out_count -= 4; 1207 *port->data_out = *(unsigned int *)port->outp; 1208 port->outp += 4; 1209 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) 1210 port->outp = port->out_buffer; 1211 break; 1212 } 1213} 1214 1215 1216static void start_dma(struct sync_port *port, const char *data, int count) 1217{ 1218 port->tr_running = 1; 1219 port->out_descr.hw_len = 0; 1220 port->out_descr.next = 0; 1221 port->out_descr.ctrl = d_eol | d_eop; /* No d_wait to avoid glitches */ 1222 port->out_descr.sw_len = count; 1223 port->out_descr.buf = virt_to_phys(data); 1224 port->out_descr.status = 0; 1225 1226 *port->output_dma_first = virt_to_phys(&port->out_descr); 1227 *port->output_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start); 1228 DEBUGTXINT(printk(KERN_DEBUG "dma %08lX c %d\n", 1229 (unsigned long)data, count)); 1230} 1231 1232static void start_dma_in(struct sync_port *port) 1233{ 1234 int i; 1235 unsigned long buf; 1236 port->writep = port->flip; 1237 1238 if (port->writep > port->flip + port->in_buffer_size) { 1239 panic("Offset too large in sync serial driver\n"); 1240 return; 1241 } 1242 buf = virt_to_phys(port->in_buffer); 1243 for (i = 0; i < NUM_IN_DESCR; i++) { 1244 port->in_descr[i].sw_len = port->inbufchunk; 1245 port->in_descr[i].ctrl = d_int; 1246 port->in_descr[i].next = virt_to_phys(&port->in_descr[i+1]); 1247 port->in_descr[i].buf = buf; 1248 port->in_descr[i].hw_len = 0; 1249 port->in_descr[i].status = 0; 1250 port->in_descr[i].fifo_len = 0; 1251 buf += port->inbufchunk; 1252 prepare_rx_descriptor(&port->in_descr[i]); 1253 } 1254 /* Link the last descriptor to the first */ 1255 port->in_descr[i-1].next = virt_to_phys(&port->in_descr[0]); 1256 port->in_descr[i-1].ctrl |= d_eol; 1257 port->next_rx_desc = &port->in_descr[0]; 1258 port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR - 1]; 1259 *port->input_dma_first = virt_to_phys(port->next_rx_desc); 1260 *port->input_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start); 1261} 1262 1263#ifdef SYNC_SER_DMA 1264static irqreturn_t tr_interrupt(int irq, void *dev_id) 1265{ 1266 unsigned long ireg = *R_IRQ_MASK2_RD; 1267 struct etrax_dma_descr *descr; 1268 unsigned int sentl; 1269 int handled = 0; 1270 int i; 1271 1272 for (i = 0; i < NUMBER_OF_PORTS; i++) { 1273 struct sync_port *port = &ports[i]; 1274 if (!port->enabled || !port->use_dma) 1275 continue; 1276 1277 /* IRQ active for the port? */ 1278 if (!(ireg & (1 << port->output_dma_bit))) 1279 continue; 1280 1281 handled = 1; 1282 1283 /* Clear IRQ */ 1284 *port->output_dma_clr_irq = 1285 IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do) | 1286 IO_STATE(R_DMA_CH0_CLR_INTR, clr_descr, do); 1287 1288 descr = &port->out_descr; 1289 if (!(descr->status & d_stop)) 1290 sentl = descr->sw_len; 1291 else 1292 /* Otherwise find amount of data sent here */ 1293 sentl = descr->hw_len; 1294 1295 port->out_count -= sentl; 1296 port->outp += sentl; 1297 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) 1298 port->outp = port->out_buffer; 1299 if (port->out_count) { 1300 int c = port->out_buffer + OUT_BUFFER_SIZE - port->outp; 1301 if (c > port->out_count) 1302 c = port->out_count; 1303 DEBUGTXINT(printk(KERN_DEBUG 1304 "tx_int DMAWRITE %i %i\n", sentl, c)); 1305 start_dma(port, port->outp, c); 1306 } else { 1307 DEBUGTXINT(printk(KERN_DEBUG 1308 "tx_int DMA stop %i\n", sentl)); 1309 port->tr_running = 0; 1310 } 1311 /* wake up the waiting process */ 1312 wake_up_interruptible(&port->out_wait_q); 1313 } 1314 return IRQ_RETVAL(handled); 1315} /* tr_interrupt */ 1316 1317static irqreturn_t rx_interrupt(int irq, void *dev_id) 1318{ 1319 unsigned long ireg = *R_IRQ_MASK2_RD; 1320 int i; 1321 int handled = 0; 1322 1323 for (i = 0; i < NUMBER_OF_PORTS; i++) { 1324 struct sync_port *port = &ports[i]; 1325 1326 if (!port->enabled || !port->use_dma) 1327 continue; 1328 1329 if (!(ireg & (1 << port->input_dma_descr_bit))) 1330 continue; 1331 1332 /* Descriptor interrupt */ 1333 handled = 1; 1334 while (*port->input_dma_descr != 1335 virt_to_phys(port->next_rx_desc)) { 1336 if (port->writep + port->inbufchunk > port->flip + 1337 port->in_buffer_size) { 1338 int first_size = port->flip + 1339 port->in_buffer_size - port->writep; 1340 memcpy(port->writep, 1341 phys_to_virt(port->next_rx_desc->buf), 1342 first_size); 1343 memcpy(port->flip, 1344 phys_to_virt(port->next_rx_desc->buf + 1345 first_size), 1346 port->inbufchunk - first_size); 1347 port->writep = port->flip + 1348 port->inbufchunk - first_size; 1349 } else { 1350 memcpy(port->writep, 1351 phys_to_virt(port->next_rx_desc->buf), 1352 port->inbufchunk); 1353 port->writep += port->inbufchunk; 1354 if (port->writep >= port->flip 1355 + port->in_buffer_size) 1356 port->writep = port->flip; 1357 } 1358 if (port->writep == port->readp) 1359 port->full = 1; 1360 prepare_rx_descriptor(port->next_rx_desc); 1361 port->next_rx_desc->ctrl |= d_eol; 1362 port->prev_rx_desc->ctrl &= ~d_eol; 1363 port->prev_rx_desc = phys_to_virt((unsigned) 1364 port->next_rx_desc); 1365 port->next_rx_desc = phys_to_virt((unsigned) 1366 port->next_rx_desc->next); 1367 /* Wake up the waiting process */ 1368 wake_up_interruptible(&port->in_wait_q); 1369 *port->input_dma_cmd = IO_STATE(R_DMA_CH1_CMD, 1370 cmd, restart); 1371 /* DMA has reached end of descriptor */ 1372 *port->input_dma_clr_irq = IO_STATE(R_DMA_CH0_CLR_INTR, 1373 clr_descr, do); 1374 } 1375 } 1376 return IRQ_RETVAL(handled); 1377} /* rx_interrupt */ 1378#endif /* SYNC_SER_DMA */ 1379 1380#ifdef SYNC_SER_MANUAL 1381static irqreturn_t manual_interrupt(int irq, void *dev_id) 1382{ 1383 int i; 1384 int handled = 0; 1385 1386 for (i = 0; i < NUMBER_OF_PORTS; i++) { 1387 struct sync_port *port = &ports[i]; 1388 1389 if (!port->enabled || port->use_dma) 1390 continue; 1391 1392 /* Data received? */ 1393 if (*R_IRQ_MASK1_RD & (1 << port->data_avail_bit)) { 1394 handled = 1; 1395 /* Read data */ 1396 switch (port->ctrl_data_shadow & 1397 IO_MASK(R_SYNC_SERIAL1_CTRL, wordsize)) { 1398 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit): 1399 *port->writep++ = 1400 *(volatile char *)port->data_in; 1401 break; 1402 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit): 1403 { 1404 int data = *(unsigned short *)port->data_in; 1405 *port->writep = (data & 0x0ff0) >> 4; 1406 *(port->writep + 1) = data & 0x0f; 1407 port->writep += 2; 1408 break; 1409 } 1410 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit): 1411 *(unsigned short *)port->writep = 1412 *(volatile unsigned short *)port->data_in; 1413 port->writep += 2; 1414 break; 1415 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit): 1416 *(unsigned int *)port->writep = *port->data_in; 1417 port->writep += 3; 1418 break; 1419 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit): 1420 *(unsigned int *)port->writep = *port->data_in; 1421 port->writep += 4; 1422 break; 1423 } 1424 1425 /* Wrap? */ 1426 if (port->writep >= port->flip + port->in_buffer_size) 1427 port->writep = port->flip; 1428 if (port->writep == port->readp) { 1429 /* Receive buffer overrun, discard oldest */ 1430 port->readp++; 1431 /* Wrap? */ 1432 if (port->readp >= port->flip + 1433 port->in_buffer_size) 1434 port->readp = port->flip; 1435 } 1436 if (sync_data_avail(port) >= port->inbufchunk) { 1437 /* Wake up application */ 1438 wake_up_interruptible(&port->in_wait_q); 1439 } 1440 } 1441 1442 /* Transmitter ready? */ 1443 if (*R_IRQ_MASK1_RD & (1 << port->transmitter_ready_bit)) { 1444 if (port->out_count > 0) { 1445 /* More data to send */ 1446 send_word(port); 1447 } else { 1448 /* Transmission finished */ 1449 /* Turn off IRQ */ 1450 *R_IRQ_MASK1_CLR = 1 << 1451 port->transmitter_ready_bit; 1452 /* Wake up application */ 1453 wake_up_interruptible(&port->out_wait_q); 1454 } 1455 } 1456 } 1457 return IRQ_RETVAL(handled); 1458} 1459#endif 1460 1461module_init(etrax_sync_serial_init); 1462