1#include <linux/pci.h>
2#include <linux/kernel.h>
3#include <arch/hwregs/intr_vect.h>
4
5void __devinit  pcibios_fixup_bus(struct pci_bus *b)
6{
7}
8
9char * __devinit  pcibios_setup(char *str)
10{
11	return NULL;
12}
13
14void pcibios_set_master(struct pci_dev *dev)
15{
16	u8 lat;
17	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
18	printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
19	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
20}
21
22int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
23			enum pci_mmap_state mmap_state, int write_combine)
24{
25	unsigned long prot;
26
27	/* Leave vm_pgoff as-is, the PCI space address is the physical
28	 * address on this platform.
29	 */
30	prot = pgprot_val(vma->vm_page_prot);
31	vma->vm_page_prot = __pgprot(prot);
32
33	/* Write-combine setting is ignored, it is changed via the mtrr
34	 * interfaces on this platform.
35	 */
36	if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
37			     vma->vm_end - vma->vm_start,
38			     vma->vm_page_prot))
39		return -EAGAIN;
40
41	return 0;
42}
43
44resource_size_t
45pcibios_align_resource(void *data, const struct resource *res,
46		       resource_size_t size, resource_size_t align)
47{
48	resource_size_t start = res->start;
49
50	if ((res->flags & IORESOURCE_IO) && (start & 0x300))
51		start = (start + 0x3ff) & ~0x3ff;
52
53	return start;
54}
55
56int pcibios_enable_resources(struct pci_dev *dev, int mask)
57{
58	u16 cmd, old_cmd;
59	int idx;
60	struct resource *r;
61
62	pci_read_config_word(dev, PCI_COMMAND, &cmd);
63	old_cmd = cmd;
64	for(idx=0; idx<6; idx++) {
65		/* Only set up the requested stuff */
66		if (!(mask & (1<<idx)))
67			continue;
68
69		r = &dev->resource[idx];
70		if (!r->start && r->end) {
71			printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
72			return -EINVAL;
73		}
74		if (r->flags & IORESOURCE_IO)
75			cmd |= PCI_COMMAND_IO;
76		if (r->flags & IORESOURCE_MEM)
77			cmd |= PCI_COMMAND_MEMORY;
78	}
79	if (dev->resource[PCI_ROM_RESOURCE].start)
80		cmd |= PCI_COMMAND_MEMORY;
81	if (cmd != old_cmd) {
82		printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
83		pci_write_config_word(dev, PCI_COMMAND, cmd);
84	}
85	return 0;
86}
87
88int pcibios_enable_irq(struct pci_dev *dev)
89{
90	dev->irq = EXT_INTR_VECT;
91	return 0;
92}
93
94int pcibios_enable_device(struct pci_dev *dev, int mask)
95{
96	int err;
97
98	if ((err = pcibios_enable_resources(dev, mask)) < 0)
99		return err;
100
101	if (!dev->msi_enabled)
102		pcibios_enable_irq(dev);
103	return 0;
104}
105
106int pcibios_assign_resources(void)
107{
108	struct pci_dev *dev = NULL;
109	int idx;
110	struct resource *r;
111
112	while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
113		int class = dev->class >> 8;
114
115		/* Don't touch classless devices and host bridges */
116		if (!class || class == PCI_CLASS_BRIDGE_HOST)
117			continue;
118
119		for(idx=0; idx<6; idx++) {
120			r = &dev->resource[idx];
121
122			if (!r->start && r->end)
123				pci_assign_resource(dev, idx);
124		}
125	}
126	return 0;
127}
128
129EXPORT_SYMBOL(pcibios_assign_resources);
130