11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This file is subject to the terms and conditions of the GNU General Public 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * License. See the file "COPYING" in the main directory of this archive 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * for more details. 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Inline assembly cache operations. 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 879add6277396b91c638f16eb2f1338badc47760dJustin P. Mattock * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright (C) 1997 - 2002 Ralf Baechle (ralf@gnu.org) 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org) 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifndef _ASM_R4KCACHE_H 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define _ASM_R4KCACHE_H 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/asm.h> 161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/cacheops.h> 1741700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto#include <asm/cpu-features.h> 1841c594ab65fc89573af296d192aa5235d09717abRalf Baechle#include <asm/mipsmtregs.h> 191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This macro return a properly sign-extended address suitable as base address 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * for indexed cache operations. Two issues here: 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - The MIPS32 and MIPS64 specs permit an implementation to directly derive 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the index bits from the virtual address. This breaks with tradition 262fe25f67a55ea0e6416304fa43d58fae93b7300aThiemo Seufer * set by the R4000. To keep unpleasant surprises from happening we pick 271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * an address in KSEG0 / CKSEG0. 281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * - We need a properly sign extended address for 64-bit code. To get away 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * without ifdefs we let the compiler do it by a type cast. 301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define INDEX_BASE CKSEG0 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define cache_op(op,addr) \ 341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __asm__ __volatile__( \ 352fe25f67a55ea0e6416304fa43d58fae93b7300aThiemo Seufer " .set push \n" \ 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " .set noreorder \n" \ 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " .set mips3\n\t \n" \ 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %0, %1 \n" \ 392fe25f67a55ea0e6416304fa43d58fae93b7300aThiemo Seufer " .set pop \n" \ 401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds : \ 41675055bfb5f99be56a20a6a214439adf23591786Ralf Baechle : "i" (op), "R" (*(unsigned char *)(addr))) 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4341c594ab65fc89573af296d192aa5235d09717abRalf Baechle#ifdef CONFIG_MIPS_MT 4441c594ab65fc89573af296d192aa5235d09717abRalf Baechle/* 4541c594ab65fc89573af296d192aa5235d09717abRalf Baechle * Temporary hacks for SMTC debug. Optionally force single-threaded 4641c594ab65fc89573af296d192aa5235d09717abRalf Baechle * execution during I-cache flushes. 4741c594ab65fc89573af296d192aa5235d09717abRalf Baechle */ 4841c594ab65fc89573af296d192aa5235d09717abRalf Baechle 4941c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define PROTECT_CACHE_FLUSHES 1 5041c594ab65fc89573af296d192aa5235d09717abRalf Baechle 5141c594ab65fc89573af296d192aa5235d09717abRalf Baechle#ifdef PROTECT_CACHE_FLUSHES 5241c594ab65fc89573af296d192aa5235d09717abRalf Baechle 5341c594ab65fc89573af296d192aa5235d09717abRalf Baechleextern int mt_protiflush; 5441c594ab65fc89573af296d192aa5235d09717abRalf Baechleextern int mt_protdflush; 5541c594ab65fc89573af296d192aa5235d09717abRalf Baechleextern void mt_cflush_lockdown(void); 5641c594ab65fc89573af296d192aa5235d09717abRalf Baechleextern void mt_cflush_release(void); 5741c594ab65fc89573af296d192aa5235d09717abRalf Baechle 5841c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define BEGIN_MT_IPROT \ 5941c594ab65fc89573af296d192aa5235d09717abRalf Baechle unsigned long flags = 0; \ 6041c594ab65fc89573af296d192aa5235d09717abRalf Baechle unsigned long mtflags = 0; \ 6141c594ab65fc89573af296d192aa5235d09717abRalf Baechle if(mt_protiflush) { \ 6241c594ab65fc89573af296d192aa5235d09717abRalf Baechle local_irq_save(flags); \ 6341c594ab65fc89573af296d192aa5235d09717abRalf Baechle ehb(); \ 6441c594ab65fc89573af296d192aa5235d09717abRalf Baechle mtflags = dvpe(); \ 6541c594ab65fc89573af296d192aa5235d09717abRalf Baechle mt_cflush_lockdown(); \ 6641c594ab65fc89573af296d192aa5235d09717abRalf Baechle } 6741c594ab65fc89573af296d192aa5235d09717abRalf Baechle 6841c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define END_MT_IPROT \ 6941c594ab65fc89573af296d192aa5235d09717abRalf Baechle if(mt_protiflush) { \ 7041c594ab65fc89573af296d192aa5235d09717abRalf Baechle mt_cflush_release(); \ 7141c594ab65fc89573af296d192aa5235d09717abRalf Baechle evpe(mtflags); \ 7241c594ab65fc89573af296d192aa5235d09717abRalf Baechle local_irq_restore(flags); \ 7341c594ab65fc89573af296d192aa5235d09717abRalf Baechle } 7441c594ab65fc89573af296d192aa5235d09717abRalf Baechle 7541c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define BEGIN_MT_DPROT \ 7641c594ab65fc89573af296d192aa5235d09717abRalf Baechle unsigned long flags = 0; \ 7741c594ab65fc89573af296d192aa5235d09717abRalf Baechle unsigned long mtflags = 0; \ 7841c594ab65fc89573af296d192aa5235d09717abRalf Baechle if(mt_protdflush) { \ 7941c594ab65fc89573af296d192aa5235d09717abRalf Baechle local_irq_save(flags); \ 8041c594ab65fc89573af296d192aa5235d09717abRalf Baechle ehb(); \ 8141c594ab65fc89573af296d192aa5235d09717abRalf Baechle mtflags = dvpe(); \ 8241c594ab65fc89573af296d192aa5235d09717abRalf Baechle mt_cflush_lockdown(); \ 8341c594ab65fc89573af296d192aa5235d09717abRalf Baechle } 8441c594ab65fc89573af296d192aa5235d09717abRalf Baechle 8541c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define END_MT_DPROT \ 8641c594ab65fc89573af296d192aa5235d09717abRalf Baechle if(mt_protdflush) { \ 8741c594ab65fc89573af296d192aa5235d09717abRalf Baechle mt_cflush_release(); \ 8841c594ab65fc89573af296d192aa5235d09717abRalf Baechle evpe(mtflags); \ 8941c594ab65fc89573af296d192aa5235d09717abRalf Baechle local_irq_restore(flags); \ 9041c594ab65fc89573af296d192aa5235d09717abRalf Baechle } 9141c594ab65fc89573af296d192aa5235d09717abRalf Baechle 9241c594ab65fc89573af296d192aa5235d09717abRalf Baechle#else 9341c594ab65fc89573af296d192aa5235d09717abRalf Baechle 9441c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define BEGIN_MT_IPROT 9541c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define BEGIN_MT_DPROT 9641c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define END_MT_IPROT 9741c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define END_MT_DPROT 9841c594ab65fc89573af296d192aa5235d09717abRalf Baechle 9941c594ab65fc89573af296d192aa5235d09717abRalf Baechle#endif /* PROTECT_CACHE_FLUSHES */ 10041c594ab65fc89573af296d192aa5235d09717abRalf Baechle 10141c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define __iflush_prologue \ 10241c594ab65fc89573af296d192aa5235d09717abRalf Baechle unsigned long redundance; \ 10341c594ab65fc89573af296d192aa5235d09717abRalf Baechle extern int mt_n_iflushes; \ 10441c594ab65fc89573af296d192aa5235d09717abRalf Baechle BEGIN_MT_IPROT \ 10541c594ab65fc89573af296d192aa5235d09717abRalf Baechle for (redundance = 0; redundance < mt_n_iflushes; redundance++) { 10641c594ab65fc89573af296d192aa5235d09717abRalf Baechle 10741c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define __iflush_epilogue \ 10841c594ab65fc89573af296d192aa5235d09717abRalf Baechle END_MT_IPROT \ 10941c594ab65fc89573af296d192aa5235d09717abRalf Baechle } 11041c594ab65fc89573af296d192aa5235d09717abRalf Baechle 11141c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define __dflush_prologue \ 11241c594ab65fc89573af296d192aa5235d09717abRalf Baechle unsigned long redundance; \ 11341c594ab65fc89573af296d192aa5235d09717abRalf Baechle extern int mt_n_dflushes; \ 11441c594ab65fc89573af296d192aa5235d09717abRalf Baechle BEGIN_MT_DPROT \ 11541c594ab65fc89573af296d192aa5235d09717abRalf Baechle for (redundance = 0; redundance < mt_n_dflushes; redundance++) { 11641c594ab65fc89573af296d192aa5235d09717abRalf Baechle 11741c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define __dflush_epilogue \ 11841c594ab65fc89573af296d192aa5235d09717abRalf Baechle END_MT_DPROT \ 11941c594ab65fc89573af296d192aa5235d09717abRalf Baechle } 12041c594ab65fc89573af296d192aa5235d09717abRalf Baechle 12141c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define __inv_dflush_prologue __dflush_prologue 12241c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define __inv_dflush_epilogue __dflush_epilogue 12341c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define __sflush_prologue { 12441c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define __sflush_epilogue } 12541c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define __inv_sflush_prologue __sflush_prologue 12641c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define __inv_sflush_epilogue __sflush_epilogue 12741c594ab65fc89573af296d192aa5235d09717abRalf Baechle 12841c594ab65fc89573af296d192aa5235d09717abRalf Baechle#else /* CONFIG_MIPS_MT */ 12941c594ab65fc89573af296d192aa5235d09717abRalf Baechle 13041c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define __iflush_prologue { 13141c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define __iflush_epilogue } 13241c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define __dflush_prologue { 13341c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define __dflush_epilogue } 13441c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define __inv_dflush_prologue { 13541c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define __inv_dflush_epilogue } 13641c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define __sflush_prologue { 13741c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define __sflush_epilogue } 13841c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define __inv_sflush_prologue { 13941c594ab65fc89573af296d192aa5235d09717abRalf Baechle#define __inv_sflush_epilogue } 14041c594ab65fc89573af296d192aa5235d09717abRalf Baechle 14141c594ab65fc89573af296d192aa5235d09717abRalf Baechle#endif /* CONFIG_MIPS_MT */ 14241c594ab65fc89573af296d192aa5235d09717abRalf Baechle 1431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline void flush_icache_line_indexed(unsigned long addr) 1441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 14541c594ab65fc89573af296d192aa5235d09717abRalf Baechle __iflush_prologue 1461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cache_op(Index_Invalidate_I, addr); 14741c594ab65fc89573af296d192aa5235d09717abRalf Baechle __iflush_epilogue 1481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 1491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline void flush_dcache_line_indexed(unsigned long addr) 1511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 15241c594ab65fc89573af296d192aa5235d09717abRalf Baechle __dflush_prologue 1531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cache_op(Index_Writeback_Inv_D, addr); 15441c594ab65fc89573af296d192aa5235d09717abRalf Baechle __dflush_epilogue 1551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 1561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline void flush_scache_line_indexed(unsigned long addr) 1581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 1591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cache_op(Index_Writeback_Inv_SD, addr); 1601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 1611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline void flush_icache_line(unsigned long addr) 1631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 16441c594ab65fc89573af296d192aa5235d09717abRalf Baechle __iflush_prologue 1651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cache_op(Hit_Invalidate_I, addr); 16641c594ab65fc89573af296d192aa5235d09717abRalf Baechle __iflush_epilogue 1671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 1681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline void flush_dcache_line(unsigned long addr) 1701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 17141c594ab65fc89573af296d192aa5235d09717abRalf Baechle __dflush_prologue 1721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cache_op(Hit_Writeback_Inv_D, addr); 17341c594ab65fc89573af296d192aa5235d09717abRalf Baechle __dflush_epilogue 1741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 1751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline void invalidate_dcache_line(unsigned long addr) 1771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 17841c594ab65fc89573af296d192aa5235d09717abRalf Baechle __dflush_prologue 1791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cache_op(Hit_Invalidate_D, addr); 18041c594ab65fc89573af296d192aa5235d09717abRalf Baechle __dflush_epilogue 1811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 1821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline void invalidate_scache_line(unsigned long addr) 1841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 1851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cache_op(Hit_Invalidate_SD, addr); 1861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 1871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline void flush_scache_line(unsigned long addr) 1891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 1901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cache_op(Hit_Writeback_Inv_SD, addr); 1911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 1921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 19341700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto#define protected_cache_op(op,addr) \ 19441700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto __asm__ __volatile__( \ 19541700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto " .set push \n" \ 19641700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto " .set noreorder \n" \ 19741700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto " .set mips3 \n" \ 19841700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto "1: cache %0, (%1) \n" \ 19941700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto "2: .set pop \n" \ 20041700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto " .section __ex_table,\"a\" \n" \ 20141700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto " "STR(PTR)" 1b, 2b \n" \ 20241700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto " .previous" \ 20341700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto : \ 20441700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto : "i" (op), "r" (addr)) 20541700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto 2061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * The next two are for badland addresses like signal trampolines. 2081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline void protected_flush_icache_line(unsigned long addr) 2101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 21141700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto protected_cache_op(Hit_Invalidate_I, addr); 2121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 2131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D 2161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style 2171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * caches. We're talking about one cacheline unnecessarily getting invalidated 2182fe25f67a55ea0e6416304fa43d58fae93b7300aThiemo Seufer * here so the penalty isn't overly hard. 2191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline void protected_writeback_dcache_line(unsigned long addr) 2211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 22241700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto protected_cache_op(Hit_Writeback_Inv_D, addr); 2231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 2241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline void protected_writeback_scache_line(unsigned long addr) 2261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 22741700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto protected_cache_op(Hit_Writeback_Inv_SD, addr); 2281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 2291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This one is RM7000-specific 2321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline void invalidate_tcache_page(unsigned long addr) 2341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 2351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cache_op(Page_Invalidate_T, addr); 2361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 2371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define cache16_unroll32(base,op) \ 2391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __asm__ __volatile__( \ 2402fe25f67a55ea0e6416304fa43d58fae93b7300aThiemo Seufer " .set push \n" \ 2411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " .set noreorder \n" \ 2421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " .set mips3 \n" \ 2431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ 2441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \ 2451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \ 2461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \ 2471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \ 2481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \ 2491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \ 2501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \ 2511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \ 2521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \ 2531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \ 2541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \ 2551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \ 2561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \ 2571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \ 2581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \ 2592fe25f67a55ea0e6416304fa43d58fae93b7300aThiemo Seufer " .set pop \n" \ 2601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds : \ 2611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds : "r" (base), \ 2621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "i" (op)); 2631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define cache32_unroll32(base,op) \ 2651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __asm__ __volatile__( \ 2662fe25f67a55ea0e6416304fa43d58fae93b7300aThiemo Seufer " .set push \n" \ 2671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " .set noreorder \n" \ 2681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " .set mips3 \n" \ 2691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x000(%0); cache %1, 0x020(%0) \n" \ 2701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x040(%0); cache %1, 0x060(%0) \n" \ 2711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x080(%0); cache %1, 0x0a0(%0) \n" \ 2721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x0c0(%0); cache %1, 0x0e0(%0) \n" \ 2731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x100(%0); cache %1, 0x120(%0) \n" \ 2741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x140(%0); cache %1, 0x160(%0) \n" \ 2751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x180(%0); cache %1, 0x1a0(%0) \n" \ 2761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x1c0(%0); cache %1, 0x1e0(%0) \n" \ 2771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x200(%0); cache %1, 0x220(%0) \n" \ 2781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x240(%0); cache %1, 0x260(%0) \n" \ 2791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x280(%0); cache %1, 0x2a0(%0) \n" \ 2801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x2c0(%0); cache %1, 0x2e0(%0) \n" \ 2811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x300(%0); cache %1, 0x320(%0) \n" \ 2821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x340(%0); cache %1, 0x360(%0) \n" \ 2831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x380(%0); cache %1, 0x3a0(%0) \n" \ 2841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x3c0(%0); cache %1, 0x3e0(%0) \n" \ 2852fe25f67a55ea0e6416304fa43d58fae93b7300aThiemo Seufer " .set pop \n" \ 2861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds : \ 2871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds : "r" (base), \ 2881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "i" (op)); 2891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define cache64_unroll32(base,op) \ 2911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __asm__ __volatile__( \ 2922fe25f67a55ea0e6416304fa43d58fae93b7300aThiemo Seufer " .set push \n" \ 2931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " .set noreorder \n" \ 2941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " .set mips3 \n" \ 2951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x000(%0); cache %1, 0x040(%0) \n" \ 2961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x080(%0); cache %1, 0x0c0(%0) \n" \ 2971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x100(%0); cache %1, 0x140(%0) \n" \ 2981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x180(%0); cache %1, 0x1c0(%0) \n" \ 2991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x200(%0); cache %1, 0x240(%0) \n" \ 3001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x280(%0); cache %1, 0x2c0(%0) \n" \ 3011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x300(%0); cache %1, 0x340(%0) \n" \ 3021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x380(%0); cache %1, 0x3c0(%0) \n" \ 3031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x400(%0); cache %1, 0x440(%0) \n" \ 3041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x480(%0); cache %1, 0x4c0(%0) \n" \ 3051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x500(%0); cache %1, 0x540(%0) \n" \ 3061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x580(%0); cache %1, 0x5c0(%0) \n" \ 3071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x600(%0); cache %1, 0x640(%0) \n" \ 3081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x680(%0); cache %1, 0x6c0(%0) \n" \ 3091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x700(%0); cache %1, 0x740(%0) \n" \ 3101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x780(%0); cache %1, 0x7c0(%0) \n" \ 3112fe25f67a55ea0e6416304fa43d58fae93b7300aThiemo Seufer " .set pop \n" \ 3121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds : \ 3131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds : "r" (base), \ 3141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "i" (op)); 3151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define cache128_unroll32(base,op) \ 3171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __asm__ __volatile__( \ 3182fe25f67a55ea0e6416304fa43d58fae93b7300aThiemo Seufer " .set push \n" \ 3191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " .set noreorder \n" \ 3201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " .set mips3 \n" \ 3211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x000(%0); cache %1, 0x080(%0) \n" \ 3221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x100(%0); cache %1, 0x180(%0) \n" \ 3231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x200(%0); cache %1, 0x280(%0) \n" \ 3241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x300(%0); cache %1, 0x380(%0) \n" \ 3251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x400(%0); cache %1, 0x480(%0) \n" \ 3261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x500(%0); cache %1, 0x580(%0) \n" \ 3271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x600(%0); cache %1, 0x680(%0) \n" \ 3281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x700(%0); cache %1, 0x780(%0) \n" \ 3291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x800(%0); cache %1, 0x880(%0) \n" \ 3301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0x900(%0); cache %1, 0x980(%0) \n" \ 3311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0xa00(%0); cache %1, 0xa80(%0) \n" \ 3321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0xb00(%0); cache %1, 0xb80(%0) \n" \ 3331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0xc00(%0); cache %1, 0xc80(%0) \n" \ 3341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0xd00(%0); cache %1, 0xd80(%0) \n" \ 3351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0xe00(%0); cache %1, 0xe80(%0) \n" \ 3361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds " cache %1, 0xf00(%0); cache %1, 0xf80(%0) \n" \ 3372fe25f67a55ea0e6416304fa43d58fae93b7300aThiemo Seufer " .set pop \n" \ 3381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds : \ 3391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds : "r" (base), \ 3401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "i" (op)); 3411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 34276f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */ 34376f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \ 34476f072a46f179be371aa10a84c85db06a387713bAtsushi Nemotostatic inline void blast_##pfx##cache##lsize(void) \ 34576f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto{ \ 34676f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto unsigned long start = INDEX_BASE; \ 34776f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto unsigned long end = start + current_cpu_data.desc.waysize; \ 34876f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ 34976f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto unsigned long ws_end = current_cpu_data.desc.ways << \ 35076f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto current_cpu_data.desc.waybit; \ 35176f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto unsigned long ws, addr; \ 35276f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto \ 35341c594ab65fc89573af296d192aa5235d09717abRalf Baechle __##pfx##flush_prologue \ 35441c594ab65fc89573af296d192aa5235d09717abRalf Baechle \ 35576f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto for (ws = 0; ws < ws_end; ws += ws_inc) \ 35676f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto for (addr = start; addr < end; addr += lsize * 32) \ 35721a151d8ca3aa74ee79f9791a9d4dc370d3e0636Ralf Baechle cache##lsize##_unroll32(addr|ws, indexop); \ 35841c594ab65fc89573af296d192aa5235d09717abRalf Baechle \ 35941c594ab65fc89573af296d192aa5235d09717abRalf Baechle __##pfx##flush_epilogue \ 36076f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto} \ 36176f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto \ 36276f072a46f179be371aa10a84c85db06a387713bAtsushi Nemotostatic inline void blast_##pfx##cache##lsize##_page(unsigned long page) \ 36376f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto{ \ 36476f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto unsigned long start = page; \ 36576f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto unsigned long end = page + PAGE_SIZE; \ 36676f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto \ 36741c594ab65fc89573af296d192aa5235d09717abRalf Baechle __##pfx##flush_prologue \ 36841c594ab65fc89573af296d192aa5235d09717abRalf Baechle \ 36976f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto do { \ 37021a151d8ca3aa74ee79f9791a9d4dc370d3e0636Ralf Baechle cache##lsize##_unroll32(start, hitop); \ 37176f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto start += lsize * 32; \ 37276f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto } while (start < end); \ 37341c594ab65fc89573af296d192aa5235d09717abRalf Baechle \ 37441c594ab65fc89573af296d192aa5235d09717abRalf Baechle __##pfx##flush_epilogue \ 37576f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto} \ 37676f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto \ 37776f072a46f179be371aa10a84c85db06a387713bAtsushi Nemotostatic inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \ 37876f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto{ \ 379de62893bc0725f8b5f0445250577cd7a10b2d8f8Atsushi Nemoto unsigned long indexmask = current_cpu_data.desc.waysize - 1; \ 380de62893bc0725f8b5f0445250577cd7a10b2d8f8Atsushi Nemoto unsigned long start = INDEX_BASE + (page & indexmask); \ 38176f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto unsigned long end = start + PAGE_SIZE; \ 38276f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ 38376f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto unsigned long ws_end = current_cpu_data.desc.ways << \ 38476f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto current_cpu_data.desc.waybit; \ 38576f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto unsigned long ws, addr; \ 38676f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto \ 38741c594ab65fc89573af296d192aa5235d09717abRalf Baechle __##pfx##flush_prologue \ 38841c594ab65fc89573af296d192aa5235d09717abRalf Baechle \ 38976f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto for (ws = 0; ws < ws_end; ws += ws_inc) \ 39076f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto for (addr = start; addr < end; addr += lsize * 32) \ 39121a151d8ca3aa74ee79f9791a9d4dc370d3e0636Ralf Baechle cache##lsize##_unroll32(addr|ws, indexop); \ 39241c594ab65fc89573af296d192aa5235d09717abRalf Baechle \ 39341c594ab65fc89573af296d192aa5235d09717abRalf Baechle __##pfx##flush_epilogue \ 39476f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto} 39576f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto 39676f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16) 39776f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16) 39876f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16) 39976f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32) 40076f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32) 40176f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32) 402605b7ef7b79cee8e36ae5c48700e1a1eec74d38aKevin Cernekee__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64) 40376f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) 40476f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64) 40576f072a46f179be371aa10a84c85db06a387713bAtsushi Nemoto__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128) 4061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 407e9c33572a92aa2ee565da5136745ea304ac23d9aThomas Bogendoerfer__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16) 408e9c33572a92aa2ee565da5136745ea304ac23d9aThomas Bogendoerfer__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32) 409e9c33572a92aa2ee565da5136745ea304ac23d9aThomas Bogendoerfer__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16) 410e9c33572a92aa2ee565da5136745ea304ac23d9aThomas Bogendoerfer__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32) 411e9c33572a92aa2ee565da5136745ea304ac23d9aThomas Bogendoerfer__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64) 412e9c33572a92aa2ee565da5136745ea304ac23d9aThomas Bogendoerfer__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128) 413e9c33572a92aa2ee565da5136745ea304ac23d9aThomas Bogendoerfer 41441700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto/* build blast_xxx_range, protected_blast_xxx_range */ 41541700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \ 41641700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemotostatic inline void prot##blast_##pfx##cache##_range(unsigned long start, \ 41741700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto unsigned long end) \ 41841700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto{ \ 41941700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto unsigned long lsize = cpu_##desc##_line_size(); \ 42041700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto unsigned long addr = start & ~(lsize - 1); \ 42141700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto unsigned long aend = (end - 1) & ~(lsize - 1); \ 42241c594ab65fc89573af296d192aa5235d09717abRalf Baechle \ 42341c594ab65fc89573af296d192aa5235d09717abRalf Baechle __##pfx##flush_prologue \ 42441c594ab65fc89573af296d192aa5235d09717abRalf Baechle \ 42541700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto while (1) { \ 42641700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto prot##cache_op(hitop, addr); \ 42741700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto if (addr == aend) \ 42841700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto break; \ 42941700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto addr += lsize; \ 43041700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto } \ 43141c594ab65fc89573af296d192aa5235d09717abRalf Baechle \ 43241c594ab65fc89573af296d192aa5235d09717abRalf Baechle __##pfx##flush_epilogue \ 43341700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto} 43441700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto 43541700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_) 43641700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_) 43741700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_) 43841700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, ) 43941700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, ) 44041700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto/* blast_inv_dcache_range */ 44141700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, ) 44237caa934af02bc01d0e1366a49e1c89360fa0f29Atsushi Nemoto__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, ) 44341700e73995d6c814932cb55e12525bd34be1ca5Atsushi Nemoto 4441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif /* _ASM_R4KCACHE_H */ 445