perf_event_mipsxx.c revision 2c1b54d331bde7afbf8da24789cce2402e155495
1/* 2 * Linux performance counter support for MIPS. 3 * 4 * Copyright (C) 2010 MIPS Technologies, Inc. 5 * Copyright (C) 2011 Cavium Networks, Inc. 6 * Author: Deng-Cheng Zhu 7 * 8 * This code is based on the implementation for ARM, which is in turn 9 * based on the sparc64 perf event code and the x86 code. Performance 10 * counter access is based on the MIPS Oprofile code. And the callchain 11 * support references the code of MIPS stacktrace.c. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License version 2 as 15 * published by the Free Software Foundation. 16 */ 17 18#include <linux/cpumask.h> 19#include <linux/interrupt.h> 20#include <linux/smp.h> 21#include <linux/kernel.h> 22#include <linux/perf_event.h> 23#include <linux/uaccess.h> 24 25#include <asm/irq.h> 26#include <asm/irq_regs.h> 27#include <asm/stacktrace.h> 28#include <asm/time.h> /* For perf_irq */ 29 30#define MIPS_MAX_HWEVENTS 4 31 32struct cpu_hw_events { 33 /* Array of events on this cpu. */ 34 struct perf_event *events[MIPS_MAX_HWEVENTS]; 35 36 /* 37 * Set the bit (indexed by the counter number) when the counter 38 * is used for an event. 39 */ 40 unsigned long used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)]; 41 42 /* 43 * Software copy of the control register for each performance counter. 44 * MIPS CPUs vary in performance counters. They use this differently, 45 * and even may not use it. 46 */ 47 unsigned int saved_ctrl[MIPS_MAX_HWEVENTS]; 48}; 49DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { 50 .saved_ctrl = {0}, 51}; 52 53/* The description of MIPS performance events. */ 54struct mips_perf_event { 55 unsigned int event_id; 56 /* 57 * MIPS performance counters are indexed starting from 0. 58 * CNTR_EVEN indicates the indexes of the counters to be used are 59 * even numbers. 60 */ 61 unsigned int cntr_mask; 62 #define CNTR_EVEN 0x55555555 63 #define CNTR_ODD 0xaaaaaaaa 64 #define CNTR_ALL 0xffffffff 65#ifdef CONFIG_MIPS_MT_SMP 66 enum { 67 T = 0, 68 V = 1, 69 P = 2, 70 } range; 71#else 72 #define T 73 #define V 74 #define P 75#endif 76}; 77 78static struct mips_perf_event raw_event; 79static DEFINE_MUTEX(raw_event_mutex); 80 81#define UNSUPPORTED_PERF_EVENT_ID 0xffffffff 82#define C(x) PERF_COUNT_HW_CACHE_##x 83 84struct mips_pmu { 85 u64 max_period; 86 u64 valid_count; 87 u64 overflow; 88 const char *name; 89 int irq; 90 u64 (*read_counter)(unsigned int idx); 91 void (*write_counter)(unsigned int idx, u64 val); 92 const struct mips_perf_event *(*map_raw_event)(u64 config); 93 const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX]; 94 const struct mips_perf_event (*cache_event_map) 95 [PERF_COUNT_HW_CACHE_MAX] 96 [PERF_COUNT_HW_CACHE_OP_MAX] 97 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 98 unsigned int num_counters; 99}; 100 101static struct mips_pmu mipspmu; 102 103#define M_CONFIG1_PC (1 << 4) 104 105#define M_PERFCTL_EXL (1 << 0) 106#define M_PERFCTL_KERNEL (1 << 1) 107#define M_PERFCTL_SUPERVISOR (1 << 2) 108#define M_PERFCTL_USER (1 << 3) 109#define M_PERFCTL_INTERRUPT_ENABLE (1 << 4) 110#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5) 111#define M_PERFCTL_VPEID(vpe) ((vpe) << 16) 112#define M_PERFCTL_MT_EN(filter) ((filter) << 20) 113#define M_TC_EN_ALL M_PERFCTL_MT_EN(0) 114#define M_TC_EN_VPE M_PERFCTL_MT_EN(1) 115#define M_TC_EN_TC M_PERFCTL_MT_EN(2) 116#define M_PERFCTL_TCID(tcid) ((tcid) << 22) 117#define M_PERFCTL_WIDE (1 << 30) 118#define M_PERFCTL_MORE (1 << 31) 119 120#define M_PERFCTL_COUNT_EVENT_WHENEVER (M_PERFCTL_EXL | \ 121 M_PERFCTL_KERNEL | \ 122 M_PERFCTL_USER | \ 123 M_PERFCTL_SUPERVISOR | \ 124 M_PERFCTL_INTERRUPT_ENABLE) 125 126#ifdef CONFIG_MIPS_MT_SMP 127#define M_PERFCTL_CONFIG_MASK 0x3fff801f 128#else 129#define M_PERFCTL_CONFIG_MASK 0x1f 130#endif 131#define M_PERFCTL_EVENT_MASK 0xfe0 132 133 134#ifdef CONFIG_MIPS_MT_SMP 135static int cpu_has_mipsmt_pertccounters; 136 137static DEFINE_RWLOCK(pmuint_rwlock); 138 139/* 140 * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because 141 * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs. 142 */ 143#if defined(CONFIG_HW_PERF_EVENTS) 144#define vpe_id() (cpu_has_mipsmt_pertccounters ? \ 145 0 : smp_processor_id()) 146#else 147#define vpe_id() (cpu_has_mipsmt_pertccounters ? \ 148 0 : cpu_data[smp_processor_id()].vpe_id) 149#endif 150 151/* Copied from op_model_mipsxx.c */ 152static unsigned int vpe_shift(void) 153{ 154 if (num_possible_cpus() > 1) 155 return 1; 156 157 return 0; 158} 159 160static unsigned int counters_total_to_per_cpu(unsigned int counters) 161{ 162 return counters >> vpe_shift(); 163} 164 165static unsigned int counters_per_cpu_to_total(unsigned int counters) 166{ 167 return counters << vpe_shift(); 168} 169 170#else /* !CONFIG_MIPS_MT_SMP */ 171#define vpe_id() 0 172 173#endif /* CONFIG_MIPS_MT_SMP */ 174 175static void resume_local_counters(void); 176static void pause_local_counters(void); 177static irqreturn_t mipsxx_pmu_handle_irq(int, void *); 178static int mipsxx_pmu_handle_shared_irq(void); 179 180static unsigned int mipsxx_pmu_swizzle_perf_idx(unsigned int idx) 181{ 182 if (vpe_id() == 1) 183 idx = (idx + 2) & 3; 184 return idx; 185} 186 187static u64 mipsxx_pmu_read_counter(unsigned int idx) 188{ 189 idx = mipsxx_pmu_swizzle_perf_idx(idx); 190 191 switch (idx) { 192 case 0: 193 /* 194 * The counters are unsigned, we must cast to truncate 195 * off the high bits. 196 */ 197 return (u32)read_c0_perfcntr0(); 198 case 1: 199 return (u32)read_c0_perfcntr1(); 200 case 2: 201 return (u32)read_c0_perfcntr2(); 202 case 3: 203 return (u32)read_c0_perfcntr3(); 204 default: 205 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); 206 return 0; 207 } 208} 209 210static u64 mipsxx_pmu_read_counter_64(unsigned int idx) 211{ 212 idx = mipsxx_pmu_swizzle_perf_idx(idx); 213 214 switch (idx) { 215 case 0: 216 return read_c0_perfcntr0_64(); 217 case 1: 218 return read_c0_perfcntr1_64(); 219 case 2: 220 return read_c0_perfcntr2_64(); 221 case 3: 222 return read_c0_perfcntr3_64(); 223 default: 224 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); 225 return 0; 226 } 227} 228 229static void mipsxx_pmu_write_counter(unsigned int idx, u64 val) 230{ 231 idx = mipsxx_pmu_swizzle_perf_idx(idx); 232 233 switch (idx) { 234 case 0: 235 write_c0_perfcntr0(val); 236 return; 237 case 1: 238 write_c0_perfcntr1(val); 239 return; 240 case 2: 241 write_c0_perfcntr2(val); 242 return; 243 case 3: 244 write_c0_perfcntr3(val); 245 return; 246 } 247} 248 249static void mipsxx_pmu_write_counter_64(unsigned int idx, u64 val) 250{ 251 idx = mipsxx_pmu_swizzle_perf_idx(idx); 252 253 switch (idx) { 254 case 0: 255 write_c0_perfcntr0_64(val); 256 return; 257 case 1: 258 write_c0_perfcntr1_64(val); 259 return; 260 case 2: 261 write_c0_perfcntr2_64(val); 262 return; 263 case 3: 264 write_c0_perfcntr3_64(val); 265 return; 266 } 267} 268 269static unsigned int mipsxx_pmu_read_control(unsigned int idx) 270{ 271 idx = mipsxx_pmu_swizzle_perf_idx(idx); 272 273 switch (idx) { 274 case 0: 275 return read_c0_perfctrl0(); 276 case 1: 277 return read_c0_perfctrl1(); 278 case 2: 279 return read_c0_perfctrl2(); 280 case 3: 281 return read_c0_perfctrl3(); 282 default: 283 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); 284 return 0; 285 } 286} 287 288static void mipsxx_pmu_write_control(unsigned int idx, unsigned int val) 289{ 290 idx = mipsxx_pmu_swizzle_perf_idx(idx); 291 292 switch (idx) { 293 case 0: 294 write_c0_perfctrl0(val); 295 return; 296 case 1: 297 write_c0_perfctrl1(val); 298 return; 299 case 2: 300 write_c0_perfctrl2(val); 301 return; 302 case 3: 303 write_c0_perfctrl3(val); 304 return; 305 } 306} 307 308static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc, 309 struct hw_perf_event *hwc) 310{ 311 int i; 312 313 /* 314 * We only need to care the counter mask. The range has been 315 * checked definitely. 316 */ 317 unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff; 318 319 for (i = mipspmu.num_counters - 1; i >= 0; i--) { 320 /* 321 * Note that some MIPS perf events can be counted by both 322 * even and odd counters, wheresas many other are only by 323 * even _or_ odd counters. This introduces an issue that 324 * when the former kind of event takes the counter the 325 * latter kind of event wants to use, then the "counter 326 * allocation" for the latter event will fail. In fact if 327 * they can be dynamically swapped, they both feel happy. 328 * But here we leave this issue alone for now. 329 */ 330 if (test_bit(i, &cntr_mask) && 331 !test_and_set_bit(i, cpuc->used_mask)) 332 return i; 333 } 334 335 return -EAGAIN; 336} 337 338static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx) 339{ 340 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 341 342 WARN_ON(idx < 0 || idx >= mipspmu.num_counters); 343 344 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) | 345 (evt->config_base & M_PERFCTL_CONFIG_MASK) | 346 /* Make sure interrupt enabled. */ 347 M_PERFCTL_INTERRUPT_ENABLE; 348 /* 349 * We do not actually let the counter run. Leave it until start(). 350 */ 351} 352 353static void mipsxx_pmu_disable_event(int idx) 354{ 355 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 356 unsigned long flags; 357 358 WARN_ON(idx < 0 || idx >= mipspmu.num_counters); 359 360 local_irq_save(flags); 361 cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) & 362 ~M_PERFCTL_COUNT_EVENT_WHENEVER; 363 mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]); 364 local_irq_restore(flags); 365} 366 367static int mipspmu_event_set_period(struct perf_event *event, 368 struct hw_perf_event *hwc, 369 int idx) 370{ 371 u64 left = local64_read(&hwc->period_left); 372 u64 period = hwc->sample_period; 373 int ret = 0; 374 375 if (unlikely((left + period) & (1ULL << 63))) { 376 /* left underflowed by more than period. */ 377 left = period; 378 local64_set(&hwc->period_left, left); 379 hwc->last_period = period; 380 ret = 1; 381 } else if (unlikely((left + period) <= period)) { 382 /* left underflowed by less than period. */ 383 left += period; 384 local64_set(&hwc->period_left, left); 385 hwc->last_period = period; 386 ret = 1; 387 } 388 389 if (left > mipspmu.max_period) { 390 left = mipspmu.max_period; 391 local64_set(&hwc->period_left, left); 392 } 393 394 local64_set(&hwc->prev_count, mipspmu.overflow - left); 395 396 mipspmu.write_counter(idx, mipspmu.overflow - left); 397 398 perf_event_update_userpage(event); 399 400 return ret; 401} 402 403static void mipspmu_event_update(struct perf_event *event, 404 struct hw_perf_event *hwc, 405 int idx) 406{ 407 u64 prev_raw_count, new_raw_count; 408 u64 delta; 409 410again: 411 prev_raw_count = local64_read(&hwc->prev_count); 412 new_raw_count = mipspmu.read_counter(idx); 413 414 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, 415 new_raw_count) != prev_raw_count) 416 goto again; 417 418 delta = new_raw_count - prev_raw_count; 419 420 local64_add(delta, &event->count); 421 local64_sub(delta, &hwc->period_left); 422} 423 424static void mipspmu_start(struct perf_event *event, int flags) 425{ 426 struct hw_perf_event *hwc = &event->hw; 427 428 if (flags & PERF_EF_RELOAD) 429 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); 430 431 hwc->state = 0; 432 433 /* Set the period for the event. */ 434 mipspmu_event_set_period(event, hwc, hwc->idx); 435 436 /* Enable the event. */ 437 mipsxx_pmu_enable_event(hwc, hwc->idx); 438} 439 440static void mipspmu_stop(struct perf_event *event, int flags) 441{ 442 struct hw_perf_event *hwc = &event->hw; 443 444 if (!(hwc->state & PERF_HES_STOPPED)) { 445 /* We are working on a local event. */ 446 mipsxx_pmu_disable_event(hwc->idx); 447 barrier(); 448 mipspmu_event_update(event, hwc, hwc->idx); 449 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; 450 } 451} 452 453static int mipspmu_add(struct perf_event *event, int flags) 454{ 455 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 456 struct hw_perf_event *hwc = &event->hw; 457 int idx; 458 int err = 0; 459 460 perf_pmu_disable(event->pmu); 461 462 /* To look for a free counter for this event. */ 463 idx = mipsxx_pmu_alloc_counter(cpuc, hwc); 464 if (idx < 0) { 465 err = idx; 466 goto out; 467 } 468 469 /* 470 * If there is an event in the counter we are going to use then 471 * make sure it is disabled. 472 */ 473 event->hw.idx = idx; 474 mipsxx_pmu_disable_event(idx); 475 cpuc->events[idx] = event; 476 477 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; 478 if (flags & PERF_EF_START) 479 mipspmu_start(event, PERF_EF_RELOAD); 480 481 /* Propagate our changes to the userspace mapping. */ 482 perf_event_update_userpage(event); 483 484out: 485 perf_pmu_enable(event->pmu); 486 return err; 487} 488 489static void mipspmu_del(struct perf_event *event, int flags) 490{ 491 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 492 struct hw_perf_event *hwc = &event->hw; 493 int idx = hwc->idx; 494 495 WARN_ON(idx < 0 || idx >= mipspmu.num_counters); 496 497 mipspmu_stop(event, PERF_EF_UPDATE); 498 cpuc->events[idx] = NULL; 499 clear_bit(idx, cpuc->used_mask); 500 501 perf_event_update_userpage(event); 502} 503 504static void mipspmu_read(struct perf_event *event) 505{ 506 struct hw_perf_event *hwc = &event->hw; 507 508 /* Don't read disabled counters! */ 509 if (hwc->idx < 0) 510 return; 511 512 mipspmu_event_update(event, hwc, hwc->idx); 513} 514 515static void mipspmu_enable(struct pmu *pmu) 516{ 517#ifdef CONFIG_MIPS_MT_SMP 518 write_unlock(&pmuint_rwlock); 519#endif 520 resume_local_counters(); 521} 522 523/* 524 * MIPS performance counters can be per-TC. The control registers can 525 * not be directly accessed accross CPUs. Hence if we want to do global 526 * control, we need cross CPU calls. on_each_cpu() can help us, but we 527 * can not make sure this function is called with interrupts enabled. So 528 * here we pause local counters and then grab a rwlock and leave the 529 * counters on other CPUs alone. If any counter interrupt raises while 530 * we own the write lock, simply pause local counters on that CPU and 531 * spin in the handler. Also we know we won't be switched to another 532 * CPU after pausing local counters and before grabbing the lock. 533 */ 534static void mipspmu_disable(struct pmu *pmu) 535{ 536 pause_local_counters(); 537#ifdef CONFIG_MIPS_MT_SMP 538 write_lock(&pmuint_rwlock); 539#endif 540} 541 542static atomic_t active_events = ATOMIC_INIT(0); 543static DEFINE_MUTEX(pmu_reserve_mutex); 544static int (*save_perf_irq)(void); 545 546static int mipspmu_get_irq(void) 547{ 548 int err; 549 550 if (mipspmu.irq >= 0) { 551 /* Request my own irq handler. */ 552 err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq, 553 IRQF_PERCPU | IRQF_NOBALANCING, 554 "mips_perf_pmu", NULL); 555 if (err) { 556 pr_warning("Unable to request IRQ%d for MIPS " 557 "performance counters!\n", mipspmu.irq); 558 } 559 } else if (cp0_perfcount_irq < 0) { 560 /* 561 * We are sharing the irq number with the timer interrupt. 562 */ 563 save_perf_irq = perf_irq; 564 perf_irq = mipsxx_pmu_handle_shared_irq; 565 err = 0; 566 } else { 567 pr_warning("The platform hasn't properly defined its " 568 "interrupt controller.\n"); 569 err = -ENOENT; 570 } 571 572 return err; 573} 574 575static void mipspmu_free_irq(void) 576{ 577 if (mipspmu.irq >= 0) 578 free_irq(mipspmu.irq, NULL); 579 else if (cp0_perfcount_irq < 0) 580 perf_irq = save_perf_irq; 581} 582 583/* 584 * mipsxx/rm9000/loongson2 have different performance counters, they have 585 * specific low-level init routines. 586 */ 587static void reset_counters(void *arg); 588static int __hw_perf_event_init(struct perf_event *event); 589 590static void hw_perf_event_destroy(struct perf_event *event) 591{ 592 if (atomic_dec_and_mutex_lock(&active_events, 593 &pmu_reserve_mutex)) { 594 /* 595 * We must not call the destroy function with interrupts 596 * disabled. 597 */ 598 on_each_cpu(reset_counters, 599 (void *)(long)mipspmu.num_counters, 1); 600 mipspmu_free_irq(); 601 mutex_unlock(&pmu_reserve_mutex); 602 } 603} 604 605static int mipspmu_event_init(struct perf_event *event) 606{ 607 int err = 0; 608 609 switch (event->attr.type) { 610 case PERF_TYPE_RAW: 611 case PERF_TYPE_HARDWARE: 612 case PERF_TYPE_HW_CACHE: 613 break; 614 615 default: 616 return -ENOENT; 617 } 618 619 if (event->cpu >= nr_cpumask_bits || 620 (event->cpu >= 0 && !cpu_online(event->cpu))) 621 return -ENODEV; 622 623 if (!atomic_inc_not_zero(&active_events)) { 624 if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) { 625 atomic_dec(&active_events); 626 return -ENOSPC; 627 } 628 629 mutex_lock(&pmu_reserve_mutex); 630 if (atomic_read(&active_events) == 0) 631 err = mipspmu_get_irq(); 632 633 if (!err) 634 atomic_inc(&active_events); 635 mutex_unlock(&pmu_reserve_mutex); 636 } 637 638 if (err) 639 return err; 640 641 err = __hw_perf_event_init(event); 642 if (err) 643 hw_perf_event_destroy(event); 644 645 return err; 646} 647 648static struct pmu pmu = { 649 .pmu_enable = mipspmu_enable, 650 .pmu_disable = mipspmu_disable, 651 .event_init = mipspmu_event_init, 652 .add = mipspmu_add, 653 .del = mipspmu_del, 654 .start = mipspmu_start, 655 .stop = mipspmu_stop, 656 .read = mipspmu_read, 657}; 658 659static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev) 660{ 661/* 662 * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for 663 * event_id. 664 */ 665#ifdef CONFIG_MIPS_MT_SMP 666 return ((unsigned int)pev->range << 24) | 667 (pev->cntr_mask & 0xffff00) | 668 (pev->event_id & 0xff); 669#else 670 return (pev->cntr_mask & 0xffff00) | 671 (pev->event_id & 0xff); 672#endif 673} 674 675static const struct mips_perf_event *mipspmu_map_general_event(int idx) 676{ 677 const struct mips_perf_event *pev; 678 679 pev = ((*mipspmu.general_event_map)[idx].event_id == 680 UNSUPPORTED_PERF_EVENT_ID ? ERR_PTR(-EOPNOTSUPP) : 681 &(*mipspmu.general_event_map)[idx]); 682 683 return pev; 684} 685 686static const struct mips_perf_event *mipspmu_map_cache_event(u64 config) 687{ 688 unsigned int cache_type, cache_op, cache_result; 689 const struct mips_perf_event *pev; 690 691 cache_type = (config >> 0) & 0xff; 692 if (cache_type >= PERF_COUNT_HW_CACHE_MAX) 693 return ERR_PTR(-EINVAL); 694 695 cache_op = (config >> 8) & 0xff; 696 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) 697 return ERR_PTR(-EINVAL); 698 699 cache_result = (config >> 16) & 0xff; 700 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 701 return ERR_PTR(-EINVAL); 702 703 pev = &((*mipspmu.cache_event_map) 704 [cache_type] 705 [cache_op] 706 [cache_result]); 707 708 if (pev->event_id == UNSUPPORTED_PERF_EVENT_ID) 709 return ERR_PTR(-EOPNOTSUPP); 710 711 return pev; 712 713} 714 715static int validate_event(struct cpu_hw_events *cpuc, 716 struct perf_event *event) 717{ 718 struct hw_perf_event fake_hwc = event->hw; 719 720 /* Allow mixed event group. So return 1 to pass validation. */ 721 if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF) 722 return 1; 723 724 return mipsxx_pmu_alloc_counter(cpuc, &fake_hwc) >= 0; 725} 726 727static int validate_group(struct perf_event *event) 728{ 729 struct perf_event *sibling, *leader = event->group_leader; 730 struct cpu_hw_events fake_cpuc; 731 732 memset(&fake_cpuc, 0, sizeof(fake_cpuc)); 733 734 if (!validate_event(&fake_cpuc, leader)) 735 return -ENOSPC; 736 737 list_for_each_entry(sibling, &leader->sibling_list, group_entry) { 738 if (!validate_event(&fake_cpuc, sibling)) 739 return -ENOSPC; 740 } 741 742 if (!validate_event(&fake_cpuc, event)) 743 return -ENOSPC; 744 745 return 0; 746} 747 748/* This is needed by specific irq handlers in perf_event_*.c */ 749static void handle_associated_event(struct cpu_hw_events *cpuc, 750 int idx, struct perf_sample_data *data, 751 struct pt_regs *regs) 752{ 753 struct perf_event *event = cpuc->events[idx]; 754 struct hw_perf_event *hwc = &event->hw; 755 756 mipspmu_event_update(event, hwc, idx); 757 data->period = event->hw.last_period; 758 if (!mipspmu_event_set_period(event, hwc, idx)) 759 return; 760 761 if (perf_event_overflow(event, data, regs)) 762 mipsxx_pmu_disable_event(idx); 763} 764 765 766static int __n_counters(void) 767{ 768 if (!(read_c0_config1() & M_CONFIG1_PC)) 769 return 0; 770 if (!(read_c0_perfctrl0() & M_PERFCTL_MORE)) 771 return 1; 772 if (!(read_c0_perfctrl1() & M_PERFCTL_MORE)) 773 return 2; 774 if (!(read_c0_perfctrl2() & M_PERFCTL_MORE)) 775 return 3; 776 777 return 4; 778} 779 780static int n_counters(void) 781{ 782 int counters; 783 784 switch (current_cpu_type()) { 785 case CPU_R10000: 786 counters = 2; 787 break; 788 789 case CPU_R12000: 790 case CPU_R14000: 791 counters = 4; 792 break; 793 794 default: 795 counters = __n_counters(); 796 } 797 798 return counters; 799} 800 801static void reset_counters(void *arg) 802{ 803 int counters = (int)(long)arg; 804 switch (counters) { 805 case 4: 806 mipsxx_pmu_write_control(3, 0); 807 mipspmu.write_counter(3, 0); 808 case 3: 809 mipsxx_pmu_write_control(2, 0); 810 mipspmu.write_counter(2, 0); 811 case 2: 812 mipsxx_pmu_write_control(1, 0); 813 mipspmu.write_counter(1, 0); 814 case 1: 815 mipsxx_pmu_write_control(0, 0); 816 mipspmu.write_counter(0, 0); 817 } 818} 819 820/* 24K/34K/1004K cores can share the same event map. */ 821static const struct mips_perf_event mipsxxcore_event_map 822 [PERF_COUNT_HW_MAX] = { 823 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, 824 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, 825 [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID }, 826 [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID }, 827 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T }, 828 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T }, 829 [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID }, 830}; 831 832/* 74K core has different branch event code. */ 833static const struct mips_perf_event mipsxx74Kcore_event_map 834 [PERF_COUNT_HW_MAX] = { 835 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, 836 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, 837 [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID }, 838 [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID }, 839 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T }, 840 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T }, 841 [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID }, 842}; 843 844static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = { 845 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL }, 846 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL }, 847 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL }, 848 [PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL }, 849 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL }, 850 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL }, 851 [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL }, 852}; 853 854/* 24K/34K/1004K cores can share the same cache event map. */ 855static const struct mips_perf_event mipsxxcore_cache_map 856 [PERF_COUNT_HW_CACHE_MAX] 857 [PERF_COUNT_HW_CACHE_OP_MAX] 858 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 859[C(L1D)] = { 860 /* 861 * Like some other architectures (e.g. ARM), the performance 862 * counters don't differentiate between read and write 863 * accesses/misses, so this isn't strictly correct, but it's the 864 * best we can do. Writes and reads get combined. 865 */ 866 [C(OP_READ)] = { 867 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T }, 868 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T }, 869 }, 870 [C(OP_WRITE)] = { 871 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T }, 872 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T }, 873 }, 874 [C(OP_PREFETCH)] = { 875 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 876 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 877 }, 878}, 879[C(L1I)] = { 880 [C(OP_READ)] = { 881 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T }, 882 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T }, 883 }, 884 [C(OP_WRITE)] = { 885 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T }, 886 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T }, 887 }, 888 [C(OP_PREFETCH)] = { 889 [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T }, 890 /* 891 * Note that MIPS has only "hit" events countable for 892 * the prefetch operation. 893 */ 894 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 895 }, 896}, 897[C(LL)] = { 898 [C(OP_READ)] = { 899 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P }, 900 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, 901 }, 902 [C(OP_WRITE)] = { 903 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P }, 904 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, 905 }, 906 [C(OP_PREFETCH)] = { 907 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 908 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 909 }, 910}, 911[C(DTLB)] = { 912 [C(OP_READ)] = { 913 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, 914 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, 915 }, 916 [C(OP_WRITE)] = { 917 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, 918 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, 919 }, 920 [C(OP_PREFETCH)] = { 921 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 922 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 923 }, 924}, 925[C(ITLB)] = { 926 [C(OP_READ)] = { 927 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T }, 928 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T }, 929 }, 930 [C(OP_WRITE)] = { 931 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T }, 932 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T }, 933 }, 934 [C(OP_PREFETCH)] = { 935 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 936 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 937 }, 938}, 939[C(BPU)] = { 940 /* Using the same code for *HW_BRANCH* */ 941 [C(OP_READ)] = { 942 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T }, 943 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, 944 }, 945 [C(OP_WRITE)] = { 946 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T }, 947 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, 948 }, 949 [C(OP_PREFETCH)] = { 950 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 951 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 952 }, 953}, 954[C(NODE)] = { 955 [C(OP_READ)] = { 956 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 957 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 958 }, 959 [C(OP_WRITE)] = { 960 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 961 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 962 }, 963 [C(OP_PREFETCH)] = { 964 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 965 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 966 }, 967}, 968}; 969 970/* 74K core has completely different cache event map. */ 971static const struct mips_perf_event mipsxx74Kcore_cache_map 972 [PERF_COUNT_HW_CACHE_MAX] 973 [PERF_COUNT_HW_CACHE_OP_MAX] 974 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 975[C(L1D)] = { 976 /* 977 * Like some other architectures (e.g. ARM), the performance 978 * counters don't differentiate between read and write 979 * accesses/misses, so this isn't strictly correct, but it's the 980 * best we can do. Writes and reads get combined. 981 */ 982 [C(OP_READ)] = { 983 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T }, 984 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T }, 985 }, 986 [C(OP_WRITE)] = { 987 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T }, 988 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T }, 989 }, 990 [C(OP_PREFETCH)] = { 991 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 992 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 993 }, 994}, 995[C(L1I)] = { 996 [C(OP_READ)] = { 997 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, 998 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, 999 }, 1000 [C(OP_WRITE)] = { 1001 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, 1002 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, 1003 }, 1004 [C(OP_PREFETCH)] = { 1005 [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T }, 1006 /* 1007 * Note that MIPS has only "hit" events countable for 1008 * the prefetch operation. 1009 */ 1010 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1011 }, 1012}, 1013[C(LL)] = { 1014 [C(OP_READ)] = { 1015 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, 1016 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P }, 1017 }, 1018 [C(OP_WRITE)] = { 1019 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, 1020 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P }, 1021 }, 1022 [C(OP_PREFETCH)] = { 1023 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1024 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1025 }, 1026}, 1027[C(DTLB)] = { 1028 /* 74K core does not have specific DTLB events. */ 1029 [C(OP_READ)] = { 1030 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1031 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1032 }, 1033 [C(OP_WRITE)] = { 1034 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1035 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1036 }, 1037 [C(OP_PREFETCH)] = { 1038 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1039 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1040 }, 1041}, 1042[C(ITLB)] = { 1043 [C(OP_READ)] = { 1044 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T }, 1045 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T }, 1046 }, 1047 [C(OP_WRITE)] = { 1048 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T }, 1049 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T }, 1050 }, 1051 [C(OP_PREFETCH)] = { 1052 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1053 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1054 }, 1055}, 1056[C(BPU)] = { 1057 /* Using the same code for *HW_BRANCH* */ 1058 [C(OP_READ)] = { 1059 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T }, 1060 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T }, 1061 }, 1062 [C(OP_WRITE)] = { 1063 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T }, 1064 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T }, 1065 }, 1066 [C(OP_PREFETCH)] = { 1067 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1068 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1069 }, 1070}, 1071[C(NODE)] = { 1072 [C(OP_READ)] = { 1073 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1074 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1075 }, 1076 [C(OP_WRITE)] = { 1077 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1078 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1079 }, 1080 [C(OP_PREFETCH)] = { 1081 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1082 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1083 }, 1084}, 1085}; 1086 1087 1088static const struct mips_perf_event octeon_cache_map 1089 [PERF_COUNT_HW_CACHE_MAX] 1090 [PERF_COUNT_HW_CACHE_OP_MAX] 1091 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1092[C(L1D)] = { 1093 [C(OP_READ)] = { 1094 [C(RESULT_ACCESS)] = { 0x2b, CNTR_ALL }, 1095 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, 1096 }, 1097 [C(OP_WRITE)] = { 1098 [C(RESULT_ACCESS)] = { 0x30, CNTR_ALL }, 1099 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1100 }, 1101 [C(OP_PREFETCH)] = { 1102 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1103 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1104 }, 1105}, 1106[C(L1I)] = { 1107 [C(OP_READ)] = { 1108 [C(RESULT_ACCESS)] = { 0x18, CNTR_ALL }, 1109 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1110 }, 1111 [C(OP_WRITE)] = { 1112 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1113 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1114 }, 1115 [C(OP_PREFETCH)] = { 1116 [C(RESULT_ACCESS)] = { 0x19, CNTR_ALL }, 1117 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1118 }, 1119}, 1120[C(LL)] = { 1121 [C(OP_READ)] = { 1122 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1123 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1124 }, 1125 [C(OP_WRITE)] = { 1126 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1127 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1128 }, 1129 [C(OP_PREFETCH)] = { 1130 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1131 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1132 }, 1133}, 1134[C(DTLB)] = { 1135 /* 1136 * Only general DTLB misses are counted use the same event for 1137 * read and write. 1138 */ 1139 [C(OP_READ)] = { 1140 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1141 [C(RESULT_MISS)] = { 0x35, CNTR_ALL }, 1142 }, 1143 [C(OP_WRITE)] = { 1144 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1145 [C(RESULT_MISS)] = { 0x35, CNTR_ALL }, 1146 }, 1147 [C(OP_PREFETCH)] = { 1148 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1149 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1150 }, 1151}, 1152[C(ITLB)] = { 1153 [C(OP_READ)] = { 1154 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1155 [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, 1156 }, 1157 [C(OP_WRITE)] = { 1158 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1159 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1160 }, 1161 [C(OP_PREFETCH)] = { 1162 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1163 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1164 }, 1165}, 1166[C(BPU)] = { 1167 /* Using the same code for *HW_BRANCH* */ 1168 [C(OP_READ)] = { 1169 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1170 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1171 }, 1172 [C(OP_WRITE)] = { 1173 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1174 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1175 }, 1176 [C(OP_PREFETCH)] = { 1177 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1178 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID }, 1179 }, 1180}, 1181}; 1182 1183#ifdef CONFIG_MIPS_MT_SMP 1184static void check_and_calc_range(struct perf_event *event, 1185 const struct mips_perf_event *pev) 1186{ 1187 struct hw_perf_event *hwc = &event->hw; 1188 1189 if (event->cpu >= 0) { 1190 if (pev->range > V) { 1191 /* 1192 * The user selected an event that is processor 1193 * wide, while expecting it to be VPE wide. 1194 */ 1195 hwc->config_base |= M_TC_EN_ALL; 1196 } else { 1197 /* 1198 * FIXME: cpu_data[event->cpu].vpe_id reports 0 1199 * for both CPUs. 1200 */ 1201 hwc->config_base |= M_PERFCTL_VPEID(event->cpu); 1202 hwc->config_base |= M_TC_EN_VPE; 1203 } 1204 } else 1205 hwc->config_base |= M_TC_EN_ALL; 1206} 1207#else 1208static void check_and_calc_range(struct perf_event *event, 1209 const struct mips_perf_event *pev) 1210{ 1211} 1212#endif 1213 1214static int __hw_perf_event_init(struct perf_event *event) 1215{ 1216 struct perf_event_attr *attr = &event->attr; 1217 struct hw_perf_event *hwc = &event->hw; 1218 const struct mips_perf_event *pev; 1219 int err; 1220 1221 /* Returning MIPS event descriptor for generic perf event. */ 1222 if (PERF_TYPE_HARDWARE == event->attr.type) { 1223 if (event->attr.config >= PERF_COUNT_HW_MAX) 1224 return -EINVAL; 1225 pev = mipspmu_map_general_event(event->attr.config); 1226 } else if (PERF_TYPE_HW_CACHE == event->attr.type) { 1227 pev = mipspmu_map_cache_event(event->attr.config); 1228 } else if (PERF_TYPE_RAW == event->attr.type) { 1229 /* We are working on the global raw event. */ 1230 mutex_lock(&raw_event_mutex); 1231 pev = mipspmu.map_raw_event(event->attr.config); 1232 } else { 1233 /* The event type is not (yet) supported. */ 1234 return -EOPNOTSUPP; 1235 } 1236 1237 if (IS_ERR(pev)) { 1238 if (PERF_TYPE_RAW == event->attr.type) 1239 mutex_unlock(&raw_event_mutex); 1240 return PTR_ERR(pev); 1241 } 1242 1243 /* 1244 * We allow max flexibility on how each individual counter shared 1245 * by the single CPU operates (the mode exclusion and the range). 1246 */ 1247 hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE; 1248 1249 /* Calculate range bits and validate it. */ 1250 if (num_possible_cpus() > 1) 1251 check_and_calc_range(event, pev); 1252 1253 hwc->event_base = mipspmu_perf_event_encode(pev); 1254 if (PERF_TYPE_RAW == event->attr.type) 1255 mutex_unlock(&raw_event_mutex); 1256 1257 if (!attr->exclude_user) 1258 hwc->config_base |= M_PERFCTL_USER; 1259 if (!attr->exclude_kernel) { 1260 hwc->config_base |= M_PERFCTL_KERNEL; 1261 /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */ 1262 hwc->config_base |= M_PERFCTL_EXL; 1263 } 1264 if (!attr->exclude_hv) 1265 hwc->config_base |= M_PERFCTL_SUPERVISOR; 1266 1267 hwc->config_base &= M_PERFCTL_CONFIG_MASK; 1268 /* 1269 * The event can belong to another cpu. We do not assign a local 1270 * counter for it for now. 1271 */ 1272 hwc->idx = -1; 1273 hwc->config = 0; 1274 1275 if (!hwc->sample_period) { 1276 hwc->sample_period = mipspmu.max_period; 1277 hwc->last_period = hwc->sample_period; 1278 local64_set(&hwc->period_left, hwc->sample_period); 1279 } 1280 1281 err = 0; 1282 if (event->group_leader != event) { 1283 err = validate_group(event); 1284 if (err) 1285 return -EINVAL; 1286 } 1287 1288 event->destroy = hw_perf_event_destroy; 1289 return err; 1290} 1291 1292static void pause_local_counters(void) 1293{ 1294 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 1295 int ctr = mipspmu.num_counters; 1296 unsigned long flags; 1297 1298 local_irq_save(flags); 1299 do { 1300 ctr--; 1301 cpuc->saved_ctrl[ctr] = mipsxx_pmu_read_control(ctr); 1302 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr] & 1303 ~M_PERFCTL_COUNT_EVENT_WHENEVER); 1304 } while (ctr > 0); 1305 local_irq_restore(flags); 1306} 1307 1308static void resume_local_counters(void) 1309{ 1310 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 1311 int ctr = mipspmu.num_counters; 1312 1313 do { 1314 ctr--; 1315 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr]); 1316 } while (ctr > 0); 1317} 1318 1319static int mipsxx_pmu_handle_shared_irq(void) 1320{ 1321 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 1322 struct perf_sample_data data; 1323 unsigned int counters = mipspmu.num_counters; 1324 u64 counter; 1325 int handled = IRQ_NONE; 1326 struct pt_regs *regs; 1327 1328 if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26))) 1329 return handled; 1330 /* 1331 * First we pause the local counters, so that when we are locked 1332 * here, the counters are all paused. When it gets locked due to 1333 * perf_disable(), the timer interrupt handler will be delayed. 1334 * 1335 * See also mipsxx_pmu_start(). 1336 */ 1337 pause_local_counters(); 1338#ifdef CONFIG_MIPS_MT_SMP 1339 read_lock(&pmuint_rwlock); 1340#endif 1341 1342 regs = get_irq_regs(); 1343 1344 perf_sample_data_init(&data, 0); 1345 1346 switch (counters) { 1347#define HANDLE_COUNTER(n) \ 1348 case n + 1: \ 1349 if (test_bit(n, cpuc->used_mask)) { \ 1350 counter = mipspmu.read_counter(n); \ 1351 if (counter & mipspmu.overflow) { \ 1352 handle_associated_event(cpuc, n, &data, regs); \ 1353 handled = IRQ_HANDLED; \ 1354 } \ 1355 } 1356 HANDLE_COUNTER(3) 1357 HANDLE_COUNTER(2) 1358 HANDLE_COUNTER(1) 1359 HANDLE_COUNTER(0) 1360 } 1361 1362 /* 1363 * Do all the work for the pending perf events. We can do this 1364 * in here because the performance counter interrupt is a regular 1365 * interrupt, not NMI. 1366 */ 1367 if (handled == IRQ_HANDLED) 1368 irq_work_run(); 1369 1370#ifdef CONFIG_MIPS_MT_SMP 1371 read_unlock(&pmuint_rwlock); 1372#endif 1373 resume_local_counters(); 1374 return handled; 1375} 1376 1377static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev) 1378{ 1379 return mipsxx_pmu_handle_shared_irq(); 1380} 1381 1382/* 24K */ 1383#define IS_BOTH_COUNTERS_24K_EVENT(b) \ 1384 ((b) == 0 || (b) == 1 || (b) == 11) 1385 1386/* 34K */ 1387#define IS_BOTH_COUNTERS_34K_EVENT(b) \ 1388 ((b) == 0 || (b) == 1 || (b) == 11) 1389#ifdef CONFIG_MIPS_MT_SMP 1390#define IS_RANGE_P_34K_EVENT(r, b) \ 1391 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \ 1392 (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 || \ 1393 (r) == 176 || ((b) >= 50 && (b) <= 55) || \ 1394 ((b) >= 64 && (b) <= 67)) 1395#define IS_RANGE_V_34K_EVENT(r) ((r) == 47) 1396#endif 1397 1398/* 74K */ 1399#define IS_BOTH_COUNTERS_74K_EVENT(b) \ 1400 ((b) == 0 || (b) == 1) 1401 1402/* 1004K */ 1403#define IS_BOTH_COUNTERS_1004K_EVENT(b) \ 1404 ((b) == 0 || (b) == 1 || (b) == 11) 1405#ifdef CONFIG_MIPS_MT_SMP 1406#define IS_RANGE_P_1004K_EVENT(r, b) \ 1407 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \ 1408 (b) == 25 || (b) == 36 || (b) == 39 || (r) == 44 || \ 1409 (r) == 174 || (r) == 176 || ((b) >= 50 && (b) <= 59) || \ 1410 (r) == 188 || (b) == 61 || (b) == 62 || \ 1411 ((b) >= 64 && (b) <= 67)) 1412#define IS_RANGE_V_1004K_EVENT(r) ((r) == 47) 1413#endif 1414 1415/* 1416 * User can use 0-255 raw events, where 0-127 for the events of even 1417 * counters, and 128-255 for odd counters. Note that bit 7 is used to 1418 * indicate the parity. So, for example, when user wants to take the 1419 * Event Num of 15 for odd counters (by referring to the user manual), 1420 * then 128 needs to be added to 15 as the input for the event config, 1421 * i.e., 143 (0x8F) to be used. 1422 */ 1423static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) 1424{ 1425 unsigned int raw_id = config & 0xff; 1426 unsigned int base_id = raw_id & 0x7f; 1427 1428 raw_event.event_id = base_id; 1429 1430 switch (current_cpu_type()) { 1431 case CPU_24K: 1432 if (IS_BOTH_COUNTERS_24K_EVENT(base_id)) 1433 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1434 else 1435 raw_event.cntr_mask = 1436 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; 1437#ifdef CONFIG_MIPS_MT_SMP 1438 /* 1439 * This is actually doing nothing. Non-multithreading 1440 * CPUs will not check and calculate the range. 1441 */ 1442 raw_event.range = P; 1443#endif 1444 break; 1445 case CPU_34K: 1446 if (IS_BOTH_COUNTERS_34K_EVENT(base_id)) 1447 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1448 else 1449 raw_event.cntr_mask = 1450 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; 1451#ifdef CONFIG_MIPS_MT_SMP 1452 if (IS_RANGE_P_34K_EVENT(raw_id, base_id)) 1453 raw_event.range = P; 1454 else if (unlikely(IS_RANGE_V_34K_EVENT(raw_id))) 1455 raw_event.range = V; 1456 else 1457 raw_event.range = T; 1458#endif 1459 break; 1460 case CPU_74K: 1461 if (IS_BOTH_COUNTERS_74K_EVENT(base_id)) 1462 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1463 else 1464 raw_event.cntr_mask = 1465 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; 1466#ifdef CONFIG_MIPS_MT_SMP 1467 raw_event.range = P; 1468#endif 1469 break; 1470 case CPU_1004K: 1471 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id)) 1472 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1473 else 1474 raw_event.cntr_mask = 1475 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; 1476#ifdef CONFIG_MIPS_MT_SMP 1477 if (IS_RANGE_P_1004K_EVENT(raw_id, base_id)) 1478 raw_event.range = P; 1479 else if (unlikely(IS_RANGE_V_1004K_EVENT(raw_id))) 1480 raw_event.range = V; 1481 else 1482 raw_event.range = T; 1483#endif 1484 break; 1485 } 1486 1487 return &raw_event; 1488} 1489 1490static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config) 1491{ 1492 unsigned int raw_id = config & 0xff; 1493 unsigned int base_id = raw_id & 0x7f; 1494 1495 1496 raw_event.cntr_mask = CNTR_ALL; 1497 raw_event.event_id = base_id; 1498 1499 if (current_cpu_type() == CPU_CAVIUM_OCTEON2) { 1500 if (base_id > 0x42) 1501 return ERR_PTR(-EOPNOTSUPP); 1502 } else { 1503 if (base_id > 0x3a) 1504 return ERR_PTR(-EOPNOTSUPP); 1505 } 1506 1507 switch (base_id) { 1508 case 0x00: 1509 case 0x0f: 1510 case 0x1e: 1511 case 0x1f: 1512 case 0x2f: 1513 case 0x34: 1514 case 0x3b ... 0x3f: 1515 return ERR_PTR(-EOPNOTSUPP); 1516 default: 1517 break; 1518 } 1519 1520 return &raw_event; 1521} 1522 1523static int __init 1524init_hw_perf_events(void) 1525{ 1526 int counters, irq; 1527 int counter_bits; 1528 1529 pr_info("Performance counters: "); 1530 1531 counters = n_counters(); 1532 if (counters == 0) { 1533 pr_cont("No available PMU.\n"); 1534 return -ENODEV; 1535 } 1536 1537#ifdef CONFIG_MIPS_MT_SMP 1538 cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19); 1539 if (!cpu_has_mipsmt_pertccounters) 1540 counters = counters_total_to_per_cpu(counters); 1541#endif 1542 1543#ifdef MSC01E_INT_BASE 1544 if (cpu_has_veic) { 1545 /* 1546 * Using platform specific interrupt controller defines. 1547 */ 1548 irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; 1549 } else { 1550#endif 1551 if (cp0_perfcount_irq >= 0) 1552 irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; 1553 else 1554 irq = -1; 1555#ifdef MSC01E_INT_BASE 1556 } 1557#endif 1558 1559 mipspmu.map_raw_event = mipsxx_pmu_map_raw_event; 1560 1561 switch (current_cpu_type()) { 1562 case CPU_24K: 1563 mipspmu.name = "mips/24K"; 1564 mipspmu.general_event_map = &mipsxxcore_event_map; 1565 mipspmu.cache_event_map = &mipsxxcore_cache_map; 1566 break; 1567 case CPU_34K: 1568 mipspmu.name = "mips/34K"; 1569 mipspmu.general_event_map = &mipsxxcore_event_map; 1570 mipspmu.cache_event_map = &mipsxxcore_cache_map; 1571 break; 1572 case CPU_74K: 1573 mipspmu.name = "mips/74K"; 1574 mipspmu.general_event_map = &mipsxx74Kcore_event_map; 1575 mipspmu.cache_event_map = &mipsxx74Kcore_cache_map; 1576 break; 1577 case CPU_1004K: 1578 mipspmu.name = "mips/1004K"; 1579 mipspmu.general_event_map = &mipsxxcore_event_map; 1580 mipspmu.cache_event_map = &mipsxxcore_cache_map; 1581 break; 1582 case CPU_CAVIUM_OCTEON: 1583 case CPU_CAVIUM_OCTEON_PLUS: 1584 case CPU_CAVIUM_OCTEON2: 1585 mipspmu.name = "octeon"; 1586 mipspmu.general_event_map = &octeon_event_map; 1587 mipspmu.cache_event_map = &octeon_cache_map; 1588 mipspmu.map_raw_event = octeon_pmu_map_raw_event; 1589 break; 1590 default: 1591 pr_cont("Either hardware does not support performance " 1592 "counters, or not yet implemented.\n"); 1593 return -ENODEV; 1594 } 1595 1596 mipspmu.num_counters = counters; 1597 mipspmu.irq = irq; 1598 1599 if (read_c0_perfctrl0() & M_PERFCTL_WIDE) { 1600 mipspmu.max_period = (1ULL << 63) - 1; 1601 mipspmu.valid_count = (1ULL << 63) - 1; 1602 mipspmu.overflow = 1ULL << 63; 1603 mipspmu.read_counter = mipsxx_pmu_read_counter_64; 1604 mipspmu.write_counter = mipsxx_pmu_write_counter_64; 1605 counter_bits = 64; 1606 } else { 1607 mipspmu.max_period = (1ULL << 31) - 1; 1608 mipspmu.valid_count = (1ULL << 31) - 1; 1609 mipspmu.overflow = 1ULL << 31; 1610 mipspmu.read_counter = mipsxx_pmu_read_counter; 1611 mipspmu.write_counter = mipsxx_pmu_write_counter; 1612 counter_bits = 32; 1613 } 1614 1615 on_each_cpu(reset_counters, (void *)(long)counters, 1); 1616 1617 pr_cont("%s PMU enabled, %d %d-bit counters available to each " 1618 "CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq, 1619 irq < 0 ? " (share with timer interrupt)" : ""); 1620 1621 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); 1622 1623 return 0; 1624} 1625early_initcall(init_hw_perf_events); 1626