1e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon/* 2e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * This file is subject to the terms and conditions of the GNU General Public 3e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * License. See the file "COPYING" in the main directory of this archive 4e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * for more details. 5e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * 6e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 7e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon */ 8e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 9e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon#include <linux/types.h> 10e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon#include <linux/pci.h> 11e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon#include <linux/kernel.h> 12e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon#include <linux/init.h> 13e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon#include <asm/bootinfo.h> 14e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 15e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon#include "pci-bcm63xx.h" 16e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 17e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon/* 18e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * Allow PCI to be disabled at runtime depending on board nvram 19e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * configuration 20e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon */ 21e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizonint bcm63xx_pci_enabled; 22e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 23e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizonstatic struct resource bcm_pci_mem_resource = { 24e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .name = "bcm63xx PCI memory space", 25e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .start = BCM_PCI_MEM_BASE_PA, 26e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .end = BCM_PCI_MEM_END_PA, 27e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .flags = IORESOURCE_MEM 28e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon}; 29e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 30e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizonstatic struct resource bcm_pci_io_resource = { 31e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .name = "bcm63xx PCI IO space", 32e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .start = BCM_PCI_IO_BASE_PA, 33e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon#ifdef CONFIG_CARDBUS 34e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .end = BCM_PCI_IO_HALF_PA, 35e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon#else 36e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .end = BCM_PCI_IO_END_PA, 37e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon#endif 38e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .flags = IORESOURCE_IO 39e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon}; 40e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 41e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizonstruct pci_controller bcm63xx_controller = { 42e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .pci_ops = &bcm63xx_pci_ops, 43e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .io_resource = &bcm_pci_io_resource, 44e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .mem_resource = &bcm_pci_mem_resource, 45e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon}; 46e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 47e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon/* 48e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * We handle cardbus via a fake Cardbus bridge, memory and io spaces 49e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * have to be clearly separated from PCI one since we have different 50e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * memory decoder. 51e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon */ 52e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon#ifdef CONFIG_CARDBUS 53e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizonstatic struct resource bcm_cb_mem_resource = { 54e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .name = "bcm63xx Cardbus memory space", 55e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .start = BCM_CB_MEM_BASE_PA, 56e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .end = BCM_CB_MEM_END_PA, 57e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .flags = IORESOURCE_MEM 58e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon}; 59e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 60e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizonstatic struct resource bcm_cb_io_resource = { 61e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .name = "bcm63xx Cardbus IO space", 62e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .start = BCM_PCI_IO_HALF_PA + 1, 63e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .end = BCM_PCI_IO_END_PA, 64e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .flags = IORESOURCE_IO 65e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon}; 66e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 67e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizonstruct pci_controller bcm63xx_cb_controller = { 68e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .pci_ops = &bcm63xx_cb_ops, 69e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .io_resource = &bcm_cb_io_resource, 70e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon .mem_resource = &bcm_cb_mem_resource, 71e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon}; 72e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon#endif 73e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 74e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizonstatic u32 bcm63xx_int_cfg_readl(u32 reg) 75e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon{ 76e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon u32 tmp; 77e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 78e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK; 79e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon tmp |= MPI_PCICFGCTL_WRITEEN_MASK; 80e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG); 81e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon iob(); 82e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon return bcm_mpi_readl(MPI_PCICFGDATA_REG); 83e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon} 84e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 85e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizonstatic void bcm63xx_int_cfg_writel(u32 val, u32 reg) 86e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon{ 87e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon u32 tmp; 88e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 89e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK; 90e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon tmp |= MPI_PCICFGCTL_WRITEEN_MASK; 91e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG); 92e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm_mpi_writel(val, MPI_PCICFGDATA_REG); 93e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon} 94e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 95e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizonvoid __iomem *pci_iospace_start; 96e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 97e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizonstatic int __init bcm63xx_pci_init(void) 98e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon{ 99e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon unsigned int mem_size; 100e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon u32 val; 101e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 10204712f3ff6e3a42ef658b55b0f99478f4f0682e3Maxime Bizon if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368()) 103e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon return -ENODEV; 104e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 105e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon if (!bcm63xx_pci_enabled) 106e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon return -ENODEV; 107e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 108e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon /* 109e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * configuration access are done through IO space, remap 4 110e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * first bytes to access it from CPU. 111e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * 112e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * this means that no io access from CPU should happen while 113e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * we do a configuration cycle, but there's no way we can add 114e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * a spinlock for each io access, so this is currently kind of 115e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * broken on SMP. 116e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon */ 117e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon pci_iospace_start = ioremap_nocache(BCM_PCI_IO_BASE_PA, 4); 118e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon if (!pci_iospace_start) 119e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon return -ENOMEM; 120e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 121e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon /* setup local bus to PCI access (PCI memory) */ 122e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon val = BCM_PCI_MEM_BASE_PA & MPI_L2P_BASE_MASK; 123e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm_mpi_writel(val, MPI_L2PMEMBASE1_REG); 124e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm_mpi_writel(~(BCM_PCI_MEM_SIZE - 1), MPI_L2PMEMRANGE1_REG); 125e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PMEMREMAP1_REG); 126e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 127e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon /* set Cardbus IDSEL (type 0 cfg access on primary bus for 128e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * this IDSEL will be done on Cardbus instead) */ 129e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon val = bcm_pcmcia_readl(PCMCIA_C1_REG); 130e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon val &= ~PCMCIA_C1_CBIDSEL_MASK; 131e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT); 132e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm_pcmcia_writel(val, PCMCIA_C1_REG); 133e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 134e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon#ifdef CONFIG_CARDBUS 135e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon /* setup local bus to PCI access (Cardbus memory) */ 136e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon val = BCM_CB_MEM_BASE_PA & MPI_L2P_BASE_MASK; 137e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm_mpi_writel(val, MPI_L2PMEMBASE2_REG); 138e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm_mpi_writel(~(BCM_CB_MEM_SIZE - 1), MPI_L2PMEMRANGE2_REG); 139e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK; 140e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm_mpi_writel(val, MPI_L2PMEMREMAP2_REG); 141e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon#else 142e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon /* disable second access windows */ 143e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG); 144e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon#endif 145e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 146e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon /* setup local bus to PCI access (IO memory), we have only 1 147e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * IO window for both PCI and cardbus, but it cannot handle 148e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * both at the same time, assume standard PCI for now, if 149e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * cardbus card has IO zone, PCI fixup will change window to 150e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * cardbus */ 151e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK; 152e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm_mpi_writel(val, MPI_L2PIOBASE_REG); 153e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm_mpi_writel(~(BCM_PCI_IO_SIZE - 1), MPI_L2PIORANGE_REG); 154e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PIOREMAP_REG); 155e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 156e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon /* enable PCI related GPIO pins */ 157e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm_mpi_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK, MPI_LOCBUSCTL_REG); 158e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 159e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon /* setup PCI to local bus access, used by PCI device to target 160e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * local RAM while bus mastering */ 161e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3); 16204712f3ff6e3a42ef658b55b0f99478f4f0682e3Maxime Bizon if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) 163e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon val = MPI_SP0_REMAP_ENABLE_MASK; 164e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon else 165e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon val = 0; 166e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm_mpi_writel(val, MPI_SP0_REMAP_REG); 167e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 168e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm63xx_int_cfg_writel(0x0, PCI_BASE_ADDRESS_4); 169e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm_mpi_writel(0, MPI_SP1_REMAP_REG); 170e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 171e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon mem_size = bcm63xx_get_memory_size(); 172e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 173e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon /* 6348 before rev b0 exposes only 16 MB of RAM memory through 174e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * PCI, throw a warning if we have more memory */ 175e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() & 0xf0) == 0xa0) { 176e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon if (mem_size > (16 * 1024 * 1024)) 177e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon printk(KERN_WARNING "bcm63xx: this CPU " 178e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon "revision cannot handle more than 16MB " 179e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon "of RAM for PCI bus mastering\n"); 180e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon } else { 181e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon /* setup sp0 range to local RAM size */ 182e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm_mpi_writel(~(mem_size - 1), MPI_SP0_RANGE_REG); 183e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm_mpi_writel(0, MPI_SP1_RANGE_REG); 184e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon } 185e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 186e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon /* change host bridge retry counter to infinite number of 187e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * retry, needed for some broadcom wifi cards with Silicon 188e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * Backplane bus where access to srom seems very slow */ 189e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS); 190e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon val &= ~REG_TIMER_RETRY_MASK; 191e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm63xx_int_cfg_writel(val, BCMPCI_REG_TIMERS); 192e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 193e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon /* enable memory decoder and bus mastering */ 194e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon val = bcm63xx_int_cfg_readl(PCI_COMMAND); 195e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 196e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm63xx_int_cfg_writel(val, PCI_COMMAND); 197e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 198e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon /* enable read prefetching & disable byte swapping for bus 199e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon * mastering transfers */ 200e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon val = bcm_mpi_readl(MPI_PCIMODESEL_REG); 201e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK; 202e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK; 203e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon val &= ~MPI_PCIMODESEL_PREFETCH_MASK; 204e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT); 205e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm_mpi_writel(val, MPI_PCIMODESEL_REG); 206e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 207e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon /* enable pci interrupt */ 208e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon val = bcm_mpi_readl(MPI_LOCINT_REG); 209e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT); 210e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon bcm_mpi_writel(val, MPI_LOCINT_REG); 211e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 212e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon register_pci_controller(&bcm63xx_controller); 213e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 214e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon#ifdef CONFIG_CARDBUS 215e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon register_pci_controller(&bcm63xx_cb_controller); 216e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon#endif 217e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 218e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon /* mark memory space used for IO mapping as reserved */ 219e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE, 220e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon "bcm63xx PCI IO space"); 221e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon return 0; 222e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon} 223e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizon 224e7300d04bd0809eb7ea10a2ed8c729459f816e36Maxime Bizonarch_initcall(bcm63xx_pci_init); 225