1368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi/* ASB2303-specific timer specifications 2b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells * 3730c1fad0ee22a170d2ee76a904709ee304931c0Mark Salter * Copyright (C) 2007, 2010 Red Hat, Inc. All Rights Reserved. 4b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells * Written by David Howells (dhowells@redhat.com) 5b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells * 6b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells * This program is free software; you can redistribute it and/or 7b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells * modify it under the terms of the GNU General Public Licence 8b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells * as published by the Free Software Foundation; either version 9b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells * 2 of the Licence, or (at your option) any later version. 10b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells */ 11b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells#ifndef _ASM_UNIT_TIMEX_H 12b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells#define _ASM_UNIT_TIMEX_H 13b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 14b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells#ifndef __ASSEMBLY__ 15b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells#include <linux/irq.h> 16b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells#endif /* __ASSEMBLY__ */ 17b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 18b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells#include <asm/timer-regs.h> 192f2a2132ff056bb45697dc855eb4fd95b70b38cbDavid Howells#include <unit/clock.h> 20368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi#include <asm/param.h> 21b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 22b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells/* 23b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells * jiffies counter specifications 24b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells */ 25b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 26b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells#define TMJCBR_MAX 0xffff 27b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells#define TMJCIRQ TM1IRQ 28b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells#define TMJCICR TM1ICR 29b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 30b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells#ifndef __ASSEMBLY__ 31b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 32368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi#define MN10300_SRC_IOCLK MN10300_IOCLK 33368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi 34368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi#ifndef HZ 35368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi# error HZ undeclared. 36368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi#endif /* !HZ */ 37368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi/* use as little prescaling as possible to avoid losing accuracy */ 38368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi#if (MN10300_SRC_IOCLK + HZ / 2) / HZ - 1 <= TMJCBR_MAX 39368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi# define IOCLK_PRESCALE 1 40368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi# define JC_TIMER_CLKSRC TM0MD_SRC_IOCLK 41368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi# define TSC_TIMER_CLKSRC TM4MD_SRC_IOCLK 42368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi#elif (MN10300_SRC_IOCLK / 8 + HZ / 2) / HZ - 1 <= TMJCBR_MAX 43368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi# define IOCLK_PRESCALE 8 44368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi# define JC_TIMER_CLKSRC TM0MD_SRC_IOCLK_8 45368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi# define TSC_TIMER_CLKSRC TM4MD_SRC_IOCLK_8 46368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi#elif (MN10300_SRC_IOCLK / 32 + HZ / 2) / HZ - 1 <= TMJCBR_MAX 47368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi# define IOCLK_PRESCALE 32 48368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi# define JC_TIMER_CLKSRC TM0MD_SRC_IOCLK_32 49368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi# define TSC_TIMER_CLKSRC TM4MD_SRC_IOCLK_32 50368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi#else 51368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi# error You lose. 52368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi#endif 53368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi 54368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi#define MN10300_JCCLK (MN10300_SRC_IOCLK / IOCLK_PRESCALE) 55368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi#define MN10300_TSCCLK (MN10300_SRC_IOCLK / IOCLK_PRESCALE) 56368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi 57368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi#define MN10300_JC_PER_HZ ((MN10300_JCCLK + HZ / 2) / HZ) 58368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi#define MN10300_TSC_PER_HZ ((MN10300_TSCCLK + HZ / 2) / HZ) 59368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi 60730c1fad0ee22a170d2ee76a904709ee304931c0Mark Salterstatic inline void stop_jiffies_counter(void) 61b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells{ 62730c1fad0ee22a170d2ee76a904709ee304931c0Mark Salter u16 tmp; 63730c1fad0ee22a170d2ee76a904709ee304931c0Mark Salter TM01MD = JC_TIMER_CLKSRC | TM1MD_SRC_TM0CASCADE << 8; 64730c1fad0ee22a170d2ee76a904709ee304931c0Mark Salter tmp = TM01MD; 65730c1fad0ee22a170d2ee76a904709ee304931c0Mark Salter} 66b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 67730c1fad0ee22a170d2ee76a904709ee304931c0Mark Salterstatic inline void reload_jiffies_counter(u32 cnt) 68730c1fad0ee22a170d2ee76a904709ee304931c0Mark Salter{ 69730c1fad0ee22a170d2ee76a904709ee304931c0Mark Salter u32 tmp; 70b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 71730c1fad0ee22a170d2ee76a904709ee304931c0Mark Salter TM01BR = cnt; 72730c1fad0ee22a170d2ee76a904709ee304931c0Mark Salter tmp = TM01BR; 73b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 74730c1fad0ee22a170d2ee76a904709ee304931c0Mark Salter TM01MD = JC_TIMER_CLKSRC | \ 75730c1fad0ee22a170d2ee76a904709ee304931c0Mark Salter TM1MD_SRC_TM0CASCADE << 8 | \ 76730c1fad0ee22a170d2ee76a904709ee304931c0Mark Salter TM0MD_INIT_COUNTER | \ 77730c1fad0ee22a170d2ee76a904709ee304931c0Mark Salter TM1MD_INIT_COUNTER << 8; 78b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 79b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 80730c1fad0ee22a170d2ee76a904709ee304931c0Mark Salter TM01MD = JC_TIMER_CLKSRC | \ 81730c1fad0ee22a170d2ee76a904709ee304931c0Mark Salter TM1MD_SRC_TM0CASCADE << 8 | \ 82730c1fad0ee22a170d2ee76a904709ee304931c0Mark Salter TM0MD_COUNT_ENABLE | \ 83730c1fad0ee22a170d2ee76a904709ee304931c0Mark Salter TM1MD_COUNT_ENABLE << 8; 84b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 85730c1fad0ee22a170d2ee76a904709ee304931c0Mark Salter tmp = TM01MD; 86b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells} 87b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 88b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells#endif /* !__ASSEMBLY__ */ 89b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 90b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 91b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells/* 92b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells * timestamp counter specifications 93b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells */ 94b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 95b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells#define TMTSCBR_MAX 0xffffffff 96b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells#define TMTSCBC TM45BC 97b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 98b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells#ifndef __ASSEMBLY__ 99b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 100b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howellsstatic inline void startup_timestamp_counter(void) 101b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells{ 102368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi u32 t32; 103368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi 104b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells /* set up timer 4 & 5 cascaded as a 32-bit counter to count real time 105b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells * - count down from 4Gig-1 to 0 and wrap at IOCLK rate 106b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells */ 107b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells TM45BR = TMTSCBR_MAX; 108368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi t32 = TM45BR; 109b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 110368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi TM4MD = TSC_TIMER_CLKSRC; 111b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells TM4MD |= TM4MD_INIT_COUNTER; 112b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells TM4MD &= ~TM4MD_INIT_COUNTER; 113b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells TM4ICR = 0; 114368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi t32 = TM4ICR; 115b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 116b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells TM5MD = TM5MD_SRC_TM4CASCADE; 117b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells TM5MD |= TM5MD_INIT_COUNTER; 118b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells TM5MD &= ~TM5MD_INIT_COUNTER; 119b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells TM5ICR = 0; 120368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi t32 = TM5ICR; 121b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 122b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells TM5MD |= TM5MD_COUNT_ENABLE; 123b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells TM4MD |= TM4MD_COUNT_ENABLE; 124368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi t32 = TM5MD; 125368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi t32 = TM4MD; 126b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells} 127b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 128b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howellsstatic inline void shutdown_timestamp_counter(void) 129b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells{ 130368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi u8 t8; 131b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells TM4MD = 0; 132b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells TM5MD = 0; 133368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi t8 = TM4MD; 134368dd5acd154b09c043cc4392a74da01599b37d5Akira Takeuchi t8 = TM5MD; 135b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells} 136b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 137b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells/* 138b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells * we use a cascaded pair of 16-bit down-counting timers to count I/O 139b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells * clock cycles for the purposes of time keeping 140b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells */ 141b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howellstypedef unsigned long cycles_t; 142b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 143b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howellsstatic inline cycles_t read_timestamp_counter(void) 144b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells{ 145730c1fad0ee22a170d2ee76a904709ee304931c0Mark Salter return (cycles_t)~TMTSCBC; 146b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells} 147b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 148b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells#endif /* !__ASSEMBLY__ */ 149b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells 150b920de1b77b72ca9432ac3f97edb26541e65e5ddDavid Howells#endif /* _ASM_UNIT_TIMEX_H */ 151