gef_ppc9a.dts revision 740d36ae6344f38c4da64c2ede765d7d2dd1f132 
1/*
2 * GE Fanuc PPC9A Device Tree Source
3 *
4 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 *
11 * Based on: SBS CM6 Device Tree Source
12 * Copyright 2007 SBS Technologies GmbH & Co. KG
13 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
14 * Copyright 2006 Freescale Semiconductor Inc.
15 */
16
17/*
18 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
19 */
20
21/dts-v1/;
22
23/ {
24	model = "GEF_PPC9A";
25	compatible = "gef,ppc9a";
26	#address-cells = <1>;
27	#size-cells = <1>;
28
29	aliases {
30		ethernet0 = &enet0;
31		ethernet1 = &enet1;
32		serial0 = &serial0;
33		serial1 = &serial1;
34		pci0 = &pci0;
35	};
36
37	cpus {
38		#address-cells = <1>;
39		#size-cells = <0>;
40
41		PowerPC,8641@0 {
42			device_type = "cpu";
43			reg = <0>;
44			d-cache-line-size = <32>;	// 32 bytes
45			i-cache-line-size = <32>;	// 32 bytes
46			d-cache-size = <32768>;		// L1, 32K
47			i-cache-size = <32768>;		// L1, 32K
48			timebase-frequency = <0>;	// From uboot
49			bus-frequency = <0>;		// From uboot
50			clock-frequency = <0>;		// From uboot
51		};
52		PowerPC,8641@1 {
53			device_type = "cpu";
54			reg = <1>;
55			d-cache-line-size = <32>;	// 32 bytes
56			i-cache-line-size = <32>;	// 32 bytes
57			d-cache-size = <32768>;		// L1, 32K
58			i-cache-size = <32768>;		// L1, 32K
59			timebase-frequency = <0>;	// From uboot
60			bus-frequency = <0>;		// From uboot
61			clock-frequency = <0>;		// From uboot
62		};
63	};
64
65	memory {
66		device_type = "memory";
67		reg = <0x0 0x40000000>;	// set by uboot
68	};
69
70	localbus@fef05000 {
71		#address-cells = <2>;
72		#size-cells = <1>;
73		compatible = "fsl,mpc8641-localbus", "simple-bus";
74		reg = <0xfef05000 0x1000>;
75		interrupts = <19 2>;
76		interrupt-parent = <&mpic>;
77
78		ranges = <0 0 0xff000000 0x01000000	// 16MB Boot flash
79			  1 0 0xe8000000 0x08000000	// Paged Flash 0
80			  2 0 0xe0000000 0x08000000	// Paged Flash 1
81			  3 0 0xfc100000 0x00020000	// NVRAM
82			  4 0 0xfc000000 0x00008000	// FPGA
83			  5 0 0xfc008000 0x00008000	// AFIX FPGA
84			  6 0 0xfd000000 0x00800000	// IO FPGA (8-bit)
85			  7 0 0xfd800000 0x00800000>;	// IO FPGA (32-bit)
86
87		/* flash@0,0 is a mirror of part of the memory in flash@1,0
88		flash@0,0 {
89			compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
90			reg = <0x0 0x0 0x1000000>;
91			bank-width = <4>;
92			device-width = <2>;
93			#address-cells = <1>;
94			#size-cells = <1>;
95			partition@0 {
96				label = "firmware";
97				reg = <0x0 0x1000000>;
98				read-only;
99			};
100		};
101		*/
102
103		flash@1,0 {
104			compatible = "gef,ppc9a-paged-flash", "cfi-flash";
105			reg = <0x1 0x0 0x8000000>;
106			bank-width = <4>;
107			device-width = <2>;
108			#address-cells = <1>;
109			#size-cells = <1>;
110			partition@0 {
111				label = "user";
112				reg = <0x0 0x7800000>;
113			};
114			partition@7800000 {
115				label = "firmware";
116				reg = <0x7800000 0x800000>;
117				read-only;
118			};
119		};
120
121		fpga@4,0 {
122			compatible = "gef,ppc9a-fpga-regs";
123			reg = <0x4 0x0 0x40>;
124		};
125
126		wdt@4,2000 {
127			compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
128				"gef,fpga-wdt";
129			reg = <0x4 0x2000 0x8>;
130			interrupts = <0x1a 0x4>;
131			interrupt-parent = <&gef_pic>;
132		};
133		/* Second watchdog available, driver currently supports one.
134		wdt@4,2010 {
135			compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
136				"gef,fpga-wdt";
137			reg = <0x4 0x2010 0x8>;
138			interrupts = <0x1b 0x4>;
139			interrupt-parent = <&gef_pic>;
140		};
141		*/
142		gef_pic: pic@4,4000 {
143			#interrupt-cells = <1>;
144			interrupt-controller;
145			compatible = "gef,ppc9a-fpga-pic", "gef,fpga-pic-1.00";
146			reg = <0x4 0x4000 0x20>;
147			interrupts = <0x8
148				      0x9>;
149			interrupt-parent = <&mpic>;
150
151		};
152		gef_gpio: gpio@7,14000 {
153			#gpio-cells = <2>;
154			compatible = "gef,ppc9a-gpio", "gef,sbc610-gpio";
155			reg = <0x7 0x14000 0x24>;
156			gpio-controller;
157		};
158	};
159
160	soc@fef00000 {
161		#address-cells = <1>;
162		#size-cells = <1>;
163		#interrupt-cells = <2>;
164		compatible = "fsl,mpc8641-soc", "simple-bus";
165		ranges = <0x0 0xfef00000 0x00100000>;
166		reg = <0xfef00000 0x100000>;	// CCSRBAR 1M
167		bus-frequency = <33333333>;
168
169		i2c1: i2c@3000 {
170			#address-cells = <1>;
171			#size-cells = <0>;
172			compatible = "fsl-i2c";
173			reg = <0x3000 0x100>;
174			interrupts = <0x2b 0x2>;
175			interrupt-parent = <&mpic>;
176			dfsrr;
177
178			hwmon@48 {
179				compatible = "national,lm92";
180				reg = <0x48>;
181			};
182
183			hwmon@4c {
184				compatible = "adi,adt7461";
185				reg = <0x4c>;
186			};
187
188			rtc@51 {
189				compatible = "epson,rx8581";
190				reg = <0x00000051>;
191			};
192
193			eti@6b {
194				compatible = "dallas,ds1682";
195				reg = <0x6b>;
196			};
197		};
198
199		i2c2: i2c@3100 {
200			#address-cells = <1>;
201			#size-cells = <0>;
202			compatible = "fsl-i2c";
203			reg = <0x3100 0x100>;
204			interrupts = <0x2b 0x2>;
205			interrupt-parent = <&mpic>;
206			dfsrr;
207		};
208
209		dma@21300 {
210			#address-cells = <1>;
211			#size-cells = <1>;
212			compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
213			reg = <0x21300 0x4>;
214			ranges = <0x0 0x21100 0x200>;
215			cell-index = <0>;
216			dma-channel@0 {
217				compatible = "fsl,mpc8641-dma-channel",
218					   "fsl,eloplus-dma-channel";
219				reg = <0x0 0x80>;
220				cell-index = <0>;
221				interrupt-parent = <&mpic>;
222				interrupts = <20 2>;
223			};
224			dma-channel@80 {
225				compatible = "fsl,mpc8641-dma-channel",
226					   "fsl,eloplus-dma-channel";
227				reg = <0x80 0x80>;
228				cell-index = <1>;
229				interrupt-parent = <&mpic>;
230				interrupts = <21 2>;
231			};
232			dma-channel@100 {
233				compatible = "fsl,mpc8641-dma-channel",
234					   "fsl,eloplus-dma-channel";
235				reg = <0x100 0x80>;
236				cell-index = <2>;
237				interrupt-parent = <&mpic>;
238				interrupts = <22 2>;
239			};
240			dma-channel@180 {
241				compatible = "fsl,mpc8641-dma-channel",
242					   "fsl,eloplus-dma-channel";
243				reg = <0x180 0x80>;
244				cell-index = <3>;
245				interrupt-parent = <&mpic>;
246				interrupts = <23 2>;
247			};
248		};
249
250		mdio@24520 {
251			#address-cells = <1>;
252			#size-cells = <0>;
253			compatible = "fsl,gianfar-mdio";
254			reg = <0x24520 0x20>;
255
256			phy0: ethernet-phy@0 {
257				interrupt-parent = <&gef_pic>;
258				interrupts = <0x9 0x4>;
259				reg = <1>;
260			};
261			phy2: ethernet-phy@2 {
262				interrupt-parent = <&gef_pic>;
263				interrupts = <0x8 0x4>;
264				reg = <3>;
265			};
266		};
267
268		enet0: ethernet@24000 {
269			device_type = "network";
270			model = "eTSEC";
271			compatible = "gianfar";
272			reg = <0x24000 0x1000>;
273			local-mac-address = [ 00 00 00 00 00 00 ];
274			interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
275			interrupt-parent = <&mpic>;
276			phy-handle = <&phy0>;
277			phy-connection-type = "gmii";
278		};
279
280		enet1: ethernet@26000 {
281			device_type = "network";
282			model = "eTSEC";
283			compatible = "gianfar";
284			reg = <0x26000 0x1000>;
285			local-mac-address = [ 00 00 00 00 00 00 ];
286			interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
287			interrupt-parent = <&mpic>;
288			phy-handle = <&phy2>;
289			phy-connection-type = "gmii";
290		};
291
292		serial0: serial@4500 {
293			cell-index = <0>;
294			device_type = "serial";
295			compatible = "ns16550";
296			reg = <0x4500 0x100>;
297			clock-frequency = <0>;
298			interrupts = <0x2a 0x2>;
299			interrupt-parent = <&mpic>;
300		};
301
302		serial1: serial@4600 {
303			cell-index = <1>;
304			device_type = "serial";
305			compatible = "ns16550";
306			reg = <0x4600 0x100>;
307			clock-frequency = <0>;
308			interrupts = <0x1c 0x2>;
309			interrupt-parent = <&mpic>;
310		};
311
312		mpic: pic@40000 {
313			clock-frequency = <0>;
314			interrupt-controller;
315			#address-cells = <0>;
316			#interrupt-cells = <2>;
317			reg = <0x40000 0x40000>;
318			compatible = "chrp,open-pic";
319			device_type = "open-pic";
320		};
321
322		global-utilities@e0000 {
323			compatible = "fsl,mpc8641-guts";
324			reg = <0xe0000 0x1000>;
325			fsl,has-rstcr;
326		};
327	};
328
329	pci0: pcie@fef08000 {
330		compatible = "fsl,mpc8641-pcie";
331		device_type = "pci";
332		#interrupt-cells = <1>;
333		#size-cells = <2>;
334		#address-cells = <3>;
335		reg = <0xfef08000 0x1000>;
336		bus-range = <0x0 0xff>;
337		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
338			  0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
339		clock-frequency = <33333333>;
340		interrupt-parent = <&mpic>;
341		interrupts = <0x18 0x2>;
342		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
343		interrupt-map = <
344			0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
345			0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
346			0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
347			0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
348		>;
349
350		pcie@0 {
351			reg = <0 0 0 0 0>;
352			#size-cells = <2>;
353			#address-cells = <3>;
354			device_type = "pci";
355			ranges = <0x02000000 0x0 0x80000000
356				  0x02000000 0x0 0x80000000
357				  0x0 0x40000000
358
359				  0x01000000 0x0 0x00000000
360				  0x01000000 0x0 0x00000000
361				  0x0 0x00400000>;
362		};
363	};
364};
365