xref: /arch/powerpc/boot/dts/mpc8572ds.dtsi

/*
 * MPC8572DS Device Tree Source stub (no addresses or top-level ranges)
 *
 * Copyright 2011 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

&board_lbc {
	nor@0,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "cfi-flash";
		reg = <0x0 0x0 0x8000000>;
		bank-width = <2>;
		device-width = <1>;

		partition@0 {
			reg = <0x0 0x03000000>;
			label = "ramdisk-nor";
		};

		partition@3000000 {
			reg = <0x03000000 0x00e00000>;
			label = "diagnostic-nor";
			read-only;
		};

		partition@3e00000 {
			reg = <0x03e00000 0x00200000>;
			label = "dink-nor";
			read-only;
		};

		partition@4000000 {
			reg = <0x04000000 0x00400000>;
			label = "kernel-nor";
		};

		partition@4400000 {
			reg = <0x04400000 0x03b00000>;
			label = "fs-nor";
		};

		partition@7f00000 {
			reg = <0x07f00000 0x00060000>;
			label = "dtb-nor";
		};

		partition@7f60000 {
			reg = <0x07f60000 0x00020000>;
			label = "env-nor";
			read-only;
		};

		partition@7f80000 {
			reg = <0x07f80000 0x00080000>;
			label = "u-boot-nor";
			read-only;
		};
	};

	nand@2,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "fsl,mpc8572-fcm-nand",
			     "fsl,elbc-fcm-nand";
		reg = <0x2 0x0 0x40000>;

		partition@0 {
			reg = <0x0 0x02000000>;
			label = "u-boot-nand";
			read-only;
		};

		partition@2000000 {
			reg = <0x02000000 0x10000000>;
			label = "fs-nand";
		};

		partition@12000000 {
			reg = <0x12000000 0x08000000>;
			label = "ramdisk-nand";
		};

		partition@1a000000 {
			reg = <0x1a000000 0x04000000>;
			label = "kernel-nand";
		};

		partition@1e000000 {
			reg = <0x1e000000 0x01000000>;
			label = "dtb-nand";
		};

		partition@1f000000 {
			reg = <0x1f000000 0x21000000>;
			label = "empty-nand";
		};
	};

	nand@4,0 {
		compatible = "fsl,mpc8572-fcm-nand",
			     "fsl,elbc-fcm-nand";
		reg = <0x4 0x0 0x40000>;
	};

	nand@5,0 {
		compatible = "fsl,mpc8572-fcm-nand",
			     "fsl,elbc-fcm-nand";
		reg = <0x5 0x0 0x40000>;
	};

	nand@6,0 {
		compatible = "fsl,mpc8572-fcm-nand",
			     "fsl,elbc-fcm-nand";
		reg = <0x6 0x0 0x40000>;
	};
};

&board_soc {
	enet0: ethernet@24000 {
		tbi-handle = <&tbi0>;
		phy-handle = <&phy0>;
		phy-connection-type = "rgmii-id";
	};

	mdio@24520 {
		phy0: ethernet-phy@0 {
			interrupts = <10 1 0 0>;
			reg = <0x0>;
		};
		phy1: ethernet-phy@1 {
			interrupts = <10 1 0 0>;
			reg = <0x1>;
		};
		phy2: ethernet-phy@2 {
			interrupts = <10 1 0 0>;
			reg = <0x2>;
		};
		phy3: ethernet-phy@3 {
			interrupts = <10 1 0 0>;
			reg = <0x3>;
		};

		tbi0: tbi-phy@11 {
			reg = <0x11>;
			device_type = "tbi-phy";
		};
	};

	ptp_clock@24e00 {
		fsl,tclk-period = <5>;
		fsl,tmr-prsc = <200>;
		fsl,tmr-add = <0xAAAAAAAB>;
		fsl,tmr-fiper1 = <0x3B9AC9FB>;
		fsl,tmr-fiper2 = <0x3B9AC9FB>;
		fsl,max-adj = <499999999>;
	};

	enet1: ethernet@25000 {
		tbi-handle = <&tbi1>;
		phy-handle = <&phy1>;
		phy-connection-type = "rgmii-id";

	};

	mdio@25520 {
		tbi1: tbi-phy@11 {
			reg = <0x11>;
			device_type = "tbi-phy";
		};
	};

	enet2: ethernet@26000 {
		tbi-handle = <&tbi2>;
		phy-handle = <&phy2>;
		phy-connection-type = "rgmii-id";

	};
	mdio@26520 {
		tbi2: tbi-phy@11 {
			reg = <0x11>;
			device_type = "tbi-phy";
		};
	};

	enet3: ethernet@27000 {
		tbi-handle = <&tbi3>;
		phy-handle = <&phy3>;
		phy-connection-type = "rgmii-id";
	};

	mdio@27520 {
		tbi3: tbi-phy@11 {
			reg = <0x11>;
			device_type = "tbi-phy";
		};
	};
};

&board_pci0 {
	pcie@0 {
		interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
		interrupt-map = <
			/* IDSEL 0x11 func 0 - PCI slot 1 */
			0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
			0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
			0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
			0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0

			/* IDSEL 0x11 func 1 - PCI slot 1 */
			0x8900 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
			0x8900 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
			0x8900 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
			0x8900 0x0 0x0 0x4 &mpic 0x1 0x1 0 0

			/* IDSEL 0x11 func 2 - PCI slot 1 */
			0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
			0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
			0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
			0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0

			/* IDSEL 0x11 func 3 - PCI slot 1 */
			0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
			0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
			0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
			0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0

			/* IDSEL 0x11 func 4 - PCI slot 1 */
			0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
			0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
			0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
			0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0

			/* IDSEL 0x11 func 5 - PCI slot 1 */
			0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
			0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
			0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
			0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0

			/* IDSEL 0x11 func 6 - PCI slot 1 */
			0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
			0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
			0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
			0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0

			/* IDSEL 0x11 func 7 - PCI slot 1 */
			0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
			0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
			0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
			0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0

			/* IDSEL 0x12 func 0 - PCI slot 2 */
			0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
			0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
			0x9000 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
			0x9000 0x0 0x0 0x4 &mpic 0x2 0x1 0 0

			/* IDSEL 0x12 func 1 - PCI slot 2 */
			0x9100 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
			0x9100 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
			0x9100 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
			0x9100 0x0 0x0 0x4 &mpic 0x2 0x1 0 0

			/* IDSEL 0x12 func 2 - PCI slot 2 */
			0x9200 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
			0x9200 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
			0x9200 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
			0x9200 0x0 0x0 0x4 &mpic 0x2 0x1 0 0

			/* IDSEL 0x12 func 3 - PCI slot 2 */
			0x9300 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
			0x9300 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
			0x9300 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
			0x9300 0x0 0x0 0x4 &mpic 0x2 0x1 0 0

			/* IDSEL 0x12 func 4 - PCI slot 2 */
			0x9400 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
			0x9400 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
			0x9400 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
			0x9400 0x0 0x0 0x4 &mpic 0x2 0x1 0 0

			/* IDSEL 0x12 func 5 - PCI slot 2 */
			0x9500 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
			0x9500 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
			0x9500 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
			0x9500 0x0 0x0 0x4 &mpic 0x2 0x1 0 0

			/* IDSEL 0x12 func 6 - PCI slot 2 */
			0x9600 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
			0x9600 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
			0x9600 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
			0x9600 0x0 0x0 0x4 &mpic 0x2 0x1 0 0

			/* IDSEL 0x12 func 7 - PCI slot 2 */
			0x9700 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
			0x9700 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
			0x9700 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
			0x9700 0x0 0x0 0x4 &mpic 0x2 0x1 0 0

			// IDSEL 0x1c  USB
			0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
			0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
			0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
			0xe300 0x0 0x0 0x4 &i8259 0xb 0x2

			// IDSEL 0x1d  Audio
			0xe800 0x0 0x0 0x1 &i8259 0x6 0x2

			// IDSEL 0x1e Legacy
			0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
			0xf100 0x0 0x0 0x1 &i8259 0x7 0x2

			// IDSEL 0x1f IDE/SATA
			0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
			0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
			>;


		uli1575@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			ranges = <0x2000000 0x0 0x80000000
				  0x2000000 0x0 0x80000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x10000>;
			isa@1e {
				device_type = "isa";
				#interrupt-cells = <2>;
				#size-cells = <1>;
				#address-cells = <2>;
				reg = <0xf000 0x0 0x0 0x0 0x0>;
				ranges = <0x1 0x0 0x1000000 0x0 0x0
					  0x1000>;
				interrupt-parent = <&i8259>;

				i8259: interrupt-controller@20 {
					reg = <0x1 0x20 0x2
					       0x1 0xa0 0x2
					       0x1 0x4d0 0x2>;
					interrupt-controller;
					device_type = "interrupt-controller";
					#address-cells = <0>;
					#interrupt-cells = <2>;
					compatible = "chrp,iic";
					interrupts = <9 2 0 0>;
					interrupt-parent = <&mpic>;
				};

				i8042@60 {
					#size-cells = <0>;
					#address-cells = <1>;
					reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
					interrupts = <1 3 12 3>;
					interrupt-parent =
						<&i8259>;

					keyboard@0 {
						reg = <0x0>;
						compatible = "pnpPNP,303";
					};

					mouse@1 {
						reg = <0x1>;
						compatible = "pnpPNP,f03";
					};
				};

				rtc@70 {
					compatible = "pnpPNP,b00";
					reg = <0x1 0x70 0x2>;
				};

				gpio@400 {
					reg = <0x1 0x400 0x80>;
				};
			};
		};
	};
};