1bbeb3f4c55f666df7bcd2655b303dfb8c4d1a119Stephen Rothwell#ifndef _ASM_POWERPC_MPIC_H 2bbeb3f4c55f666df7bcd2655b303dfb8c4d1a119Stephen Rothwell#define _ASM_POWERPC_MPIC_H 388ced0314938814e1772b4d0d7ab20c52e4472b6Arnd Bergmann#ifdef __KERNEL__ 4bbeb3f4c55f666df7bcd2655b303dfb8c4d1a119Stephen Rothwell 514cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#include <linux/irq.h> 6fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt#include <asm/dcr.h> 725235f712b680d00756a73ee64289137989fc6fdMichael Ellerman#include <asm/msi_bitmap.h> 814cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 914cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras/* 1014cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * Global registers 1114cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras */ 1214cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 1314cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_BASE 0x01000 1414cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 1514cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_FEATURE_0 0x00000 1614cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000 1714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16 1814cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00 1914cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8 2014cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_FEATURE_VERSION_MASK 0xff 2114cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_FEATURE_1 0x00010 2214cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_GLOBAL_CONF_0 0x00020 2314cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_GCONF_RESET 0x80000000 24d91e4ea7047d96733d763f1626f1f21ff4298cefKumar Gala/* On the FSL mpic implementations the Mode field is expand to be 25d91e4ea7047d96733d763f1626f1f21ff4298cefKumar Gala * 2 bits wide: 26d91e4ea7047d96733d763f1626f1f21ff4298cefKumar Gala * 0b00 = pass through (interrupts routed to IRQ0) 27d91e4ea7047d96733d763f1626f1f21ff4298cefKumar Gala * 0b01 = Mixed mode 28d91e4ea7047d96733d763f1626f1f21ff4298cefKumar Gala * 0b10 = reserved 29d91e4ea7047d96733d763f1626f1f21ff4298cefKumar Gala * 0b11 = External proxy / coreint 30d91e4ea7047d96733d763f1626f1f21ff4298cefKumar Gala */ 31d91e4ea7047d96733d763f1626f1f21ff4298cefKumar Gala#define MPIC_GREG_GCONF_COREINT 0x60000000 3214cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000 33d87bf3bed71375b141e95b5fdbac413ac4b65184Olof Johansson#define MPIC_GREG_GCONF_NO_BIAS 0x10000000 3414cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff 35f365355e65ee619e3b7baeca69b46fd2c4a5ec68Olof Johansson#define MPIC_GREG_GCONF_MCK 0x08000000 3614cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_GLOBAL_CONF_1 0x00030 37868ea0c9256b658b14603e1ad7361b81b92ccacdMark A. Greer#define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000 38868ea0c9256b658b14603e1ad7361b81b92ccacdMark A. Greer#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000 39868ea0c9256b658b14603e1ad7361b81b92ccacdMark A. Greer#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r) \ 40868ea0c9256b658b14603e1ad7361b81b92ccacdMark A. Greer (((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK) 4114cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_VENDOR_0 0x00040 4214cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_VENDOR_1 0x00050 4314cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_VENDOR_2 0x00060 4414cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_VENDOR_3 0x00070 4514cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_VENDOR_ID 0x00080 4614cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000 4714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16 4814cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00 4914cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8 5014cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff 5114cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_PROCESSOR_INIT 0x00090 5214cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0 5314cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0 5414cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0 5514cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0 567233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define MPIC_GREG_IPI_STRIDE 0x10 5714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_SPURIOUS 0x000e0 5814cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_GREG_TIMER_FREQ 0x000f0 5914cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 6014cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras/* 6114cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * 6214cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * Timer registers 6314cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras */ 6414cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_TIMER_BASE 0x01100 6514cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_TIMER_STRIDE 0x40 6614cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 6714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_TIMER_CURRENT_CNT 0x00000 6814cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_TIMER_BASE_CNT 0x00010 6914cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_TIMER_VECTOR_PRI 0x00020 7014cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_TIMER_DESTINATION 0x00030 7114cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 7214cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras/* 7314cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * Per-Processor registers 7414cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras */ 7514cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 7614cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_CPU_THISBASE 0x00000 7714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_CPU_BASE 0x20000 7814cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_CPU_STRIDE 0x01000 7914cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 8014cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_CPU_IPI_DISPATCH_0 0x00040 8114cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_CPU_IPI_DISPATCH_1 0x00050 8214cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_CPU_IPI_DISPATCH_2 0x00060 8314cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_CPU_IPI_DISPATCH_3 0x00070 847233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010 8514cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_CPU_CURRENT_TASK_PRI 0x00080 8614cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_CPU_TASKPRI_MASK 0x0000000f 8714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_CPU_WHOAMI 0x00090 8814cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_CPU_WHOAMI_MASK 0x0000001f 8914cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_CPU_INTACK 0x000a0 9014cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_CPU_EOI 0x000b0 91f365355e65ee619e3b7baeca69b46fd2c4a5ec68Olof Johansson#define MPIC_CPU_MCACK 0x000c0 9214cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 9314cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras/* 9414cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * Per-source registers 9514cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras */ 9614cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 9714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_IRQ_BASE 0x10000 9814cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_IRQ_STRIDE 0x00020 9914cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_IRQ_VECTOR_PRI 0x00000 10014cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_VECPRI_MASK 0x80000000 10114cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */ 10214cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_VECPRI_PRIORITY_MASK 0x000f0000 10314cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_VECPRI_PRIORITY_SHIFT 16 10414cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_VECPRI_VECTOR_MASK 0x000007ff 10514cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000 10614cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000 10714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_VECPRI_POLARITY_MASK 0x00800000 10814cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_VECPRI_SENSE_LEVEL 0x00400000 10914cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_VECPRI_SENSE_EDGE 0x00000000 11014cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_VECPRI_SENSE_MASK 0x00400000 11114cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_IRQ_DESTINATION 0x00010 11214cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 11314cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_MAX_IRQ_SOURCES 2048 11414cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_MAX_CPUS 32 11514cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_MAX_ISU 32 11614cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 11714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras/* 1187233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r * Tsi108 implementation of MPIC has many differences from the original one 1197233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r */ 1207233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r 1217233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r/* 1227233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r * Global registers 1237233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r */ 1247233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r 1257233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_GREG_BASE 0x00000 1267233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_GREG_FEATURE_0 0x00000 1277233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_GREG_GLOBAL_CONF_0 0x00004 1287233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_GREG_VENDOR_ID 0x0000c 1297233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */ 1307233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_GREG_IPI_STRIDE 0x0c 1317233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_GREG_SPURIOUS 0x00010 1327233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_GREG_TIMER_FREQ 0x00014 1337233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r 1347233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r/* 1357233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r * Timer registers 1367233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r */ 1377233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_TIMER_BASE 0x0030 1387233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_TIMER_STRIDE 0x10 1397233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_TIMER_CURRENT_CNT 0x00000 1407233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_TIMER_BASE_CNT 0x00004 1417233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_TIMER_VECTOR_PRI 0x00008 1427233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_TIMER_DESTINATION 0x0000c 1437233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r 1447233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r/* 1457233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r * Per-Processor registers 1467233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r */ 1477233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_CPU_BASE 0x00300 1487233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_CPU_STRIDE 0x00040 1497233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_CPU_IPI_DISPATCH_0 0x00200 1507233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000 1517233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_CPU_CURRENT_TASK_PRI 0x00000 1527233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_CPU_WHOAMI 0xffffffff 1537233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_CPU_INTACK 0x00004 1547233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_CPU_EOI 0x00008 155f365355e65ee619e3b7baeca69b46fd2c4a5ec68Olof Johansson#define TSI108_CPU_MCACK 0x00004 /* Doesn't really exist here */ 1567233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r 1577233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r/* 1587233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r * Per-source registers 1597233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r */ 1607233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_IRQ_BASE 0x00100 1617233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_IRQ_STRIDE 0x00008 1627233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_IRQ_VECTOR_PRI 0x00000 1637233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_VECPRI_VECTOR_MASK 0x000000ff 1647233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000 1657233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000 1667233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_VECPRI_SENSE_LEVEL 0x02000000 1677233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_VECPRI_SENSE_EDGE 0x00000000 1687233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_VECPRI_POLARITY_MASK 0x01000000 1697233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_VECPRI_SENSE_MASK 0x02000000 1707233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define TSI108_IRQ_DESTINATION 0x00004 1717233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r 1727233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r/* weird mpic register indices and mask bits in the HW info array */ 1737233593b7844c2db930594ee9c0c872a6900bfccZang Roy-renum { 1747233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_GREG_BASE = 0, 1757233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_GREG_FEATURE_0, 1767233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_GREG_GLOBAL_CONF_0, 1777233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_GREG_VENDOR_ID, 1787233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_GREG_IPI_VECTOR_PRI_0, 1797233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_GREG_IPI_STRIDE, 1807233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_GREG_SPURIOUS, 1817233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_GREG_TIMER_FREQ, 1827233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r 1837233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_TIMER_BASE, 1847233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_TIMER_STRIDE, 1857233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_TIMER_CURRENT_CNT, 1867233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_TIMER_BASE_CNT, 1877233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_TIMER_VECTOR_PRI, 1887233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_TIMER_DESTINATION, 1897233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r 1907233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_CPU_BASE, 1917233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_CPU_STRIDE, 1927233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_CPU_IPI_DISPATCH_0, 1937233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_CPU_IPI_DISPATCH_STRIDE, 1947233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_CPU_CURRENT_TASK_PRI, 1957233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_CPU_WHOAMI, 1967233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_CPU_INTACK, 1977233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_CPU_EOI, 198f365355e65ee619e3b7baeca69b46fd2c4a5ec68Olof Johansson MPIC_IDX_CPU_MCACK, 1997233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r 2007233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_IRQ_BASE, 2017233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_IRQ_STRIDE, 2027233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_IRQ_VECTOR_PRI, 2037233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r 2047233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_VECPRI_VECTOR_MASK, 2057233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_VECPRI_POLARITY_POSITIVE, 2067233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_VECPRI_POLARITY_NEGATIVE, 2077233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_VECPRI_SENSE_LEVEL, 2087233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_VECPRI_SENSE_EDGE, 2097233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_VECPRI_POLARITY_MASK, 2107233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_VECPRI_SENSE_MASK, 2117233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_IRQ_DESTINATION, 2127233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r MPIC_IDX_END 2137233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r}; 2147233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r 2157233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r 2166cfef5b27e49e826125f12637ee0d7210a896044Michael Ellerman#ifdef CONFIG_MPIC_U3_HT_IRQS 21714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras/* Fixup table entry */ 21814cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerrasstruct mpic_irq_fixup 21914cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras{ 22014cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras u8 __iomem *base; 2211beb6a7d6cbed3ac03500ce9b5b9bb632c512039Benjamin Herrenschmidt u8 __iomem *applebase; 222c4b22f268914ff824a6334b62afd23f7ad79df11Segher Boessenkool u32 data; 2231beb6a7d6cbed3ac03500ce9b5b9bb632c512039Benjamin Herrenschmidt unsigned int index; 22414cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras}; 2256cfef5b27e49e826125f12637ee0d7210a896044Michael Ellerman#endif /* CONFIG_MPIC_U3_HT_IRQS */ 22614cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 22714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 228fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidtenum mpic_reg_type { 229fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt mpic_access_mmio_le, 230fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt mpic_access_mmio_be, 231fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt#ifdef CONFIG_PPC_DCR 232fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt mpic_access_dcr 233fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt#endif 234fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt}; 235fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt 236fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidtstruct mpic_reg_bank { 237fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt u32 __iomem *base; 238fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt#ifdef CONFIG_PPC_DCR 239fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt dcr_host_t dhost; 240fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt#endif /* CONFIG_PPC_DCR */ 241fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt}; 242fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt 2433669e930481d6dd510718279cd4bacb15ca3ae91Johannes Bergstruct mpic_irq_save { 2443669e930481d6dd510718279cd4bacb15ca3ae91Johannes Berg u32 vecprio, 2453669e930481d6dd510718279cd4bacb15ca3ae91Johannes Berg dest; 2463669e930481d6dd510718279cd4bacb15ca3ae91Johannes Berg#ifdef CONFIG_MPIC_U3_HT_IRQS 2473669e930481d6dd510718279cd4bacb15ca3ae91Johannes Berg u32 fixup_data; 2483669e930481d6dd510718279cd4bacb15ca3ae91Johannes Berg#endif 2493669e930481d6dd510718279cd4bacb15ca3ae91Johannes Berg}; 2503669e930481d6dd510718279cd4bacb15ca3ae91Johannes Berg 25114cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras/* The instance data of a given MPIC */ 25214cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerrasstruct mpic 25314cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras{ 254c51242e7080d2265761de309cdea222d7e27bdfeKyle Moffett /* The OpenFirmware dt node for this MPIC */ 255c51242e7080d2265761de309cdea222d7e27bdfeKyle Moffett struct device_node *node; 256c51242e7080d2265761de309cdea222d7e27bdfeKyle Moffett 2570ebfff1491ef85d41ddf9c633834838be144f69fBenjamin Herrenschmidt /* The remapper for this MPIC */ 258bae1d8f19983fbfa25559aa3cb6a81a84aa82a18Grant Likely struct irq_domain *irqhost; 2590ebfff1491ef85d41ddf9c633834838be144f69fBenjamin Herrenschmidt 26014cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras /* The "linux" controller struct */ 261b9e5b4e6a991a5a6d521f2e20a65835404b4169fBenjamin Herrenschmidt struct irq_chip hc_irq; 2626cfef5b27e49e826125f12637ee0d7210a896044Michael Ellerman#ifdef CONFIG_MPIC_U3_HT_IRQS 263b9e5b4e6a991a5a6d521f2e20a65835404b4169fBenjamin Herrenschmidt struct irq_chip hc_ht_irq; 264b9e5b4e6a991a5a6d521f2e20a65835404b4169fBenjamin Herrenschmidt#endif 26514cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#ifdef CONFIG_SMP 266b9e5b4e6a991a5a6d521f2e20a65835404b4169fBenjamin Herrenschmidt struct irq_chip hc_ipi; 26714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#endif 268ea94187face757e723aa461a60698ca43c09fbb9Scott Wood struct irq_chip hc_tm; 26914cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras const char *name; 27014cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras /* Flags */ 27114cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras unsigned int flags; 27214cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras /* How many irq sources in a given ISU */ 27314cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras unsigned int isu_size; 27414cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras unsigned int isu_shift; 27514cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras unsigned int isu_mask; 27614cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras /* Number of sources */ 27714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras unsigned int num_sources; 27814cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 2797df2457db83bc922fcc8b462526b77f1ffe8c84bOlof Johansson /* vector numbers used for internal sources (ipi/timers) */ 2807df2457db83bc922fcc8b462526b77f1ffe8c84bOlof Johansson unsigned int ipi_vecs[4]; 281ea94187face757e723aa461a60698ca43c09fbb9Scott Wood unsigned int timer_vecs[8]; 2827df2457db83bc922fcc8b462526b77f1ffe8c84bOlof Johansson 2837df2457db83bc922fcc8b462526b77f1ffe8c84bOlof Johansson /* Spurious vector to program into unused sources */ 2847df2457db83bc922fcc8b462526b77f1ffe8c84bOlof Johansson unsigned int spurious_vec; 2857df2457db83bc922fcc8b462526b77f1ffe8c84bOlof Johansson 2866cfef5b27e49e826125f12637ee0d7210a896044Michael Ellerman#ifdef CONFIG_MPIC_U3_HT_IRQS 28714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras /* The fixup table */ 28814cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras struct mpic_irq_fixup *fixups; 289203041ad1f66d2afb893c2adb9c11bfd13209d06Thomas Gleixner raw_spinlock_t fixup_lock; 29014cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#endif 29114cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 292fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt /* Register access method */ 293fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt enum mpic_reg_type reg_type; 294fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt 295e7a98675caf272a11dc1012c7a8c6c00cab09f5bKyle Moffett /* The physical base address of the MPIC */ 296e7a98675caf272a11dc1012c7a8c6c00cab09f5bKyle Moffett phys_addr_t paddr; 297e7a98675caf272a11dc1012c7a8c6c00cab09f5bKyle Moffett 29814cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras /* The various ioremap'ed bases */ 299fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt struct mpic_reg_bank gregs; 300fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt struct mpic_reg_bank tmregs; 301fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS]; 302fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt struct mpic_reg_bank isus[MPIC_MAX_ISU]; 303fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt 3047fd7218610600b16f6f0af3f9d9353ba0265c09fBenjamin Herrenschmidt /* Protected sources */ 3057fd7218610600b16f6f0af3f9d9353ba0265c09fBenjamin Herrenschmidt unsigned long *protected; 3067fd7218610600b16f6f0af3f9d9353ba0265c09fBenjamin Herrenschmidt 3077233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#ifdef CONFIG_MPIC_WEIRD 3087233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r /* Pointer to HW info array */ 3097233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r u32 *hw_set; 3107233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#endif 3117233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r 312a7de7c74227edda719b257eb15aecd73790ff894Michael Ellerman#ifdef CONFIG_PCI_MSI 31325235f712b680d00756a73ee64289137989fc6fdMichael Ellerman struct msi_bitmap msi_bitmap; 314a7de7c74227edda719b257eb15aecd73790ff894Michael Ellerman#endif 315a7de7c74227edda719b257eb15aecd73790ff894Michael Ellerman 3160d72ba930cbc9140a584af7e4e65041b6c7a7d18Olof Johansson#ifdef CONFIG_MPIC_BROKEN_REGREAD 3170d72ba930cbc9140a584af7e4e65041b6c7a7d18Olof Johansson u32 isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES]; 3180d72ba930cbc9140a584af7e4e65041b6c7a7d18Olof Johansson#endif 3190d72ba930cbc9140a584af7e4e65041b6c7a7d18Olof Johansson 32014cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras /* link */ 32114cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras struct mpic *next; 3223669e930481d6dd510718279cd4bacb15ca3ae91Johannes Berg 3233669e930481d6dd510718279cd4bacb15ca3ae91Johannes Berg#ifdef CONFIG_PM 3243669e930481d6dd510718279cd4bacb15ca3ae91Johannes Berg struct mpic_irq_save *save_data; 3253669e930481d6dd510718279cd4bacb15ca3ae91Johannes Berg#endif 32614cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras}; 32714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 3287233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r/* 3297233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r * MPIC flags (passed to mpic_alloc) 3307233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r * 3317233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r * The top 4 bits contain an MPIC bhw id that is used to index the 3327233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r * register offsets and some masks when CONFIG_MPIC_WEIRD is set. 3337233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r * Note setting any ID (leaving those bits to 0) means standard MPIC 3347233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r */ 3357233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r 336be8bec56dfac0574c4c08a50cd37e09bea941e3fKyle Moffett/* 337be8bec56dfac0574c4c08a50cd37e09bea941e3fKyle Moffett * This is a secondary ("chained") controller; it only uses the CPU0 338be8bec56dfac0574c4c08a50cd37e09bea941e3fKyle Moffett * registers. Primary controllers have IPIs and affinity control. 33914cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras */ 340be8bec56dfac0574c4c08a50cd37e09bea941e3fKyle Moffett#define MPIC_SECONDARY 0x00000001 3417233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r 34214cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras/* Set this for a big-endian MPIC */ 34314cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_BIG_ENDIAN 0x00000002 34414cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras/* Broken U3 MPIC */ 3456cfef5b27e49e826125f12637ee0d7210a896044Michael Ellerman#define MPIC_U3_HT_IRQS 0x00000004 34614cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras/* Broken IPI registers (autodetected) */ 34714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras#define MPIC_BROKEN_IPI 0x00000008 3487233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r/* Spurious vector requires EOI */ 3497233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define MPIC_SPV_EOI 0x00000020 3507233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r/* No passthrough disable */ 3517233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define MPIC_NO_PTHROU_DIS 0x00000040 352fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt/* DCR based MPIC */ 353fbf0274e43b7e17ee740fee2d693932be093d56dBenjamin Herrenschmidt#define MPIC_USES_DCR 0x00000080 3547df2457db83bc922fcc8b462526b77f1ffe8c84bOlof Johansson/* MPIC has 11-bit vector fields (or larger) */ 3557df2457db83bc922fcc8b462526b77f1ffe8c84bOlof Johansson#define MPIC_LARGE_VECTORS 0x00000100 356f365355e65ee619e3b7baeca69b46fd2c4a5ec68Olof Johansson/* Enable delivery of prio 15 interrupts as MCK instead of EE */ 357f365355e65ee619e3b7baeca69b46fd2c4a5ec68Olof Johansson#define MPIC_ENABLE_MCK 0x00000200 358d87bf3bed71375b141e95b5fdbac413ac4b65184Olof Johansson/* Disable bias among target selection, spread interrupts evenly */ 359d87bf3bed71375b141e95b5fdbac413ac4b65184Olof Johansson#define MPIC_NO_BIAS 0x00000400 3603c10c9c45e290022ca7d2aa1ad33a0b6ed767520Kumar Gala/* Destination only supports a single CPU at a time */ 3613c10c9c45e290022ca7d2aa1ad33a0b6ed767520Kumar Gala#define MPIC_SINGLE_DEST_CPU 0x00001000 362d91e4ea7047d96733d763f1626f1f21ff4298cefKumar Gala/* Enable CoreInt delivery of interrupts */ 363d91e4ea7047d96733d763f1626f1f21ff4298cefKumar Gala#define MPIC_ENABLE_COREINT 0x00002000 364e55d7f737d3daf4aaf41945c1829138c608662e9Kyle Moffett/* Do not reset the MPIC during initialization */ 365dfec2202729e2460d67649a04756f0c3d8dcd8a6Meador Inge#define MPIC_NO_RESET 0x00004000 36622d168ce60272ca112e86e58c5ebde82f20f9c83Scott Wood/* Freescale MPIC (compatible includes "fsl,mpic") */ 36722d168ce60272ca112e86e58c5ebde82f20f9c83Scott Wood#define MPIC_FSL 0x00008000 3687233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r 3697233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r/* MPIC HW modification ID */ 3707233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define MPIC_REGSET_MASK 0xf0000000 3717233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define MPIC_REGSET(val) (((val) & 0xf ) << 28) 3727233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define MPIC_GET_REGSET(flags) (((flags) >> 28) & 0xf) 3737233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r 3747233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */ 3757233593b7844c2db930594ee9c0c872a6900bfccZang Roy-r#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */ 37614cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 37714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras/* Allocate the controller structure and setup the linux irq descs 37814cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * for the range if interrupts passed in. No HW initialization is 37914cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * actually performed. 38014cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * 38114cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * @phys_addr: physial base address of the MPIC 38214cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * @flags: flags, see constants above 38314cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * @isu_size: number of interrupts in an ISU. Use 0 to use a 38414cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * standard ISU-less setup (aka powermac) 38514cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * @irq_offset: first irq number to assign to this mpic 38614cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0 38714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * to match the number of sources 38814cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * @ipi_offset: first irq number to assign to this mpic IPI sources, 38914cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * used only on primary mpic 39014cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * @senses: array of sense values 39114cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * @senses_num: number of entries in the array 39214cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * 39314cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * Note about the sense array. If none is passed, all interrupts are 3946cfef5b27e49e826125f12637ee0d7210a896044Michael Ellerman * setup to be level negative unless MPIC_U3_HT_IRQS is set in which 39514cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * case they are edge positive (and the array is ignored anyway). 39614cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * The values in the array start at the first source of the MPIC, 39714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * that is senses[0] correspond to linux irq "irq_offset". 39814cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras */ 3990ebfff1491ef85d41ddf9c633834838be144f69fBenjamin Herrenschmidtextern struct mpic *mpic_alloc(struct device_node *node, 400a959ff56bbf07954ea4fa1cf72f99a38795eadb3Benjamin Herrenschmidt phys_addr_t phys_addr, 40114cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras unsigned int flags, 40214cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras unsigned int isu_size, 40314cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras unsigned int irq_count, 40414cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras const char *name); 40514cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 40614cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras/* Assign ISUs, to call before mpic_init() 40714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * 40814cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * @mpic: controller structure as returned by mpic_alloc() 40914cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * @isu_num: ISU number 41014cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * @phys_addr: physical address of the ISU 41114cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras */ 41214cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerrasextern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, 413a959ff56bbf07954ea4fa1cf72f99a38795eadb3Benjamin Herrenschmidt phys_addr_t phys_addr); 41414cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 4150ebfff1491ef85d41ddf9c633834838be144f69fBenjamin Herrenschmidt 41614cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras/* Initialize the controller. After this has been called, none of the above 41714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * should be called again for this mpic 41814cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras */ 41914cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerrasextern void mpic_init(struct mpic *mpic); 42014cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 42114cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras/* 42214cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * All of the following functions must only be used after the 42314cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * ISUs have been assigned and the controller fully initialized 42414cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * with mpic_init() 42514cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras */ 42614cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 42714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 42806a901c5621f85e07e00ac4816c7ca95620ee74aStephen Rothwell/* Change the priority of an interrupt. Default is 8 for irqs and 42914cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the 43014cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras * IPI number is then the offset'ed (linux irq number mapped to the IPI) 43114cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras */ 43214cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerrasextern void mpic_irq_set_priority(unsigned int irq, unsigned int pri); 43314cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 43414cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras/* Setup a non-boot CPU */ 43514cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerrasextern void mpic_setup_this_cpu(void); 43614cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 43714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras/* Clean up for kexec (or cpu offline or ...) */ 43814cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerrasextern void mpic_teardown_this_cpu(int secondary); 43914cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 44014cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras/* Get the current cpu priority for this cpu (0..15) */ 44114cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerrasextern int mpic_cpu_get_priority(void); 44214cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 44314cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras/* Set the current cpu priority for this cpu */ 44414cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerrasextern void mpic_cpu_set_priority(int prio); 44514cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 44614cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras/* Request IPIs on primary mpic */ 44714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerrasextern void mpic_request_ipis(void); 44814cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 449a9c59264690aea9d0df2d2d76683bc39ec6b7288Paul Mackerras/* Send a message (IPI) to a given target (cpu number or MSG_*) */ 450a9c59264690aea9d0df2d2d76683bc39ec6b7288Paul Mackerrasvoid smp_mpic_message_pass(int target, int msg); 451a9c59264690aea9d0df2d2d76683bc39ec6b7288Paul Mackerras 452f365355e65ee619e3b7baeca69b46fd2c4a5ec68Olof Johansson/* Unmask a specific virq */ 453835c0553eb151588b6a1b52b28ecbbd59f7ff052Lennert Buytenhekextern void mpic_unmask_irq(struct irq_data *d); 454f365355e65ee619e3b7baeca69b46fd2c4a5ec68Olof Johansson/* Mask a specific virq */ 455835c0553eb151588b6a1b52b28ecbbd59f7ff052Lennert Buytenhekextern void mpic_mask_irq(struct irq_data *d); 456f365355e65ee619e3b7baeca69b46fd2c4a5ec68Olof Johansson/* EOI a specific virq */ 457835c0553eb151588b6a1b52b28ecbbd59f7ff052Lennert Buytenhekextern void mpic_end_irq(struct irq_data *d); 458f365355e65ee619e3b7baeca69b46fd2c4a5ec68Olof Johansson 45914cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras/* Fetch interrupt from a given mpic */ 46035a84c2f56e0f77ea2c5a4327b17104705f4c8c7Olaf Heringextern unsigned int mpic_get_one_irq(struct mpic *mpic); 461f365355e65ee619e3b7baeca69b46fd2c4a5ec68Olof Johansson/* This one gets from the primary mpic */ 46235a84c2f56e0f77ea2c5a4327b17104705f4c8c7Olaf Heringextern unsigned int mpic_get_irq(void); 463d91e4ea7047d96733d763f1626f1f21ff4298cefKumar Gala/* This one gets from the primary mpic via CoreInt*/ 464d91e4ea7047d96733d763f1626f1f21ff4298cefKumar Galaextern unsigned int mpic_get_coreint_irq(void); 465f365355e65ee619e3b7baeca69b46fd2c4a5ec68Olof Johansson/* Fetch Machine Check interrupt from primary mpic */ 466f365355e65ee619e3b7baeca69b46fd2c4a5ec68Olof Johanssonextern unsigned int mpic_get_mcirq(void); 46714cf11af6cf608eb8c23e989ddb17a715ddce109Paul Mackerras 468868ea0c9256b658b14603e1ad7361b81b92ccacdMark A. Greer/* Set the EPIC clock ratio */ 469868ea0c9256b658b14603e1ad7361b81b92ccacdMark A. Greervoid mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio); 470868ea0c9256b658b14603e1ad7361b81b92ccacdMark A. Greer 471868ea0c9256b658b14603e1ad7361b81b92ccacdMark A. Greer/* Enable/Disable EPIC serial interrupt mode */ 472868ea0c9256b658b14603e1ad7361b81b92ccacdMark A. Greervoid mpic_set_serial_int(struct mpic *mpic, int enable); 473868ea0c9256b658b14603e1ad7361b81b92ccacdMark A. Greer 47488ced0314938814e1772b4d0d7ab20c52e4472b6Arnd Bergmann#endif /* __KERNEL__ */ 475bbeb3f4c55f666df7bcd2655b303dfb8c4d1a119Stephen Rothwell#endif /* _ASM_POWERPC_MPIC_H */ 476