1/* 2 * Contains register definitions common to the Book E PowerPC 3 * specification. Notice that while the IBM-40x series of CPUs 4 * are not true Book E PowerPCs, they borrowed a number of features 5 * before Book E was finalized, and are included here as well. Unfortunately, 6 * they sometimes used different locations than true Book E CPUs did. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License version 2 10 * as published by the Free Software Foundation. 11 * 12 * Copyright 2009-2010 Freescale Semiconductor, Inc. 13 */ 14#ifdef __KERNEL__ 15#ifndef __ASM_POWERPC_REG_BOOKE_H__ 16#define __ASM_POWERPC_REG_BOOKE_H__ 17 18/* Machine State Register (MSR) Fields */ 19#define MSR_GS (1<<28) /* Guest state */ 20#define MSR_UCLE (1<<26) /* User-mode cache lock enable */ 21#define MSR_SPE (1<<25) /* Enable SPE */ 22#define MSR_DWE (1<<10) /* Debug Wait Enable */ 23#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ 24#define MSR_IS MSR_IR /* Instruction Space */ 25#define MSR_DS MSR_DR /* Data Space */ 26#define MSR_PMM (1<<2) /* Performance monitor mark bit */ 27#define MSR_CM (1<<31) /* Computation Mode (0=32-bit, 1=64-bit) */ 28 29#if defined(CONFIG_PPC_BOOK3E_64) 30#define MSR_64BIT MSR_CM 31 32#define MSR_ MSR_ME | MSR_CE 33#define MSR_KERNEL MSR_ | MSR_64BIT 34#define MSR_USER32 MSR_ | MSR_PR | MSR_EE 35#define MSR_USER64 MSR_USER32 | MSR_64BIT 36#elif defined (CONFIG_40x) 37#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE) 38#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) 39#else 40#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE) 41#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) 42#endif 43 44/* Special Purpose Registers (SPRNs)*/ 45#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ 46#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ 47#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ 48#define SPRN_SPRG3R 0x103 /* Special Purpose Register General 3 Read */ 49#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ 50#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ 51#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ 52#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ 53#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ 54#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ 55#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ 56#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ 57#define SPRN_EPCR 0x133 /* Embedded Processor Control Register */ 58#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ 59#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ 60#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ 61#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ 62#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ 63#define SPRN_MAS8 0x155 /* MMU Assist Register 8 */ 64#define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */ 65#define SPRN_TLB1PS 0x159 /* TLB 1 Page Size Register */ 66#define SPRN_MAS5_MAS6 0x15c /* MMU Assist Register 5 || 6 */ 67#define SPRN_MAS8_MAS1 0x15d /* MMU Assist Register 8 || 1 */ 68#define SPRN_EPTCFG 0x15e /* Embedded Page Table Config */ 69#define SPRN_MAS7_MAS3 0x174 /* MMU Assist Register 7 || 3 */ 70#define SPRN_MAS0_MAS1 0x175 /* MMU Assist Register 0 || 1 */ 71#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ 72#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ 73#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ 74#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ 75#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ 76#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ 77#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ 78#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ 79#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ 80#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ 81#define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */ 82#define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */ 83#define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */ 84#define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */ 85#define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */ 86#define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */ 87#define SPRN_IVOR38 0x1B0 /* Interrupt Vector Offset Register 38 */ 88#define SPRN_IVOR39 0x1B1 /* Interrupt Vector Offset Register 39 */ 89#define SPRN_IVOR40 0x1B2 /* Interrupt Vector Offset Register 40 */ 90#define SPRN_IVOR41 0x1B3 /* Interrupt Vector Offset Register 41 */ 91#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ 92#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ 93#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ 94#define SPRN_L1CFG0 0x203 /* L1 Cache Configure Register 0 */ 95#define SPRN_L1CFG1 0x204 /* L1 Cache Configure Register 1 */ 96#define SPRN_ATB 0x20E /* Alternate Time Base */ 97#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */ 98#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */ 99#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ 100#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ 101#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ 102#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ 103#define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */ 104#define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */ 105#define SPRN_MCARU 0x239 /* Machine Check Address Register Upper */ 106#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */ 107#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ 108#define SPRN_MCSR 0x23C /* Machine Check Status Register */ 109#define SPRN_MCAR 0x23D /* Machine Check Address Register */ 110#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */ 111#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */ 112#define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */ 113#define SPRN_SPRG9 0x25D /* Special Purpose Register General 9 */ 114#define SPRN_L1CSR2 0x25E /* L1 Cache Control and Status Register 2 */ 115#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ 116#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ 117#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ 118#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ 119#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ 120#define SPRN_MAS5 0x153 /* MMU Assist Register 5 */ 121#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ 122#define SPRN_PID1 0x279 /* Process ID Register 1 */ 123#define SPRN_PID2 0x27A /* Process ID Register 2 */ 124#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ 125#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ 126#define SPRN_TLB2CFG 0x2B2 /* TLB 2 Config Register */ 127#define SPRN_TLB3CFG 0x2B3 /* TLB 3 Config Register */ 128#define SPRN_EPR 0x2BE /* External Proxy Register */ 129#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */ 130#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */ 131#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ 132#define SPRN_MMUCR 0x3B2 /* MMU Control Register */ 133#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ 134#define SPRN_EPLC 0x3B3 /* External Process ID Load Context */ 135#define SPRN_EPSC 0x3B4 /* External Process ID Store Context */ 136#define SPRN_SGR 0x3B9 /* Storage Guarded Register */ 137#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ 138#define SPRN_SLER 0x3BB /* Little-endian real mode */ 139#define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */ 140#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ 141#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ 142#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ 143#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ 144#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ 145#define SPRN_MMUCSR0 0x3F4 /* MMU Control and Status Register 0 */ 146#define SPRN_MMUCFG 0x3F7 /* MMU Configuration Register */ 147#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ 148#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */ 149#define SPRN_L2CSR0 0x3F9 /* L2 Data Cache Control and Status Register 0 */ 150#define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */ 151#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ 152#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ 153#define SPRN_SVR 0x3FF /* System Version Register */ 154 155/* 156 * SPRs which have conflicting definitions on true Book E versus classic, 157 * or IBM 40x. 158 */ 159#ifdef CONFIG_BOOKE 160#define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */ 161#define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */ 162#define SPRN_DEAR 0x03D /* Data Error Address Register */ 163#define SPRN_ESR 0x03E /* Exception Syndrome Register */ 164#define SPRN_PIR 0x11E /* Processor Identification Register */ 165#define SPRN_DBSR 0x130 /* Debug Status Register */ 166#define SPRN_DBCR0 0x134 /* Debug Control Register 0 */ 167#define SPRN_DBCR1 0x135 /* Debug Control Register 1 */ 168#define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */ 169#define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */ 170#define SPRN_DAC1 0x13C /* Data Address Compare 1 */ 171#define SPRN_DAC2 0x13D /* Data Address Compare 2 */ 172#define SPRN_TSR 0x150 /* Timer Status Register */ 173#define SPRN_TCR 0x154 /* Timer Control Register */ 174#endif /* Book E */ 175#ifdef CONFIG_40x 176#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ 177#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ 178#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ 179#define SPRN_TSR 0x3D8 /* Timer Status Register */ 180#define SPRN_TCR 0x3DA /* Timer Control Register */ 181#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ 182#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ 183#define SPRN_DBSR 0x3F0 /* Debug Status Register */ 184#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ 185#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ 186#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ 187#define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */ 188#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */ 189#endif 190 191#ifdef CONFIG_PPC_ICSWX 192#define SPRN_HACOP 0x15F /* Hypervisor Available Coprocessor Register */ 193#endif 194 195/* Bit definitions for CCR1. */ 196#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ 197#define CCR1_TCS 0x00000080 /* Timer Clock Select */ 198 199/* Bit definitions for the MCSR. */ 200#define MCSR_MCS 0x80000000 /* Machine Check Summary */ 201#define MCSR_IB 0x40000000 /* Instruction PLB Error */ 202#define MCSR_DRB 0x20000000 /* Data Read PLB Error */ 203#define MCSR_DWB 0x10000000 /* Data Write PLB Error */ 204#define MCSR_TLBP 0x08000000 /* TLB Parity Error */ 205#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ 206#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ 207#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ 208#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ 209 210#define PPC47x_MCSR_GPR 0x01000000 /* GPR parity error */ 211#define PPC47x_MCSR_FPR 0x00800000 /* FPR parity error */ 212#define PPC47x_MCSR_IPR 0x00400000 /* Imprecise Machine Check Exception */ 213 214#ifdef CONFIG_E500 215/* All e500 */ 216#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ 217#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */ 218 219/* e500v1/v2 */ 220#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */ 221#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */ 222#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */ 223#define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */ 224#define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */ 225#define MCSR_BUS_IBERR 0x00000010UL /* Instruction Data Error */ 226#define MCSR_BUS_RBERR 0x00000008UL /* Read Data Bus Error */ 227#define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */ 228#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */ 229#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */ 230 231/* e500mc */ 232#define MCSR_DCPERR_MC 0x20000000UL /* D-Cache Parity Error */ 233#define MCSR_L2MMU_MHIT 0x04000000UL /* Hit on multiple TLB entries */ 234#define MCSR_NMI 0x00100000UL /* Non-Maskable Interrupt */ 235#define MCSR_MAV 0x00080000UL /* MCAR address valid */ 236#define MCSR_MEA 0x00040000UL /* MCAR is effective address */ 237#define MCSR_IF 0x00010000UL /* Instruction Fetch */ 238#define MCSR_LD 0x00008000UL /* Load */ 239#define MCSR_ST 0x00004000UL /* Store */ 240#define MCSR_LDG 0x00002000UL /* Guarded Load */ 241#define MCSR_TLBSYNC 0x00000002UL /* Multiple tlbsyncs detected */ 242#define MCSR_BSL2_ERR 0x00000001UL /* Backside L2 cache error */ 243#endif 244 245#ifdef CONFIG_E200 246#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ 247#define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */ 248#define MCSR_CPERR 0x10000000UL /* Cache Parity Error */ 249#define MCSR_EXCP_ERR 0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn 250 fetch for an exception handler */ 251#define MCSR_BUS_IRERR 0x00000010UL /* Read Bus Error on instruction fetch*/ 252#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */ 253#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered 254 store or cache line push */ 255#endif 256 257/* Bit definitions for the HID1 */ 258#ifdef CONFIG_E500 259/* e500v1/v2 */ 260#define HID1_PLL_CFG_MASK 0xfc000000 /* PLL_CFG input pins */ 261#define HID1_RFXE 0x00020000 /* Read fault exception enable */ 262#define HID1_R1DPE 0x00008000 /* R1 data bus parity enable */ 263#define HID1_R2DPE 0x00004000 /* R2 data bus parity enable */ 264#define HID1_ASTME 0x00002000 /* Address bus streaming mode enable */ 265#define HID1_ABE 0x00001000 /* Address broadcast enable */ 266#define HID1_MPXTT 0x00000400 /* MPX re-map transfer type */ 267#define HID1_ATS 0x00000080 /* Atomic status */ 268#define HID1_MID_MASK 0x0000000f /* MID input pins */ 269#endif 270 271/* Bit definitions for the DBSR. */ 272/* 273 * DBSR bits which have conflicting definitions on true Book E versus IBM 40x. 274 */ 275#ifdef CONFIG_BOOKE 276#define DBSR_IC 0x08000000 /* Instruction Completion */ 277#define DBSR_BT 0x04000000 /* Branch Taken */ 278#define DBSR_IRPT 0x02000000 /* Exception Debug Event */ 279#define DBSR_TIE 0x01000000 /* Trap Instruction Event */ 280#define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */ 281#define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */ 282#define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */ 283#define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */ 284#define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */ 285#define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */ 286#define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */ 287#define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */ 288#define DBSR_RET 0x00008000 /* Return Debug Event */ 289#define DBSR_CIRPT 0x00000040 /* Critical Interrupt Taken Event */ 290#define DBSR_CRET 0x00000020 /* Critical Return Debug Event */ 291#define DBSR_IAC12ATS 0x00000002 /* Instr Address Compare 1/2 Toggle */ 292#define DBSR_IAC34ATS 0x00000001 /* Instr Address Compare 3/4 Toggle */ 293#endif 294#ifdef CONFIG_40x 295#define DBSR_IC 0x80000000 /* Instruction Completion */ 296#define DBSR_BT 0x40000000 /* Branch taken */ 297#define DBSR_IRPT 0x20000000 /* Exception Debug Event */ 298#define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */ 299#define DBSR_IAC1 0x04000000 /* Instruction Address Compare 1 Event */ 300#define DBSR_IAC2 0x02000000 /* Instruction Address Compare 2 Event */ 301#define DBSR_IAC3 0x00080000 /* Instruction Address Compare 3 Event */ 302#define DBSR_IAC4 0x00040000 /* Instruction Address Compare 4 Event */ 303#define DBSR_DAC1R 0x01000000 /* Data Address Compare 1 Read Event */ 304#define DBSR_DAC1W 0x00800000 /* Data Address Compare 1 Write Event */ 305#define DBSR_DAC2R 0x00400000 /* Data Address Compare 2 Read Event */ 306#define DBSR_DAC2W 0x00200000 /* Data Address Compare 2 Write Event */ 307#endif 308 309/* Bit definitions related to the ESR. */ 310#define ESR_MCI 0x80000000 /* Machine Check - Instruction */ 311#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ 312#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ 313#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ 314#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ 315#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ 316#define ESR_PPR 0x04000000 /* Program Exception - Privileged */ 317#define ESR_PTR 0x02000000 /* Program Exception - Trap */ 318#define ESR_FP 0x01000000 /* Floating Point Operation */ 319#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ 320#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ 321#define ESR_ST 0x00800000 /* Store Operation */ 322#define ESR_DLK 0x00200000 /* Data Cache Locking */ 323#define ESR_ILK 0x00100000 /* Instr. Cache Locking */ 324#define ESR_PUO 0x00040000 /* Unimplemented Operation exception */ 325#define ESR_BO 0x00020000 /* Byte Ordering */ 326#define ESR_SPV 0x00000080 /* Signal Processing operation */ 327 328/* Bit definitions related to the DBCR0. */ 329#if defined(CONFIG_40x) 330#define DBCR0_EDM 0x80000000 /* External Debug Mode */ 331#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ 332#define DBCR0_RST 0x30000000 /* all the bits in the RST field */ 333#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */ 334#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */ 335#define DBCR0_RST_CORE 0x10000000 /* Core Reset */ 336#define DBCR0_RST_NONE 0x00000000 /* No Reset */ 337#define DBCR0_IC 0x08000000 /* Instruction Completion */ 338#define DBCR0_ICMP DBCR0_IC 339#define DBCR0_BT 0x04000000 /* Branch Taken */ 340#define DBCR0_BRT DBCR0_BT 341#define DBCR0_EDE 0x02000000 /* Exception Debug Event */ 342#define DBCR0_IRPT DBCR0_EDE 343#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */ 344#define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */ 345#define DBCR0_IAC1 DBCR0_IA1 346#define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */ 347#define DBCR0_IAC2 DBCR0_IA2 348#define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */ 349#define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */ 350#define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */ 351#define DBCR0_IAC3 DBCR0_IA3 352#define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */ 353#define DBCR0_IAC4 DBCR0_IA4 354#define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */ 355#define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */ 356#define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */ 357#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */ 358#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ 359 360#define dbcr_iac_range(task) ((task)->thread.dbcr0) 361#define DBCR_IAC12I DBCR0_IA12 /* Range Inclusive */ 362#define DBCR_IAC12X (DBCR0_IA12 | DBCR0_IA12X) /* Range Exclusive */ 363#define DBCR_IAC12MODE (DBCR0_IA12 | DBCR0_IA12X) /* IAC 1-2 Mode Bits */ 364#define DBCR_IAC34I DBCR0_IA34 /* Range Inclusive */ 365#define DBCR_IAC34X (DBCR0_IA34 | DBCR0_IA34X) /* Range Exclusive */ 366#define DBCR_IAC34MODE (DBCR0_IA34 | DBCR0_IA34X) /* IAC 3-4 Mode Bits */ 367 368/* Bit definitions related to the DBCR1. */ 369#define DBCR1_DAC1R 0x80000000 /* DAC1 Read Debug Event */ 370#define DBCR1_DAC2R 0x40000000 /* DAC2 Read Debug Event */ 371#define DBCR1_DAC1W 0x20000000 /* DAC1 Write Debug Event */ 372#define DBCR1_DAC2W 0x10000000 /* DAC2 Write Debug Event */ 373 374#define dbcr_dac(task) ((task)->thread.dbcr1) 375#define DBCR_DAC1R DBCR1_DAC1R 376#define DBCR_DAC1W DBCR1_DAC1W 377#define DBCR_DAC2R DBCR1_DAC2R 378#define DBCR_DAC2W DBCR1_DAC2W 379 380/* 381 * Are there any active Debug Events represented in the 382 * Debug Control Registers? 383 */ 384#define DBCR0_ACTIVE_EVENTS (DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \ 385 DBCR0_IAC3 | DBCR0_IAC4) 386#define DBCR1_ACTIVE_EVENTS (DBCR1_DAC1R | DBCR1_DAC2R | \ 387 DBCR1_DAC1W | DBCR1_DAC2W) 388#define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1) (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \ 389 ((dbcr1) & DBCR1_ACTIVE_EVENTS)) 390 391#elif defined(CONFIG_BOOKE) 392#define DBCR0_EDM 0x80000000 /* External Debug Mode */ 393#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ 394#define DBCR0_RST 0x30000000 /* all the bits in the RST field */ 395/* DBCR0_RST_* is 44x specific and not followed in fsl booke */ 396#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */ 397#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */ 398#define DBCR0_RST_CORE 0x10000000 /* Core Reset */ 399#define DBCR0_RST_NONE 0x00000000 /* No Reset */ 400#define DBCR0_ICMP 0x08000000 /* Instruction Completion */ 401#define DBCR0_IC DBCR0_ICMP 402#define DBCR0_BRT 0x04000000 /* Branch Taken */ 403#define DBCR0_BT DBCR0_BRT 404#define DBCR0_IRPT 0x02000000 /* Exception Debug Event */ 405#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */ 406#define DBCR0_TIE DBCR0_TDE 407#define DBCR0_IAC1 0x00800000 /* Instr Addr compare 1 enable */ 408#define DBCR0_IAC2 0x00400000 /* Instr Addr compare 2 enable */ 409#define DBCR0_IAC3 0x00200000 /* Instr Addr compare 3 enable */ 410#define DBCR0_IAC4 0x00100000 /* Instr Addr compare 4 enable */ 411#define DBCR0_DAC1R 0x00080000 /* DAC 1 Read enable */ 412#define DBCR0_DAC1W 0x00040000 /* DAC 1 Write enable */ 413#define DBCR0_DAC2R 0x00020000 /* DAC 2 Read enable */ 414#define DBCR0_DAC2W 0x00010000 /* DAC 2 Write enable */ 415#define DBCR0_RET 0x00008000 /* Return Debug Event */ 416#define DBCR0_CIRPT 0x00000040 /* Critical Interrupt Taken Event */ 417#define DBCR0_CRET 0x00000020 /* Critical Return Debug Event */ 418#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ 419 420#define dbcr_dac(task) ((task)->thread.dbcr0) 421#define DBCR_DAC1R DBCR0_DAC1R 422#define DBCR_DAC1W DBCR0_DAC1W 423#define DBCR_DAC2R DBCR0_DAC2R 424#define DBCR_DAC2W DBCR0_DAC2W 425 426/* Bit definitions related to the DBCR1. */ 427#define DBCR1_IAC1US 0xC0000000 /* Instr Addr Cmp 1 Sup/User */ 428#define DBCR1_IAC1ER 0x30000000 /* Instr Addr Cmp 1 Eff/Real */ 429#define DBCR1_IAC1ER_01 0x10000000 /* reserved */ 430#define DBCR1_IAC1ER_10 0x20000000 /* Instr Addr Cmp 1 Eff/Real MSR[IS]=0 */ 431#define DBCR1_IAC1ER_11 0x30000000 /* Instr Addr Cmp 1 Eff/Real MSR[IS]=1 */ 432#define DBCR1_IAC2US 0x0C000000 /* Instr Addr Cmp 2 Sup/User */ 433#define DBCR1_IAC2ER 0x03000000 /* Instr Addr Cmp 2 Eff/Real */ 434#define DBCR1_IAC2ER_01 0x01000000 /* reserved */ 435#define DBCR1_IAC2ER_10 0x02000000 /* Instr Addr Cmp 2 Eff/Real MSR[IS]=0 */ 436#define DBCR1_IAC2ER_11 0x03000000 /* Instr Addr Cmp 2 Eff/Real MSR[IS]=1 */ 437#define DBCR1_IAC12M 0x00800000 /* Instr Addr 1-2 range enable */ 438#define DBCR1_IAC12MX 0x00C00000 /* Instr Addr 1-2 range eXclusive */ 439#define DBCR1_IAC12AT 0x00010000 /* Instr Addr 1-2 range Toggle */ 440#define DBCR1_IAC3US 0x0000C000 /* Instr Addr Cmp 3 Sup/User */ 441#define DBCR1_IAC3ER 0x00003000 /* Instr Addr Cmp 3 Eff/Real */ 442#define DBCR1_IAC3ER_01 0x00001000 /* reserved */ 443#define DBCR1_IAC3ER_10 0x00002000 /* Instr Addr Cmp 3 Eff/Real MSR[IS]=0 */ 444#define DBCR1_IAC3ER_11 0x00003000 /* Instr Addr Cmp 3 Eff/Real MSR[IS]=1 */ 445#define DBCR1_IAC4US 0x00000C00 /* Instr Addr Cmp 4 Sup/User */ 446#define DBCR1_IAC4ER 0x00000300 /* Instr Addr Cmp 4 Eff/Real */ 447#define DBCR1_IAC4ER_01 0x00000100 /* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */ 448#define DBCR1_IAC4ER_10 0x00000200 /* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */ 449#define DBCR1_IAC4ER_11 0x00000300 /* Instr Addr Cmp 4 Eff/Real MSR[IS]=1 */ 450#define DBCR1_IAC34M 0x00000080 /* Instr Addr 3-4 range enable */ 451#define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */ 452#define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */ 453 454#define dbcr_iac_range(task) ((task)->thread.dbcr1) 455#define DBCR_IAC12I DBCR1_IAC12M /* Range Inclusive */ 456#define DBCR_IAC12X DBCR1_IAC12MX /* Range Exclusive */ 457#define DBCR_IAC12MODE DBCR1_IAC12MX /* IAC 1-2 Mode Bits */ 458#define DBCR_IAC34I DBCR1_IAC34M /* Range Inclusive */ 459#define DBCR_IAC34X DBCR1_IAC34MX /* Range Exclusive */ 460#define DBCR_IAC34MODE DBCR1_IAC34MX /* IAC 3-4 Mode Bits */ 461 462/* Bit definitions related to the DBCR2. */ 463#define DBCR2_DAC1US 0xC0000000 /* Data Addr Cmp 1 Sup/User */ 464#define DBCR2_DAC1ER 0x30000000 /* Data Addr Cmp 1 Eff/Real */ 465#define DBCR2_DAC2US 0x0C000000 /* Data Addr Cmp 2 Sup/User */ 466#define DBCR2_DAC2ER 0x03000000 /* Data Addr Cmp 2 Eff/Real */ 467#define DBCR2_DAC12M 0x00800000 /* DAC 1-2 range enable */ 468#define DBCR2_DAC12MM 0x00400000 /* DAC 1-2 Mask mode*/ 469#define DBCR2_DAC12MX 0x00C00000 /* DAC 1-2 range eXclusive */ 470#define DBCR2_DAC12MODE 0x00C00000 /* DAC 1-2 Mode Bits */ 471#define DBCR2_DAC12A 0x00200000 /* DAC 1-2 Asynchronous */ 472#define DBCR2_DVC1M 0x000C0000 /* Data Value Comp 1 Mode */ 473#define DBCR2_DVC1M_SHIFT 18 /* # of bits to shift DBCR2_DVC1M */ 474#define DBCR2_DVC2M 0x00030000 /* Data Value Comp 2 Mode */ 475#define DBCR2_DVC2M_SHIFT 16 /* # of bits to shift DBCR2_DVC2M */ 476#define DBCR2_DVC1BE 0x00000F00 /* Data Value Comp 1 Byte */ 477#define DBCR2_DVC1BE_SHIFT 8 /* # of bits to shift DBCR2_DVC1BE */ 478#define DBCR2_DVC2BE 0x0000000F /* Data Value Comp 2 Byte */ 479#define DBCR2_DVC2BE_SHIFT 0 /* # of bits to shift DBCR2_DVC2BE */ 480 481/* 482 * Are there any active Debug Events represented in the 483 * Debug Control Registers? 484 */ 485#define DBCR0_ACTIVE_EVENTS (DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \ 486 DBCR0_IAC3 | DBCR0_IAC4 | DBCR0_DAC1R | \ 487 DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W) 488#define DBCR1_ACTIVE_EVENTS 0 489 490#define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1) (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \ 491 ((dbcr1) & DBCR1_ACTIVE_EVENTS)) 492#endif /* #elif defined(CONFIG_BOOKE) */ 493 494/* Bit definitions related to the TCR. */ 495#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ 496#define TCR_WP_MASK TCR_WP(3) 497#define WP_2_17 0 /* 2^17 clocks */ 498#define WP_2_21 1 /* 2^21 clocks */ 499#define WP_2_25 2 /* 2^25 clocks */ 500#define WP_2_29 3 /* 2^29 clocks */ 501#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ 502#define TCR_WRC_MASK TCR_WRC(3) 503#define WRC_NONE 0 /* No reset will occur */ 504#define WRC_CORE 1 /* Core reset will occur */ 505#define WRC_CHIP 2 /* Chip reset will occur */ 506#define WRC_SYSTEM 3 /* System reset will occur */ 507#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ 508#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ 509#define TCR_DIE TCR_PIE /* DEC Interrupt Enable */ 510#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ 511#define TCR_FP_MASK TCR_FP(3) 512#define FP_2_9 0 /* 2^9 clocks */ 513#define FP_2_13 1 /* 2^13 clocks */ 514#define FP_2_17 2 /* 2^17 clocks */ 515#define FP_2_21 3 /* 2^21 clocks */ 516#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ 517#define TCR_ARE 0x00400000 /* Auto Reload Enable */ 518 519/* Bit definitions for the TSR. */ 520#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ 521#define TSR_WIS 0x40000000 /* WDT Interrupt Status */ 522#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ 523#define WRS_NONE 0 /* No WDT reset occurred */ 524#define WRS_CORE 1 /* WDT forced core reset */ 525#define WRS_CHIP 2 /* WDT forced chip reset */ 526#define WRS_SYSTEM 3 /* WDT forced system reset */ 527#define TSR_PIS 0x08000000 /* PIT Interrupt Status */ 528#define TSR_DIS TSR_PIS /* DEC Interrupt Status */ 529#define TSR_FIS 0x04000000 /* FIT Interrupt Status */ 530 531/* Bit definitions for the DCCR. */ 532#define DCCR_NOCACHE 0 /* Noncacheable */ 533#define DCCR_CACHE 1 /* Cacheable */ 534 535/* Bit definitions for DCWR. */ 536#define DCWR_COPY 0 /* Copy-back */ 537#define DCWR_WRITE 1 /* Write-through */ 538 539/* Bit definitions for ICCR. */ 540#define ICCR_NOCACHE 0 /* Noncacheable */ 541#define ICCR_CACHE 1 /* Cacheable */ 542 543/* Bit definitions for L1CSR0. */ 544#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ 545#define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */ 546#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ 547#define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */ 548#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ 549 550/* Bit definitions for L1CSR1. */ 551#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ 552#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ 553#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ 554#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ 555 556/* Bit definitions for L1CSR2. */ 557#define L1CSR2_DCWS 0x40000000 /* Data Cache write shadow */ 558 559/* Bit definitions for L2CSR0. */ 560#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ 561#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ 562#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */ 563#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */ 564#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */ 565#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */ 566#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */ 567#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */ 568#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */ 569#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */ 570#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */ 571#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */ 572 573/* Bit definitions for SGR. */ 574#define SGR_NORMAL 0 /* Speculative fetching allowed. */ 575#define SGR_GUARDED 1 /* Speculative fetching disallowed. */ 576 577/* Bit definitions for EPCR */ 578#define SPRN_EPCR_EXTGS 0x80000000 /* External Input interrupt 579 * directed to Guest state */ 580#define SPRN_EPCR_DTLBGS 0x40000000 /* Data TLB Error interrupt 581 * directed to guest state */ 582#define SPRN_EPCR_ITLBGS 0x20000000 /* Instr. TLB error interrupt 583 * directed to guest state */ 584#define SPRN_EPCR_DSIGS 0x10000000 /* Data Storage interrupt 585 * directed to guest state */ 586#define SPRN_EPCR_ISIGS 0x08000000 /* Instr. Storage interrupt 587 * directed to guest state */ 588#define SPRN_EPCR_DUVD 0x04000000 /* Disable Hypervisor Debug */ 589#define SPRN_EPCR_ICM 0x02000000 /* Interrupt computation mode 590 * (copied to MSR:CM on intr) */ 591#define SPRN_EPCR_GICM 0x01000000 /* Guest Interrupt Comp. mode */ 592#define SPRN_EPCR_DGTMI 0x00800000 /* Disable TLB Guest Management 593 * instructions */ 594#define SPRN_EPCR_DMIUH 0x00400000 /* Disable MAS Interrupt updates 595 * for hypervisor */ 596 597 598/* 599 * The IBM-403 is an even more odd special case, as it is much 600 * older than the IBM-405 series. We put these down here incase someone 601 * wishes to support these machines again. 602 */ 603#ifdef CONFIG_403GCX 604/* Special Purpose Registers (SPRNs)*/ 605#define SPRN_TBHU 0x3CC /* Time Base High User-mode */ 606#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ 607#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ 608#define SPRN_TBHI 0x3DC /* Time Base High */ 609#define SPRN_TBLO 0x3DD /* Time Base Low */ 610#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ 611#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ 612#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ 613#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ 614#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ 615 616 617/* Bit definitions for the DBCR. */ 618#define DBCR_EDM DBCR0_EDM 619#define DBCR_IDM DBCR0_IDM 620#define DBCR_RST(x) (((x) & 0x3) << 28) 621#define DBCR_RST_NONE 0 622#define DBCR_RST_CORE 1 623#define DBCR_RST_CHIP 2 624#define DBCR_RST_SYSTEM 3 625#define DBCR_IC DBCR0_IC /* Instruction Completion Debug Evnt */ 626#define DBCR_BT DBCR0_BT /* Branch Taken Debug Event */ 627#define DBCR_EDE DBCR0_EDE /* Exception Debug Event */ 628#define DBCR_TDE DBCR0_TDE /* TRAP Debug Event */ 629#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ 630#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ 631#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ 632#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ 633#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ 634#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ 635#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ 636#define DAC_BYTE 0 637#define DAC_HALF 1 638#define DAC_WORD 2 639#define DAC_QUAD 3 640#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ 641#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ 642#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ 643#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ 644#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ 645#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ 646#define DBCR_SIA 0x00000008 /* Second IAC Enable */ 647#define DBCR_SDA 0x00000004 /* Second DAC Enable */ 648#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ 649#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ 650#endif /* 403GCX */ 651 652/* Some 476 specific registers */ 653#define SPRN_SSPCR 830 654#define SPRN_USPCR 831 655#define SPRN_ISPCR 829 656#define SPRN_MMUBE0 820 657#define MMUBE0_IBE0_SHIFT 24 658#define MMUBE0_IBE1_SHIFT 16 659#define MMUBE0_IBE2_SHIFT 8 660#define MMUBE0_VBE0 0x00000004 661#define MMUBE0_VBE1 0x00000002 662#define MMUBE0_VBE2 0x00000001 663#define SPRN_MMUBE1 821 664#define MMUBE1_IBE3_SHIFT 24 665#define MMUBE1_IBE4_SHIFT 16 666#define MMUBE1_IBE5_SHIFT 8 667#define MMUBE1_VBE3 0x00000004 668#define MMUBE1_VBE4 0x00000002 669#define MMUBE1_VBE5 0x00000001 670 671#endif /* __ASM_POWERPC_REG_BOOKE_H__ */ 672#endif /* __KERNEL__ */ 673