15713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt/* 25713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt * Low-Level PCI Express Support for the SH7786 35713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt * 41da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt * Copyright (C) 2009 - 2011 Paul Mundt 55713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt * 65713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt * This file is subject to the terms and conditions of the GNU General Public 75713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt * License. See the file "COPYING" in the main directory of this archive 85713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt * for more details. 95713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt */ 101da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt#define pr_fmt(fmt) "PCI: " fmt 111da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt 125713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt#include <linux/pci.h> 135713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt#include <linux/init.h> 145713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt#include <linux/kernel.h> 155713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt#include <linux/io.h> 161da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt#include <linux/async.h> 175713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt#include <linux/delay.h> 185a0e3ad6af8660be21ca98a971cd00f331318c05Tejun Heo#include <linux/slab.h> 19c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt#include <linux/clk.h> 20c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt#include <linux/sh_clk.h> 215713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt#include "pcie-sh7786.h" 225713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt#include <asm/sizes.h> 235713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 245713e602106545ff601c158d0864ce8e79de6d0aPaul Mundtstruct sh7786_pcie_port { 255713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt struct pci_channel *hose; 26c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt struct clk *fclk, phy_clk; 275713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt unsigned int index; 285713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt int endpoint; 295713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt int link; 305713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt}; 315713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 325713e602106545ff601c158d0864ce8e79de6d0aPaul Mundtstatic struct sh7786_pcie_port *sh7786_pcie_ports; 335713e602106545ff601c158d0864ce8e79de6d0aPaul Mundtstatic unsigned int nr_ports; 345713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 355713e602106545ff601c158d0864ce8e79de6d0aPaul Mundtstatic struct sh7786_pcie_hwops { 365713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt int (*core_init)(void); 371da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt async_func_ptr *port_init_hw; 385713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt} *sh7786_pcie_hwops; 395713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 407561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundtstatic struct resource sh7786_pci0_resources[] = { 415713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt { 427561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .name = "PCIe0 IO", 437561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .start = 0xfd000000, 447561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .end = 0xfd000000 + SZ_8M - 1, 457561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .flags = IORESOURCE_IO, 465713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt }, { 477561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .name = "PCIe0 MEM 0", 487561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .start = 0xc0000000, 497561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .end = 0xc0000000 + SZ_512M - 1, 507561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, 515713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt }, { 527561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .name = "PCIe0 MEM 1", 537561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .start = 0x10000000, 547561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .end = 0x10000000 + SZ_64M - 1, 555713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt .flags = IORESOURCE_MEM, 567561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt }, { 577561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .name = "PCIe0 MEM 2", 587561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .start = 0xfe100000, 597561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .end = 0xfe100000 + SZ_1M - 1, 601c3bb3871af53a2a8620bc48b5535f6d83386773Paul Mundt .flags = IORESOURCE_MEM, 615713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt }, 625713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt}; 635713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 647561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundtstatic struct resource sh7786_pci1_resources[] = { 657561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt { 667561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .name = "PCIe1 IO", 677561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .start = 0xfd800000, 687561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .end = 0xfd800000 + SZ_8M - 1, 697561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .flags = IORESOURCE_IO, 707561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt }, { 717561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .name = "PCIe1 MEM 0", 727561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .start = 0xa0000000, 737561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .end = 0xa0000000 + SZ_512M - 1, 747561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, 757561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt }, { 767561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .name = "PCIe1 MEM 1", 777561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .start = 0x30000000, 787561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .end = 0x30000000 + SZ_256M - 1, 797561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, 807561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt }, { 817561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .name = "PCIe1 MEM 2", 827561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .start = 0xfe300000, 837561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .end = 0xfe300000 + SZ_1M - 1, 841c3bb3871af53a2a8620bc48b5535f6d83386773Paul Mundt .flags = IORESOURCE_MEM, 857561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt }, 865713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt}; 875713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 887561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundtstatic struct resource sh7786_pci2_resources[] = { 895713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt { 907561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .name = "PCIe2 IO", 917561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .start = 0xfc800000, 927561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .end = 0xfc800000 + SZ_4M - 1, 93f048519309dbaedd03807ddbb9fa22f5616cfd43Paul Mundt .flags = IORESOURCE_IO, 945713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt }, { 957561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .name = "PCIe2 MEM 0", 967561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .start = 0x80000000, 977561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .end = 0x80000000 + SZ_512M - 1, 987561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, 995713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt }, { 1007561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .name = "PCIe2 MEM 1", 1017561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .start = 0x20000000, 1027561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .end = 0x20000000 + SZ_256M - 1, 1037561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, 1047561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt }, { 1057561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .name = "PCIe2 MEM 2", 1067561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .start = 0xfcd00000, 1077561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .end = 0xfcd00000 + SZ_1M - 1, 1081c3bb3871af53a2a8620bc48b5535f6d83386773Paul Mundt .flags = IORESOURCE_MEM, 1095713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt }, 1105713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt}; 1115713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 1125713e602106545ff601c158d0864ce8e79de6d0aPaul Mundtextern struct pci_ops sh7786_pci_ops; 1135713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 1147561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt#define DEFINE_CONTROLLER(start, idx) \ 1157561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt{ \ 1167561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .pci_ops = &sh7786_pci_ops, \ 1177561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .resources = sh7786_pci##idx##_resources, \ 1187561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .nr_resources = ARRAY_SIZE(sh7786_pci##idx##_resources), \ 1197561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .reg_base = start, \ 1207561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .mem_offset = 0, \ 1217561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt .io_offset = 0, \ 1225713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt} 1235713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 1245713e602106545ff601c158d0864ce8e79de6d0aPaul Mundtstatic struct pci_channel sh7786_pci_channels[] = { 1255713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt DEFINE_CONTROLLER(0xfe000000, 0), 1265713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt DEFINE_CONTROLLER(0xfe200000, 1), 1275713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt DEFINE_CONTROLLER(0xfcc00000, 2), 1285713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt}; 1295713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 130c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundtstatic struct clk fixed_pciexclkp = { 131c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt .rate = 100000000, /* 100 MHz reference clock */ 132c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt}; 133c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt 1342c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundtstatic void __devinit sh7786_pci_fixup(struct pci_dev *dev) 1352c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt{ 1362c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt /* 1372c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt * Prevent enumeration of root complex resources. 1382c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt */ 1392c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt if (pci_is_root_bus(dev->bus) && dev->devfn == 0) { 1402c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt int i; 1412c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt 1422c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1432c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt dev->resource[i].start = 0; 1442c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt dev->resource[i].end = 0; 1452c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt dev->resource[i].flags = 0; 1462c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt } 1472c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt } 1482c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt} 1492c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul MundtDECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_SH7786, 1502c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt sh7786_pci_fixup); 1512c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt 152c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundtstatic int __init phy_wait_for_ack(struct pci_channel *chan) 1535713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt{ 1545713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt unsigned int timeout = 100; 1555713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 1565713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt while (timeout--) { 1575713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt if (pci_read_reg(chan, SH4A_PCIEPHYADRR) & (1 << BITS_ACK)) 1585713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt return 0; 1595713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 1605713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt udelay(100); 1615713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt } 1625713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 1635713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt return -ETIMEDOUT; 1645713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt} 1655713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 166c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundtstatic int __init pci_wait_for_irq(struct pci_channel *chan, unsigned int mask) 1675713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt{ 1685713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt unsigned int timeout = 100; 1695713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 1705713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt while (timeout--) { 1715713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt if ((pci_read_reg(chan, SH4A_PCIEINTR) & mask) == mask) 1725713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt return 0; 1735713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 1745713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt udelay(100); 1755713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt } 1765713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 1775713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt return -ETIMEDOUT; 1785713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt} 1795713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 180c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundtstatic void __init phy_write_reg(struct pci_channel *chan, unsigned int addr, 181c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt unsigned int lane, unsigned int data) 1825713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt{ 18353178d71b9f2d5c96bfcd2dd2c4b99c4e95a77d5Paul Mundt unsigned long phyaddr; 1845713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 1855713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) + 1865713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt ((addr & 0xff) << BITS_ADR); 1875713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 1885713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt /* Set write data */ 1895713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR); 1905713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR); 1915713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 1925713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt phy_wait_for_ack(chan); 1935713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 1945713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt /* Clear command */ 19553178d71b9f2d5c96bfcd2dd2c4b99c4e95a77d5Paul Mundt pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR); 1965713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt pci_write_reg(chan, 0, SH4A_PCIEPHYADRR); 1975713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 1985713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt phy_wait_for_ack(chan); 1995713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt} 2005713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 201c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundtstatic int __init pcie_clk_init(struct sh7786_pcie_port *port) 202c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt{ 203c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt struct pci_channel *chan = port->hose; 204c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt struct clk *clk; 205c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt char fclk_name[16]; 206c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt int ret; 207c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt 208c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt /* 209c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt * First register the fixed clock 210c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt */ 211c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt ret = clk_register(&fixed_pciexclkp); 212c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt if (unlikely(ret != 0)) 213c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt return ret; 214c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt 215c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt /* 216c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt * Grab the port's function clock, which the PHY clock depends 217c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt * on. clock lookups don't help us much at this point, since no 218c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt * dev_id is available this early. Lame. 219c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt */ 220c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt snprintf(fclk_name, sizeof(fclk_name), "pcie%d_fck", port->index); 221c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt 222c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt port->fclk = clk_get(NULL, fclk_name); 223c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt if (IS_ERR(port->fclk)) { 224c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt ret = PTR_ERR(port->fclk); 225c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt goto err_fclk; 226c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt } 227c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt 228c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt clk_enable(port->fclk); 229c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt 230c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt /* 231c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt * And now, set up the PHY clock 232c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt */ 233c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt clk = &port->phy_clk; 234c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt 235c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt memset(clk, 0, sizeof(struct clk)); 236c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt 237c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt clk->parent = &fixed_pciexclkp; 238c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR); 239c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt clk->enable_bit = BITS_CKE; 240c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt 241c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt ret = sh_clk_mstp32_register(clk, 1); 242c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt if (unlikely(ret < 0)) 243c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt goto err_phy; 244c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt 245c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt return 0; 246c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt 247c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundterr_phy: 248c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt clk_disable(port->fclk); 249c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt clk_put(port->fclk); 250c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundterr_fclk: 251c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt clk_unregister(&fixed_pciexclkp); 252c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt 253c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt return ret; 254c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt} 255c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt 256c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundtstatic int __init phy_init(struct sh7786_pcie_port *port) 2575713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt{ 258c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt struct pci_channel *chan = port->hose; 2595713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt unsigned int timeout = 100; 2605713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 261c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt clk_enable(&port->phy_clk); 26253178d71b9f2d5c96bfcd2dd2c4b99c4e95a77d5Paul Mundt 2635713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt /* Initialize the phy */ 2645713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt phy_write_reg(chan, 0x60, 0xf, 0x004b008b); 2655713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt phy_write_reg(chan, 0x61, 0xf, 0x00007b41); 2665713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt phy_write_reg(chan, 0x64, 0xf, 0x00ff4f00); 2675713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt phy_write_reg(chan, 0x65, 0xf, 0x09070907); 2685713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt phy_write_reg(chan, 0x66, 0xf, 0x00000010); 2695713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt phy_write_reg(chan, 0x74, 0xf, 0x0007001c); 2705713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt phy_write_reg(chan, 0x79, 0xf, 0x01fc000d); 27153178d71b9f2d5c96bfcd2dd2c4b99c4e95a77d5Paul Mundt phy_write_reg(chan, 0xb0, 0xf, 0x00000610); 2725713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 2735713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt /* Deassert Standby */ 27453178d71b9f2d5c96bfcd2dd2c4b99c4e95a77d5Paul Mundt phy_write_reg(chan, 0x67, 0x1, 0x00000400); 27553178d71b9f2d5c96bfcd2dd2c4b99c4e95a77d5Paul Mundt 27653178d71b9f2d5c96bfcd2dd2c4b99c4e95a77d5Paul Mundt /* Disable clock */ 277c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt clk_disable(&port->phy_clk); 2785713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 2795713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt while (timeout--) { 2805713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt if (pci_read_reg(chan, SH4A_PCIEPHYSR)) 2815713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt return 0; 2825713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 2835713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt udelay(100); 2845713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt } 2855713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 2865713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt return -ETIMEDOUT; 2875713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt} 2885713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 289c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundtstatic void __init pcie_reset(struct sh7786_pcie_port *port) 2902dbfa1e37dc703631d5421e0b04aecc5a7aff37dPaul Mundt{ 2912dbfa1e37dc703631d5421e0b04aecc5a7aff37dPaul Mundt struct pci_channel *chan = port->hose; 2922dbfa1e37dc703631d5421e0b04aecc5a7aff37dPaul Mundt 2932dbfa1e37dc703631d5421e0b04aecc5a7aff37dPaul Mundt pci_write_reg(chan, 1, SH4A_PCIESRSTR); 2942dbfa1e37dc703631d5421e0b04aecc5a7aff37dPaul Mundt pci_write_reg(chan, 0, SH4A_PCIETCTLR); 2952dbfa1e37dc703631d5421e0b04aecc5a7aff37dPaul Mundt pci_write_reg(chan, 0, SH4A_PCIESRSTR); 2962dbfa1e37dc703631d5421e0b04aecc5a7aff37dPaul Mundt pci_write_reg(chan, 0, SH4A_PCIETXVC0SR); 2972dbfa1e37dc703631d5421e0b04aecc5a7aff37dPaul Mundt} 2982dbfa1e37dc703631d5421e0b04aecc5a7aff37dPaul Mundt 299c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundtstatic int __init pcie_init(struct sh7786_pcie_port *port) 3005713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt{ 3015713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt struct pci_channel *chan = port->hose; 3025713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt unsigned int data; 3037578a4c625a5cc32812946338a4549f3090be113Paul Mundt phys_addr_t memphys; 3047578a4c625a5cc32812946338a4549f3090be113Paul Mundt size_t memsize; 305da03a63ac843711887a85e5d90dd69399b1b9164Paul Mundt int ret, i, win; 3065713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 3075713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt /* Begin initialization */ 3082dbfa1e37dc703631d5421e0b04aecc5a7aff37dPaul Mundt pcie_reset(port); 3095713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 3102c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt /* 3112c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt * Initial header for port config space is type 1, set the device 3122c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt * class to match. Hardware takes care of propagating the IDSETR 3132c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt * settings, so there is no need to bother with a quirk. 3142c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt */ 3152c65d75ec4dde5e619a462e70cdd7b67e0e64bb8Paul Mundt pci_write_reg(chan, PCI_CLASS_BRIDGE_PCI << 16, SH4A_PCIEIDSETR1); 3165713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 3175713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt /* Initialize default capabilities. */ 3185713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt data = pci_read_reg(chan, SH4A_PCIEEXPCAP0); 3195713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt data &= ~(PCI_EXP_FLAGS_TYPE << 16); 3205713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 3215713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt if (port->endpoint) 3225713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt data |= PCI_EXP_TYPE_ENDPOINT << 20; 3235713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt else 3245713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt data |= PCI_EXP_TYPE_ROOT_PORT << 20; 3255713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 3265713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt data |= PCI_CAP_ID_EXP; 3275713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt pci_write_reg(chan, data, SH4A_PCIEEXPCAP0); 3285713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 3297578a4c625a5cc32812946338a4549f3090be113Paul Mundt /* Enable data link layer active state reporting */ 3307578a4c625a5cc32812946338a4549f3090be113Paul Mundt pci_write_reg(chan, PCI_EXP_LNKCAP_DLLLARC, SH4A_PCIEEXPCAP3); 3317578a4c625a5cc32812946338a4549f3090be113Paul Mundt 3327578a4c625a5cc32812946338a4549f3090be113Paul Mundt /* Enable extended sync and ASPM L0s support */ 3335713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt data = pci_read_reg(chan, SH4A_PCIEEXPCAP4); 3347578a4c625a5cc32812946338a4549f3090be113Paul Mundt data &= ~PCI_EXP_LNKCTL_ASPMC; 3357578a4c625a5cc32812946338a4549f3090be113Paul Mundt data |= PCI_EXP_LNKCTL_ES | 1; 3365713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt pci_write_reg(chan, data, SH4A_PCIEEXPCAP4); 3375713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 3387578a4c625a5cc32812946338a4549f3090be113Paul Mundt /* Write out the physical slot number */ 3397578a4c625a5cc32812946338a4549f3090be113Paul Mundt data = pci_read_reg(chan, SH4A_PCIEEXPCAP5); 3407578a4c625a5cc32812946338a4549f3090be113Paul Mundt data &= ~PCI_EXP_SLTCAP_PSN; 3417578a4c625a5cc32812946338a4549f3090be113Paul Mundt data |= (port->index + 1) << 19; 3427578a4c625a5cc32812946338a4549f3090be113Paul Mundt pci_write_reg(chan, data, SH4A_PCIEEXPCAP5); 3437578a4c625a5cc32812946338a4549f3090be113Paul Mundt 3445713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt /* Set the completion timer timeout to the maximum 32ms. */ 3455713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt data = pci_read_reg(chan, SH4A_PCIETLCTLR); 3467578a4c625a5cc32812946338a4549f3090be113Paul Mundt data &= ~0x3f00; 3475713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt data |= 0x32 << 8; 3485713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt pci_write_reg(chan, data, SH4A_PCIETLCTLR); 3495713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 3505713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt /* 3515713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt * Set fast training sequences to the maximum 255, 3525713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt * and enable MAC data scrambling. 3535713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt */ 3545713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt data = pci_read_reg(chan, SH4A_PCIEMACCTLR); 3555713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt data &= ~PCIEMACCTLR_SCR_DIS; 3565713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt data |= (0xff << 16); 3575713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt pci_write_reg(chan, data, SH4A_PCIEMACCTLR); 3585713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 3597578a4c625a5cc32812946338a4549f3090be113Paul Mundt memphys = __pa(memory_start); 3607578a4c625a5cc32812946338a4549f3090be113Paul Mundt memsize = roundup_pow_of_two(memory_end - memory_start); 3617578a4c625a5cc32812946338a4549f3090be113Paul Mundt 3627578a4c625a5cc32812946338a4549f3090be113Paul Mundt /* 3637578a4c625a5cc32812946338a4549f3090be113Paul Mundt * If there's more than 512MB of memory, we need to roll over to 3647578a4c625a5cc32812946338a4549f3090be113Paul Mundt * LAR1/LAMR1. 3657578a4c625a5cc32812946338a4549f3090be113Paul Mundt */ 3667578a4c625a5cc32812946338a4549f3090be113Paul Mundt if (memsize > SZ_512M) { 367cecf48e23fd9270053850643a56e8e791322e3d5Paul Mundt pci_write_reg(chan, memphys + SZ_512M, SH4A_PCIELAR1); 368cecf48e23fd9270053850643a56e8e791322e3d5Paul Mundt pci_write_reg(chan, ((memsize - SZ_512M) - SZ_256) | 1, 369cecf48e23fd9270053850643a56e8e791322e3d5Paul Mundt SH4A_PCIELAMR1); 3707578a4c625a5cc32812946338a4549f3090be113Paul Mundt memsize = SZ_512M; 3717578a4c625a5cc32812946338a4549f3090be113Paul Mundt } else { 3727578a4c625a5cc32812946338a4549f3090be113Paul Mundt /* 3737578a4c625a5cc32812946338a4549f3090be113Paul Mundt * Otherwise just zero it out and disable it. 3747578a4c625a5cc32812946338a4549f3090be113Paul Mundt */ 375cecf48e23fd9270053850643a56e8e791322e3d5Paul Mundt pci_write_reg(chan, 0, SH4A_PCIELAR1); 376cecf48e23fd9270053850643a56e8e791322e3d5Paul Mundt pci_write_reg(chan, 0, SH4A_PCIELAMR1); 3777578a4c625a5cc32812946338a4549f3090be113Paul Mundt } 3787578a4c625a5cc32812946338a4549f3090be113Paul Mundt 3797578a4c625a5cc32812946338a4549f3090be113Paul Mundt /* 3807578a4c625a5cc32812946338a4549f3090be113Paul Mundt * LAR0/LAMR0 covers up to the first 512MB, which is enough to 3817578a4c625a5cc32812946338a4549f3090be113Paul Mundt * cover all of lowmem on most platforms. 3827578a4c625a5cc32812946338a4549f3090be113Paul Mundt */ 383cecf48e23fd9270053850643a56e8e791322e3d5Paul Mundt pci_write_reg(chan, memphys, SH4A_PCIELAR0); 384cecf48e23fd9270053850643a56e8e791322e3d5Paul Mundt pci_write_reg(chan, (memsize - SZ_256) | 1, SH4A_PCIELAMR0); 3857578a4c625a5cc32812946338a4549f3090be113Paul Mundt 3865713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt /* Finish initialization */ 3875713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt data = pci_read_reg(chan, SH4A_PCIETCTLR); 3885713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt data |= 0x1; 3895713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt pci_write_reg(chan, data, SH4A_PCIETCTLR); 3905713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 39181df84f4060f4f19c7e6f39c7c527a6098436a2aPaul Mundt /* Let things settle down a bit.. */ 39281df84f4060f4f19c7e6f39c7c527a6098436a2aPaul Mundt mdelay(100); 39381df84f4060f4f19c7e6f39c7c527a6098436a2aPaul Mundt 3945713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt /* Enable DL_Active Interrupt generation */ 3955713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt data = pci_read_reg(chan, SH4A_PCIEDLINTENR); 3965713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt data |= PCIEDLINTENR_DLL_ACT_ENABLE; 3975713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt pci_write_reg(chan, data, SH4A_PCIEDLINTENR); 3985713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 3995713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt /* Disable MAC data scrambling. */ 4005713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt data = pci_read_reg(chan, SH4A_PCIEMACCTLR); 4015713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt data |= PCIEMACCTLR_SCR_DIS | (0xff << 16); 4025713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt pci_write_reg(chan, data, SH4A_PCIEMACCTLR); 4035713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 404bd792aea441a3dcdede462486ab8c63045803844Paul Mundt /* 405bd792aea441a3dcdede462486ab8c63045803844Paul Mundt * This will timeout if we don't have a link, but we permit the 406bd792aea441a3dcdede462486ab8c63045803844Paul Mundt * port to register anyways in order to support hotplug on future 407bd792aea441a3dcdede462486ab8c63045803844Paul Mundt * hardware. 408bd792aea441a3dcdede462486ab8c63045803844Paul Mundt */ 4095713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt ret = pci_wait_for_irq(chan, MASK_INT_TX_CTRL); 4105713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 4117578a4c625a5cc32812946338a4549f3090be113Paul Mundt data = pci_read_reg(chan, SH4A_PCIEPCICONF1); 4127578a4c625a5cc32812946338a4549f3090be113Paul Mundt data &= ~(PCI_STATUS_DEVSEL_MASK << 16); 4137578a4c625a5cc32812946338a4549f3090be113Paul Mundt data |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 4147578a4c625a5cc32812946338a4549f3090be113Paul Mundt (PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_FAST) << 16; 4157578a4c625a5cc32812946338a4549f3090be113Paul Mundt pci_write_reg(chan, data, SH4A_PCIEPCICONF1); 4167578a4c625a5cc32812946338a4549f3090be113Paul Mundt 4175713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR); 4185713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR); 4195713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 4205713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt wmb(); 4215713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 422bd792aea441a3dcdede462486ab8c63045803844Paul Mundt if (ret == 0) { 423bd792aea441a3dcdede462486ab8c63045803844Paul Mundt data = pci_read_reg(chan, SH4A_PCIEMACSR); 424bd792aea441a3dcdede462486ab8c63045803844Paul Mundt printk(KERN_NOTICE "PCI: PCIe#%d x%d link detected\n", 425bd792aea441a3dcdede462486ab8c63045803844Paul Mundt port->index, (data >> 20) & 0x3f); 426bd792aea441a3dcdede462486ab8c63045803844Paul Mundt } else 427bd792aea441a3dcdede462486ab8c63045803844Paul Mundt printk(KERN_NOTICE "PCI: PCIe#%d link down\n", 428bd792aea441a3dcdede462486ab8c63045803844Paul Mundt port->index); 4295713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 430da03a63ac843711887a85e5d90dd69399b1b9164Paul Mundt for (i = win = 0; i < chan->nr_resources; i++) { 4317578a4c625a5cc32812946338a4549f3090be113Paul Mundt struct resource *res = chan->resources + i; 4327578a4c625a5cc32812946338a4549f3090be113Paul Mundt resource_size_t size; 433cecf48e23fd9270053850643a56e8e791322e3d5Paul Mundt u32 mask; 4347578a4c625a5cc32812946338a4549f3090be113Paul Mundt 435da03a63ac843711887a85e5d90dd69399b1b9164Paul Mundt /* 436da03a63ac843711887a85e5d90dd69399b1b9164Paul Mundt * We can't use the 32-bit mode windows in legacy 29-bit 437da03a63ac843711887a85e5d90dd69399b1b9164Paul Mundt * mode, so just skip them entirely. 438da03a63ac843711887a85e5d90dd69399b1b9164Paul Mundt */ 439da03a63ac843711887a85e5d90dd69399b1b9164Paul Mundt if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode()) 440da03a63ac843711887a85e5d90dd69399b1b9164Paul Mundt continue; 441da03a63ac843711887a85e5d90dd69399b1b9164Paul Mundt 442da03a63ac843711887a85e5d90dd69399b1b9164Paul Mundt pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win)); 4437578a4c625a5cc32812946338a4549f3090be113Paul Mundt 4447578a4c625a5cc32812946338a4549f3090be113Paul Mundt /* 4457578a4c625a5cc32812946338a4549f3090be113Paul Mundt * The PAMR mask is calculated in units of 256kB, which 4467578a4c625a5cc32812946338a4549f3090be113Paul Mundt * keeps things pretty simple. 4477578a4c625a5cc32812946338a4549f3090be113Paul Mundt */ 448cecf48e23fd9270053850643a56e8e791322e3d5Paul Mundt size = resource_size(res); 449cecf48e23fd9270053850643a56e8e791322e3d5Paul Mundt mask = (roundup_pow_of_two(size) / SZ_256K) - 1; 450cecf48e23fd9270053850643a56e8e791322e3d5Paul Mundt pci_write_reg(chan, mask << 18, SH4A_PCIEPAMR(win)); 4517578a4c625a5cc32812946338a4549f3090be113Paul Mundt 452a80be1680502f99de5f9565c491208e90a9a3afePaul Mundt pci_write_reg(chan, upper_32_bits(res->start), 453cecf48e23fd9270053850643a56e8e791322e3d5Paul Mundt SH4A_PCIEPARH(win)); 454a80be1680502f99de5f9565c491208e90a9a3afePaul Mundt pci_write_reg(chan, lower_32_bits(res->start), 455cecf48e23fd9270053850643a56e8e791322e3d5Paul Mundt SH4A_PCIEPARL(win)); 4567578a4c625a5cc32812946338a4549f3090be113Paul Mundt 457cecf48e23fd9270053850643a56e8e791322e3d5Paul Mundt mask = MASK_PARE; 4587578a4c625a5cc32812946338a4549f3090be113Paul Mundt if (res->flags & IORESOURCE_IO) 459cecf48e23fd9270053850643a56e8e791322e3d5Paul Mundt mask |= MASK_SPC; 4607578a4c625a5cc32812946338a4549f3090be113Paul Mundt 461cecf48e23fd9270053850643a56e8e791322e3d5Paul Mundt pci_write_reg(chan, mask, SH4A_PCIEPTCTLR(win)); 462da03a63ac843711887a85e5d90dd69399b1b9164Paul Mundt 463da03a63ac843711887a85e5d90dd69399b1b9164Paul Mundt win++; 4647578a4c625a5cc32812946338a4549f3090be113Paul Mundt } 4655713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 4665713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt return 0; 4675713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt} 4685713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 469d5341942d784134f2997b3ff82cd63cf71d1f932Ralf Baechleint __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin) 4705713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt{ 4715713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt return 71; 4725713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt} 4735713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 474c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundtstatic int __init sh7786_pcie_core_init(void) 4755713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt{ 4765713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt /* Return the number of ports */ 4775713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt return test_mode_pin(MODE_PIN12) ? 3 : 2; 4785713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt} 4795713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 4801da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundtstatic void __init sh7786_pcie_init_hw(void *data, async_cookie_t cookie) 4815713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt{ 4821da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt struct sh7786_pcie_port *port = data; 4835713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt int ret; 4845713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 4855713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt /* 4865713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt * Check if we are configured in endpoint or root complex mode, 4875713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt * this is a fixed pin setting that applies to all PCIe ports. 4885713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt */ 4895713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt port->endpoint = test_mode_pin(MODE_PIN11); 4905713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 491c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt /* 492c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt * Setup clocks, needed both for PHY and PCIe registers. 493c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt */ 494c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt ret = pcie_clk_init(port); 4951da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt if (unlikely(ret < 0)) { 4961da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt pr_err("clock initialization failed for port#%d\n", 4971da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt port->index); 4981da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt return; 4991da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt } 500c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt 501c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt ret = phy_init(port); 5021da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt if (unlikely(ret < 0)) { 5031da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt pr_err("phy initialization failed for port#%d\n", 5041da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt port->index); 5051da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt return; 5061da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt } 507c524ebf5a6b78d25219d64a05b3876cde719b5ffPaul Mundt 5085713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt ret = pcie_init(port); 5091da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt if (unlikely(ret < 0)) { 5101da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt pr_err("core initialization failed for port#%d\n", 5111da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt port->index); 5121da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt return; 5131da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt } 5145713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 5151da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt /* In the interest of preserving device ordering, synchronize */ 5161da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt async_synchronize_cookie(cookie); 5171da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt 5181da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt register_pci_controller(port->hose); 5195713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt} 5205713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 5215713e602106545ff601c158d0864ce8e79de6d0aPaul Mundtstatic struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = { 5225713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt .core_init = sh7786_pcie_core_init, 5235713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt .port_init_hw = sh7786_pcie_init_hw, 5245713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt}; 5255713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 5265713e602106545ff601c158d0864ce8e79de6d0aPaul Mundtstatic int __init sh7786_pcie_init(void) 5275713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt{ 528b6b77b2d5ffd2f8ee74fcc27661f7f4962c34705Paul Mundt struct clk *platclk; 5291da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt int i; 5305713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 5313b554c33dcde9d67efcb8d0a5acca201afd44730Matt Fleming printk(KERN_NOTICE "PCI: Starting initialization.\n"); 5325713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 5335713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt sh7786_pcie_hwops = &sh7786_65nm_pcie_hwops; 5345713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 5355713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt nr_ports = sh7786_pcie_hwops->core_init(); 5365713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt BUG_ON(nr_ports > ARRAY_SIZE(sh7786_pci_channels)); 5375713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 5385713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt if (unlikely(nr_ports == 0)) 5395713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt return -ENODEV; 5405713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 5415713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt sh7786_pcie_ports = kzalloc(nr_ports * sizeof(struct sh7786_pcie_port), 5425713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt GFP_KERNEL); 5435713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt if (unlikely(!sh7786_pcie_ports)) 5445713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt return -ENOMEM; 5455713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 546b6b77b2d5ffd2f8ee74fcc27661f7f4962c34705Paul Mundt /* 547b6b77b2d5ffd2f8ee74fcc27661f7f4962c34705Paul Mundt * Fetch any optional platform clock associated with this block. 548b6b77b2d5ffd2f8ee74fcc27661f7f4962c34705Paul Mundt * 549b6b77b2d5ffd2f8ee74fcc27661f7f4962c34705Paul Mundt * This is a rather nasty hack for boards with spec-mocking FPGAs 550b6b77b2d5ffd2f8ee74fcc27661f7f4962c34705Paul Mundt * that have a secondary set of clocks outside of the on-chip 551b6b77b2d5ffd2f8ee74fcc27661f7f4962c34705Paul Mundt * ones that need to be accounted for before there is any chance 552b6b77b2d5ffd2f8ee74fcc27661f7f4962c34705Paul Mundt * of touching the existing MSTP bits or CPG clocks. 553b6b77b2d5ffd2f8ee74fcc27661f7f4962c34705Paul Mundt */ 554b6b77b2d5ffd2f8ee74fcc27661f7f4962c34705Paul Mundt platclk = clk_get(NULL, "pcie_plat_clk"); 555b6b77b2d5ffd2f8ee74fcc27661f7f4962c34705Paul Mundt if (IS_ERR(platclk)) { 556b6b77b2d5ffd2f8ee74fcc27661f7f4962c34705Paul Mundt /* Sane hardware should probably get a WARN_ON.. */ 557b6b77b2d5ffd2f8ee74fcc27661f7f4962c34705Paul Mundt platclk = NULL; 558b6b77b2d5ffd2f8ee74fcc27661f7f4962c34705Paul Mundt } 559b6b77b2d5ffd2f8ee74fcc27661f7f4962c34705Paul Mundt 560b6b77b2d5ffd2f8ee74fcc27661f7f4962c34705Paul Mundt clk_enable(platclk); 561b6b77b2d5ffd2f8ee74fcc27661f7f4962c34705Paul Mundt 5625713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt printk(KERN_NOTICE "PCI: probing %d ports.\n", nr_ports); 5635713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 5645713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt for (i = 0; i < nr_ports; i++) { 5655713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt struct sh7786_pcie_port *port = sh7786_pcie_ports + i; 5665713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 5675713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt port->index = i; 5685713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt port->hose = sh7786_pci_channels + i; 5697561f2dd393bd0c6397e6b2a6b021cdb827a2eb1Paul Mundt port->hose->io_map_base = port->hose->resources[0].start; 5705713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 5711da09c43ce5f4fcd98143feb7d2513fe6fd62848Paul Mundt async_schedule(sh7786_pcie_hwops->port_init_hw, port); 572b6b77b2d5ffd2f8ee74fcc27661f7f4962c34705Paul Mundt } 5735713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt 574cd7bb53ff88a5acef942a87c1d04e6211b6470dcPaul Mundt async_synchronize_full(); 575cd7bb53ff88a5acef942a87c1d04e6211b6470dcPaul Mundt 5765713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt return 0; 5775713e602106545ff601c158d0864ce8e79de6d0aPaul Mundt} 5785713e602106545ff601c158d0864ce8e79de6d0aPaul Mundtarch_initcall(sh7786_pcie_init); 579