cache-sh4.c revision 55661fc1f105ed75852e937bf8ea408270eb0cca
11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * arch/sh/mm/cache-sh4.c 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright (C) 1999, 2000, 2002 Niibe Yutaka 5deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt * Copyright (C) 2001 - 2009 Paul Mundt 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright (C) 2003 Richard Curnow 709b5a10c1944214a6008712bfa92b29f00b84a1aChris Smith * Copyright (c) 2007 STMicroelectronics (R&D) Ltd. 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This file is subject to the terms and conditions of the GNU General Public 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * License. See the file "COPYING" in the main directory of this archive 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * for more details. 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/init.h> 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/mm.h> 1552e27782e1c4afa1feca0fdf194d279595e0431cPaul Mundt#include <linux/io.h> 1652e27782e1c4afa1feca0fdf194d279595e0431cPaul Mundt#include <linux/mutex.h> 172277ab4a1df50e05bc732fe9488d4e902bb8399aPaul Mundt#include <linux/fs.h> 18deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt#include <linux/highmem.h> 19deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt#include <asm/pgtable.h> 201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/mmu_context.h> 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/cacheflush.h> 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2328ccf7f91b1ac42ee1f18480a69d2a7486b625cePaul Mundt/* 2428ccf7f91b1ac42ee1f18480a69d2a7486b625cePaul Mundt * The maximum number of pages we support up to when doing ranged dcache 2528ccf7f91b1ac42ee1f18480a69d2a7486b625cePaul Mundt * flushing. Anything exceeding this will simply flush the dcache in its 2628ccf7f91b1ac42ee1f18480a69d2a7486b625cePaul Mundt * entirety. 2728ccf7f91b1ac42ee1f18480a69d2a7486b625cePaul Mundt */ 2809b5a10c1944214a6008712bfa92b29f00b84a1aChris Smith#define MAX_ICACHE_PAGES 32 2928ccf7f91b1ac42ee1f18480a69d2a7486b625cePaul Mundt 30a7a7c0e1d12bcfb4a96cae439951232b08c91841Valentin Sitdikovstatic void __flush_cache_one(unsigned long addr, unsigned long phys, 31a252710fc5b63b24934905ca47ecf661702d7f00Paul Mundt unsigned long exec_offset); 32b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow 33b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow/* 341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Write back the range of D-cache, and purge the I-cache. 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 3609b5a10c1944214a6008712bfa92b29f00b84a1aChris Smith * Called from kernel/module.c:sys_init_module and routine for a.out format, 3709b5a10c1944214a6008712bfa92b29f00b84a1aChris Smith * signal handler code and kprobes code 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 392dc2f8e0c46864e2a3722c84eaa96513d4cf8b2fPaul Mundtstatic void sh4_flush_icache_range(void *args) 401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 41f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt struct flusher_data *data = args; 42f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt unsigned long start, end; 43983f4c514c4c9ddac1077a2c805fd16cbe3f7487Paul Mundt unsigned long flags, v; 441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int i; 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 46f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt start = data->addr1; 47f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt end = data->addr2; 48f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt 49682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt /* If there are too many pages then just blow away the caches */ 50682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) { 51682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt local_flush_cache_all(NULL); 52682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt return; 53682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt } 54682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt 55682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt /* 56682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt * Selectively flush d-cache then invalidate the i-cache. 57682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt * This is inefficient, so only use this for small ranges. 58682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt */ 59682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt start &= ~(L1_CACHE_BYTES-1); 60682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt end += L1_CACHE_BYTES-1; 61682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt end &= ~(L1_CACHE_BYTES-1); 62983f4c514c4c9ddac1077a2c805fd16cbe3f7487Paul Mundt 63682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt local_irq_save(flags); 64682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt jump_to_uncached(); 65983f4c514c4c9ddac1077a2c805fd16cbe3f7487Paul Mundt 66682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt for (v = start; v < end; v += L1_CACHE_BYTES) { 67682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt unsigned long icacheaddr; 68a9d244a2ff163247b607c4bb64803230ca8f8acbMatt Fleming int j, n; 69983f4c514c4c9ddac1077a2c805fd16cbe3f7487Paul Mundt 70682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt __ocbwb(v); 71983f4c514c4c9ddac1077a2c805fd16cbe3f7487Paul Mundt 72682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt icacheaddr = CACHE_IC_ADDRESS_ARRAY | (v & 73682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt cpu_data->icache.entry_mask); 7409b5a10c1944214a6008712bfa92b29f00b84a1aChris Smith 75682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt /* Clear i-cache line valid-bit */ 76a9d244a2ff163247b607c4bb64803230ca8f8acbMatt Fleming n = boot_cpu_data.icache.n_aliases; 77682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt for (i = 0; i < cpu_data->icache.ways; i++) { 78a9d244a2ff163247b607c4bb64803230ca8f8acbMatt Fleming for (j = 0; j < n; j++) 79a9d244a2ff163247b607c4bb64803230ca8f8acbMatt Fleming __raw_writel(0, icacheaddr + (j * PAGE_SIZE)); 80682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt icacheaddr += cpu_data->icache.way_incr; 81682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt } 8209b5a10c1944214a6008712bfa92b29f00b84a1aChris Smith } 83682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt 84682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt back_to_cached(); 85682f88ab74e55dae55ea3bf30b46f56f71b793bdPaul Mundt local_irq_restore(flags); 861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 88a7a7c0e1d12bcfb4a96cae439951232b08c91841Valentin Sitdikovstatic inline void flush_cache_one(unsigned long start, unsigned long phys) 891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 90983f4c514c4c9ddac1077a2c805fd16cbe3f7487Paul Mundt unsigned long flags, exec_offset = 0; 9133573c0e3243aaa38b6ad96942de85a1b713c2ffPaul Mundt 921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 931f69b6af9171f50135cce8023c84d82fbf42a8f5Matt Fleming * All types of SH-4 require PC to be uncached to operate on the I-cache. 941f69b6af9171f50135cce8023c84d82fbf42a8f5Matt Fleming * Some types of SH-4 require PC to be uncached to operate on the D-cache. 951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 967ec9d6f8c0e6932d380da1964021fbebf2311f04Paul Mundt if ((boot_cpu_data.flags & CPU_HAS_P2_FLUSH_BUG) || 9733573c0e3243aaa38b6ad96942de85a1b713c2ffPaul Mundt (start < CACHE_OC_ADDRESS_ARRAY)) 981f69b6af9171f50135cce8023c84d82fbf42a8f5Matt Fleming exec_offset = cached_to_uncached; 9933573c0e3243aaa38b6ad96942de85a1b713c2ffPaul Mundt 100983f4c514c4c9ddac1077a2c805fd16cbe3f7487Paul Mundt local_irq_save(flags); 101a781d1e5ff6277f80ff3c9503775521bc64cf131Matt Fleming __flush_cache_one(start, phys, exec_offset); 102983f4c514c4c9ddac1077a2c805fd16cbe3f7487Paul Mundt local_irq_restore(flags); 1031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 1041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Write back & invalidate the D-cache of the page. 1071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * (To avoid "alias" issues) 1081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 109e76a0136a3cf1859fbc07f122e42293d22229558Paul Mundtstatic void sh4_flush_dcache_page(void *arg) 1101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 111e76a0136a3cf1859fbc07f122e42293d22229558Paul Mundt struct page *page = arg; 112b4c892762373c5e59c7e8db35f5f9a7658602bdaMatt Fleming unsigned long addr = (unsigned long)page_address(page); 113c139a595878b0e8156476668e3d5c27b6aca7624Paul Mundt#ifndef CONFIG_SMP 1142277ab4a1df50e05bc732fe9488d4e902bb8399aPaul Mundt struct address_space *mapping = page_mapping(page); 1152277ab4a1df50e05bc732fe9488d4e902bb8399aPaul Mundt 1162277ab4a1df50e05bc732fe9488d4e902bb8399aPaul Mundt if (mapping && !mapping_mapped(mapping)) 11755661fc1f105ed75852e937bf8ea408270eb0ccaPaul Mundt clear_bit(PG_dcache_clean, &page->flags); 1182277ab4a1df50e05bc732fe9488d4e902bb8399aPaul Mundt else 1192277ab4a1df50e05bc732fe9488d4e902bb8399aPaul Mundt#endif 120b4c892762373c5e59c7e8db35f5f9a7658602bdaMatt Fleming flush_cache_one(CACHE_OC_ADDRESS_ARRAY | 121b4c892762373c5e59c7e8db35f5f9a7658602bdaMatt Fleming (addr & shm_align_mask), page_to_phys(page)); 122fdfc74f9fcebdda14609159d5010b758a9409acfPaul Mundt 123fdfc74f9fcebdda14609159d5010b758a9409acfPaul Mundt wmb(); 1241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 1251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 12628ccf7f91b1ac42ee1f18480a69d2a7486b625cePaul Mundt/* TODO: Selective icache invalidation through IC address array.. */ 1272dc2f8e0c46864e2a3722c84eaa96513d4cf8b2fPaul Mundtstatic void flush_icache_all(void) 1281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 129983f4c514c4c9ddac1077a2c805fd16cbe3f7487Paul Mundt unsigned long flags, ccr; 1301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 131983f4c514c4c9ddac1077a2c805fd16cbe3f7487Paul Mundt local_irq_save(flags); 132cbaa118ecfd99fc5ed7adbd9c34a30e1c05e3c93Stuart Menefy jump_to_uncached(); 1331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Flush I-cache */ 1359d56dd3b083a3bec56e9da35ce07baca81030b03Paul Mundt ccr = __raw_readl(CCR); 1361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ccr |= CCR_CACHE_ICI; 1379d56dd3b083a3bec56e9da35ce07baca81030b03Paul Mundt __raw_writel(ccr, CCR); 1381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 139298476220d1f793ca0ac6c9e5dc817e1ad3e9851Paul Mundt /* 140cbaa118ecfd99fc5ed7adbd9c34a30e1c05e3c93Stuart Menefy * back_to_cached() will take care of the barrier for us, don't add 141298476220d1f793ca0ac6c9e5dc817e1ad3e9851Paul Mundt * another one! 142298476220d1f793ca0ac6c9e5dc817e1ad3e9851Paul Mundt */ 143983f4c514c4c9ddac1077a2c805fd16cbe3f7487Paul Mundt 144cbaa118ecfd99fc5ed7adbd9c34a30e1c05e3c93Stuart Menefy back_to_cached(); 145983f4c514c4c9ddac1077a2c805fd16cbe3f7487Paul Mundt local_irq_restore(flags); 1461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 1471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 148bd6df57481b329dfeeb4889068848ee4f4761561Paul Mundtstatic void flush_dcache_all(void) 1491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 150bd6df57481b329dfeeb4889068848ee4f4761561Paul Mundt unsigned long addr, end_addr, entry_offset; 151bd6df57481b329dfeeb4889068848ee4f4761561Paul Mundt 152bd6df57481b329dfeeb4889068848ee4f4761561Paul Mundt end_addr = CACHE_OC_ADDRESS_ARRAY + 153bd6df57481b329dfeeb4889068848ee4f4761561Paul Mundt (current_cpu_data.dcache.sets << 154bd6df57481b329dfeeb4889068848ee4f4761561Paul Mundt current_cpu_data.dcache.entry_shift) * 155bd6df57481b329dfeeb4889068848ee4f4761561Paul Mundt current_cpu_data.dcache.ways; 156bd6df57481b329dfeeb4889068848ee4f4761561Paul Mundt 157bd6df57481b329dfeeb4889068848ee4f4761561Paul Mundt entry_offset = 1 << current_cpu_data.dcache.entry_shift; 158bd6df57481b329dfeeb4889068848ee4f4761561Paul Mundt 159bd6df57481b329dfeeb4889068848ee4f4761561Paul Mundt for (addr = CACHE_OC_ADDRESS_ARRAY; addr < end_addr; ) { 160bd6df57481b329dfeeb4889068848ee4f4761561Paul Mundt __raw_writel(0, addr); addr += entry_offset; 161bd6df57481b329dfeeb4889068848ee4f4761561Paul Mundt __raw_writel(0, addr); addr += entry_offset; 162bd6df57481b329dfeeb4889068848ee4f4761561Paul Mundt __raw_writel(0, addr); addr += entry_offset; 163bd6df57481b329dfeeb4889068848ee4f4761561Paul Mundt __raw_writel(0, addr); addr += entry_offset; 164bd6df57481b329dfeeb4889068848ee4f4761561Paul Mundt __raw_writel(0, addr); addr += entry_offset; 165bd6df57481b329dfeeb4889068848ee4f4761561Paul Mundt __raw_writel(0, addr); addr += entry_offset; 166bd6df57481b329dfeeb4889068848ee4f4761561Paul Mundt __raw_writel(0, addr); addr += entry_offset; 167bd6df57481b329dfeeb4889068848ee4f4761561Paul Mundt __raw_writel(0, addr); addr += entry_offset; 168bd6df57481b329dfeeb4889068848ee4f4761561Paul Mundt } 169a252710fc5b63b24934905ca47ecf661702d7f00Paul Mundt} 170a252710fc5b63b24934905ca47ecf661702d7f00Paul Mundt 171f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundtstatic void sh4_flush_cache_all(void *unused) 172a252710fc5b63b24934905ca47ecf661702d7f00Paul Mundt{ 173a252710fc5b63b24934905ca47ecf661702d7f00Paul Mundt flush_dcache_all(); 1741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds flush_icache_all(); 1751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 1761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 17728ccf7f91b1ac42ee1f18480a69d2a7486b625cePaul Mundt/* 17828ccf7f91b1ac42ee1f18480a69d2a7486b625cePaul Mundt * Note : (RPC) since the caches are physically tagged, the only point 17928ccf7f91b1ac42ee1f18480a69d2a7486b625cePaul Mundt * of flush_cache_mm for SH-4 is to get rid of aliases from the 18028ccf7f91b1ac42ee1f18480a69d2a7486b625cePaul Mundt * D-cache. The assumption elsewhere, e.g. flush_cache_range, is that 18128ccf7f91b1ac42ee1f18480a69d2a7486b625cePaul Mundt * lines can stay resident so long as the virtual address they were 18228ccf7f91b1ac42ee1f18480a69d2a7486b625cePaul Mundt * accessed with (hence cache set) is in accord with the physical 183654d364e26c797e8a5f9e2a1393607e6ca0106ebPaul Mundt * address (i.e. tag). It's no different here. 18428ccf7f91b1ac42ee1f18480a69d2a7486b625cePaul Mundt * 18528ccf7f91b1ac42ee1f18480a69d2a7486b625cePaul Mundt * Caller takes mm->mmap_sem. 18628ccf7f91b1ac42ee1f18480a69d2a7486b625cePaul Mundt */ 187f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundtstatic void sh4_flush_cache_mm(void *arg) 1881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 189f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt struct mm_struct *mm = arg; 190f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt 191e7b8b7f16edc9b363573eadf2ab2683473626071Paul Mundt if (cpu_context(smp_processor_id(), mm) == NO_CONTEXT) 192e7b8b7f16edc9b363573eadf2ab2683473626071Paul Mundt return; 193e7b8b7f16edc9b363573eadf2ab2683473626071Paul Mundt 194654d364e26c797e8a5f9e2a1393607e6ca0106ebPaul Mundt flush_dcache_all(); 1951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 1961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Write back and invalidate I/D-caches for the page. 1991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * ADDR: Virtual Address (U0 address) 2011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * PFN: Physical page number 2021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 203f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundtstatic void sh4_flush_cache_page(void *args) 2041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 205f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt struct flusher_data *data = args; 206f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt struct vm_area_struct *vma; 207deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt struct page *page; 208f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt unsigned long address, pfn, phys; 209deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt int map_coherent = 0; 210deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt pgd_t *pgd; 211deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt pud_t *pud; 212deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt pmd_t *pmd; 213deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt pte_t *pte; 214deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt void *vaddr; 215b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow 216f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt vma = data->vma; 217abeaf33a4101764291ec79cf286e08c0966eb26ePaul Mundt address = data->addr1 & PAGE_MASK; 218f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt pfn = data->addr2; 219f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt phys = pfn << PAGE_SHIFT; 220deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt page = pfn_to_page(pfn); 221f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt 222e7b8b7f16edc9b363573eadf2ab2683473626071Paul Mundt if (cpu_context(smp_processor_id(), vma->vm_mm) == NO_CONTEXT) 223e7b8b7f16edc9b363573eadf2ab2683473626071Paul Mundt return; 224e7b8b7f16edc9b363573eadf2ab2683473626071Paul Mundt 225deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt pgd = pgd_offset(vma->vm_mm, address); 226deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt pud = pud_offset(pgd, address); 227deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt pmd = pmd_offset(pud, address); 228deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt pte = pte_offset_kernel(pmd, address); 229deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt 230deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt /* If the page isn't present, there is nothing to do here. */ 231deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt if (!(pte_val(*pte) & _PAGE_PRESENT)) 232deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt return; 2331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 234deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt if ((vma->vm_mm == current->active_mm)) 235deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt vaddr = NULL; 236deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt else { 237b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow /* 238deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt * Use kmap_coherent or kmap_atomic to do flushes for 239deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt * another ASID than the current one. 240b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow */ 241deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt map_coherent = (current_cpu_data.dcache.n_aliases && 24255661fc1f105ed75852e937bf8ea408270eb0ccaPaul Mundt test_bit(PG_dcache_clean, &page->flags) && 243deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt page_mapped(page)); 244deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt if (map_coherent) 245deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt vaddr = kmap_coherent(page, address); 246deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt else 247deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt vaddr = kmap_atomic(page, KM_USER0); 248deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt 249deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt address = (unsigned long)vaddr; 250deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt } 251deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt 252e717cc6c07f006be36e35189aacb28be4e30ad14Matt Fleming flush_cache_one(CACHE_OC_ADDRESS_ARRAY | 253deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt (address & shm_align_mask), phys); 254deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt 255deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt if (vma->vm_flags & VM_EXEC) 256deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt flush_icache_all(); 257deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt 258deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt if (vaddr) { 259deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt if (map_coherent) 260deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt kunmap_coherent(vaddr); 261deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt else 262deaef20e9789d93c06d2d3b5ffc99939814802caPaul Mundt kunmap_atomic(vaddr, KM_USER0); 263b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow } 2641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 2651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 2671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Write back and invalidate D-caches. 2681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * START, END: Virtual Address (U0 address) 2701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * NOTE: We need to flush the _physical_ page entry. 2721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Flushing the cache lines for U0 only isn't enough. 2731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * We need to flush for P1 too, which may contain aliases. 2741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 275f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundtstatic void sh4_flush_cache_range(void *args) 2761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 277f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt struct flusher_data *data = args; 278f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt struct vm_area_struct *vma; 279f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt unsigned long start, end; 280f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt 281f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt vma = data->vma; 282f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt start = data->addr1; 283f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt end = data->addr2; 284f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt 285e7b8b7f16edc9b363573eadf2ab2683473626071Paul Mundt if (cpu_context(smp_processor_id(), vma->vm_mm) == NO_CONTEXT) 286e7b8b7f16edc9b363573eadf2ab2683473626071Paul Mundt return; 287e7b8b7f16edc9b363573eadf2ab2683473626071Paul Mundt 288b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow /* 289b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * If cache is only 4k-per-way, there are never any 'aliases'. Since 290b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * the cache is physically tagged, the data can just be left in there. 291b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow */ 2927ec9d6f8c0e6932d380da1964021fbebf2311f04Paul Mundt if (boot_cpu_data.dcache.n_aliases == 0) 293b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow return; 294b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow 295654d364e26c797e8a5f9e2a1393607e6ca0106ebPaul Mundt flush_dcache_all(); 296b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow 297654d364e26c797e8a5f9e2a1393607e6ca0106ebPaul Mundt if (vma->vm_flags & VM_EXEC) 2981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds flush_icache_all(); 2991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 3001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 301b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow/** 302a7a7c0e1d12bcfb4a96cae439951232b08c91841Valentin Sitdikov * __flush_cache_one 303b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * 304b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * @addr: address in memory mapped cache array 305b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * @phys: P1 address to flush (has to match tags if addr has 'A' bit 306b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * set i.e. associative write) 307b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * @exec_offset: set to 0x20000000 if flush has to be executed from P2 308b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * region else 0x0 309b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * 310b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * The offset into the cache array implied by 'addr' selects the 311b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * 'colour' of the virtual address range that will be flushed. The 312b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * operation (purge/write-back) is selected by the lower 2 bits of 313b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * 'phys'. 314b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow */ 315a7a7c0e1d12bcfb4a96cae439951232b08c91841Valentin Sitdikovstatic void __flush_cache_one(unsigned long addr, unsigned long phys, 316b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow unsigned long exec_offset) 317b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow{ 318b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow int way_count; 319b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow unsigned long base_addr = addr; 320b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow struct cache_info *dcache; 321b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow unsigned long way_incr; 322b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow unsigned long a, ea, p; 323b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow unsigned long temp_pc; 324b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow 3257ec9d6f8c0e6932d380da1964021fbebf2311f04Paul Mundt dcache = &boot_cpu_data.dcache; 326b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow /* Write this way for better assembly. */ 327b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow way_count = dcache->ways; 328b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow way_incr = dcache->way_incr; 329b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow 330b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow /* 331b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * Apply exec_offset (i.e. branch to P2 if required.). 332b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * 333b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * FIXME: 334b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * 335b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * If I write "=r" for the (temp_pc), it puts this in r6 hence 336b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * trashing exec_offset before it's been added on - why? Hence 337b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * "=&r" as a 'workaround' 338b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow */ 339b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow asm volatile("mov.l 1f, %0\n\t" 340b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow "add %1, %0\n\t" 341b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow "jmp @%0\n\t" 342b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow "nop\n\t" 343b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow ".balign 4\n\t" 344b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow "1: .long 2f\n\t" 345b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow "2:\n" : "=&r" (temp_pc) : "r" (exec_offset)); 346b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow 347b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow /* 348b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * We know there will be >=1 iteration, so write as do-while to avoid 349b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * pointless nead-of-loop check for 0 iterations. 350b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow */ 351b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow do { 352b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow ea = base_addr + PAGE_SIZE; 353b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow a = base_addr; 354b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow p = phys; 355b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow 356b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow do { 357b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow *(volatile unsigned long *)a = p; 358b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow /* 359b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * Next line: intentionally not p+32, saves an add, p 360b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * will do since only the cache tag bits need to 361b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow * match. 362b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow */ 363b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow *(volatile unsigned long *)(a+32) = p; 364b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow a += 64; 365b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow p += 64; 366b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow } while (a < ea); 367b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow 368b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow base_addr += way_incr; 369b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow } while (--way_count != 0); 370b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow} 371b638d0b921dc95229af0dfd09cd24850336a2f75Richard Curnow 37237443ef3f0406e855e169c87ae3f4ffb4b6ff635Paul Mundtextern void __weak sh4__flush_region_init(void); 37337443ef3f0406e855e169c87ae3f4ffb4b6ff635Paul Mundt 37437443ef3f0406e855e169c87ae3f4ffb4b6ff635Paul Mundt/* 37537443ef3f0406e855e169c87ae3f4ffb4b6ff635Paul Mundt * SH-4 has virtually indexed and physically tagged cache. 37637443ef3f0406e855e169c87ae3f4ffb4b6ff635Paul Mundt */ 37737443ef3f0406e855e169c87ae3f4ffb4b6ff635Paul Mundtvoid __init sh4_cache_init(void) 37837443ef3f0406e855e169c87ae3f4ffb4b6ff635Paul Mundt{ 37937443ef3f0406e855e169c87ae3f4ffb4b6ff635Paul Mundt printk("PVR=%08x CVR=%08x PRR=%08x\n", 3809d56dd3b083a3bec56e9da35ce07baca81030b03Paul Mundt __raw_readl(CCN_PVR), 3819d56dd3b083a3bec56e9da35ce07baca81030b03Paul Mundt __raw_readl(CCN_CVR), 3829d56dd3b083a3bec56e9da35ce07baca81030b03Paul Mundt __raw_readl(CCN_PRR)); 38337443ef3f0406e855e169c87ae3f4ffb4b6ff635Paul Mundt 384f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt local_flush_icache_range = sh4_flush_icache_range; 385f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt local_flush_dcache_page = sh4_flush_dcache_page; 386f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt local_flush_cache_all = sh4_flush_cache_all; 387f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt local_flush_cache_mm = sh4_flush_cache_mm; 388f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt local_flush_cache_dup_mm = sh4_flush_cache_mm; 389f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt local_flush_cache_page = sh4_flush_cache_page; 390f26b2a562b46ab186c8383993ab1332673ac4a47Paul Mundt local_flush_cache_range = sh4_flush_cache_range; 39137443ef3f0406e855e169c87ae3f4ffb4b6ff635Paul Mundt 39237443ef3f0406e855e169c87ae3f4ffb4b6ff635Paul Mundt sh4__flush_region_init(); 39337443ef3f0406e855e169c87ae3f4ffb4b6ff635Paul Mundt} 394