libahci.c revision 7faa33da9b7add01db9f1ad92c6a5d9145e940a7
1/* 2 * libahci.c - Common AHCI SATA low-level routines 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35#include <linux/kernel.h> 36#include <linux/gfp.h> 37#include <linux/module.h> 38#include <linux/init.h> 39#include <linux/blkdev.h> 40#include <linux/delay.h> 41#include <linux/interrupt.h> 42#include <linux/dma-mapping.h> 43#include <linux/device.h> 44#include <scsi/scsi_host.h> 45#include <scsi/scsi_cmnd.h> 46#include <linux/libata.h> 47#include "ahci.h" 48 49static int ahci_skip_host_reset; 50int ahci_ignore_sss; 51EXPORT_SYMBOL_GPL(ahci_ignore_sss); 52 53module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); 54MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); 55 56module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); 57MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); 58 59static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 60 unsigned hints); 61static ssize_t ahci_led_show(struct ata_port *ap, char *buf); 62static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 63 size_t size); 64static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 65 ssize_t size); 66 67 68 69static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 70static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 71static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); 72static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 73static int ahci_port_start(struct ata_port *ap); 74static void ahci_port_stop(struct ata_port *ap); 75static void ahci_qc_prep(struct ata_queued_cmd *qc); 76static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); 77static void ahci_freeze(struct ata_port *ap); 78static void ahci_thaw(struct ata_port *ap); 79static void ahci_enable_fbs(struct ata_port *ap); 80static void ahci_disable_fbs(struct ata_port *ap); 81static void ahci_pmp_attach(struct ata_port *ap); 82static void ahci_pmp_detach(struct ata_port *ap); 83static int ahci_softreset(struct ata_link *link, unsigned int *class, 84 unsigned long deadline); 85static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 86 unsigned long deadline); 87static int ahci_hardreset(struct ata_link *link, unsigned int *class, 88 unsigned long deadline); 89static void ahci_postreset(struct ata_link *link, unsigned int *class); 90static void ahci_error_handler(struct ata_port *ap); 91static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 92static void ahci_dev_config(struct ata_device *dev); 93#ifdef CONFIG_PM 94static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 95#endif 96static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); 97static ssize_t ahci_activity_store(struct ata_device *dev, 98 enum sw_activity val); 99static void ahci_init_sw_activity(struct ata_link *link); 100 101static ssize_t ahci_show_host_caps(struct device *dev, 102 struct device_attribute *attr, char *buf); 103static ssize_t ahci_show_host_cap2(struct device *dev, 104 struct device_attribute *attr, char *buf); 105static ssize_t ahci_show_host_version(struct device *dev, 106 struct device_attribute *attr, char *buf); 107static ssize_t ahci_show_port_cmd(struct device *dev, 108 struct device_attribute *attr, char *buf); 109static ssize_t ahci_read_em_buffer(struct device *dev, 110 struct device_attribute *attr, char *buf); 111static ssize_t ahci_store_em_buffer(struct device *dev, 112 struct device_attribute *attr, 113 const char *buf, size_t size); 114static ssize_t ahci_show_em_supported(struct device *dev, 115 struct device_attribute *attr, char *buf); 116 117static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); 118static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); 119static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); 120static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); 121static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO, 122 ahci_read_em_buffer, ahci_store_em_buffer); 123static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL); 124 125struct device_attribute *ahci_shost_attrs[] = { 126 &dev_attr_link_power_management_policy, 127 &dev_attr_em_message_type, 128 &dev_attr_em_message, 129 &dev_attr_ahci_host_caps, 130 &dev_attr_ahci_host_cap2, 131 &dev_attr_ahci_host_version, 132 &dev_attr_ahci_port_cmd, 133 &dev_attr_em_buffer, 134 &dev_attr_em_message_supported, 135 NULL 136}; 137EXPORT_SYMBOL_GPL(ahci_shost_attrs); 138 139struct device_attribute *ahci_sdev_attrs[] = { 140 &dev_attr_sw_activity, 141 &dev_attr_unload_heads, 142 NULL 143}; 144EXPORT_SYMBOL_GPL(ahci_sdev_attrs); 145 146struct ata_port_operations ahci_ops = { 147 .inherits = &sata_pmp_port_ops, 148 149 .qc_defer = ahci_pmp_qc_defer, 150 .qc_prep = ahci_qc_prep, 151 .qc_issue = ahci_qc_issue, 152 .qc_fill_rtf = ahci_qc_fill_rtf, 153 154 .freeze = ahci_freeze, 155 .thaw = ahci_thaw, 156 .softreset = ahci_softreset, 157 .hardreset = ahci_hardreset, 158 .postreset = ahci_postreset, 159 .pmp_softreset = ahci_softreset, 160 .error_handler = ahci_error_handler, 161 .post_internal_cmd = ahci_post_internal_cmd, 162 .dev_config = ahci_dev_config, 163 164 .scr_read = ahci_scr_read, 165 .scr_write = ahci_scr_write, 166 .pmp_attach = ahci_pmp_attach, 167 .pmp_detach = ahci_pmp_detach, 168 169 .set_lpm = ahci_set_lpm, 170 .em_show = ahci_led_show, 171 .em_store = ahci_led_store, 172 .sw_activity_show = ahci_activity_show, 173 .sw_activity_store = ahci_activity_store, 174#ifdef CONFIG_PM 175 .port_suspend = ahci_port_suspend, 176 .port_resume = ahci_port_resume, 177#endif 178 .port_start = ahci_port_start, 179 .port_stop = ahci_port_stop, 180}; 181EXPORT_SYMBOL_GPL(ahci_ops); 182 183struct ata_port_operations ahci_pmp_retry_srst_ops = { 184 .inherits = &ahci_ops, 185 .softreset = ahci_pmp_retry_softreset, 186}; 187EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops); 188 189int ahci_em_messages = 1; 190EXPORT_SYMBOL_GPL(ahci_em_messages); 191module_param(ahci_em_messages, int, 0444); 192/* add other LED protocol types when they become supported */ 193MODULE_PARM_DESC(ahci_em_messages, 194 "AHCI Enclosure Management Message control (0 = off, 1 = on)"); 195 196static void ahci_enable_ahci(void __iomem *mmio) 197{ 198 int i; 199 u32 tmp; 200 201 /* turn on AHCI_EN */ 202 tmp = readl(mmio + HOST_CTL); 203 if (tmp & HOST_AHCI_EN) 204 return; 205 206 /* Some controllers need AHCI_EN to be written multiple times. 207 * Try a few times before giving up. 208 */ 209 for (i = 0; i < 5; i++) { 210 tmp |= HOST_AHCI_EN; 211 writel(tmp, mmio + HOST_CTL); 212 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ 213 if (tmp & HOST_AHCI_EN) 214 return; 215 msleep(10); 216 } 217 218 WARN_ON(1); 219} 220 221static ssize_t ahci_show_host_caps(struct device *dev, 222 struct device_attribute *attr, char *buf) 223{ 224 struct Scsi_Host *shost = class_to_shost(dev); 225 struct ata_port *ap = ata_shost_to_port(shost); 226 struct ahci_host_priv *hpriv = ap->host->private_data; 227 228 return sprintf(buf, "%x\n", hpriv->cap); 229} 230 231static ssize_t ahci_show_host_cap2(struct device *dev, 232 struct device_attribute *attr, char *buf) 233{ 234 struct Scsi_Host *shost = class_to_shost(dev); 235 struct ata_port *ap = ata_shost_to_port(shost); 236 struct ahci_host_priv *hpriv = ap->host->private_data; 237 238 return sprintf(buf, "%x\n", hpriv->cap2); 239} 240 241static ssize_t ahci_show_host_version(struct device *dev, 242 struct device_attribute *attr, char *buf) 243{ 244 struct Scsi_Host *shost = class_to_shost(dev); 245 struct ata_port *ap = ata_shost_to_port(shost); 246 struct ahci_host_priv *hpriv = ap->host->private_data; 247 void __iomem *mmio = hpriv->mmio; 248 249 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION)); 250} 251 252static ssize_t ahci_show_port_cmd(struct device *dev, 253 struct device_attribute *attr, char *buf) 254{ 255 struct Scsi_Host *shost = class_to_shost(dev); 256 struct ata_port *ap = ata_shost_to_port(shost); 257 void __iomem *port_mmio = ahci_port_base(ap); 258 259 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); 260} 261 262static ssize_t ahci_read_em_buffer(struct device *dev, 263 struct device_attribute *attr, char *buf) 264{ 265 struct Scsi_Host *shost = class_to_shost(dev); 266 struct ata_port *ap = ata_shost_to_port(shost); 267 struct ahci_host_priv *hpriv = ap->host->private_data; 268 void __iomem *mmio = hpriv->mmio; 269 void __iomem *em_mmio = mmio + hpriv->em_loc; 270 u32 em_ctl, msg; 271 unsigned long flags; 272 size_t count; 273 int i; 274 275 spin_lock_irqsave(ap->lock, flags); 276 277 em_ctl = readl(mmio + HOST_EM_CTL); 278 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT || 279 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) { 280 spin_unlock_irqrestore(ap->lock, flags); 281 return -EINVAL; 282 } 283 284 if (!(em_ctl & EM_CTL_MR)) { 285 spin_unlock_irqrestore(ap->lock, flags); 286 return -EAGAIN; 287 } 288 289 if (!(em_ctl & EM_CTL_SMB)) 290 em_mmio += hpriv->em_buf_sz; 291 292 count = hpriv->em_buf_sz; 293 294 /* the count should not be larger than PAGE_SIZE */ 295 if (count > PAGE_SIZE) { 296 if (printk_ratelimit()) 297 ata_port_warn(ap, 298 "EM read buffer size too large: " 299 "buffer size %u, page size %lu\n", 300 hpriv->em_buf_sz, PAGE_SIZE); 301 count = PAGE_SIZE; 302 } 303 304 for (i = 0; i < count; i += 4) { 305 msg = readl(em_mmio + i); 306 buf[i] = msg & 0xff; 307 buf[i + 1] = (msg >> 8) & 0xff; 308 buf[i + 2] = (msg >> 16) & 0xff; 309 buf[i + 3] = (msg >> 24) & 0xff; 310 } 311 312 spin_unlock_irqrestore(ap->lock, flags); 313 314 return i; 315} 316 317static ssize_t ahci_store_em_buffer(struct device *dev, 318 struct device_attribute *attr, 319 const char *buf, size_t size) 320{ 321 struct Scsi_Host *shost = class_to_shost(dev); 322 struct ata_port *ap = ata_shost_to_port(shost); 323 struct ahci_host_priv *hpriv = ap->host->private_data; 324 void __iomem *mmio = hpriv->mmio; 325 void __iomem *em_mmio = mmio + hpriv->em_loc; 326 const unsigned char *msg_buf = buf; 327 u32 em_ctl, msg; 328 unsigned long flags; 329 int i; 330 331 /* check size validity */ 332 if (!(ap->flags & ATA_FLAG_EM) || 333 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) || 334 size % 4 || size > hpriv->em_buf_sz) 335 return -EINVAL; 336 337 spin_lock_irqsave(ap->lock, flags); 338 339 em_ctl = readl(mmio + HOST_EM_CTL); 340 if (em_ctl & EM_CTL_TM) { 341 spin_unlock_irqrestore(ap->lock, flags); 342 return -EBUSY; 343 } 344 345 for (i = 0; i < size; i += 4) { 346 msg = msg_buf[i] | msg_buf[i + 1] << 8 | 347 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24; 348 writel(msg, em_mmio + i); 349 } 350 351 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 352 353 spin_unlock_irqrestore(ap->lock, flags); 354 355 return size; 356} 357 358static ssize_t ahci_show_em_supported(struct device *dev, 359 struct device_attribute *attr, char *buf) 360{ 361 struct Scsi_Host *shost = class_to_shost(dev); 362 struct ata_port *ap = ata_shost_to_port(shost); 363 struct ahci_host_priv *hpriv = ap->host->private_data; 364 void __iomem *mmio = hpriv->mmio; 365 u32 em_ctl; 366 367 em_ctl = readl(mmio + HOST_EM_CTL); 368 369 return sprintf(buf, "%s%s%s%s\n", 370 em_ctl & EM_CTL_LED ? "led " : "", 371 em_ctl & EM_CTL_SAFTE ? "saf-te " : "", 372 em_ctl & EM_CTL_SES ? "ses-2 " : "", 373 em_ctl & EM_CTL_SGPIO ? "sgpio " : ""); 374} 375 376/** 377 * ahci_save_initial_config - Save and fixup initial config values 378 * @dev: target AHCI device 379 * @hpriv: host private area to store config values 380 * @force_port_map: force port map to a specified value 381 * @mask_port_map: mask out particular bits from port map 382 * 383 * Some registers containing configuration info might be setup by 384 * BIOS and might be cleared on reset. This function saves the 385 * initial values of those registers into @hpriv such that they 386 * can be restored after controller reset. 387 * 388 * If inconsistent, config values are fixed up by this function. 389 * 390 * LOCKING: 391 * None. 392 */ 393void ahci_save_initial_config(struct device *dev, 394 struct ahci_host_priv *hpriv, 395 unsigned int force_port_map, 396 unsigned int mask_port_map) 397{ 398 void __iomem *mmio = hpriv->mmio; 399 u32 cap, cap2, vers, port_map; 400 int i; 401 402 /* make sure AHCI mode is enabled before accessing CAP */ 403 ahci_enable_ahci(mmio); 404 405 /* Values prefixed with saved_ are written back to host after 406 * reset. Values without are used for driver operation. 407 */ 408 hpriv->saved_cap = cap = readl(mmio + HOST_CAP); 409 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); 410 411 /* CAP2 register is only defined for AHCI 1.2 and later */ 412 vers = readl(mmio + HOST_VERSION); 413 if ((vers >> 16) > 1 || 414 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) 415 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); 416 else 417 hpriv->saved_cap2 = cap2 = 0; 418 419 /* some chips have errata preventing 64bit use */ 420 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 421 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n"); 422 cap &= ~HOST_CAP_64; 423 } 424 425 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 426 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n"); 427 cap &= ~HOST_CAP_NCQ; 428 } 429 430 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { 431 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n"); 432 cap |= HOST_CAP_NCQ; 433 } 434 435 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 436 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n"); 437 cap &= ~HOST_CAP_PMP; 438 } 439 440 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { 441 dev_info(dev, 442 "controller can't do SNTF, turning off CAP_SNTF\n"); 443 cap &= ~HOST_CAP_SNTF; 444 } 445 446 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) { 447 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n"); 448 cap |= HOST_CAP_FBS; 449 } 450 451 if (force_port_map && port_map != force_port_map) { 452 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n", 453 port_map, force_port_map); 454 port_map = force_port_map; 455 } 456 457 if (mask_port_map) { 458 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n", 459 port_map, 460 port_map & mask_port_map); 461 port_map &= mask_port_map; 462 } 463 464 /* cross check port_map and cap.n_ports */ 465 if (port_map) { 466 int map_ports = 0; 467 468 for (i = 0; i < AHCI_MAX_PORTS; i++) 469 if (port_map & (1 << i)) 470 map_ports++; 471 472 /* If PI has more ports than n_ports, whine, clear 473 * port_map and let it be generated from n_ports. 474 */ 475 if (map_ports > ahci_nr_ports(cap)) { 476 dev_warn(dev, 477 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n", 478 port_map, ahci_nr_ports(cap)); 479 port_map = 0; 480 } 481 } 482 483 /* fabricate port_map from cap.nr_ports */ 484 if (!port_map) { 485 port_map = (1 << ahci_nr_ports(cap)) - 1; 486 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map); 487 488 /* write the fixed up value to the PI register */ 489 hpriv->saved_port_map = port_map; 490 } 491 492 /* record values to use during operation */ 493 hpriv->cap = cap; 494 hpriv->cap2 = cap2; 495 hpriv->port_map = port_map; 496} 497EXPORT_SYMBOL_GPL(ahci_save_initial_config); 498 499/** 500 * ahci_restore_initial_config - Restore initial config 501 * @host: target ATA host 502 * 503 * Restore initial config stored by ahci_save_initial_config(). 504 * 505 * LOCKING: 506 * None. 507 */ 508static void ahci_restore_initial_config(struct ata_host *host) 509{ 510 struct ahci_host_priv *hpriv = host->private_data; 511 void __iomem *mmio = hpriv->mmio; 512 513 writel(hpriv->saved_cap, mmio + HOST_CAP); 514 if (hpriv->saved_cap2) 515 writel(hpriv->saved_cap2, mmio + HOST_CAP2); 516 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 517 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 518} 519 520static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 521{ 522 static const int offset[] = { 523 [SCR_STATUS] = PORT_SCR_STAT, 524 [SCR_CONTROL] = PORT_SCR_CTL, 525 [SCR_ERROR] = PORT_SCR_ERR, 526 [SCR_ACTIVE] = PORT_SCR_ACT, 527 [SCR_NOTIFICATION] = PORT_SCR_NTF, 528 }; 529 struct ahci_host_priv *hpriv = ap->host->private_data; 530 531 if (sc_reg < ARRAY_SIZE(offset) && 532 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 533 return offset[sc_reg]; 534 return 0; 535} 536 537static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 538{ 539 void __iomem *port_mmio = ahci_port_base(link->ap); 540 int offset = ahci_scr_offset(link->ap, sc_reg); 541 542 if (offset) { 543 *val = readl(port_mmio + offset); 544 return 0; 545 } 546 return -EINVAL; 547} 548 549static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 550{ 551 void __iomem *port_mmio = ahci_port_base(link->ap); 552 int offset = ahci_scr_offset(link->ap, sc_reg); 553 554 if (offset) { 555 writel(val, port_mmio + offset); 556 return 0; 557 } 558 return -EINVAL; 559} 560 561void ahci_start_engine(struct ata_port *ap) 562{ 563 void __iomem *port_mmio = ahci_port_base(ap); 564 u32 tmp; 565 566 /* start DMA */ 567 tmp = readl(port_mmio + PORT_CMD); 568 tmp |= PORT_CMD_START; 569 writel(tmp, port_mmio + PORT_CMD); 570 readl(port_mmio + PORT_CMD); /* flush */ 571} 572EXPORT_SYMBOL_GPL(ahci_start_engine); 573 574int ahci_stop_engine(struct ata_port *ap) 575{ 576 void __iomem *port_mmio = ahci_port_base(ap); 577 u32 tmp; 578 579 tmp = readl(port_mmio + PORT_CMD); 580 581 /* check if the HBA is idle */ 582 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 583 return 0; 584 585 /* setting HBA to idle */ 586 tmp &= ~PORT_CMD_START; 587 writel(tmp, port_mmio + PORT_CMD); 588 589 /* wait for engine to stop. This could be as long as 500 msec */ 590 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 591 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 592 if (tmp & PORT_CMD_LIST_ON) 593 return -EIO; 594 595 return 0; 596} 597EXPORT_SYMBOL_GPL(ahci_stop_engine); 598 599static void ahci_start_fis_rx(struct ata_port *ap) 600{ 601 void __iomem *port_mmio = ahci_port_base(ap); 602 struct ahci_host_priv *hpriv = ap->host->private_data; 603 struct ahci_port_priv *pp = ap->private_data; 604 u32 tmp; 605 606 /* set FIS registers */ 607 if (hpriv->cap & HOST_CAP_64) 608 writel((pp->cmd_slot_dma >> 16) >> 16, 609 port_mmio + PORT_LST_ADDR_HI); 610 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 611 612 if (hpriv->cap & HOST_CAP_64) 613 writel((pp->rx_fis_dma >> 16) >> 16, 614 port_mmio + PORT_FIS_ADDR_HI); 615 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 616 617 /* enable FIS reception */ 618 tmp = readl(port_mmio + PORT_CMD); 619 tmp |= PORT_CMD_FIS_RX; 620 writel(tmp, port_mmio + PORT_CMD); 621 622 /* flush */ 623 readl(port_mmio + PORT_CMD); 624} 625 626static int ahci_stop_fis_rx(struct ata_port *ap) 627{ 628 void __iomem *port_mmio = ahci_port_base(ap); 629 u32 tmp; 630 631 /* disable FIS reception */ 632 tmp = readl(port_mmio + PORT_CMD); 633 tmp &= ~PORT_CMD_FIS_RX; 634 writel(tmp, port_mmio + PORT_CMD); 635 636 /* wait for completion, spec says 500ms, give it 1000 */ 637 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 638 PORT_CMD_FIS_ON, 10, 1000); 639 if (tmp & PORT_CMD_FIS_ON) 640 return -EBUSY; 641 642 return 0; 643} 644 645static void ahci_power_up(struct ata_port *ap) 646{ 647 struct ahci_host_priv *hpriv = ap->host->private_data; 648 void __iomem *port_mmio = ahci_port_base(ap); 649 u32 cmd; 650 651 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 652 653 /* spin up device */ 654 if (hpriv->cap & HOST_CAP_SSS) { 655 cmd |= PORT_CMD_SPIN_UP; 656 writel(cmd, port_mmio + PORT_CMD); 657 } 658 659 /* wake up link */ 660 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 661} 662 663static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 664 unsigned int hints) 665{ 666 struct ata_port *ap = link->ap; 667 struct ahci_host_priv *hpriv = ap->host->private_data; 668 struct ahci_port_priv *pp = ap->private_data; 669 void __iomem *port_mmio = ahci_port_base(ap); 670 671 if (policy != ATA_LPM_MAX_POWER) { 672 /* 673 * Disable interrupts on Phy Ready. This keeps us from 674 * getting woken up due to spurious phy ready 675 * interrupts. 676 */ 677 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 678 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 679 680 sata_link_scr_lpm(link, policy, false); 681 } 682 683 if (hpriv->cap & HOST_CAP_ALPM) { 684 u32 cmd = readl(port_mmio + PORT_CMD); 685 686 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) { 687 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE); 688 cmd |= PORT_CMD_ICC_ACTIVE; 689 690 writel(cmd, port_mmio + PORT_CMD); 691 readl(port_mmio + PORT_CMD); 692 693 /* wait 10ms to be sure we've come out of LPM state */ 694 ata_msleep(ap, 10); 695 } else { 696 cmd |= PORT_CMD_ALPE; 697 if (policy == ATA_LPM_MIN_POWER) 698 cmd |= PORT_CMD_ASP; 699 700 /* write out new cmd value */ 701 writel(cmd, port_mmio + PORT_CMD); 702 } 703 } 704 705 if (policy == ATA_LPM_MAX_POWER) { 706 sata_link_scr_lpm(link, policy, false); 707 708 /* turn PHYRDY IRQ back on */ 709 pp->intr_mask |= PORT_IRQ_PHYRDY; 710 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 711 } 712 713 return 0; 714} 715 716#ifdef CONFIG_PM 717static void ahci_power_down(struct ata_port *ap) 718{ 719 struct ahci_host_priv *hpriv = ap->host->private_data; 720 void __iomem *port_mmio = ahci_port_base(ap); 721 u32 cmd, scontrol; 722 723 if (!(hpriv->cap & HOST_CAP_SSS)) 724 return; 725 726 /* put device into listen mode, first set PxSCTL.DET to 0 */ 727 scontrol = readl(port_mmio + PORT_SCR_CTL); 728 scontrol &= ~0xf; 729 writel(scontrol, port_mmio + PORT_SCR_CTL); 730 731 /* then set PxCMD.SUD to 0 */ 732 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 733 cmd &= ~PORT_CMD_SPIN_UP; 734 writel(cmd, port_mmio + PORT_CMD); 735} 736#endif 737 738static void ahci_start_port(struct ata_port *ap) 739{ 740 struct ahci_port_priv *pp = ap->private_data; 741 struct ata_link *link; 742 struct ahci_em_priv *emp; 743 ssize_t rc; 744 int i; 745 746 /* enable FIS reception */ 747 ahci_start_fis_rx(ap); 748 749 /* turn on LEDs */ 750 if (ap->flags & ATA_FLAG_EM) { 751 ata_for_each_link(link, ap, EDGE) { 752 emp = &pp->em_priv[link->pmp]; 753 754 /* EM Transmit bit maybe busy during init */ 755 for (i = 0; i < EM_MAX_RETRY; i++) { 756 rc = ahci_transmit_led_message(ap, 757 emp->led_state, 758 4); 759 if (rc == -EBUSY) 760 ata_msleep(ap, 1); 761 else 762 break; 763 } 764 } 765 } 766 767 if (ap->flags & ATA_FLAG_SW_ACTIVITY) 768 ata_for_each_link(link, ap, EDGE) 769 ahci_init_sw_activity(link); 770 771} 772 773static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 774{ 775 int rc; 776 777 /* disable DMA */ 778 rc = ahci_stop_engine(ap); 779 if (rc) { 780 *emsg = "failed to stop engine"; 781 return rc; 782 } 783 784 /* disable FIS reception */ 785 rc = ahci_stop_fis_rx(ap); 786 if (rc) { 787 *emsg = "failed stop FIS RX"; 788 return rc; 789 } 790 791 return 0; 792} 793 794int ahci_reset_controller(struct ata_host *host) 795{ 796 struct ahci_host_priv *hpriv = host->private_data; 797 void __iomem *mmio = hpriv->mmio; 798 u32 tmp; 799 800 /* we must be in AHCI mode, before using anything 801 * AHCI-specific, such as HOST_RESET. 802 */ 803 ahci_enable_ahci(mmio); 804 805 /* global controller reset */ 806 if (!ahci_skip_host_reset) { 807 tmp = readl(mmio + HOST_CTL); 808 if ((tmp & HOST_RESET) == 0) { 809 writel(tmp | HOST_RESET, mmio + HOST_CTL); 810 readl(mmio + HOST_CTL); /* flush */ 811 } 812 813 /* 814 * to perform host reset, OS should set HOST_RESET 815 * and poll until this bit is read to be "0". 816 * reset must complete within 1 second, or 817 * the hardware should be considered fried. 818 */ 819 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET, 820 HOST_RESET, 10, 1000); 821 822 if (tmp & HOST_RESET) { 823 dev_err(host->dev, "controller reset failed (0x%x)\n", 824 tmp); 825 return -EIO; 826 } 827 828 /* turn on AHCI mode */ 829 ahci_enable_ahci(mmio); 830 831 /* Some registers might be cleared on reset. Restore 832 * initial values. 833 */ 834 ahci_restore_initial_config(host); 835 } else 836 dev_info(host->dev, "skipping global host reset\n"); 837 838 return 0; 839} 840EXPORT_SYMBOL_GPL(ahci_reset_controller); 841 842static void ahci_sw_activity(struct ata_link *link) 843{ 844 struct ata_port *ap = link->ap; 845 struct ahci_port_priv *pp = ap->private_data; 846 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 847 848 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) 849 return; 850 851 emp->activity++; 852 if (!timer_pending(&emp->timer)) 853 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); 854} 855 856static void ahci_sw_activity_blink(unsigned long arg) 857{ 858 struct ata_link *link = (struct ata_link *)arg; 859 struct ata_port *ap = link->ap; 860 struct ahci_port_priv *pp = ap->private_data; 861 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 862 unsigned long led_message = emp->led_state; 863 u32 activity_led_state; 864 unsigned long flags; 865 866 led_message &= EM_MSG_LED_VALUE; 867 led_message |= ap->port_no | (link->pmp << 8); 868 869 /* check to see if we've had activity. If so, 870 * toggle state of LED and reset timer. If not, 871 * turn LED to desired idle state. 872 */ 873 spin_lock_irqsave(ap->lock, flags); 874 if (emp->saved_activity != emp->activity) { 875 emp->saved_activity = emp->activity; 876 /* get the current LED state */ 877 activity_led_state = led_message & EM_MSG_LED_VALUE_ON; 878 879 if (activity_led_state) 880 activity_led_state = 0; 881 else 882 activity_led_state = 1; 883 884 /* clear old state */ 885 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 886 887 /* toggle state */ 888 led_message |= (activity_led_state << 16); 889 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); 890 } else { 891 /* switch to idle */ 892 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 893 if (emp->blink_policy == BLINK_OFF) 894 led_message |= (1 << 16); 895 } 896 spin_unlock_irqrestore(ap->lock, flags); 897 ahci_transmit_led_message(ap, led_message, 4); 898} 899 900static void ahci_init_sw_activity(struct ata_link *link) 901{ 902 struct ata_port *ap = link->ap; 903 struct ahci_port_priv *pp = ap->private_data; 904 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 905 906 /* init activity stats, setup timer */ 907 emp->saved_activity = emp->activity = 0; 908 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link); 909 910 /* check our blink policy and set flag for link if it's enabled */ 911 if (emp->blink_policy) 912 link->flags |= ATA_LFLAG_SW_ACTIVITY; 913} 914 915int ahci_reset_em(struct ata_host *host) 916{ 917 struct ahci_host_priv *hpriv = host->private_data; 918 void __iomem *mmio = hpriv->mmio; 919 u32 em_ctl; 920 921 em_ctl = readl(mmio + HOST_EM_CTL); 922 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) 923 return -EINVAL; 924 925 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); 926 return 0; 927} 928EXPORT_SYMBOL_GPL(ahci_reset_em); 929 930static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 931 ssize_t size) 932{ 933 struct ahci_host_priv *hpriv = ap->host->private_data; 934 struct ahci_port_priv *pp = ap->private_data; 935 void __iomem *mmio = hpriv->mmio; 936 u32 em_ctl; 937 u32 message[] = {0, 0}; 938 unsigned long flags; 939 int pmp; 940 struct ahci_em_priv *emp; 941 942 /* get the slot number from the message */ 943 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 944 if (pmp < EM_MAX_SLOTS) 945 emp = &pp->em_priv[pmp]; 946 else 947 return -EINVAL; 948 949 spin_lock_irqsave(ap->lock, flags); 950 951 /* 952 * if we are still busy transmitting a previous message, 953 * do not allow 954 */ 955 em_ctl = readl(mmio + HOST_EM_CTL); 956 if (em_ctl & EM_CTL_TM) { 957 spin_unlock_irqrestore(ap->lock, flags); 958 return -EBUSY; 959 } 960 961 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) { 962 /* 963 * create message header - this is all zero except for 964 * the message size, which is 4 bytes. 965 */ 966 message[0] |= (4 << 8); 967 968 /* ignore 0:4 of byte zero, fill in port info yourself */ 969 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); 970 971 /* write message to EM_LOC */ 972 writel(message[0], mmio + hpriv->em_loc); 973 writel(message[1], mmio + hpriv->em_loc+4); 974 975 /* 976 * tell hardware to transmit the message 977 */ 978 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 979 } 980 981 /* save off new led state for port/slot */ 982 emp->led_state = state; 983 984 spin_unlock_irqrestore(ap->lock, flags); 985 return size; 986} 987 988static ssize_t ahci_led_show(struct ata_port *ap, char *buf) 989{ 990 struct ahci_port_priv *pp = ap->private_data; 991 struct ata_link *link; 992 struct ahci_em_priv *emp; 993 int rc = 0; 994 995 ata_for_each_link(link, ap, EDGE) { 996 emp = &pp->em_priv[link->pmp]; 997 rc += sprintf(buf, "%lx\n", emp->led_state); 998 } 999 return rc; 1000} 1001 1002static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 1003 size_t size) 1004{ 1005 int state; 1006 int pmp; 1007 struct ahci_port_priv *pp = ap->private_data; 1008 struct ahci_em_priv *emp; 1009 1010 state = simple_strtoul(buf, NULL, 0); 1011 1012 /* get the slot number from the message */ 1013 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1014 if (pmp < EM_MAX_SLOTS) 1015 emp = &pp->em_priv[pmp]; 1016 else 1017 return -EINVAL; 1018 1019 /* mask off the activity bits if we are in sw_activity 1020 * mode, user should turn off sw_activity before setting 1021 * activity led through em_message 1022 */ 1023 if (emp->blink_policy) 1024 state &= ~EM_MSG_LED_VALUE_ACTIVITY; 1025 1026 return ahci_transmit_led_message(ap, state, size); 1027} 1028 1029static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) 1030{ 1031 struct ata_link *link = dev->link; 1032 struct ata_port *ap = link->ap; 1033 struct ahci_port_priv *pp = ap->private_data; 1034 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1035 u32 port_led_state = emp->led_state; 1036 1037 /* save the desired Activity LED behavior */ 1038 if (val == OFF) { 1039 /* clear LFLAG */ 1040 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); 1041 1042 /* set the LED to OFF */ 1043 port_led_state &= EM_MSG_LED_VALUE_OFF; 1044 port_led_state |= (ap->port_no | (link->pmp << 8)); 1045 ahci_transmit_led_message(ap, port_led_state, 4); 1046 } else { 1047 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1048 if (val == BLINK_OFF) { 1049 /* set LED to ON for idle */ 1050 port_led_state &= EM_MSG_LED_VALUE_OFF; 1051 port_led_state |= (ap->port_no | (link->pmp << 8)); 1052 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ 1053 ahci_transmit_led_message(ap, port_led_state, 4); 1054 } 1055 } 1056 emp->blink_policy = val; 1057 return 0; 1058} 1059 1060static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) 1061{ 1062 struct ata_link *link = dev->link; 1063 struct ata_port *ap = link->ap; 1064 struct ahci_port_priv *pp = ap->private_data; 1065 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1066 1067 /* display the saved value of activity behavior for this 1068 * disk. 1069 */ 1070 return sprintf(buf, "%d\n", emp->blink_policy); 1071} 1072 1073static void ahci_port_init(struct device *dev, struct ata_port *ap, 1074 int port_no, void __iomem *mmio, 1075 void __iomem *port_mmio) 1076{ 1077 const char *emsg = NULL; 1078 int rc; 1079 u32 tmp; 1080 1081 /* make sure port is not active */ 1082 rc = ahci_deinit_port(ap, &emsg); 1083 if (rc) 1084 dev_warn(dev, "%s (%d)\n", emsg, rc); 1085 1086 /* clear SError */ 1087 tmp = readl(port_mmio + PORT_SCR_ERR); 1088 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); 1089 writel(tmp, port_mmio + PORT_SCR_ERR); 1090 1091 /* clear port IRQ */ 1092 tmp = readl(port_mmio + PORT_IRQ_STAT); 1093 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1094 if (tmp) 1095 writel(tmp, port_mmio + PORT_IRQ_STAT); 1096 1097 writel(1 << port_no, mmio + HOST_IRQ_STAT); 1098} 1099 1100void ahci_init_controller(struct ata_host *host) 1101{ 1102 struct ahci_host_priv *hpriv = host->private_data; 1103 void __iomem *mmio = hpriv->mmio; 1104 int i; 1105 void __iomem *port_mmio; 1106 u32 tmp; 1107 1108 for (i = 0; i < host->n_ports; i++) { 1109 struct ata_port *ap = host->ports[i]; 1110 1111 port_mmio = ahci_port_base(ap); 1112 if (ata_port_is_dummy(ap)) 1113 continue; 1114 1115 ahci_port_init(host->dev, ap, i, mmio, port_mmio); 1116 } 1117 1118 tmp = readl(mmio + HOST_CTL); 1119 VPRINTK("HOST_CTL 0x%x\n", tmp); 1120 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1121 tmp = readl(mmio + HOST_CTL); 1122 VPRINTK("HOST_CTL 0x%x\n", tmp); 1123} 1124EXPORT_SYMBOL_GPL(ahci_init_controller); 1125 1126static void ahci_dev_config(struct ata_device *dev) 1127{ 1128 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; 1129 1130 if (hpriv->flags & AHCI_HFLAG_SECT255) { 1131 dev->max_sectors = 255; 1132 ata_dev_info(dev, 1133 "SB600 AHCI: limiting to 255 sectors per cmd\n"); 1134 } 1135} 1136 1137static unsigned int ahci_dev_classify(struct ata_port *ap) 1138{ 1139 void __iomem *port_mmio = ahci_port_base(ap); 1140 struct ata_taskfile tf; 1141 u32 tmp; 1142 1143 tmp = readl(port_mmio + PORT_SIG); 1144 tf.lbah = (tmp >> 24) & 0xff; 1145 tf.lbam = (tmp >> 16) & 0xff; 1146 tf.lbal = (tmp >> 8) & 0xff; 1147 tf.nsect = (tmp) & 0xff; 1148 1149 return ata_dev_classify(&tf); 1150} 1151 1152void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1153 u32 opts) 1154{ 1155 dma_addr_t cmd_tbl_dma; 1156 1157 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1158 1159 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1160 pp->cmd_slot[tag].status = 0; 1161 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1162 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1163} 1164EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot); 1165 1166int ahci_kick_engine(struct ata_port *ap) 1167{ 1168 void __iomem *port_mmio = ahci_port_base(ap); 1169 struct ahci_host_priv *hpriv = ap->host->private_data; 1170 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1171 u32 tmp; 1172 int busy, rc; 1173 1174 /* stop engine */ 1175 rc = ahci_stop_engine(ap); 1176 if (rc) 1177 goto out_restart; 1178 1179 /* need to do CLO? 1180 * always do CLO if PMP is attached (AHCI-1.3 9.2) 1181 */ 1182 busy = status & (ATA_BUSY | ATA_DRQ); 1183 if (!busy && !sata_pmp_attached(ap)) { 1184 rc = 0; 1185 goto out_restart; 1186 } 1187 1188 if (!(hpriv->cap & HOST_CAP_CLO)) { 1189 rc = -EOPNOTSUPP; 1190 goto out_restart; 1191 } 1192 1193 /* perform CLO */ 1194 tmp = readl(port_mmio + PORT_CMD); 1195 tmp |= PORT_CMD_CLO; 1196 writel(tmp, port_mmio + PORT_CMD); 1197 1198 rc = 0; 1199 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 1200 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1201 if (tmp & PORT_CMD_CLO) 1202 rc = -EIO; 1203 1204 /* restart engine */ 1205 out_restart: 1206 ahci_start_engine(ap); 1207 return rc; 1208} 1209EXPORT_SYMBOL_GPL(ahci_kick_engine); 1210 1211static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1212 struct ata_taskfile *tf, int is_cmd, u16 flags, 1213 unsigned long timeout_msec) 1214{ 1215 const u32 cmd_fis_len = 5; /* five dwords */ 1216 struct ahci_port_priv *pp = ap->private_data; 1217 void __iomem *port_mmio = ahci_port_base(ap); 1218 u8 *fis = pp->cmd_tbl; 1219 u32 tmp; 1220 1221 /* prep the command */ 1222 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1223 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1224 1225 /* issue & wait */ 1226 writel(1, port_mmio + PORT_CMD_ISSUE); 1227 1228 if (timeout_msec) { 1229 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE, 1230 0x1, 0x1, 1, timeout_msec); 1231 if (tmp & 0x1) { 1232 ahci_kick_engine(ap); 1233 return -EBUSY; 1234 } 1235 } else 1236 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1237 1238 return 0; 1239} 1240 1241int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1242 int pmp, unsigned long deadline, 1243 int (*check_ready)(struct ata_link *link)) 1244{ 1245 struct ata_port *ap = link->ap; 1246 struct ahci_host_priv *hpriv = ap->host->private_data; 1247 const char *reason = NULL; 1248 unsigned long now, msecs; 1249 struct ata_taskfile tf; 1250 int rc; 1251 1252 DPRINTK("ENTER\n"); 1253 1254 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1255 rc = ahci_kick_engine(ap); 1256 if (rc && rc != -EOPNOTSUPP) 1257 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc); 1258 1259 ata_tf_init(link->device, &tf); 1260 1261 /* issue the first D2H Register FIS */ 1262 msecs = 0; 1263 now = jiffies; 1264 if (time_after(deadline, now)) 1265 msecs = jiffies_to_msecs(deadline - now); 1266 1267 tf.ctl |= ATA_SRST; 1268 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1269 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1270 rc = -EIO; 1271 reason = "1st FIS failed"; 1272 goto fail; 1273 } 1274 1275 /* spec says at least 5us, but be generous and sleep for 1ms */ 1276 ata_msleep(ap, 1); 1277 1278 /* issue the second D2H Register FIS */ 1279 tf.ctl &= ~ATA_SRST; 1280 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1281 1282 /* wait for link to become ready */ 1283 rc = ata_wait_after_reset(link, deadline, check_ready); 1284 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { 1285 /* 1286 * Workaround for cases where link online status can't 1287 * be trusted. Treat device readiness timeout as link 1288 * offline. 1289 */ 1290 ata_link_info(link, "device not ready, treating as offline\n"); 1291 *class = ATA_DEV_NONE; 1292 } else if (rc) { 1293 /* link occupied, -ENODEV too is an error */ 1294 reason = "device not ready"; 1295 goto fail; 1296 } else 1297 *class = ahci_dev_classify(ap); 1298 1299 DPRINTK("EXIT, class=%u\n", *class); 1300 return 0; 1301 1302 fail: 1303 ata_link_err(link, "softreset failed (%s)\n", reason); 1304 return rc; 1305} 1306 1307int ahci_check_ready(struct ata_link *link) 1308{ 1309 void __iomem *port_mmio = ahci_port_base(link->ap); 1310 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1311 1312 return ata_check_ready(status); 1313} 1314EXPORT_SYMBOL_GPL(ahci_check_ready); 1315 1316static int ahci_softreset(struct ata_link *link, unsigned int *class, 1317 unsigned long deadline) 1318{ 1319 int pmp = sata_srst_pmp(link); 1320 1321 DPRINTK("ENTER\n"); 1322 1323 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 1324} 1325EXPORT_SYMBOL_GPL(ahci_do_softreset); 1326 1327static int ahci_bad_pmp_check_ready(struct ata_link *link) 1328{ 1329 void __iomem *port_mmio = ahci_port_base(link->ap); 1330 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1331 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); 1332 1333 /* 1334 * There is no need to check TFDATA if BAD PMP is found due to HW bug, 1335 * which can save timeout delay. 1336 */ 1337 if (irq_status & PORT_IRQ_BAD_PMP) 1338 return -EIO; 1339 1340 return ata_check_ready(status); 1341} 1342 1343int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 1344 unsigned long deadline) 1345{ 1346 struct ata_port *ap = link->ap; 1347 void __iomem *port_mmio = ahci_port_base(ap); 1348 int pmp = sata_srst_pmp(link); 1349 int rc; 1350 u32 irq_sts; 1351 1352 DPRINTK("ENTER\n"); 1353 1354 rc = ahci_do_softreset(link, class, pmp, deadline, 1355 ahci_bad_pmp_check_ready); 1356 1357 /* 1358 * Soft reset fails with IPMS set when PMP is enabled but 1359 * SATA HDD/ODD is connected to SATA port, do soft reset 1360 * again to port 0. 1361 */ 1362 if (rc == -EIO) { 1363 irq_sts = readl(port_mmio + PORT_IRQ_STAT); 1364 if (irq_sts & PORT_IRQ_BAD_PMP) { 1365 ata_link_printk(link, KERN_WARNING, 1366 "applying PMP SRST workaround " 1367 "and retrying\n"); 1368 rc = ahci_do_softreset(link, class, 0, deadline, 1369 ahci_check_ready); 1370 } 1371 } 1372 1373 return rc; 1374} 1375 1376static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1377 unsigned long deadline) 1378{ 1379 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 1380 struct ata_port *ap = link->ap; 1381 struct ahci_port_priv *pp = ap->private_data; 1382 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1383 struct ata_taskfile tf; 1384 bool online; 1385 int rc; 1386 1387 DPRINTK("ENTER\n"); 1388 1389 ahci_stop_engine(ap); 1390 1391 /* clear D2H reception area to properly wait for D2H FIS */ 1392 ata_tf_init(link->device, &tf); 1393 tf.command = 0x80; 1394 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1395 1396 rc = sata_link_hardreset(link, timing, deadline, &online, 1397 ahci_check_ready); 1398 1399 ahci_start_engine(ap); 1400 1401 if (online) 1402 *class = ahci_dev_classify(ap); 1403 1404 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1405 return rc; 1406} 1407 1408static void ahci_postreset(struct ata_link *link, unsigned int *class) 1409{ 1410 struct ata_port *ap = link->ap; 1411 void __iomem *port_mmio = ahci_port_base(ap); 1412 u32 new_tmp, tmp; 1413 1414 ata_std_postreset(link, class); 1415 1416 /* Make sure port's ATAPI bit is set appropriately */ 1417 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1418 if (*class == ATA_DEV_ATAPI) 1419 new_tmp |= PORT_CMD_ATAPI; 1420 else 1421 new_tmp &= ~PORT_CMD_ATAPI; 1422 if (new_tmp != tmp) { 1423 writel(new_tmp, port_mmio + PORT_CMD); 1424 readl(port_mmio + PORT_CMD); /* flush */ 1425 } 1426} 1427 1428static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1429{ 1430 struct scatterlist *sg; 1431 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1432 unsigned int si; 1433 1434 VPRINTK("ENTER\n"); 1435 1436 /* 1437 * Next, the S/G list. 1438 */ 1439 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1440 dma_addr_t addr = sg_dma_address(sg); 1441 u32 sg_len = sg_dma_len(sg); 1442 1443 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 1444 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 1445 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); 1446 } 1447 1448 return si; 1449} 1450 1451static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) 1452{ 1453 struct ata_port *ap = qc->ap; 1454 struct ahci_port_priv *pp = ap->private_data; 1455 1456 if (!sata_pmp_attached(ap) || pp->fbs_enabled) 1457 return ata_std_qc_defer(qc); 1458 else 1459 return sata_pmp_qc_defer_cmd_switch(qc); 1460} 1461 1462static void ahci_qc_prep(struct ata_queued_cmd *qc) 1463{ 1464 struct ata_port *ap = qc->ap; 1465 struct ahci_port_priv *pp = ap->private_data; 1466 int is_atapi = ata_is_atapi(qc->tf.protocol); 1467 void *cmd_tbl; 1468 u32 opts; 1469 const u32 cmd_fis_len = 5; /* five dwords */ 1470 unsigned int n_elem; 1471 1472 /* 1473 * Fill in command table information. First, the header, 1474 * a SATA Register - Host to Device command FIS. 1475 */ 1476 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; 1477 1478 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1479 if (is_atapi) { 1480 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1481 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1482 } 1483 1484 n_elem = 0; 1485 if (qc->flags & ATA_QCFLAG_DMAMAP) 1486 n_elem = ahci_fill_sg(qc, cmd_tbl); 1487 1488 /* 1489 * Fill in command slot information. 1490 */ 1491 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1492 if (qc->tf.flags & ATA_TFLAG_WRITE) 1493 opts |= AHCI_CMD_WRITE; 1494 if (is_atapi) 1495 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1496 1497 ahci_fill_cmd_slot(pp, qc->tag, opts); 1498} 1499 1500static void ahci_fbs_dec_intr(struct ata_port *ap) 1501{ 1502 struct ahci_port_priv *pp = ap->private_data; 1503 void __iomem *port_mmio = ahci_port_base(ap); 1504 u32 fbs = readl(port_mmio + PORT_FBS); 1505 int retries = 3; 1506 1507 DPRINTK("ENTER\n"); 1508 BUG_ON(!pp->fbs_enabled); 1509 1510 /* time to wait for DEC is not specified by AHCI spec, 1511 * add a retry loop for safety. 1512 */ 1513 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); 1514 fbs = readl(port_mmio + PORT_FBS); 1515 while ((fbs & PORT_FBS_DEC) && retries--) { 1516 udelay(1); 1517 fbs = readl(port_mmio + PORT_FBS); 1518 } 1519 1520 if (fbs & PORT_FBS_DEC) 1521 dev_err(ap->host->dev, "failed to clear device error\n"); 1522} 1523 1524static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1525{ 1526 struct ahci_host_priv *hpriv = ap->host->private_data; 1527 struct ahci_port_priv *pp = ap->private_data; 1528 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1529 struct ata_link *link = NULL; 1530 struct ata_queued_cmd *active_qc; 1531 struct ata_eh_info *active_ehi; 1532 bool fbs_need_dec = false; 1533 u32 serror; 1534 1535 /* determine active link with error */ 1536 if (pp->fbs_enabled) { 1537 void __iomem *port_mmio = ahci_port_base(ap); 1538 u32 fbs = readl(port_mmio + PORT_FBS); 1539 int pmp = fbs >> PORT_FBS_DWE_OFFSET; 1540 1541 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) && 1542 ata_link_online(&ap->pmp_link[pmp])) { 1543 link = &ap->pmp_link[pmp]; 1544 fbs_need_dec = true; 1545 } 1546 1547 } else 1548 ata_for_each_link(link, ap, EDGE) 1549 if (ata_link_active(link)) 1550 break; 1551 1552 if (!link) 1553 link = &ap->link; 1554 1555 active_qc = ata_qc_from_tag(ap, link->active_tag); 1556 active_ehi = &link->eh_info; 1557 1558 /* record irq stat */ 1559 ata_ehi_clear_desc(host_ehi); 1560 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1561 1562 /* AHCI needs SError cleared; otherwise, it might lock up */ 1563 ahci_scr_read(&ap->link, SCR_ERROR, &serror); 1564 ahci_scr_write(&ap->link, SCR_ERROR, serror); 1565 host_ehi->serror |= serror; 1566 1567 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1568 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1569 irq_stat &= ~PORT_IRQ_IF_ERR; 1570 1571 if (irq_stat & PORT_IRQ_TF_ERR) { 1572 /* If qc is active, charge it; otherwise, the active 1573 * link. There's no active qc on NCQ errors. It will 1574 * be determined by EH by reading log page 10h. 1575 */ 1576 if (active_qc) 1577 active_qc->err_mask |= AC_ERR_DEV; 1578 else 1579 active_ehi->err_mask |= AC_ERR_DEV; 1580 1581 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 1582 host_ehi->serror &= ~SERR_INTERNAL; 1583 } 1584 1585 if (irq_stat & PORT_IRQ_UNK_FIS) { 1586 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); 1587 1588 active_ehi->err_mask |= AC_ERR_HSM; 1589 active_ehi->action |= ATA_EH_RESET; 1590 ata_ehi_push_desc(active_ehi, 1591 "unknown FIS %08x %08x %08x %08x" , 1592 unk[0], unk[1], unk[2], unk[3]); 1593 } 1594 1595 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { 1596 active_ehi->err_mask |= AC_ERR_HSM; 1597 active_ehi->action |= ATA_EH_RESET; 1598 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 1599 } 1600 1601 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 1602 host_ehi->err_mask |= AC_ERR_HOST_BUS; 1603 host_ehi->action |= ATA_EH_RESET; 1604 ata_ehi_push_desc(host_ehi, "host bus error"); 1605 } 1606 1607 if (irq_stat & PORT_IRQ_IF_ERR) { 1608 if (fbs_need_dec) 1609 active_ehi->err_mask |= AC_ERR_DEV; 1610 else { 1611 host_ehi->err_mask |= AC_ERR_ATA_BUS; 1612 host_ehi->action |= ATA_EH_RESET; 1613 } 1614 1615 ata_ehi_push_desc(host_ehi, "interface fatal error"); 1616 } 1617 1618 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 1619 ata_ehi_hotplugged(host_ehi); 1620 ata_ehi_push_desc(host_ehi, "%s", 1621 irq_stat & PORT_IRQ_CONNECT ? 1622 "connection status changed" : "PHY RDY changed"); 1623 } 1624 1625 /* okay, let's hand over to EH */ 1626 1627 if (irq_stat & PORT_IRQ_FREEZE) 1628 ata_port_freeze(ap); 1629 else if (fbs_need_dec) { 1630 ata_link_abort(link); 1631 ahci_fbs_dec_intr(ap); 1632 } else 1633 ata_port_abort(ap); 1634} 1635 1636static void ahci_port_intr(struct ata_port *ap) 1637{ 1638 void __iomem *port_mmio = ahci_port_base(ap); 1639 struct ata_eh_info *ehi = &ap->link.eh_info; 1640 struct ahci_port_priv *pp = ap->private_data; 1641 struct ahci_host_priv *hpriv = ap->host->private_data; 1642 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); 1643 u32 status, qc_active = 0; 1644 int rc; 1645 1646 status = readl(port_mmio + PORT_IRQ_STAT); 1647 writel(status, port_mmio + PORT_IRQ_STAT); 1648 1649 /* ignore BAD_PMP while resetting */ 1650 if (unlikely(resetting)) 1651 status &= ~PORT_IRQ_BAD_PMP; 1652 1653 /* if LPM is enabled, PHYRDY doesn't mean anything */ 1654 if (ap->link.lpm_policy > ATA_LPM_MAX_POWER) { 1655 status &= ~PORT_IRQ_PHYRDY; 1656 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG); 1657 } 1658 1659 if (unlikely(status & PORT_IRQ_ERROR)) { 1660 ahci_error_intr(ap, status); 1661 return; 1662 } 1663 1664 if (status & PORT_IRQ_SDB_FIS) { 1665 /* If SNotification is available, leave notification 1666 * handling to sata_async_notification(). If not, 1667 * emulate it by snooping SDB FIS RX area. 1668 * 1669 * Snooping FIS RX area is probably cheaper than 1670 * poking SNotification but some constrollers which 1671 * implement SNotification, ICH9 for example, don't 1672 * store AN SDB FIS into receive area. 1673 */ 1674 if (hpriv->cap & HOST_CAP_SNTF) 1675 sata_async_notification(ap); 1676 else { 1677 /* If the 'N' bit in word 0 of the FIS is set, 1678 * we just received asynchronous notification. 1679 * Tell libata about it. 1680 * 1681 * Lack of SNotification should not appear in 1682 * ahci 1.2, so the workaround is unnecessary 1683 * when FBS is enabled. 1684 */ 1685 if (pp->fbs_enabled) 1686 WARN_ON_ONCE(1); 1687 else { 1688 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1689 u32 f0 = le32_to_cpu(f[0]); 1690 if (f0 & (1 << 15)) 1691 sata_async_notification(ap); 1692 } 1693 } 1694 } 1695 1696 /* pp->active_link is not reliable once FBS is enabled, both 1697 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because 1698 * NCQ and non-NCQ commands may be in flight at the same time. 1699 */ 1700 if (pp->fbs_enabled) { 1701 if (ap->qc_active) { 1702 qc_active = readl(port_mmio + PORT_SCR_ACT); 1703 qc_active |= readl(port_mmio + PORT_CMD_ISSUE); 1704 } 1705 } else { 1706 /* pp->active_link is valid iff any command is in flight */ 1707 if (ap->qc_active && pp->active_link->sactive) 1708 qc_active = readl(port_mmio + PORT_SCR_ACT); 1709 else 1710 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 1711 } 1712 1713 1714 rc = ata_qc_complete_multiple(ap, qc_active); 1715 1716 /* while resetting, invalid completions are expected */ 1717 if (unlikely(rc < 0 && !resetting)) { 1718 ehi->err_mask |= AC_ERR_HSM; 1719 ehi->action |= ATA_EH_RESET; 1720 ata_port_freeze(ap); 1721 } 1722} 1723 1724irqreturn_t ahci_interrupt(int irq, void *dev_instance) 1725{ 1726 struct ata_host *host = dev_instance; 1727 struct ahci_host_priv *hpriv; 1728 unsigned int i, handled = 0; 1729 void __iomem *mmio; 1730 u32 irq_stat, irq_masked; 1731 1732 VPRINTK("ENTER\n"); 1733 1734 hpriv = host->private_data; 1735 mmio = hpriv->mmio; 1736 1737 /* sigh. 0xffffffff is a valid return from h/w */ 1738 irq_stat = readl(mmio + HOST_IRQ_STAT); 1739 if (!irq_stat) 1740 return IRQ_NONE; 1741 1742 irq_masked = irq_stat & hpriv->port_map; 1743 1744 spin_lock(&host->lock); 1745 1746 for (i = 0; i < host->n_ports; i++) { 1747 struct ata_port *ap; 1748 1749 if (!(irq_masked & (1 << i))) 1750 continue; 1751 1752 ap = host->ports[i]; 1753 if (ap) { 1754 ahci_port_intr(ap); 1755 VPRINTK("port %u\n", i); 1756 } else { 1757 VPRINTK("port %u (no irq)\n", i); 1758 if (ata_ratelimit()) 1759 dev_warn(host->dev, 1760 "interrupt on disabled port %u\n", i); 1761 } 1762 1763 handled = 1; 1764 } 1765 1766 /* HOST_IRQ_STAT behaves as level triggered latch meaning that 1767 * it should be cleared after all the port events are cleared; 1768 * otherwise, it will raise a spurious interrupt after each 1769 * valid one. Please read section 10.6.2 of ahci 1.1 for more 1770 * information. 1771 * 1772 * Also, use the unmasked value to clear interrupt as spurious 1773 * pending event on a dummy port might cause screaming IRQ. 1774 */ 1775 writel(irq_stat, mmio + HOST_IRQ_STAT); 1776 1777 spin_unlock(&host->lock); 1778 1779 VPRINTK("EXIT\n"); 1780 1781 return IRQ_RETVAL(handled); 1782} 1783EXPORT_SYMBOL_GPL(ahci_interrupt); 1784 1785static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 1786{ 1787 struct ata_port *ap = qc->ap; 1788 void __iomem *port_mmio = ahci_port_base(ap); 1789 struct ahci_port_priv *pp = ap->private_data; 1790 1791 /* Keep track of the currently active link. It will be used 1792 * in completion path to determine whether NCQ phase is in 1793 * progress. 1794 */ 1795 pp->active_link = qc->dev->link; 1796 1797 if (qc->tf.protocol == ATA_PROT_NCQ) 1798 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); 1799 1800 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { 1801 u32 fbs = readl(port_mmio + PORT_FBS); 1802 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1803 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; 1804 writel(fbs, port_mmio + PORT_FBS); 1805 pp->fbs_last_dev = qc->dev->link->pmp; 1806 } 1807 1808 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); 1809 1810 ahci_sw_activity(qc->dev->link); 1811 1812 return 0; 1813} 1814 1815static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 1816{ 1817 struct ahci_port_priv *pp = qc->ap->private_data; 1818 u8 *rx_fis = pp->rx_fis; 1819 1820 if (pp->fbs_enabled) 1821 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 1822 1823 /* 1824 * After a successful execution of an ATA PIO data-in command, 1825 * the device doesn't send D2H Reg FIS to update the TF and 1826 * the host should take TF and E_Status from the preceding PIO 1827 * Setup FIS. 1828 */ 1829 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && 1830 !(qc->flags & ATA_QCFLAG_FAILED)) { 1831 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); 1832 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15]; 1833 } else 1834 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); 1835 1836 return true; 1837} 1838 1839static void ahci_freeze(struct ata_port *ap) 1840{ 1841 void __iomem *port_mmio = ahci_port_base(ap); 1842 1843 /* turn IRQ off */ 1844 writel(0, port_mmio + PORT_IRQ_MASK); 1845} 1846 1847static void ahci_thaw(struct ata_port *ap) 1848{ 1849 struct ahci_host_priv *hpriv = ap->host->private_data; 1850 void __iomem *mmio = hpriv->mmio; 1851 void __iomem *port_mmio = ahci_port_base(ap); 1852 u32 tmp; 1853 struct ahci_port_priv *pp = ap->private_data; 1854 1855 /* clear IRQ */ 1856 tmp = readl(port_mmio + PORT_IRQ_STAT); 1857 writel(tmp, port_mmio + PORT_IRQ_STAT); 1858 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 1859 1860 /* turn IRQ back on */ 1861 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1862} 1863 1864static void ahci_error_handler(struct ata_port *ap) 1865{ 1866 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 1867 /* restart engine */ 1868 ahci_stop_engine(ap); 1869 ahci_start_engine(ap); 1870 } 1871 1872 sata_pmp_error_handler(ap); 1873 1874 if (!ata_dev_enabled(ap->link.device)) 1875 ahci_stop_engine(ap); 1876} 1877 1878static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 1879{ 1880 struct ata_port *ap = qc->ap; 1881 1882 /* make DMA engine forget about the failed command */ 1883 if (qc->flags & ATA_QCFLAG_FAILED) 1884 ahci_kick_engine(ap); 1885} 1886 1887static void ahci_enable_fbs(struct ata_port *ap) 1888{ 1889 struct ahci_port_priv *pp = ap->private_data; 1890 void __iomem *port_mmio = ahci_port_base(ap); 1891 u32 fbs; 1892 int rc; 1893 1894 if (!pp->fbs_supported) 1895 return; 1896 1897 fbs = readl(port_mmio + PORT_FBS); 1898 if (fbs & PORT_FBS_EN) { 1899 pp->fbs_enabled = true; 1900 pp->fbs_last_dev = -1; /* initialization */ 1901 return; 1902 } 1903 1904 rc = ahci_stop_engine(ap); 1905 if (rc) 1906 return; 1907 1908 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); 1909 fbs = readl(port_mmio + PORT_FBS); 1910 if (fbs & PORT_FBS_EN) { 1911 dev_info(ap->host->dev, "FBS is enabled\n"); 1912 pp->fbs_enabled = true; 1913 pp->fbs_last_dev = -1; /* initialization */ 1914 } else 1915 dev_err(ap->host->dev, "Failed to enable FBS\n"); 1916 1917 ahci_start_engine(ap); 1918} 1919 1920static void ahci_disable_fbs(struct ata_port *ap) 1921{ 1922 struct ahci_port_priv *pp = ap->private_data; 1923 void __iomem *port_mmio = ahci_port_base(ap); 1924 u32 fbs; 1925 int rc; 1926 1927 if (!pp->fbs_supported) 1928 return; 1929 1930 fbs = readl(port_mmio + PORT_FBS); 1931 if ((fbs & PORT_FBS_EN) == 0) { 1932 pp->fbs_enabled = false; 1933 return; 1934 } 1935 1936 rc = ahci_stop_engine(ap); 1937 if (rc) 1938 return; 1939 1940 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); 1941 fbs = readl(port_mmio + PORT_FBS); 1942 if (fbs & PORT_FBS_EN) 1943 dev_err(ap->host->dev, "Failed to disable FBS\n"); 1944 else { 1945 dev_info(ap->host->dev, "FBS is disabled\n"); 1946 pp->fbs_enabled = false; 1947 } 1948 1949 ahci_start_engine(ap); 1950} 1951 1952static void ahci_pmp_attach(struct ata_port *ap) 1953{ 1954 void __iomem *port_mmio = ahci_port_base(ap); 1955 struct ahci_port_priv *pp = ap->private_data; 1956 u32 cmd; 1957 1958 cmd = readl(port_mmio + PORT_CMD); 1959 cmd |= PORT_CMD_PMP; 1960 writel(cmd, port_mmio + PORT_CMD); 1961 1962 ahci_enable_fbs(ap); 1963 1964 pp->intr_mask |= PORT_IRQ_BAD_PMP; 1965 1966 /* 1967 * We must not change the port interrupt mask register if the 1968 * port is marked frozen, the value in pp->intr_mask will be 1969 * restored later when the port is thawed. 1970 * 1971 * Note that during initialization, the port is marked as 1972 * frozen since the irq handler is not yet registered. 1973 */ 1974 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 1975 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1976} 1977 1978static void ahci_pmp_detach(struct ata_port *ap) 1979{ 1980 void __iomem *port_mmio = ahci_port_base(ap); 1981 struct ahci_port_priv *pp = ap->private_data; 1982 u32 cmd; 1983 1984 ahci_disable_fbs(ap); 1985 1986 cmd = readl(port_mmio + PORT_CMD); 1987 cmd &= ~PORT_CMD_PMP; 1988 writel(cmd, port_mmio + PORT_CMD); 1989 1990 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 1991 1992 /* see comment above in ahci_pmp_attach() */ 1993 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 1994 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1995} 1996 1997int ahci_port_resume(struct ata_port *ap) 1998{ 1999 ahci_power_up(ap); 2000 ahci_start_port(ap); 2001 2002 if (sata_pmp_attached(ap)) 2003 ahci_pmp_attach(ap); 2004 else 2005 ahci_pmp_detach(ap); 2006 2007 return 0; 2008} 2009EXPORT_SYMBOL_GPL(ahci_port_resume); 2010 2011#ifdef CONFIG_PM 2012static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 2013{ 2014 const char *emsg = NULL; 2015 int rc; 2016 2017 rc = ahci_deinit_port(ap, &emsg); 2018 if (rc == 0) 2019 ahci_power_down(ap); 2020 else { 2021 ata_port_err(ap, "%s (%d)\n", emsg, rc); 2022 ata_port_freeze(ap); 2023 } 2024 2025 return rc; 2026} 2027#endif 2028 2029static int ahci_port_start(struct ata_port *ap) 2030{ 2031 struct ahci_host_priv *hpriv = ap->host->private_data; 2032 struct device *dev = ap->host->dev; 2033 struct ahci_port_priv *pp; 2034 void *mem; 2035 dma_addr_t mem_dma; 2036 size_t dma_sz, rx_fis_sz; 2037 2038 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 2039 if (!pp) 2040 return -ENOMEM; 2041 2042 /* check FBS capability */ 2043 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { 2044 void __iomem *port_mmio = ahci_port_base(ap); 2045 u32 cmd = readl(port_mmio + PORT_CMD); 2046 if (cmd & PORT_CMD_FBSCP) 2047 pp->fbs_supported = true; 2048 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { 2049 dev_info(dev, "port %d can do FBS, forcing FBSCP\n", 2050 ap->port_no); 2051 pp->fbs_supported = true; 2052 } else 2053 dev_warn(dev, "port %d is not capable of FBS\n", 2054 ap->port_no); 2055 } 2056 2057 if (pp->fbs_supported) { 2058 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; 2059 rx_fis_sz = AHCI_RX_FIS_SZ * 16; 2060 } else { 2061 dma_sz = AHCI_PORT_PRIV_DMA_SZ; 2062 rx_fis_sz = AHCI_RX_FIS_SZ; 2063 } 2064 2065 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); 2066 if (!mem) 2067 return -ENOMEM; 2068 memset(mem, 0, dma_sz); 2069 2070 /* 2071 * First item in chunk of DMA memory: 32-slot command table, 2072 * 32 bytes each in size 2073 */ 2074 pp->cmd_slot = mem; 2075 pp->cmd_slot_dma = mem_dma; 2076 2077 mem += AHCI_CMD_SLOT_SZ; 2078 mem_dma += AHCI_CMD_SLOT_SZ; 2079 2080 /* 2081 * Second item: Received-FIS area 2082 */ 2083 pp->rx_fis = mem; 2084 pp->rx_fis_dma = mem_dma; 2085 2086 mem += rx_fis_sz; 2087 mem_dma += rx_fis_sz; 2088 2089 /* 2090 * Third item: data area for storing a single command 2091 * and its scatter-gather table 2092 */ 2093 pp->cmd_tbl = mem; 2094 pp->cmd_tbl_dma = mem_dma; 2095 2096 /* 2097 * Save off initial list of interrupts to be enabled. 2098 * This could be changed later 2099 */ 2100 pp->intr_mask = DEF_PORT_IRQ; 2101 2102 ap->private_data = pp; 2103 2104 /* engage engines, captain */ 2105 return ahci_port_resume(ap); 2106} 2107 2108static void ahci_port_stop(struct ata_port *ap) 2109{ 2110 const char *emsg = NULL; 2111 int rc; 2112 2113 /* de-initialize port */ 2114 rc = ahci_deinit_port(ap, &emsg); 2115 if (rc) 2116 ata_port_warn(ap, "%s (%d)\n", emsg, rc); 2117} 2118 2119void ahci_print_info(struct ata_host *host, const char *scc_s) 2120{ 2121 struct ahci_host_priv *hpriv = host->private_data; 2122 void __iomem *mmio = hpriv->mmio; 2123 u32 vers, cap, cap2, impl, speed; 2124 const char *speed_s; 2125 2126 vers = readl(mmio + HOST_VERSION); 2127 cap = hpriv->cap; 2128 cap2 = hpriv->cap2; 2129 impl = hpriv->port_map; 2130 2131 speed = (cap >> 20) & 0xf; 2132 if (speed == 1) 2133 speed_s = "1.5"; 2134 else if (speed == 2) 2135 speed_s = "3"; 2136 else if (speed == 3) 2137 speed_s = "6"; 2138 else 2139 speed_s = "?"; 2140 2141 dev_info(host->dev, 2142 "AHCI %02x%02x.%02x%02x " 2143 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 2144 , 2145 2146 (vers >> 24) & 0xff, 2147 (vers >> 16) & 0xff, 2148 (vers >> 8) & 0xff, 2149 vers & 0xff, 2150 2151 ((cap >> 8) & 0x1f) + 1, 2152 (cap & 0x1f) + 1, 2153 speed_s, 2154 impl, 2155 scc_s); 2156 2157 dev_info(host->dev, 2158 "flags: " 2159 "%s%s%s%s%s%s%s" 2160 "%s%s%s%s%s%s%s" 2161 "%s%s%s%s%s%s\n" 2162 , 2163 2164 cap & HOST_CAP_64 ? "64bit " : "", 2165 cap & HOST_CAP_NCQ ? "ncq " : "", 2166 cap & HOST_CAP_SNTF ? "sntf " : "", 2167 cap & HOST_CAP_MPS ? "ilck " : "", 2168 cap & HOST_CAP_SSS ? "stag " : "", 2169 cap & HOST_CAP_ALPM ? "pm " : "", 2170 cap & HOST_CAP_LED ? "led " : "", 2171 cap & HOST_CAP_CLO ? "clo " : "", 2172 cap & HOST_CAP_ONLY ? "only " : "", 2173 cap & HOST_CAP_PMP ? "pmp " : "", 2174 cap & HOST_CAP_FBS ? "fbs " : "", 2175 cap & HOST_CAP_PIO_MULTI ? "pio " : "", 2176 cap & HOST_CAP_SSC ? "slum " : "", 2177 cap & HOST_CAP_PART ? "part " : "", 2178 cap & HOST_CAP_CCC ? "ccc " : "", 2179 cap & HOST_CAP_EMS ? "ems " : "", 2180 cap & HOST_CAP_SXS ? "sxs " : "", 2181 cap2 & HOST_CAP2_APST ? "apst " : "", 2182 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", 2183 cap2 & HOST_CAP2_BOH ? "boh " : "" 2184 ); 2185} 2186EXPORT_SYMBOL_GPL(ahci_print_info); 2187 2188void ahci_set_em_messages(struct ahci_host_priv *hpriv, 2189 struct ata_port_info *pi) 2190{ 2191 u8 messages; 2192 void __iomem *mmio = hpriv->mmio; 2193 u32 em_loc = readl(mmio + HOST_EM_LOC); 2194 u32 em_ctl = readl(mmio + HOST_EM_CTL); 2195 2196 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS)) 2197 return; 2198 2199 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; 2200 2201 if (messages) { 2202 /* store em_loc */ 2203 hpriv->em_loc = ((em_loc >> 16) * 4); 2204 hpriv->em_buf_sz = ((em_loc & 0xff) * 4); 2205 hpriv->em_msg_type = messages; 2206 pi->flags |= ATA_FLAG_EM; 2207 if (!(em_ctl & EM_CTL_ALHD)) 2208 pi->flags |= ATA_FLAG_SW_ACTIVITY; 2209 } 2210} 2211EXPORT_SYMBOL_GPL(ahci_set_em_messages); 2212 2213MODULE_AUTHOR("Jeff Garzik"); 2214MODULE_DESCRIPTION("Common AHCI SATA low-level routines"); 2215MODULE_LICENSE("GPL"); 2216