1d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* 2d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * File: drivers/ata/pata_bf54x.c 3d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Author: Sonic Zhang <sonic.zhang@analog.com> 4d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 5d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Created: 6d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Description: PATA Driver for blackfin 54x 7d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 8d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Modified: 9d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Copyright 2007 Analog Devices Inc. 10d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 11d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Bugs: Enter bugs at http://blackfin.uclinux.org/ 12d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 13d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * This program is free software; you can redistribute it and/or modify 14d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * it under the terms of the GNU General Public License as published by 15d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * the Free Software Foundation; either version 2 of the License, or 16d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * (at your option) any later version. 17d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 18d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * This program is distributed in the hope that it will be useful, 19d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * but WITHOUT ANY WARRANTY; without even the implied warranty of 20d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * GNU General Public License for more details. 22d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 23d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * You should have received a copy of the GNU General Public License 24d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * along with this program; if not, see the file COPYING, or write 25d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * to the Free Software Foundation, Inc., 26d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 27d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 28d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 29d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <linux/kernel.h> 30d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <linux/module.h> 31d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <linux/pci.h> 32d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <linux/init.h> 33d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <linux/blkdev.h> 34d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <linux/delay.h> 35d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <linux/device.h> 36d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <scsi/scsi_host.h> 37d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <linux/libata.h> 38d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <linux/platform_device.h> 39d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <asm/dma.h> 40d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <asm/gpio.h> 41d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <asm/portmux.h> 42d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 43d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define DRV_NAME "pata-bf54x" 44d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define DRV_VERSION "0.9" 45d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 46d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATA_REG_CTRL 0x0E 47d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATA_REG_ALTSTATUS ATA_REG_CTRL 48d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 49d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* These are the offset of the controller's registers */ 50d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_CONTROL 0x00 51d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_STATUS 0x04 52d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_DEV_ADDR 0x08 53d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_DEV_TXBUF 0x0c 54d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_DEV_RXBUF 0x10 55d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_INT_MASK 0x14 56d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_INT_STATUS 0x18 57d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_XFER_LEN 0x1c 58d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_LINE_STATUS 0x20 59d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_SM_STATE 0x24 60d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_TERMINATE 0x28 61d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_PIO_TFRCNT 0x2c 62d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_DMA_TFRCNT 0x30 63d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_UMAIN_TFRCNT 0x34 64d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_UDMAOUT_TFRCNT 0x38 65d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_REG_TIM_0 0x40 66d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_PIO_TIM_0 0x44 67d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_PIO_TIM_1 0x48 68d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_MULTI_TIM_0 0x50 69d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_MULTI_TIM_1 0x54 70d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_MULTI_TIM_2 0x58 71d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_ULTRA_TIM_0 0x60 72d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_ULTRA_TIM_1 0x64 73d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_ULTRA_TIM_2 0x68 74d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_ULTRA_TIM_3 0x6c 75d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 76d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 77d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_CONTROL(base)\ 78d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_CONTROL) 79d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_CONTROL(base, val)\ 80d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_CONTROL, val) 81d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_STATUS(base)\ 82d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_STATUS) 83d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_DEV_ADDR(base)\ 84d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_DEV_ADDR) 85d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_DEV_ADDR(base, val)\ 86d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val) 87d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_DEV_TXBUF(base)\ 88d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_DEV_TXBUF) 89d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_DEV_TXBUF(base, val)\ 90d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_DEV_TXBUF, val) 91d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_DEV_RXBUF(base)\ 92d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_DEV_RXBUF) 93d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_DEV_RXBUF(base, val)\ 94d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_DEV_RXBUF, val) 95d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_INT_MASK(base)\ 96d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_INT_MASK) 97d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_INT_MASK(base, val)\ 98d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_INT_MASK, val) 99d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_INT_STATUS(base)\ 100d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_INT_STATUS) 101d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_INT_STATUS(base, val)\ 102d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_INT_STATUS, val) 103d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_XFER_LEN(base)\ 104d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_XFER_LEN) 105d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_XFER_LEN(base, val)\ 106d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_XFER_LEN, val) 107d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_LINE_STATUS(base)\ 108d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_LINE_STATUS) 109d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_SM_STATE(base)\ 110d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_SM_STATE) 111d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_TERMINATE(base)\ 112d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_TERMINATE) 113d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_TERMINATE(base, val)\ 114d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_TERMINATE, val) 115d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_PIO_TFRCNT(base)\ 116d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_PIO_TFRCNT) 117d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_DMA_TFRCNT(base)\ 118d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_DMA_TFRCNT) 119d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_UMAIN_TFRCNT(base)\ 120d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_UMAIN_TFRCNT) 121d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_UDMAOUT_TFRCNT(base)\ 122d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_UDMAOUT_TFRCNT) 123d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_REG_TIM_0(base)\ 124d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_REG_TIM_0) 125d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_REG_TIM_0(base, val)\ 126d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_REG_TIM_0, val) 127d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_PIO_TIM_0(base)\ 128d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_PIO_TIM_0) 129d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_PIO_TIM_0(base, val)\ 130d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_PIO_TIM_0, val) 131d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_PIO_TIM_1(base)\ 132d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_PIO_TIM_1) 133d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_PIO_TIM_1(base, val)\ 134d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_PIO_TIM_1, val) 135d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_MULTI_TIM_0(base)\ 136d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_0) 137d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_MULTI_TIM_0(base, val)\ 138d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_0, val) 139d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_MULTI_TIM_1(base)\ 140d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_1) 141d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_MULTI_TIM_1(base, val)\ 142d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_1, val) 143d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_MULTI_TIM_2(base)\ 144d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_2) 145d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_MULTI_TIM_2(base, val)\ 146d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_2, val) 147d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_ULTRA_TIM_0(base)\ 148d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_0) 149d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_ULTRA_TIM_0(base, val)\ 150d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_0, val) 151d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_ULTRA_TIM_1(base)\ 152d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_1) 153d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_ULTRA_TIM_1(base, val)\ 154d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_1, val) 155d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_ULTRA_TIM_2(base)\ 156d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_2) 157d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_ULTRA_TIM_2(base, val)\ 158d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_2, val) 159d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_ULTRA_TIM_3(base)\ 160d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_3) 161d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_ULTRA_TIM_3(base, val)\ 162d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_3, val) 163d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 164d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 165d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * PIO Mode - Frequency compatibility 166d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 167d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* mode: 0 1 2 3 4 */ 168d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 pio_fsclk[] = 169d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 33333333, 33333333, 33333333, 33333333, 33333333 }; 170d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 171d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 172d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * MDMA Mode - Frequency compatibility 173d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 174d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* mode: 0 1 2 */ 175d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 mdma_fsclk[] = { 33333333, 33333333, 33333333 }; 176d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 177d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 178d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * UDMA Mode - Frequency compatibility 179d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 180d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * UDMA5 - 100 MB/s - SCLK = 133 MHz 181d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * UDMA4 - 66 MB/s - SCLK >= 80 MHz 182d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * UDMA3 - 44.4 MB/s - SCLK >= 50 MHz 183d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * UDMA2 - 33 MB/s - SCLK >= 40 MHz 184d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 185d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* mode: 0 1 2 3 4 5 */ 186d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_fsclk[] = 187d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 33333333, 33333333, 40000000, 50000000, 80000000, 133333333 }; 188d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 189d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 190d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Register transfer timing table 191d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 192d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* mode: 0 1 2 3 4 */ 193d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* Cycle Time */ 194d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 reg_t0min[] = { 600, 383, 330, 180, 120 }; 195d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DIOR/DIOW to end cycle */ 196d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 reg_t2min[] = { 290, 290, 290, 70, 25 }; 197d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DIOR/DIOW asserted pulse width */ 198d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 reg_teocmin[] = { 290, 290, 290, 80, 70 }; 199d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 200d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 201d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * PIO timing table 202d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 203d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* mode: 0 1 2 3 4 */ 204d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* Cycle Time */ 205d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 pio_t0min[] = { 600, 383, 240, 180, 120 }; 206d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* Address valid to DIOR/DIORW */ 207d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 pio_t1min[] = { 70, 50, 30, 30, 25 }; 208d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DIOR/DIOW to end cycle */ 209d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 pio_t2min[] = { 165, 125, 100, 80, 70 }; 210d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DIOR/DIOW asserted pulse width */ 211d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 pio_teocmin[] = { 165, 125, 100, 70, 25 }; 212d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DIOW data hold */ 213d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 pio_t4min[] = { 30, 20, 15, 10, 10 }; 214d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 215d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* ****************************************************************** 216d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Multiword DMA timing table 217d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * ****************************************************************** 218d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 219d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* mode: 0 1 2 */ 220d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* Cycle Time */ 221d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 mdma_t0min[] = { 480, 150, 120 }; 222d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DIOR/DIOW asserted pulse width */ 223d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 mdma_tdmin[] = { 215, 80, 70 }; 224d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DMACK to read data released */ 225d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 mdma_thmin[] = { 20, 15, 10 }; 226d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DIOR/DIOW to DMACK hold */ 227d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 mdma_tjmin[] = { 20, 5, 5 }; 228d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DIOR negated pulse width */ 229d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 mdma_tkrmin[] = { 50, 50, 25 }; 230d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DIOR negated pulse width */ 231d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 mdma_tkwmin[] = { 215, 50, 25 }; 232d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* CS[1:0] valid to DIOR/DIOW */ 233d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 mdma_tmmin[] = { 50, 30, 25 }; 234d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DMACK to read data released */ 235d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 mdma_tzmax[] = { 20, 25, 25 }; 236d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 237d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 238d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Ultra DMA timing table 239d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 240d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* mode: 0 1 2 3 4 5 */ 241d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_tcycmin[] = { 112, 73, 54, 39, 25, 17 }; 242d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_tdvsmin[] = { 70, 48, 31, 20, 7, 5 }; 243d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_tenvmax[] = { 70, 70, 70, 55, 55, 50 }; 244d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_trpmin[] = { 160, 125, 100, 100, 100, 85 }; 245d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_tmin[] = { 5, 5, 5, 5, 3, 3 }; 246d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 247d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 248d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_tmlimin = 20; 249d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_tzahmin = 20; 250d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_tenvmin = 20; 251d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_tackmin = 20; 252d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_tssmin = 50; 253d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 25481b0287d341535ac722de891b19f7c49212ac91cSonic Zhang#define BFIN_MAX_SG_SEGMENTS 4 25581b0287d341535ac722de891b19f7c49212ac91cSonic Zhang 256d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 257d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 258d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Function: num_clocks_min 259d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 260d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Description: 261d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * calculate number of SCLK cycles to meet minimum timing 262d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 263d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic unsigned short num_clocks_min(unsigned long tmin, 264d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned long fsclk) 265d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 266d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned long tmp ; 267d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short result; 268d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 269d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tmp = tmin * (fsclk/1000/1000) / 1000; 270d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang result = (unsigned short)tmp; 271d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if ((tmp*1000*1000) < (tmin*(fsclk/1000))) { 272d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang result++; 273d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 274d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 275d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return result; 276d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 277d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 278d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 279d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_set_piomode - Initialize host controller PATA PIO timings 280d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: Port whose timings we are configuring 281d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @adev: um 282d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 283d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Set PIO mode for device. 284d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 285d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * LOCKING: 286d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * None (inherited from caller). 287d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 288d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 289d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void bfin_set_piomode(struct ata_port *ap, struct ata_device *adev) 290d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 291d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang int mode = adev->pio_mode - XFER_PIO_0; 292d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 293d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned int fsclk = get_sclk(); 294d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short teoc_reg, t2_reg, teoc_pio; 295d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short t4_reg, t2_pio, t1_reg; 296d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short n0, n6, t6min = 5; 297d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 298d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* the most restrictive timing value is t6 and tc, the DIOW - data hold 299d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * If one SCLK pulse is longer than this minimum value then register 300d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * transfers cannot be supported at this frequency. 301d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 302d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang n6 = num_clocks_min(t6min, fsclk); 303d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (mode >= 0 && mode <= 4 && n6 >= 1) { 3049f24e82d07e2c64467d0c0c04a798de56461fd4aBryan Wu dev_dbg(adev->link->ap->dev, "set piomode: mode=%d, fsclk=%ud\n", mode, fsclk); 305d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* calculate the timing values for register transfers. */ 306d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang while (mode > 0 && pio_fsclk[mode] > fsclk) 307d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang mode--; 308d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 309d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* DIOR/DIOW to end cycle time */ 310d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang t2_reg = num_clocks_min(reg_t2min[mode], fsclk); 311d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* DIOR/DIOW asserted pulse width */ 312d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang teoc_reg = num_clocks_min(reg_teocmin[mode], fsclk); 313d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Cycle Time */ 314d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang n0 = num_clocks_min(reg_t0min[mode], fsclk); 315d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 316d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* increase t2 until we meed the minimum cycle length */ 317d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (t2_reg + teoc_reg < n0) 318d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang t2_reg = n0 - teoc_reg; 319d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 320d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* calculate the timing values for pio transfers. */ 321d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 322d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* DIOR/DIOW to end cycle time */ 323d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang t2_pio = num_clocks_min(pio_t2min[mode], fsclk); 324d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* DIOR/DIOW asserted pulse width */ 325d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang teoc_pio = num_clocks_min(pio_teocmin[mode], fsclk); 326d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Cycle Time */ 327d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang n0 = num_clocks_min(pio_t0min[mode], fsclk); 328d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 329d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* increase t2 until we meed the minimum cycle length */ 330d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (t2_pio + teoc_pio < n0) 331d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang t2_pio = n0 - teoc_pio; 332d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 333d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Address valid to DIOR/DIORW */ 334d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang t1_reg = num_clocks_min(pio_t1min[mode], fsclk); 335d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 336d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* DIOW data hold */ 337d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang t4_reg = num_clocks_min(pio_t4min[mode], fsclk); 338d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 339d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_REG_TIM_0(base, (teoc_reg<<8 | t2_reg)); 340d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_PIO_TIM_0(base, (t4_reg<<12 | t2_pio<<4 | t1_reg)); 341d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_PIO_TIM_1(base, teoc_pio); 342d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (mode > 2) { 343d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, 344d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_GET_CONTROL(base) | IORDY_EN); 345d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } else { 346d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, 347d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_GET_CONTROL(base) & ~IORDY_EN); 348d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 349d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 350d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Disable host ATAPI PIO interrupts */ 351d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_INT_MASK(base, ATAPI_GET_INT_MASK(base) 352d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang & ~(PIO_DONE_MASK | HOST_TERM_XFER_MASK)); 353d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang SSYNC(); 354d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 355d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 356d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 357d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 358d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_set_dmamode - Initialize host controller PATA DMA timings 359d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: Port whose timings we are configuring 360d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @adev: um 361d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 362d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Set UDMA mode for device. 363d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 364d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * LOCKING: 365d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * None (inherited from caller). 366d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 367d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 368d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void bfin_set_dmamode(struct ata_port *ap, struct ata_device *adev) 369d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 370d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang int mode; 371d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 372d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned long fsclk = get_sclk(); 373d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short tenv, tack, tcyc_tdvs, tdvs, tmli, tss, trp, tzah; 374d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short tm, td, tkr, tkw, teoc, th; 375d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short n0, nf, tfmin = 5; 376d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short nmin, tcyc; 377d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 378d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang mode = adev->dma_mode - XFER_UDMA_0; 379d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (mode >= 0 && mode <= 5) { 3809f24e82d07e2c64467d0c0c04a798de56461fd4aBryan Wu dev_dbg(adev->link->ap->dev, "set udmamode: mode=%d\n", mode); 381d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* the most restrictive timing value is t6 and tc, 382d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * the DIOW - data hold. If one SCLK pulse is longer 383d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * than this minimum value then register 384d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * transfers cannot be supported at this frequency. 385d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 386d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang while (mode > 0 && udma_fsclk[mode] > fsclk) 387d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang mode--; 388d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 389d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang nmin = num_clocks_min(udma_tmin[mode], fsclk); 390d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (nmin >= 1) { 391d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* calculate the timing values for Ultra DMA. */ 392d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tdvs = num_clocks_min(udma_tdvsmin[mode], fsclk); 393d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tcyc = num_clocks_min(udma_tcycmin[mode], fsclk); 394d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tcyc_tdvs = 2; 395d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 396d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* increase tcyc - tdvs (tcyc_tdvs) until we meed 397d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * the minimum cycle length 398d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 399d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (tdvs + tcyc_tdvs < tcyc) 400d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tcyc_tdvs = tcyc - tdvs; 401d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 402d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Mow assign the values required for the timing 403d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * registers 404d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 405d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (tcyc_tdvs < 2) 406d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tcyc_tdvs = 2; 407d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 408d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (tdvs < 2) 409d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tdvs = 2; 410d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 411d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tack = num_clocks_min(udma_tackmin, fsclk); 412d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tss = num_clocks_min(udma_tssmin, fsclk); 413d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tmli = num_clocks_min(udma_tmlimin, fsclk); 414d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tzah = num_clocks_min(udma_tzahmin, fsclk); 415d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang trp = num_clocks_min(udma_trpmin[mode], fsclk); 416d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tenv = num_clocks_min(udma_tenvmin, fsclk); 417d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (tenv <= udma_tenvmax[mode]) { 418d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_ULTRA_TIM_0(base, (tenv<<8 | tack)); 419d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_ULTRA_TIM_1(base, 420d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang (tcyc_tdvs<<8 | tdvs)); 421d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_ULTRA_TIM_2(base, (tmli<<8 | tss)); 422d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_ULTRA_TIM_3(base, (trp<<8 | tzah)); 423d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 424d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 425d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 426d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 427d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang mode = adev->dma_mode - XFER_MW_DMA_0; 428d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (mode >= 0 && mode <= 2) { 4299f24e82d07e2c64467d0c0c04a798de56461fd4aBryan Wu dev_dbg(adev->link->ap->dev, "set mdmamode: mode=%d\n", mode); 430d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* the most restrictive timing value is tf, the DMACK to 431d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * read data released. If one SCLK pulse is longer than 432d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * this maximum value then the MDMA mode 433d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * cannot be supported at this frequency. 434d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 435d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang while (mode > 0 && mdma_fsclk[mode] > fsclk) 436d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang mode--; 437d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 438d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang nf = num_clocks_min(tfmin, fsclk); 439d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (nf >= 1) { 440d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* calculate the timing values for Multi-word DMA. */ 441d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 442d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* DIOR/DIOW asserted pulse width */ 443d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang td = num_clocks_min(mdma_tdmin[mode], fsclk); 444d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 445d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* DIOR negated pulse width */ 446d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tkw = num_clocks_min(mdma_tkwmin[mode], fsclk); 447d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 448d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Cycle Time */ 449d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang n0 = num_clocks_min(mdma_t0min[mode], fsclk); 450d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 451d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* increase tk until we meed the minimum cycle length */ 452d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (tkw + td < n0) 453d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tkw = n0 - td; 454d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 455d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* DIOR negated pulse width - read */ 456d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tkr = num_clocks_min(mdma_tkrmin[mode], fsclk); 457d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* CS{1:0] valid to DIOR/DIOW */ 458d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tm = num_clocks_min(mdma_tmmin[mode], fsclk); 459d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* DIOR/DIOW to DMACK hold */ 460d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang teoc = num_clocks_min(mdma_tjmin[mode], fsclk); 461d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* DIOW Data hold */ 462d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang th = num_clocks_min(mdma_thmin[mode], fsclk); 463d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 464d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_MULTI_TIM_0(base, (tm<<8 | td)); 465d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_MULTI_TIM_1(base, (tkr<<8 | tkw)); 466d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_MULTI_TIM_2(base, (teoc<<8 | th)); 467d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang SSYNC(); 468d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 469d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 470d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return; 471d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 472d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 473d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 474d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 475d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Function: wait_complete 476d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 477d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Description: Waits the interrupt from device 478d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 479d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 480d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic inline void wait_complete(void __iomem *base, unsigned short mask) 481d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 482d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short status; 483d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned int i = 0; 484d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 485d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define PATA_BF54X_WAIT_TIMEOUT 10000 486d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 487d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang for (i = 0; i < PATA_BF54X_WAIT_TIMEOUT; i++) { 488d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang status = ATAPI_GET_INT_STATUS(base) & mask; 489d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (status) 490d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang break; 491d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 492d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 493d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_INT_STATUS(base, mask); 494d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 495d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 496d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 497d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 498d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Function: write_atapi_register 499d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 500d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Description: Writes to ATA Device Resgister 501d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 502d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 503d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 504d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void write_atapi_register(void __iomem *base, 505d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned long ata_reg, unsigned short value) 506d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 507d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_DEV_TXBUF register with write data (to be 508d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * written into the device). 509d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 510d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_DEV_TXBUF(base, value); 511d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 512d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_DEV_ADDR register with address of the 513d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * device register (0x01 to 0x0F). 514d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 515d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_DEV_ADDR(base, ata_reg); 516d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 517d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_CTRL register with dir set to write (1) 518d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 519d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR)); 520d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 521d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* ensure PIO DMA is not set */ 522d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA)); 523d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 524d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* and start the transfer */ 525d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START)); 526d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 527d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Wait for the interrupt to indicate the end of the transfer. 528d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * (We need to wait on and clear rhe ATA_DEV_INT interrupt status) 529d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 530d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang wait_complete(base, PIO_DONE_INT); 531d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 532d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 533d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 534d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 535d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Function: read_atapi_register 536d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 537d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang *Description: Reads from ATA Device Resgister 538d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 539d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 540d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 541d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic unsigned short read_atapi_register(void __iomem *base, 542d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned long ata_reg) 543d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 544d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_DEV_ADDR register with address of the 545d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * device register (0x01 to 0x0F). 546d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 547d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_DEV_ADDR(base, ata_reg); 548d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 549d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_CTRL register with dir set to read (0) and 550d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 551d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR)); 552d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 553d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* ensure PIO DMA is not set */ 554d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA)); 555d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 556d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* and start the transfer */ 557d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START)); 558d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 559d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Wait for the interrupt to indicate the end of the transfer. 560d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * (PIO_DONE interrupt is set and it doesn't seem to matter 561d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * that we don't clear it) 562d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 563d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang wait_complete(base, PIO_DONE_INT); 564d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 565d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Read the ATA_DEV_RXBUF register with write data (to be 566d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * written into the device). 567d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 568d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return ATAPI_GET_DEV_RXBUF(base); 569d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 570d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 571d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 572d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 573d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Function: write_atapi_register_data 574d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 575d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Description: Writes to ATA Device Resgister 576d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 577d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 578d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 579d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void write_atapi_data(void __iomem *base, 580d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang int len, unsigned short *buf) 581d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 582d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang int i; 583d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 584d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Set transfer length to 1 */ 585d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_XFER_LEN(base, 1); 586d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 587d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_DEV_ADDR register with address of the 588d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * ATA_REG_DATA 589d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 590d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA); 591d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 592d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_CTRL register with dir set to write (1) 593d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 594d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR)); 595d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 596d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* ensure PIO DMA is not set */ 597d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA)); 598d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 599d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang for (i = 0; i < len; i++) { 600d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_DEV_TXBUF register with write data (to be 601d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * written into the device). 602d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 603d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_DEV_TXBUF(base, buf[i]); 604d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 605d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* and start the transfer */ 606d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START)); 607d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 608d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Wait for the interrupt to indicate the end of the transfer. 609d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * (We need to wait on and clear rhe ATA_DEV_INT 610d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * interrupt status) 611d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 612d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang wait_complete(base, PIO_DONE_INT); 613d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 614d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 615d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 616d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 617d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 618d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Function: read_atapi_register_data 619d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 620d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Description: Reads from ATA Device Resgister 621d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 622d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 623d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 624d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void read_atapi_data(void __iomem *base, 625d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang int len, unsigned short *buf) 626d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 627d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang int i; 628d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 629d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Set transfer length to 1 */ 630d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_XFER_LEN(base, 1); 631d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 632d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_DEV_ADDR register with address of the 633d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * ATA_REG_DATA 634d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 635d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA); 636d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 637d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_CTRL register with dir set to read (0) and 638d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 639d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR)); 640d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 641d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* ensure PIO DMA is not set */ 642d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA)); 643d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 644d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang for (i = 0; i < len; i++) { 645d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* and start the transfer */ 646d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START)); 647d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 648d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Wait for the interrupt to indicate the end of the transfer. 649d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * (PIO_DONE interrupt is set and it doesn't seem to matter 650d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * that we don't clear it) 651d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 652d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang wait_complete(base, PIO_DONE_INT); 653d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 654d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Read the ATA_DEV_RXBUF register with write data (to be 655d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * written into the device). 656d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 657d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang buf[i] = ATAPI_GET_DEV_RXBUF(base); 658d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 659d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 660d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 661d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 662d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_tf_load - send taskfile registers to host controller 663d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: Port to which output is sent 664d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @tf: ATA taskfile register set 665d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 6669363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_tf_load(). 667d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 668d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 669d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void bfin_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) 670d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 671d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 672d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; 673d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 674d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (tf->ctl != ap->last_ctl) { 675d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_CTRL, tf->ctl); 676d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ap->last_ctl = tf->ctl; 677d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ata_wait_idle(ap); 678d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 679d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 680d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (is_addr) { 681d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (tf->flags & ATA_TFLAG_LBA48) { 682d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_FEATURE, 683d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_feature); 684d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_NSECT, 685d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_nsect); 686d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_LBAL, tf->hob_lbal); 687d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_LBAM, tf->hob_lbam); 688d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_LBAH, tf->hob_lbah); 689f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(ap->dev, "hob: feat 0x%X nsect 0x%X, lba 0x%X " 690d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang "0x%X 0x%X\n", 691d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_feature, 692d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_nsect, 693d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_lbal, 694d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_lbam, 695d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_lbah); 696d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 697d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 698d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_FEATURE, tf->feature); 699d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_NSECT, tf->nsect); 700d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_LBAL, tf->lbal); 701d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_LBAM, tf->lbam); 702d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_LBAH, tf->lbah); 703f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(ap->dev, "feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", 704d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->feature, 705d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->nsect, 706d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->lbal, 707d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->lbam, 708d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->lbah); 709d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 710d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 711d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (tf->flags & ATA_TFLAG_DEVICE) { 712d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_DEVICE, tf->device); 713f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(ap->dev, "device 0x%X\n", tf->device); 714d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 715d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 716d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ata_wait_idle(ap); 717d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 718d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 719d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 720d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_check_status - Read device status reg & clear interrupt 721d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: port where the device is 722d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 723d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Note: Original code is ata_check_status(). 724d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 725d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 726d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic u8 bfin_check_status(struct ata_port *ap) 727d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 728d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 729d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return read_atapi_register(base, ATA_REG_STATUS); 730d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 731d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 732d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 733d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_tf_read - input device's ATA taskfile shadow registers 734d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: Port from which input is read 735d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @tf: ATA taskfile register set for storing input 736d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 7379363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_tf_read(). 738d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 739d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 740d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void bfin_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 741d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 742d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 743d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 744d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->command = bfin_check_status(ap); 745d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->feature = read_atapi_register(base, ATA_REG_ERR); 746d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->nsect = read_atapi_register(base, ATA_REG_NSECT); 747d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->lbal = read_atapi_register(base, ATA_REG_LBAL); 748d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->lbam = read_atapi_register(base, ATA_REG_LBAM); 749d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->lbah = read_atapi_register(base, ATA_REG_LBAH); 750d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->device = read_atapi_register(base, ATA_REG_DEVICE); 751d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 752d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (tf->flags & ATA_TFLAG_LBA48) { 753d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_CTRL, tf->ctl | ATA_HOB); 754d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_feature = read_atapi_register(base, ATA_REG_ERR); 755d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_nsect = read_atapi_register(base, ATA_REG_NSECT); 756d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_lbal = read_atapi_register(base, ATA_REG_LBAL); 757d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_lbam = read_atapi_register(base, ATA_REG_LBAM); 758d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_lbah = read_atapi_register(base, ATA_REG_LBAH); 759d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 760d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 761d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 762d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 763d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_exec_command - issue ATA command to host controller 764d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: port to which command is being issued 765d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @tf: ATA taskfile register set 766d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 7679363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_exec_command(). 768d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 769d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 770d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void bfin_exec_command(struct ata_port *ap, 771d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang const struct ata_taskfile *tf) 772d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 773d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 774f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(ap->dev, "ata%u: cmd 0x%X\n", ap->print_id, tf->command); 775d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 776d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_CMD, tf->command); 7779363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo ata_sff_pause(ap); 778d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 779d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 780d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 781d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_check_altstatus - Read device alternate status reg 782d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: port where the device is 783d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 784d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 785d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic u8 bfin_check_altstatus(struct ata_port *ap) 786d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 787d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 788d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return read_atapi_register(base, ATA_REG_ALTSTATUS); 789d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 790d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 791d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 7929363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * bfin_dev_select - Select device 0/1 on ATA bus 793d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: ATA channel to manipulate 794d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @device: ATA device (numbered from zero) to select 795d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 7969363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_dev_select(). 797d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 798d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 7999363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heostatic void bfin_dev_select(struct ata_port *ap, unsigned int device) 800d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 801d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 802d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang u8 tmp; 803d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 804d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (device == 0) 805d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tmp = ATA_DEVICE_OBS; 806d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang else 807d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tmp = ATA_DEVICE_OBS | ATA_DEV1; 808d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 809d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_DEVICE, tmp); 8109363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo ata_sff_pause(ap); 811d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 812d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 813d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 81441dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov * bfin_set_devctl - Write device control reg 81541dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov * @ap: port where the device is 81641dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov * @ctl: value to write 81741dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov */ 81841dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov 819c0695733d56ea12ad62ee534c2eed91f917548aeMike Frysingerstatic void bfin_set_devctl(struct ata_port *ap, u8 ctl) 82041dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov{ 82141dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 82241dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov write_atapi_register(base, ATA_REG_CTRL, ctl); 82341dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov} 82441dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov 82541dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov/** 826d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_bmdma_setup - Set up IDE DMA transaction 827d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @qc: Info associated with this ATA transaction. 828d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 829d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Note: Original code is ata_bmdma_setup(). 830d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 831d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 832d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void bfin_bmdma_setup(struct ata_queued_cmd *qc) 833d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 83481b0287d341535ac722de891b19f7c49212ac91cSonic Zhang struct ata_port *ap = qc->ap; 83581b0287d341535ac722de891b19f7c49212ac91cSonic Zhang struct dma_desc_array *dma_desc_cpu = (struct dma_desc_array *)ap->bmdma_prd; 83681b0287d341535ac722de891b19f7c49212ac91cSonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 83781b0287d341535ac722de891b19f7c49212ac91cSonic Zhang unsigned short config = DMAFLOW_ARRAY | NDSIZE_5 | RESTART | WDSIZE_16 | DMAEN; 838d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang struct scatterlist *sg; 839ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo unsigned int si; 84081b0287d341535ac722de891b19f7c49212ac91cSonic Zhang unsigned int channel; 84181b0287d341535ac722de891b19f7c49212ac91cSonic Zhang unsigned int dir; 84281b0287d341535ac722de891b19f7c49212ac91cSonic Zhang unsigned int size = 0; 843d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 844f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(qc->ap->dev, "in atapi dma setup\n"); 845d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_CTRL register with dir */ 846d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (qc->tf.flags & ATA_TFLAG_WRITE) { 84781b0287d341535ac722de891b19f7c49212ac91cSonic Zhang channel = CH_ATAPI_TX; 84881b0287d341535ac722de891b19f7c49212ac91cSonic Zhang dir = DMA_TO_DEVICE; 849d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } else { 85081b0287d341535ac722de891b19f7c49212ac91cSonic Zhang channel = CH_ATAPI_RX; 85181b0287d341535ac722de891b19f7c49212ac91cSonic Zhang dir = DMA_FROM_DEVICE; 852d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang config |= WNR; 853d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 854d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 85581b0287d341535ac722de891b19f7c49212ac91cSonic Zhang dma_map_sg(ap->dev, qc->sg, qc->n_elem, dir); 856d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 85781b0287d341535ac722de891b19f7c49212ac91cSonic Zhang /* fill the ATAPI DMA controller */ 85881b0287d341535ac722de891b19f7c49212ac91cSonic Zhang for_each_sg(qc->sg, sg, qc->n_elem, si) { 85981b0287d341535ac722de891b19f7c49212ac91cSonic Zhang dma_desc_cpu[si].start_addr = sg_dma_address(sg); 86081b0287d341535ac722de891b19f7c49212ac91cSonic Zhang dma_desc_cpu[si].cfg = config; 86181b0287d341535ac722de891b19f7c49212ac91cSonic Zhang dma_desc_cpu[si].x_count = sg_dma_len(sg) >> 1; 86281b0287d341535ac722de891b19f7c49212ac91cSonic Zhang dma_desc_cpu[si].x_modify = 2; 86381b0287d341535ac722de891b19f7c49212ac91cSonic Zhang size += sg_dma_len(sg); 86481b0287d341535ac722de891b19f7c49212ac91cSonic Zhang } 865d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 86681b0287d341535ac722de891b19f7c49212ac91cSonic Zhang /* Set the last descriptor to stop mode */ 86781b0287d341535ac722de891b19f7c49212ac91cSonic Zhang dma_desc_cpu[qc->n_elem - 1].cfg &= ~(DMAFLOW | NDSIZE); 868d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 86981b0287d341535ac722de891b19f7c49212ac91cSonic Zhang flush_dcache_range((unsigned int)dma_desc_cpu, 87081b0287d341535ac722de891b19f7c49212ac91cSonic Zhang (unsigned int)dma_desc_cpu + 87181b0287d341535ac722de891b19f7c49212ac91cSonic Zhang qc->n_elem * sizeof(struct dma_desc_array)); 87281b0287d341535ac722de891b19f7c49212ac91cSonic Zhang 87381b0287d341535ac722de891b19f7c49212ac91cSonic Zhang /* Enable ATA DMA operation*/ 87481b0287d341535ac722de891b19f7c49212ac91cSonic Zhang set_dma_curr_desc_addr(channel, (unsigned long *)ap->bmdma_prd_dma); 87581b0287d341535ac722de891b19f7c49212ac91cSonic Zhang set_dma_x_count(channel, 0); 87681b0287d341535ac722de891b19f7c49212ac91cSonic Zhang set_dma_x_modify(channel, 0); 87781b0287d341535ac722de891b19f7c49212ac91cSonic Zhang set_dma_config(channel, config); 87881b0287d341535ac722de891b19f7c49212ac91cSonic Zhang 87981b0287d341535ac722de891b19f7c49212ac91cSonic Zhang SSYNC(); 880d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 88181b0287d341535ac722de891b19f7c49212ac91cSonic Zhang /* Send ATA DMA command */ 88281b0287d341535ac722de891b19f7c49212ac91cSonic Zhang bfin_exec_command(ap, &qc->tf); 883d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 88481b0287d341535ac722de891b19f7c49212ac91cSonic Zhang if (qc->tf.flags & ATA_TFLAG_WRITE) { 885d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* set ATA DMA write direction */ 886d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) 887d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang | XFER_DIR)); 888d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } else { 889d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* set ATA DMA read direction */ 890d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) 891d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang & ~XFER_DIR)); 892d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 893d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 894d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Reset all transfer count */ 895d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | TFRCNT_RST); 896d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 897b6e7b447975b0364c3430284c7b16e2e89ccf9e9Sonic Zhang /* Set ATAPI state machine contorl in terminate sequence */ 898b6e7b447975b0364c3430284c7b16e2e89ccf9e9Sonic Zhang ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | END_ON_TERM); 899b6e7b447975b0364c3430284c7b16e2e89ccf9e9Sonic Zhang 90081b0287d341535ac722de891b19f7c49212ac91cSonic Zhang /* Set transfer length to the total size of sg buffers */ 90181b0287d341535ac722de891b19f7c49212ac91cSonic Zhang ATAPI_SET_XFER_LEN(base, size >> 1); 90281b0287d341535ac722de891b19f7c49212ac91cSonic Zhang} 903d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 90481b0287d341535ac722de891b19f7c49212ac91cSonic Zhang/** 90581b0287d341535ac722de891b19f7c49212ac91cSonic Zhang * bfin_bmdma_start - Start an IDE DMA transaction 90681b0287d341535ac722de891b19f7c49212ac91cSonic Zhang * @qc: Info associated with this ATA transaction. 90781b0287d341535ac722de891b19f7c49212ac91cSonic Zhang * 90881b0287d341535ac722de891b19f7c49212ac91cSonic Zhang * Note: Original code is ata_bmdma_start(). 90981b0287d341535ac722de891b19f7c49212ac91cSonic Zhang */ 91081b0287d341535ac722de891b19f7c49212ac91cSonic Zhang 91181b0287d341535ac722de891b19f7c49212ac91cSonic Zhangstatic void bfin_bmdma_start(struct ata_queued_cmd *qc) 91281b0287d341535ac722de891b19f7c49212ac91cSonic Zhang{ 91381b0287d341535ac722de891b19f7c49212ac91cSonic Zhang struct ata_port *ap = qc->ap; 91481b0287d341535ac722de891b19f7c49212ac91cSonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 91581b0287d341535ac722de891b19f7c49212ac91cSonic Zhang 91681b0287d341535ac722de891b19f7c49212ac91cSonic Zhang dev_dbg(qc->ap->dev, "in atapi dma start\n"); 91781b0287d341535ac722de891b19f7c49212ac91cSonic Zhang 91881b0287d341535ac722de891b19f7c49212ac91cSonic Zhang if (!(ap->udma_mask || ap->mwdma_mask)) 91981b0287d341535ac722de891b19f7c49212ac91cSonic Zhang return; 92081b0287d341535ac722de891b19f7c49212ac91cSonic Zhang 92181b0287d341535ac722de891b19f7c49212ac91cSonic Zhang /* start ATAPI transfer*/ 922d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (ap->udma_mask) 923d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) 924d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang | ULTRA_START); 925d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang else 926d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) 927d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang | MULTI_START); 928d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 929d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 930d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 931d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_bmdma_stop - Stop IDE DMA transfer 932d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @qc: Command we are ending DMA for 933d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 934d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 935d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void bfin_bmdma_stop(struct ata_queued_cmd *qc) 936d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 937d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang struct ata_port *ap = qc->ap; 93881b0287d341535ac722de891b19f7c49212ac91cSonic Zhang unsigned int dir; 939d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 940f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(qc->ap->dev, "in atapi dma stop\n"); 94181b0287d341535ac722de891b19f7c49212ac91cSonic Zhang 942d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (!(ap->udma_mask || ap->mwdma_mask)) 943d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return; 944d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 945d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* stop ATAPI DMA controller*/ 94681b0287d341535ac722de891b19f7c49212ac91cSonic Zhang if (qc->tf.flags & ATA_TFLAG_WRITE) { 94781b0287d341535ac722de891b19f7c49212ac91cSonic Zhang dir = DMA_TO_DEVICE; 948d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang disable_dma(CH_ATAPI_TX); 94981b0287d341535ac722de891b19f7c49212ac91cSonic Zhang } else { 95081b0287d341535ac722de891b19f7c49212ac91cSonic Zhang dir = DMA_FROM_DEVICE; 951d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang disable_dma(CH_ATAPI_RX); 952d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 95381b0287d341535ac722de891b19f7c49212ac91cSonic Zhang 95481b0287d341535ac722de891b19f7c49212ac91cSonic Zhang dma_unmap_sg(ap->dev, qc->sg, qc->n_elem, dir); 955d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 956d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 957d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 958d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_devchk - PATA device presence detection 959d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: ATA channel to examine 960d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @device: Device to examine (starting at zero) 961d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 962d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Note: Original code is ata_devchk(). 963d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 964d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 965d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic unsigned int bfin_devchk(struct ata_port *ap, 966d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned int device) 967d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 968d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 969d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang u8 nsect, lbal; 970d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 9719363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo bfin_dev_select(ap, device); 972d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 973d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_NSECT, 0x55); 974d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_LBAL, 0xaa); 975d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 976d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_NSECT, 0xaa); 977d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_LBAL, 0x55); 978d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 979d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_NSECT, 0x55); 980d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_LBAL, 0xaa); 981d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 982d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang nsect = read_atapi_register(base, ATA_REG_NSECT); 983d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang lbal = read_atapi_register(base, ATA_REG_LBAL); 984d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 985d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if ((nsect == 0x55) && (lbal == 0xaa)) 986d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 1; /* we found a device */ 987d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 988d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 0; /* nothing found */ 989d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 990d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 991d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 992d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_bus_post_reset - PATA device post reset 993d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 994d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Note: Original code is ata_bus_post_reset(). 995d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 996d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 997d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void bfin_bus_post_reset(struct ata_port *ap, unsigned int devmask) 998d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 999d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 1000d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned int dev0 = devmask & (1 << 0); 1001d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned int dev1 = devmask & (1 << 1); 1002341c2c958ec7bdd9f54733a8b0b432fe76842a82Tejun Heo unsigned long deadline; 1003d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1004d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* if device 0 was found in ata_devchk, wait for its 1005d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * BSY bit to clear 1006d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1007d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (dev0) 10089363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo ata_sff_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT); 1009d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1010d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* if device 1 was found in ata_devchk, wait for 1011d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * register access, then wait for BSY to clear 1012d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1013341c2c958ec7bdd9f54733a8b0b432fe76842a82Tejun Heo deadline = ata_deadline(jiffies, ATA_TMOUT_BOOT); 1014d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang while (dev1) { 1015d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang u8 nsect, lbal; 1016d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 10179363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo bfin_dev_select(ap, 1); 1018d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang nsect = read_atapi_register(base, ATA_REG_NSECT); 1019d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang lbal = read_atapi_register(base, ATA_REG_LBAL); 1020d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if ((nsect == 1) && (lbal == 1)) 1021d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang break; 1022341c2c958ec7bdd9f54733a8b0b432fe76842a82Tejun Heo if (time_after(jiffies, deadline)) { 1023d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang dev1 = 0; 1024d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang break; 1025d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 102697750cebb3000a9cc08f8ce8dc8c7143be7d7201Tejun Heo ata_msleep(ap, 50); /* give drive a breather */ 1027d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 1028d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (dev1) 10299363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo ata_sff_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT); 1030d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1031d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* is all this really necessary? */ 10329363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo bfin_dev_select(ap, 0); 1033d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (dev1) 10349363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo bfin_dev_select(ap, 1); 1035d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (dev0) 10369363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo bfin_dev_select(ap, 0); 1037d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1038d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1039d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 1040d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_bus_softreset - PATA device software reset 1041d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 1042d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Note: Original code is ata_bus_softreset(). 1043d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1044d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1045d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic unsigned int bfin_bus_softreset(struct ata_port *ap, 1046d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned int devmask) 1047d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1048d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 1049d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1050d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* software reset. causes dev0 to be selected */ 1051d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_CTRL, ap->ctl); 1052d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang udelay(20); 1053d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_CTRL, ap->ctl | ATA_SRST); 1054d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang udelay(20); 1055d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_CTRL, ap->ctl); 1056d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1057d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* spec mandates ">= 2ms" before checking status. 1058d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * We wait 150ms, because that was the magic delay used for 1059d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * ATAPI devices in Hale Landis's ATADRVR, for the period of time 1060d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * between when the ATA command register is written, and then 1061d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * status is checked. Because waiting for "a while" before 1062d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * checking status is fine, post SRST, we perform this magic 1063d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * delay here as well. 1064d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 1065d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Old drivers/ide uses the 2mS rule and then waits for ready 1066d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 106797750cebb3000a9cc08f8ce8dc8c7143be7d7201Tejun Heo ata_msleep(ap, 150); 1068d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1069d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Before we perform post reset processing we want to see if 1070d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * the bus shows 0xFF because the odd clown forgets the D7 1071d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * pulldown resistor. 1072d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1073d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (bfin_check_status(ap) == 0xFF) 1074d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 0; 1075d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1076d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_bus_post_reset(ap, devmask); 1077d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1078d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 0; 1079d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1080d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1081d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 10829363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * bfin_softreset - reset host port via ATA SRST 1083d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: port to reset 1084d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @classes: resulting classes of attached devices 1085d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 10869363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_softreset(). 1087d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1088d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 10899363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heostatic int bfin_softreset(struct ata_link *link, unsigned int *classes, 10909363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo unsigned long deadline) 1091d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1092858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang struct ata_port *ap = link->ap; 1093d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; 1094d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned int devmask = 0, err_mask; 1095d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang u8 err; 1096d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1097d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* determine if device 0/1 are present */ 1098d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (bfin_devchk(ap, 0)) 1099d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang devmask |= (1 << 0); 1100d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (slave_possible && bfin_devchk(ap, 1)) 1101d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang devmask |= (1 << 1); 1102d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1103d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* select device 0 again */ 11049363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo bfin_dev_select(ap, 0); 1105d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1106d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* issue bus reset */ 1107d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang err_mask = bfin_bus_softreset(ap, devmask); 1108d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (err_mask) { 1109a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches ata_port_err(ap, "SRST failed (err_mask=0x%x)\n", 1110d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang err_mask); 1111d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return -EIO; 1112d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 1113d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1114d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* determine by signature whether we have ATA or ATAPI devices */ 11159363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo classes[0] = ata_sff_dev_classify(&ap->link.device[0], 1116858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang devmask & (1 << 0), &err); 1117d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (slave_possible && err != 0x81) 11189363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo classes[1] = ata_sff_dev_classify(&ap->link.device[1], 1119858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang devmask & (1 << 1), &err); 1120d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1121d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 0; 1122d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1123d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1124d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 1125d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_bmdma_status - Read IDE DMA status 1126d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: Port associated with this ATA transaction. 1127d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1128d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1129d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic unsigned char bfin_bmdma_status(struct ata_port *ap) 1130d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1131d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned char host_stat = 0; 1132d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 1133d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1134909fefc2511120ec71178f752c195c7b0b30269eSergei Shtylyov if (ATAPI_GET_STATUS(base) & (MULTI_XFER_ON | ULTRA_XFER_ON)) 1135dc86f6d4183c79a08fa01c08dd2191895c0c7eb0sonic zhang host_stat |= ATA_DMA_ACTIVE; 1136909fefc2511120ec71178f752c195c7b0b30269eSergei Shtylyov if (ATAPI_GET_INT_STATUS(base) & ATAPI_DEV_INT) 1137dc86f6d4183c79a08fa01c08dd2191895c0c7eb0sonic zhang host_stat |= ATA_DMA_INTR; 1138d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1139f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(ap->dev, "ATAPI: host_stat=0x%x\n", host_stat); 1140f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang 1141d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return host_stat; 1142d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1143d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1144d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 1145d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_data_xfer - Transfer data by PIO 1146d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @adev: device for this I/O 1147d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @buf: data buffer 1148d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @buflen: buffer length 1149d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @write_data: read/write 1150d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 11519363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_data_xfer(). 1152d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1153d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 115455dba3120fbcbea6800f9a18503d25f73212a347Tejun Heostatic unsigned int bfin_data_xfer(struct ata_device *dev, unsigned char *buf, 115555dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo unsigned int buflen, int rw) 1156d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 115755dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo struct ata_port *ap = dev->link->ap; 1158d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 115955dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo unsigned int words = buflen >> 1; 116055dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo unsigned short *buf16 = (u16 *)buf; 1161d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1162d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Transfer multiple of 2 bytes */ 116355dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo if (rw == READ) 1164d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang read_atapi_data(base, words, buf16); 116555dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo else 116655dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo write_atapi_data(base, words, buf16); 1167d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1168d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Transfer trailing 1 byte, if any. */ 1169d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (unlikely(buflen & 0x01)) { 1170d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short align_buf[1] = { 0 }; 1171d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned char *trailing_buf = buf + buflen - 1; 1172d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 117355dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo if (rw == READ) { 1174d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang read_atapi_data(base, 1, align_buf); 1175d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang memcpy(trailing_buf, align_buf, 1); 117655dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo } else { 117755dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo memcpy(align_buf, trailing_buf, 1); 117855dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo write_atapi_data(base, 1, align_buf); 1179d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 118055dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo words++; 1181d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 118255dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo 118355dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo return words << 1; 1184d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1185d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1186d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 1187d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_irq_clear - Clear ATAPI interrupt. 1188d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: Port associated with this ATA transaction. 1189d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 119037f65b8bc262a5ae4c8e58be92fe3032f0aaaf04Tejun Heo * Note: Original code is ata_bmdma_irq_clear(). 1191d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1192d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1193d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void bfin_irq_clear(struct ata_port *ap) 1194d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1195d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 1196d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1197f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(ap->dev, "in atapi irq clear\n"); 1198858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT 1199858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT 1200858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT); 1201d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1202d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1203d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 12049363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * bfin_thaw - Thaw DMA controller port 1205d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: port to thaw 1206d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 12079363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_thaw(). 1208d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1209d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 12109363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heovoid bfin_thaw(struct ata_port *ap) 1211d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 121265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang dev_dbg(ap->dev, "in atapi dma thaw\n"); 1213d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_check_status(ap); 1214e42a542ba9cca594897176020445023c54d903d6Sergei Shtylyov ata_sff_irq_on(ap); 1215d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1216d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1217d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 12189363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * bfin_postreset - standard postreset callback 1219d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: the target ata_port 1220d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @classes: classes of attached devices 1221d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 12229363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_postreset(). 1223d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1224d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 12259363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heostatic void bfin_postreset(struct ata_link *link, unsigned int *classes) 1226d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1227858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang struct ata_port *ap = link->ap; 1228d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 1229d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1230d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* re-enable interrupts */ 1231e42a542ba9cca594897176020445023c54d903d6Sergei Shtylyov ata_sff_irq_on(ap); 1232d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1233d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* is double-select really necessary? */ 1234d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (classes[0] != ATA_DEV_NONE) 12359363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo bfin_dev_select(ap, 1); 1236d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (classes[1] != ATA_DEV_NONE) 12379363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo bfin_dev_select(ap, 0); 1238d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1239d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* bail out if no device is present */ 1240d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) { 1241d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return; 1242d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 1243d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1244d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* set up device control */ 1245d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_CTRL, ap->ctl); 1246d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1247d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1248d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void bfin_port_stop(struct ata_port *ap) 1249d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1250f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(ap->dev, "in atapi port stop\n"); 1251d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (ap->udma_mask != 0 || ap->mwdma_mask != 0) { 125281b0287d341535ac722de891b19f7c49212ac91cSonic Zhang dma_free_coherent(ap->dev, 125381b0287d341535ac722de891b19f7c49212ac91cSonic Zhang BFIN_MAX_SG_SEGMENTS * sizeof(struct dma_desc_array), 125481b0287d341535ac722de891b19f7c49212ac91cSonic Zhang ap->bmdma_prd, 125581b0287d341535ac722de891b19f7c49212ac91cSonic Zhang ap->bmdma_prd_dma); 125681b0287d341535ac722de891b19f7c49212ac91cSonic Zhang 1257d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang free_dma(CH_ATAPI_RX); 1258d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang free_dma(CH_ATAPI_TX); 1259d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 1260d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1261d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1262d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic int bfin_port_start(struct ata_port *ap) 1263d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1264f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(ap->dev, "in atapi port start\n"); 1265d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (!(ap->udma_mask || ap->mwdma_mask)) 1266d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 0; 1267d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 126881b0287d341535ac722de891b19f7c49212ac91cSonic Zhang ap->bmdma_prd = dma_alloc_coherent(ap->dev, 126981b0287d341535ac722de891b19f7c49212ac91cSonic Zhang BFIN_MAX_SG_SEGMENTS * sizeof(struct dma_desc_array), 127081b0287d341535ac722de891b19f7c49212ac91cSonic Zhang &ap->bmdma_prd_dma, 127181b0287d341535ac722de891b19f7c49212ac91cSonic Zhang GFP_KERNEL); 127281b0287d341535ac722de891b19f7c49212ac91cSonic Zhang 127381b0287d341535ac722de891b19f7c49212ac91cSonic Zhang if (ap->bmdma_prd == NULL) { 127481b0287d341535ac722de891b19f7c49212ac91cSonic Zhang dev_info(ap->dev, "Unable to allocate DMA descriptor array.\n"); 127581b0287d341535ac722de891b19f7c49212ac91cSonic Zhang goto out; 127681b0287d341535ac722de891b19f7c49212ac91cSonic Zhang } 127781b0287d341535ac722de891b19f7c49212ac91cSonic Zhang 1278d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (request_dma(CH_ATAPI_RX, "BFIN ATAPI RX DMA") >= 0) { 1279d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (request_dma(CH_ATAPI_TX, 1280d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang "BFIN ATAPI TX DMA") >= 0) 1281d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 0; 1282d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1283d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang free_dma(CH_ATAPI_RX); 128481b0287d341535ac722de891b19f7c49212ac91cSonic Zhang dma_free_coherent(ap->dev, 128581b0287d341535ac722de891b19f7c49212ac91cSonic Zhang BFIN_MAX_SG_SEGMENTS * sizeof(struct dma_desc_array), 128681b0287d341535ac722de891b19f7c49212ac91cSonic Zhang ap->bmdma_prd, 128781b0287d341535ac722de891b19f7c49212ac91cSonic Zhang ap->bmdma_prd_dma); 1288d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 1289d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 129081b0287d341535ac722de891b19f7c49212ac91cSonic Zhangout: 1291d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ap->udma_mask = 0; 1292d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ap->mwdma_mask = 0; 1293d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang dev_err(ap->dev, "Unable to request ATAPI DMA!" 1294d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang " Continue in PIO mode.\n"); 1295d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1296d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 0; 1297d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1298d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 129965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhangstatic unsigned int bfin_ata_host_intr(struct ata_port *ap, 130065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang struct ata_queued_cmd *qc) 130165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang{ 130265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang struct ata_eh_info *ehi = &ap->link.eh_info; 130365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang u8 status, host_stat = 0; 130465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 130565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang VPRINTK("ata%u: protocol %d task_state %d\n", 130665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang ap->print_id, qc->tf.protocol, ap->hsm_task_state); 130765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 130865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang /* Check whether we are expecting interrupt in this state */ 130965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang switch (ap->hsm_task_state) { 131065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang case HSM_ST_FIRST: 131165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang /* Some pre-ATAPI-4 devices assert INTRQ 131265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang * at this state when ready to receive CDB. 131365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang */ 131465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 131565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang /* Check the ATA_DFLAG_CDB_INTR flag is enough here. 131665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang * The flag was turned on only for atapi devices. 131765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang * No need to check is_atapi_taskfile(&qc->tf) again. 131865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang */ 131965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) 132065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang goto idle_irq; 132165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang break; 132265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang case HSM_ST_LAST: 132365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang if (qc->tf.protocol == ATA_PROT_DMA || 132465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang qc->tf.protocol == ATAPI_PROT_DMA) { 132565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang /* check status of DMA engine */ 132665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang host_stat = ap->ops->bmdma_status(ap); 132765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang VPRINTK("ata%u: host_stat 0x%X\n", 132865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang ap->print_id, host_stat); 132965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 133065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang /* if it's not our irq... */ 133165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang if (!(host_stat & ATA_DMA_INTR)) 133265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang goto idle_irq; 133365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 133465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang /* before we do anything else, clear DMA-Start bit */ 133565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang ap->ops->bmdma_stop(qc); 133665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 133765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang if (unlikely(host_stat & ATA_DMA_ERR)) { 133825985edcedea6396277003854657b5f3cb31a628Lucas De Marchi /* error when transferring data to/from memory */ 133965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang qc->err_mask |= AC_ERR_HOST_BUS; 134065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang ap->hsm_task_state = HSM_ST_ERR; 134165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang } 134265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang } 134365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang break; 134465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang case HSM_ST: 134565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang break; 134665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang default: 134765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang goto idle_irq; 134865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang } 134965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 135065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang /* check altstatus */ 135165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang status = ap->ops->sff_check_altstatus(ap); 135265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang if (status & ATA_BUSY) 135365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang goto busy_ata; 135465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 135565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang /* check main status, clearing INTRQ */ 135665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang status = ap->ops->sff_check_status(ap); 135765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang if (unlikely(status & ATA_BUSY)) 135865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang goto busy_ata; 135965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 136065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang /* ack bmdma irq events */ 136165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang ap->ops->sff_irq_clear(ap); 136265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 136365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang ata_sff_hsm_move(ap, qc, status, 0); 136465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 136565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA || 136665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang qc->tf.protocol == ATAPI_PROT_DMA)) 136765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat); 136865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 136965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhangbusy_ata: 137065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang return 1; /* irq handled */ 137165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 137265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhangidle_irq: 137365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang ap->stats.idle_irq++; 137465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 137565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang#ifdef ATA_IRQ_TRAP 137665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang if ((ap->stats.idle_irq % 1000) == 0) { 137765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang ap->ops->irq_ack(ap, 0); /* debug trap */ 1378a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches ata_port_warn(ap, "irq trap\n"); 137965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang return 1; 138065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang } 138165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang#endif 138265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang return 0; /* irq not handled */ 138365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang} 138465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 138565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhangstatic irqreturn_t bfin_ata_interrupt(int irq, void *dev_instance) 138665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang{ 138765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang struct ata_host *host = dev_instance; 138865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang unsigned int i; 138965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang unsigned int handled = 0; 139065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang unsigned long flags; 139165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 139265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */ 139365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang spin_lock_irqsave(&host->lock, flags); 139465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 139565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang for (i = 0; i < host->n_ports; i++) { 13963e4ec3443f70fbe144799ccf0b1c3797f78d1715Tejun Heo struct ata_port *ap = host->ports[i]; 13973e4ec3443f70fbe144799ccf0b1c3797f78d1715Tejun Heo struct ata_queued_cmd *qc; 139865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 13993e4ec3443f70fbe144799ccf0b1c3797f78d1715Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 14003e4ec3443f70fbe144799ccf0b1c3797f78d1715Tejun Heo if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) 14013e4ec3443f70fbe144799ccf0b1c3797f78d1715Tejun Heo handled |= bfin_ata_host_intr(ap, qc); 140265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang } 140365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 140465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang spin_unlock_irqrestore(&host->lock, flags); 140565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 140665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang return IRQ_RETVAL(handled); 140765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang} 140865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 140965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 1410d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic struct scsi_host_template bfin_sht = { 141168d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BASE_SHT(DRV_NAME), 141281b0287d341535ac722de891b19f7c49212ac91cSonic Zhang .sg_tablesize = BFIN_MAX_SG_SEGMENTS, 1413d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .dma_boundary = ATA_DMA_BOUNDARY, 1414d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang}; 1415d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 141665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhangstatic struct ata_port_operations bfin_pata_ops = { 14178930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .inherits = &ata_bmdma_port_ops, 1418029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo 1419d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .set_piomode = bfin_set_piomode, 1420d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .set_dmamode = bfin_set_dmamode, 1421d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 14225682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_tf_load = bfin_tf_load, 14235682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_tf_read = bfin_tf_read, 14245682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_exec_command = bfin_exec_command, 14255682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_check_status = bfin_check_status, 14265682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_check_altstatus = bfin_check_altstatus, 14275682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_dev_select = bfin_dev_select, 142841dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov .sff_set_devctl = bfin_set_devctl, 1429d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1430d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .bmdma_setup = bfin_bmdma_setup, 1431d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .bmdma_start = bfin_bmdma_start, 1432d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .bmdma_stop = bfin_bmdma_stop, 1433d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .bmdma_status = bfin_bmdma_status, 14345682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_data_xfer = bfin_data_xfer, 1435d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1436d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .qc_prep = ata_noop_qc_prep, 1437d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 14389363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo .thaw = bfin_thaw, 14399363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo .softreset = bfin_softreset, 14409363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo .postreset = bfin_postreset, 1441d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 14425682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_irq_clear = bfin_irq_clear, 1443d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1444d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .port_start = bfin_port_start, 1445d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .port_stop = bfin_port_stop, 1446d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang}; 1447d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1448d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic struct ata_port_info bfin_port_info[] = { 1449d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang { 14509cbe056f6c467e7395d5aec39aceec47812eb98eSergei Shtylyov .flags = ATA_FLAG_SLAVE_POSS, 145114bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .pio_mask = ATA_PIO4, 1452d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .mwdma_mask = 0, 1453d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .udma_mask = 0, 1454d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .port_ops = &bfin_pata_ops, 1455d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang }, 1456d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang}; 1457d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1458d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 1459d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_reset_controller - initialize BF54x ATAPI controller. 1460d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1461d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1462d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic int bfin_reset_controller(struct ata_host *host) 1463d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1464d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)host->ports[0]->ioaddr.ctl_addr; 1465d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang int count; 1466d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short status; 1467d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1468d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Disable all ATAPI interrupts */ 1469d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_INT_MASK(base, 0); 1470d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang SSYNC(); 1471d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1472d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Assert the RESET signal 25us*/ 1473d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | DEV_RST); 1474d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang udelay(30); 1475d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1476d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Negate the RESET signal for 2ms*/ 1477d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) & ~DEV_RST); 1478d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang msleep(2); 1479d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1480d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Wait on Busy flag to clear */ 1481d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang count = 10000000; 1482d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang do { 1483d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang status = read_atapi_register(base, ATA_REG_STATUS); 1484f9d42491723dbb77bdc9b9dc7e096ea57d535992Roel Kluin } while (--count && (status & ATA_BUSY)); 1485d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1486d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Enable only ATAPI Device interrupt */ 1487d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_INT_MASK(base, 1); 1488d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang SSYNC(); 1489d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1490d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return (!count); 1491d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1492d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1493d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 1494d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * atapi_io_port - define atapi peripheral port pins. 1495d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1496d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic unsigned short atapi_io_port[] = { 1497d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang P_ATAPI_RESET, 1498d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang P_ATAPI_DIOR, 1499d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang P_ATAPI_DIOW, 1500d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang P_ATAPI_CS0, 1501d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang P_ATAPI_CS1, 1502d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang P_ATAPI_DMACK, 1503d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang P_ATAPI_DMARQ, 1504d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang P_ATAPI_INTRQ, 1505d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang P_ATAPI_IORDY, 15063439d65062a4af6af0433c8816fd54697d782ff4Sonic Zhang P_ATAPI_D0A, 15073439d65062a4af6af0433c8816fd54697d782ff4Sonic Zhang P_ATAPI_D1A, 15083439d65062a4af6af0433c8816fd54697d782ff4Sonic Zhang P_ATAPI_D2A, 15093439d65062a4af6af0433c8816fd54697d782ff4Sonic Zhang P_ATAPI_D3A, 15103439d65062a4af6af0433c8816fd54697d782ff4Sonic Zhang P_ATAPI_D4A, 15113439d65062a4af6af0433c8816fd54697d782ff4Sonic Zhang P_ATAPI_D5A, 15123439d65062a4af6af0433c8816fd54697d782ff4Sonic Zhang P_ATAPI_D6A, 15133439d65062a4af6af0433c8816fd54697d782ff4Sonic Zhang P_ATAPI_D7A, 15143439d65062a4af6af0433c8816fd54697d782ff4Sonic Zhang P_ATAPI_D8A, 15153439d65062a4af6af0433c8816fd54697d782ff4Sonic Zhang P_ATAPI_D9A, 15163439d65062a4af6af0433c8816fd54697d782ff4Sonic Zhang P_ATAPI_D10A, 15173439d65062a4af6af0433c8816fd54697d782ff4Sonic Zhang P_ATAPI_D11A, 15183439d65062a4af6af0433c8816fd54697d782ff4Sonic Zhang P_ATAPI_D12A, 15193439d65062a4af6af0433c8816fd54697d782ff4Sonic Zhang P_ATAPI_D13A, 15203439d65062a4af6af0433c8816fd54697d782ff4Sonic Zhang P_ATAPI_D14A, 15213439d65062a4af6af0433c8816fd54697d782ff4Sonic Zhang P_ATAPI_D15A, 15223439d65062a4af6af0433c8816fd54697d782ff4Sonic Zhang P_ATAPI_A0A, 15233439d65062a4af6af0433c8816fd54697d782ff4Sonic Zhang P_ATAPI_A1A, 15243439d65062a4af6af0433c8816fd54697d782ff4Sonic Zhang P_ATAPI_A2A, 1525d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 0 1526d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang}; 1527d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1528d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 1529d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_atapi_probe - attach a bfin atapi interface 1530d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @pdev: platform device 1531d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 1532d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Register a bfin atapi interface. 1533d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 1534d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 1535d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Platform devices are expected to contain 2 resources per port: 1536d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 1537d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * - I/O Base (IORESOURCE_IO) 1538d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * - IRQ (IORESOURCE_IRQ) 1539d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 1540d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1541d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic int __devinit bfin_atapi_probe(struct platform_device *pdev) 1542d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1543d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang int board_idx = 0; 1544d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang struct resource *res; 1545d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang struct ata_host *host; 1546f88c480dac88a754f84e943cb5539d59cda3c089sonic zhang unsigned int fsclk = get_sclk(); 1547f88c480dac88a754f84e943cb5539d59cda3c089sonic zhang int udma_mode = 5; 1548d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang const struct ata_port_info *ppi[] = 1549d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang { &bfin_port_info[board_idx], NULL }; 1550d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1551d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* 1552d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Simple resource validation .. 1553d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1554d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (unlikely(pdev->num_resources != 2)) { 1555d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang dev_err(&pdev->dev, "invalid number of resources\n"); 1556d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return -EINVAL; 1557d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 1558d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1559d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* 1560d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Get the register base first 1561d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1562d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1563d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (res == NULL) 1564d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return -EINVAL; 1565d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1566ed722d3d3eb2e9ea87d9f8109c291337e79d584aAndrew Morton while (bfin_port_info[board_idx].udma_mask > 0 && 1567ed722d3d3eb2e9ea87d9f8109c291337e79d584aAndrew Morton udma_fsclk[udma_mode] > fsclk) { 1568f88c480dac88a754f84e943cb5539d59cda3c089sonic zhang udma_mode--; 1569f88c480dac88a754f84e943cb5539d59cda3c089sonic zhang bfin_port_info[board_idx].udma_mask >>= 1; 1570f88c480dac88a754f84e943cb5539d59cda3c089sonic zhang } 1571f88c480dac88a754f84e943cb5539d59cda3c089sonic zhang 1572d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* 1573d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Now that that's out of the way, wire up the port.. 1574d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1575d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1); 1576d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (!host) 1577d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return -ENOMEM; 1578d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1579d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang host->ports[0]->ioaddr.ctl_addr = (void *)res->start; 1580d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1581d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (peripheral_request_list(atapi_io_port, "atapi-io-port")) { 1582426d31071ac476ea62c62656b242930c17b58c00Paul Bolle dev_err(&pdev->dev, "Requesting Peripherals failed\n"); 1583d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return -EFAULT; 1584d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 1585d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1586d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (bfin_reset_controller(host)) { 1587d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang peripheral_free_list(atapi_io_port); 1588d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang dev_err(&pdev->dev, "Fail to reset ATAPI device\n"); 1589d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return -EFAULT; 1590d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 1591d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1592d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (ata_host_activate(host, platform_get_irq(pdev, 0), 159365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang bfin_ata_interrupt, IRQF_SHARED, &bfin_sht) != 0) { 1594d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang peripheral_free_list(atapi_io_port); 1595d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang dev_err(&pdev->dev, "Fail to attach ATAPI device\n"); 1596d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return -ENODEV; 1597d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 1598d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 159967e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang dev_set_drvdata(&pdev->dev, host); 160067e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang 1601d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 0; 1602d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1603d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1604d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 1605d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_atapi_remove - unplug a bfin atapi interface 1606d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @pdev: platform device 1607d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 1608d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * A bfin atapi device has been unplugged. Perform the needed 1609d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * cleanup. Also called on module unload for any active devices. 1610d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1611d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic int __devexit bfin_atapi_remove(struct platform_device *pdev) 1612d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1613d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang struct device *dev = &pdev->dev; 1614d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang struct ata_host *host = dev_get_drvdata(dev); 1615d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1616d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ata_host_detach(host); 161767e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang dev_set_drvdata(&pdev->dev, NULL); 1618d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1619d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang peripheral_free_list(atapi_io_port); 1620d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1621d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 0; 1622d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1623d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1624d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#ifdef CONFIG_PM 162567e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhangstatic int bfin_atapi_suspend(struct platform_device *pdev, pm_message_t state) 1626d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 162767e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang struct ata_host *host = dev_get_drvdata(&pdev->dev); 162867e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang if (host) 162967e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang return ata_host_suspend(host, state); 163067e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang else 163167e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang return 0; 1632d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1633d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 163467e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhangstatic int bfin_atapi_resume(struct platform_device *pdev) 1635d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 163667e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang struct ata_host *host = dev_get_drvdata(&pdev->dev); 163767e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang int ret; 163867e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang 163967e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang if (host) { 164067e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang ret = bfin_reset_controller(host); 164167e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang if (ret) { 164267e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang printk(KERN_ERR DRV_NAME ": Error during HW init\n"); 164367e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang return ret; 164467e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang } 164567e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang ata_host_resume(host); 164667e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang } 164767e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang 1648d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 0; 1649d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 165067e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang#else 165167e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang#define bfin_atapi_suspend NULL 165267e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang#define bfin_atapi_resume NULL 1653d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#endif 1654d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1655d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic struct platform_driver bfin_atapi_driver = { 1656d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .probe = bfin_atapi_probe, 1657d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .remove = __devexit_p(bfin_atapi_remove), 165867e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang .suspend = bfin_atapi_suspend, 165967e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang .resume = bfin_atapi_resume, 1660d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .driver = { 1661d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .name = DRV_NAME, 1662d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .owner = THIS_MODULE, 1663d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang }, 1664d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang}; 1665d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1666858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang#define ATAPI_MODE_SIZE 10 1667858c9c406688bc7244986b5836265071edfd1d3fSonic Zhangstatic char bfin_atapi_mode[ATAPI_MODE_SIZE]; 1668858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang 1669d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic int __init bfin_atapi_init(void) 1670d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1671d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang pr_info("register bfin atapi driver\n"); 1672858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang 1673858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang switch(bfin_atapi_mode[0]) { 1674858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang case 'p': 1675858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang case 'P': 1676858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang break; 1677858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang case 'm': 1678858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang case 'M': 1679858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang bfin_port_info[0].mwdma_mask = ATA_MWDMA2; 1680858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang break; 1681858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang default: 1682858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang bfin_port_info[0].udma_mask = ATA_UDMA5; 1683858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang }; 1684858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang 1685d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return platform_driver_register(&bfin_atapi_driver); 1686d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1687d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1688d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void __exit bfin_atapi_exit(void) 1689d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1690d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang platform_driver_unregister(&bfin_atapi_driver); 1691d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1692d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1693d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangmodule_init(bfin_atapi_init); 1694d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangmodule_exit(bfin_atapi_exit); 1695858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang/* 1696858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang * ATAPI mode: 1697858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang * pio/PIO 1698858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang * udma/UDMA (default) 1699858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang * mwdma/MWDMA 1700858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang */ 1701858c9c406688bc7244986b5836265071edfd1d3fSonic Zhangmodule_param_string(bfin_atapi_mode, bfin_atapi_mode, ATAPI_MODE_SIZE, 0); 1702d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1703d830d1731fa5906aad20c228ac8b73005b13d468Sonic ZhangMODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>"); 1704d830d1731fa5906aad20c228ac8b73005b13d468Sonic ZhangMODULE_DESCRIPTION("PATA driver for blackfin 54x ATAPI controller"); 1705d830d1731fa5906aad20c228ac8b73005b13d468Sonic ZhangMODULE_LICENSE("GPL"); 1706d830d1731fa5906aad20c228ac8b73005b13d468Sonic ZhangMODULE_VERSION(DRV_VERSION); 1707458622fcdc5b316de8d74efd7e610803f0308c14Kay SieversMODULE_ALIAS("platform:" DRV_NAME); 1708