pata_bf54x.c revision 67e3e221d61c0e70b2f244fd921e5e601d6c7339
1d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* 2d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * File: drivers/ata/pata_bf54x.c 3d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Author: Sonic Zhang <sonic.zhang@analog.com> 4d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 5d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Created: 6d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Description: PATA Driver for blackfin 54x 7d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 8d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Modified: 9d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Copyright 2007 Analog Devices Inc. 10d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 11d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Bugs: Enter bugs at http://blackfin.uclinux.org/ 12d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 13d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * This program is free software; you can redistribute it and/or modify 14d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * it under the terms of the GNU General Public License as published by 15d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * the Free Software Foundation; either version 2 of the License, or 16d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * (at your option) any later version. 17d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 18d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * This program is distributed in the hope that it will be useful, 19d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * but WITHOUT ANY WARRANTY; without even the implied warranty of 20d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * GNU General Public License for more details. 22d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 23d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * You should have received a copy of the GNU General Public License 24d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * along with this program; if not, see the file COPYING, or write 25d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * to the Free Software Foundation, Inc., 26d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 27d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 28d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 29d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <linux/kernel.h> 30d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <linux/module.h> 31d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <linux/pci.h> 32d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <linux/init.h> 33d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <linux/blkdev.h> 34d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <linux/delay.h> 35d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <linux/device.h> 36d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <scsi/scsi_host.h> 37d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <linux/libata.h> 38d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <linux/platform_device.h> 39d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <asm/dma.h> 40d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <asm/gpio.h> 41d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#include <asm/portmux.h> 42d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 43d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define DRV_NAME "pata-bf54x" 44d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define DRV_VERSION "0.9" 45d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 46d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATA_REG_CTRL 0x0E 47d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATA_REG_ALTSTATUS ATA_REG_CTRL 48d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 49d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* These are the offset of the controller's registers */ 50d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_CONTROL 0x00 51d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_STATUS 0x04 52d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_DEV_ADDR 0x08 53d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_DEV_TXBUF 0x0c 54d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_DEV_RXBUF 0x10 55d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_INT_MASK 0x14 56d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_INT_STATUS 0x18 57d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_XFER_LEN 0x1c 58d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_LINE_STATUS 0x20 59d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_SM_STATE 0x24 60d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_TERMINATE 0x28 61d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_PIO_TFRCNT 0x2c 62d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_DMA_TFRCNT 0x30 63d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_UMAIN_TFRCNT 0x34 64d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_UDMAOUT_TFRCNT 0x38 65d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_REG_TIM_0 0x40 66d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_PIO_TIM_0 0x44 67d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_PIO_TIM_1 0x48 68d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_MULTI_TIM_0 0x50 69d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_MULTI_TIM_1 0x54 70d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_MULTI_TIM_2 0x58 71d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_ULTRA_TIM_0 0x60 72d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_ULTRA_TIM_1 0x64 73d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_ULTRA_TIM_2 0x68 74d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_OFFSET_ULTRA_TIM_3 0x6c 75d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 76d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 77d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_CONTROL(base)\ 78d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_CONTROL) 79d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_CONTROL(base, val)\ 80d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_CONTROL, val) 81d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_STATUS(base)\ 82d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_STATUS) 83d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_DEV_ADDR(base)\ 84d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_DEV_ADDR) 85d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_DEV_ADDR(base, val)\ 86d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val) 87d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_DEV_TXBUF(base)\ 88d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_DEV_TXBUF) 89d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_DEV_TXBUF(base, val)\ 90d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_DEV_TXBUF, val) 91d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_DEV_RXBUF(base)\ 92d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_DEV_RXBUF) 93d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_DEV_RXBUF(base, val)\ 94d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_DEV_RXBUF, val) 95d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_INT_MASK(base)\ 96d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_INT_MASK) 97d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_INT_MASK(base, val)\ 98d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_INT_MASK, val) 99d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_INT_STATUS(base)\ 100d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_INT_STATUS) 101d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_INT_STATUS(base, val)\ 102d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_INT_STATUS, val) 103d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_XFER_LEN(base)\ 104d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_XFER_LEN) 105d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_XFER_LEN(base, val)\ 106d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_XFER_LEN, val) 107d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_LINE_STATUS(base)\ 108d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_LINE_STATUS) 109d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_SM_STATE(base)\ 110d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_SM_STATE) 111d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_TERMINATE(base)\ 112d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_TERMINATE) 113d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_TERMINATE(base, val)\ 114d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_TERMINATE, val) 115d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_PIO_TFRCNT(base)\ 116d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_PIO_TFRCNT) 117d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_DMA_TFRCNT(base)\ 118d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_DMA_TFRCNT) 119d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_UMAIN_TFRCNT(base)\ 120d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_UMAIN_TFRCNT) 121d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_UDMAOUT_TFRCNT(base)\ 122d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_UDMAOUT_TFRCNT) 123d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_REG_TIM_0(base)\ 124d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_REG_TIM_0) 125d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_REG_TIM_0(base, val)\ 126d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_REG_TIM_0, val) 127d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_PIO_TIM_0(base)\ 128d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_PIO_TIM_0) 129d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_PIO_TIM_0(base, val)\ 130d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_PIO_TIM_0, val) 131d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_PIO_TIM_1(base)\ 132d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_PIO_TIM_1) 133d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_PIO_TIM_1(base, val)\ 134d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_PIO_TIM_1, val) 135d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_MULTI_TIM_0(base)\ 136d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_0) 137d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_MULTI_TIM_0(base, val)\ 138d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_0, val) 139d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_MULTI_TIM_1(base)\ 140d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_1) 141d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_MULTI_TIM_1(base, val)\ 142d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_1, val) 143d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_MULTI_TIM_2(base)\ 144d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_2) 145d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_MULTI_TIM_2(base, val)\ 146d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_2, val) 147d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_ULTRA_TIM_0(base)\ 148d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_0) 149d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_ULTRA_TIM_0(base, val)\ 150d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_0, val) 151d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_ULTRA_TIM_1(base)\ 152d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_1) 153d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_ULTRA_TIM_1(base, val)\ 154d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_1, val) 155d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_ULTRA_TIM_2(base)\ 156d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_2) 157d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_ULTRA_TIM_2(base, val)\ 158d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_2, val) 159d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_GET_ULTRA_TIM_3(base)\ 160d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_3) 161d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define ATAPI_SET_ULTRA_TIM_3(base, val)\ 162d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_3, val) 163d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 164d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 165d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * PIO Mode - Frequency compatibility 166d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 167d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* mode: 0 1 2 3 4 */ 168d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 pio_fsclk[] = 169d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 33333333, 33333333, 33333333, 33333333, 33333333 }; 170d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 171d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 172d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * MDMA Mode - Frequency compatibility 173d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 174d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* mode: 0 1 2 */ 175d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 mdma_fsclk[] = { 33333333, 33333333, 33333333 }; 176d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 177d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 178d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * UDMA Mode - Frequency compatibility 179d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 180d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * UDMA5 - 100 MB/s - SCLK = 133 MHz 181d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * UDMA4 - 66 MB/s - SCLK >= 80 MHz 182d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * UDMA3 - 44.4 MB/s - SCLK >= 50 MHz 183d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * UDMA2 - 33 MB/s - SCLK >= 40 MHz 184d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 185d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* mode: 0 1 2 3 4 5 */ 186d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_fsclk[] = 187d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 33333333, 33333333, 40000000, 50000000, 80000000, 133333333 }; 188d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 189d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 190d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Register transfer timing table 191d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 192d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* mode: 0 1 2 3 4 */ 193d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* Cycle Time */ 194d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 reg_t0min[] = { 600, 383, 330, 180, 120 }; 195d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DIOR/DIOW to end cycle */ 196d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 reg_t2min[] = { 290, 290, 290, 70, 25 }; 197d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DIOR/DIOW asserted pulse width */ 198d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 reg_teocmin[] = { 290, 290, 290, 80, 70 }; 199d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 200d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 201d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * PIO timing table 202d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 203d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* mode: 0 1 2 3 4 */ 204d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* Cycle Time */ 205d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 pio_t0min[] = { 600, 383, 240, 180, 120 }; 206d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* Address valid to DIOR/DIORW */ 207d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 pio_t1min[] = { 70, 50, 30, 30, 25 }; 208d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DIOR/DIOW to end cycle */ 209d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 pio_t2min[] = { 165, 125, 100, 80, 70 }; 210d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DIOR/DIOW asserted pulse width */ 211d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 pio_teocmin[] = { 165, 125, 100, 70, 25 }; 212d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DIOW data hold */ 213d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 pio_t4min[] = { 30, 20, 15, 10, 10 }; 214d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 215d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* ****************************************************************** 216d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Multiword DMA timing table 217d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * ****************************************************************** 218d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 219d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* mode: 0 1 2 */ 220d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* Cycle Time */ 221d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 mdma_t0min[] = { 480, 150, 120 }; 222d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DIOR/DIOW asserted pulse width */ 223d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 mdma_tdmin[] = { 215, 80, 70 }; 224d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DMACK to read data released */ 225d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 mdma_thmin[] = { 20, 15, 10 }; 226d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DIOR/DIOW to DMACK hold */ 227d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 mdma_tjmin[] = { 20, 5, 5 }; 228d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DIOR negated pulse width */ 229d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 mdma_tkrmin[] = { 50, 50, 25 }; 230d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DIOR negated pulse width */ 231d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 mdma_tkwmin[] = { 215, 50, 25 }; 232d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* CS[1:0] valid to DIOR/DIOW */ 233d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 mdma_tmmin[] = { 50, 30, 25 }; 234d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* DMACK to read data released */ 235d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 mdma_tzmax[] = { 20, 25, 25 }; 236d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 237d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 238d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Ultra DMA timing table 239d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 240d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/* mode: 0 1 2 3 4 5 */ 241d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_tcycmin[] = { 112, 73, 54, 39, 25, 17 }; 242d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_tdvsmin[] = { 70, 48, 31, 20, 7, 5 }; 243d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_tenvmax[] = { 70, 70, 70, 55, 55, 50 }; 244d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_trpmin[] = { 160, 125, 100, 100, 100, 85 }; 245d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_tmin[] = { 5, 5, 5, 5, 3, 3 }; 246d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 247d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 248d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_tmlimin = 20; 249d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_tzahmin = 20; 250d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_tenvmin = 20; 251d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_tackmin = 20; 252d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic const u32 udma_tssmin = 50; 253d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 254d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 255d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 256d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Function: num_clocks_min 257d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 258d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Description: 259d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * calculate number of SCLK cycles to meet minimum timing 260d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 261d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic unsigned short num_clocks_min(unsigned long tmin, 262d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned long fsclk) 263d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 264d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned long tmp ; 265d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short result; 266d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 267d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tmp = tmin * (fsclk/1000/1000) / 1000; 268d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang result = (unsigned short)tmp; 269d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if ((tmp*1000*1000) < (tmin*(fsclk/1000))) { 270d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang result++; 271d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 272d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 273d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return result; 274d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 275d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 276d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 277d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_set_piomode - Initialize host controller PATA PIO timings 278d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: Port whose timings we are configuring 279d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @adev: um 280d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 281d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Set PIO mode for device. 282d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 283d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * LOCKING: 284d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * None (inherited from caller). 285d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 286d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 287d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void bfin_set_piomode(struct ata_port *ap, struct ata_device *adev) 288d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 289d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang int mode = adev->pio_mode - XFER_PIO_0; 290d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 291d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned int fsclk = get_sclk(); 292d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short teoc_reg, t2_reg, teoc_pio; 293d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short t4_reg, t2_pio, t1_reg; 294d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short n0, n6, t6min = 5; 295d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 296d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* the most restrictive timing value is t6 and tc, the DIOW - data hold 297d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * If one SCLK pulse is longer than this minimum value then register 298d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * transfers cannot be supported at this frequency. 299d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 300d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang n6 = num_clocks_min(t6min, fsclk); 301d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (mode >= 0 && mode <= 4 && n6 >= 1) { 3029f24e82d07e2c64467d0c0c04a798de56461fd4aBryan Wu dev_dbg(adev->link->ap->dev, "set piomode: mode=%d, fsclk=%ud\n", mode, fsclk); 303d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* calculate the timing values for register transfers. */ 304d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang while (mode > 0 && pio_fsclk[mode] > fsclk) 305d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang mode--; 306d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 307d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* DIOR/DIOW to end cycle time */ 308d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang t2_reg = num_clocks_min(reg_t2min[mode], fsclk); 309d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* DIOR/DIOW asserted pulse width */ 310d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang teoc_reg = num_clocks_min(reg_teocmin[mode], fsclk); 311d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Cycle Time */ 312d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang n0 = num_clocks_min(reg_t0min[mode], fsclk); 313d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 314d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* increase t2 until we meed the minimum cycle length */ 315d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (t2_reg + teoc_reg < n0) 316d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang t2_reg = n0 - teoc_reg; 317d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 318d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* calculate the timing values for pio transfers. */ 319d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 320d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* DIOR/DIOW to end cycle time */ 321d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang t2_pio = num_clocks_min(pio_t2min[mode], fsclk); 322d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* DIOR/DIOW asserted pulse width */ 323d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang teoc_pio = num_clocks_min(pio_teocmin[mode], fsclk); 324d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Cycle Time */ 325d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang n0 = num_clocks_min(pio_t0min[mode], fsclk); 326d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 327d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* increase t2 until we meed the minimum cycle length */ 328d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (t2_pio + teoc_pio < n0) 329d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang t2_pio = n0 - teoc_pio; 330d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 331d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Address valid to DIOR/DIORW */ 332d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang t1_reg = num_clocks_min(pio_t1min[mode], fsclk); 333d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 334d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* DIOW data hold */ 335d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang t4_reg = num_clocks_min(pio_t4min[mode], fsclk); 336d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 337d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_REG_TIM_0(base, (teoc_reg<<8 | t2_reg)); 338d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_PIO_TIM_0(base, (t4_reg<<12 | t2_pio<<4 | t1_reg)); 339d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_PIO_TIM_1(base, teoc_pio); 340d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (mode > 2) { 341d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, 342d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_GET_CONTROL(base) | IORDY_EN); 343d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } else { 344d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, 345d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_GET_CONTROL(base) & ~IORDY_EN); 346d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 347d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 348d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Disable host ATAPI PIO interrupts */ 349d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_INT_MASK(base, ATAPI_GET_INT_MASK(base) 350d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang & ~(PIO_DONE_MASK | HOST_TERM_XFER_MASK)); 351d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang SSYNC(); 352d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 353d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 354d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 355d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 356d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_set_dmamode - Initialize host controller PATA DMA timings 357d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: Port whose timings we are configuring 358d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @adev: um 359d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @udma: udma mode, 0 - 6 360d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 361d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Set UDMA mode for device. 362d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 363d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * LOCKING: 364d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * None (inherited from caller). 365d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 366d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 367d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void bfin_set_dmamode(struct ata_port *ap, struct ata_device *adev) 368d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 369d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang int mode; 370d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 371d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned long fsclk = get_sclk(); 372d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short tenv, tack, tcyc_tdvs, tdvs, tmli, tss, trp, tzah; 373d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short tm, td, tkr, tkw, teoc, th; 374d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short n0, nf, tfmin = 5; 375d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short nmin, tcyc; 376d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 377d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang mode = adev->dma_mode - XFER_UDMA_0; 378d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (mode >= 0 && mode <= 5) { 3799f24e82d07e2c64467d0c0c04a798de56461fd4aBryan Wu dev_dbg(adev->link->ap->dev, "set udmamode: mode=%d\n", mode); 380d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* the most restrictive timing value is t6 and tc, 381d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * the DIOW - data hold. If one SCLK pulse is longer 382d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * than this minimum value then register 383d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * transfers cannot be supported at this frequency. 384d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 385d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang while (mode > 0 && udma_fsclk[mode] > fsclk) 386d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang mode--; 387d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 388d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang nmin = num_clocks_min(udma_tmin[mode], fsclk); 389d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (nmin >= 1) { 390d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* calculate the timing values for Ultra DMA. */ 391d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tdvs = num_clocks_min(udma_tdvsmin[mode], fsclk); 392d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tcyc = num_clocks_min(udma_tcycmin[mode], fsclk); 393d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tcyc_tdvs = 2; 394d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 395d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* increase tcyc - tdvs (tcyc_tdvs) until we meed 396d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * the minimum cycle length 397d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 398d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (tdvs + tcyc_tdvs < tcyc) 399d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tcyc_tdvs = tcyc - tdvs; 400d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 401d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Mow assign the values required for the timing 402d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * registers 403d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 404d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (tcyc_tdvs < 2) 405d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tcyc_tdvs = 2; 406d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 407d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (tdvs < 2) 408d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tdvs = 2; 409d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 410d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tack = num_clocks_min(udma_tackmin, fsclk); 411d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tss = num_clocks_min(udma_tssmin, fsclk); 412d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tmli = num_clocks_min(udma_tmlimin, fsclk); 413d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tzah = num_clocks_min(udma_tzahmin, fsclk); 414d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang trp = num_clocks_min(udma_trpmin[mode], fsclk); 415d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tenv = num_clocks_min(udma_tenvmin, fsclk); 416d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (tenv <= udma_tenvmax[mode]) { 417d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_ULTRA_TIM_0(base, (tenv<<8 | tack)); 418d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_ULTRA_TIM_1(base, 419d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang (tcyc_tdvs<<8 | tdvs)); 420d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_ULTRA_TIM_2(base, (tmli<<8 | tss)); 421d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_ULTRA_TIM_3(base, (trp<<8 | tzah)); 422d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 423d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Enable host ATAPI Untra DMA interrupts */ 424d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_INT_MASK(base, 425d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_GET_INT_MASK(base) 426d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang | UDMAIN_DONE_MASK 427d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang | UDMAOUT_DONE_MASK 428d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang | UDMAIN_TERM_MASK 429d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang | UDMAOUT_TERM_MASK); 430d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 431d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 432d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 433d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 434d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang mode = adev->dma_mode - XFER_MW_DMA_0; 435d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (mode >= 0 && mode <= 2) { 4369f24e82d07e2c64467d0c0c04a798de56461fd4aBryan Wu dev_dbg(adev->link->ap->dev, "set mdmamode: mode=%d\n", mode); 437d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* the most restrictive timing value is tf, the DMACK to 438d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * read data released. If one SCLK pulse is longer than 439d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * this maximum value then the MDMA mode 440d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * cannot be supported at this frequency. 441d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 442d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang while (mode > 0 && mdma_fsclk[mode] > fsclk) 443d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang mode--; 444d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 445d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang nf = num_clocks_min(tfmin, fsclk); 446d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (nf >= 1) { 447d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* calculate the timing values for Multi-word DMA. */ 448d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 449d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* DIOR/DIOW asserted pulse width */ 450d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang td = num_clocks_min(mdma_tdmin[mode], fsclk); 451d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 452d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* DIOR negated pulse width */ 453d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tkw = num_clocks_min(mdma_tkwmin[mode], fsclk); 454d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 455d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Cycle Time */ 456d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang n0 = num_clocks_min(mdma_t0min[mode], fsclk); 457d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 458d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* increase tk until we meed the minimum cycle length */ 459d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (tkw + td < n0) 460d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tkw = n0 - td; 461d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 462d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* DIOR negated pulse width - read */ 463d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tkr = num_clocks_min(mdma_tkrmin[mode], fsclk); 464d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* CS{1:0] valid to DIOR/DIOW */ 465d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tm = num_clocks_min(mdma_tmmin[mode], fsclk); 466d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* DIOR/DIOW to DMACK hold */ 467d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang teoc = num_clocks_min(mdma_tjmin[mode], fsclk); 468d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* DIOW Data hold */ 469d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang th = num_clocks_min(mdma_thmin[mode], fsclk); 470d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 471d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_MULTI_TIM_0(base, (tm<<8 | td)); 472d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_MULTI_TIM_1(base, (tkr<<8 | tkw)); 473d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_MULTI_TIM_2(base, (teoc<<8 | th)); 474d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 475d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Enable host ATAPI Multi DMA interrupts */ 476d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_INT_MASK(base, ATAPI_GET_INT_MASK(base) 477d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang | MULTI_DONE_MASK | MULTI_TERM_MASK); 478d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang SSYNC(); 479d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 480d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 481d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return; 482d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 483d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 484d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 485d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 486d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Function: wait_complete 487d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 488d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Description: Waits the interrupt from device 489d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 490d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 491d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic inline void wait_complete(void __iomem *base, unsigned short mask) 492d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 493d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short status; 494d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned int i = 0; 495d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 496d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#define PATA_BF54X_WAIT_TIMEOUT 10000 497d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 498d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang for (i = 0; i < PATA_BF54X_WAIT_TIMEOUT; i++) { 499d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang status = ATAPI_GET_INT_STATUS(base) & mask; 500d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (status) 501d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang break; 502d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 503d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 504d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_INT_STATUS(base, mask); 505d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 506d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 507d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 508d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 509d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Function: write_atapi_register 510d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 511d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Description: Writes to ATA Device Resgister 512d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 513d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 514d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 515d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void write_atapi_register(void __iomem *base, 516d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned long ata_reg, unsigned short value) 517d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 518d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_DEV_TXBUF register with write data (to be 519d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * written into the device). 520d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 521d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_DEV_TXBUF(base, value); 522d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 523d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_DEV_ADDR register with address of the 524d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * device register (0x01 to 0x0F). 525d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 526d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_DEV_ADDR(base, ata_reg); 527d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 528d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_CTRL register with dir set to write (1) 529d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 530d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR)); 531d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 532d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* ensure PIO DMA is not set */ 533d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA)); 534d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 535d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* and start the transfer */ 536d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START)); 537d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 538d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Wait for the interrupt to indicate the end of the transfer. 539d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * (We need to wait on and clear rhe ATA_DEV_INT interrupt status) 540d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 541d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang wait_complete(base, PIO_DONE_INT); 542d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 543d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 544d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 545d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 546d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Function: read_atapi_register 547d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 548d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang *Description: Reads from ATA Device Resgister 549d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 550d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 551d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 552d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic unsigned short read_atapi_register(void __iomem *base, 553d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned long ata_reg) 554d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 555d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_DEV_ADDR register with address of the 556d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * device register (0x01 to 0x0F). 557d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 558d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_DEV_ADDR(base, ata_reg); 559d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 560d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_CTRL register with dir set to read (0) and 561d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 562d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR)); 563d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 564d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* ensure PIO DMA is not set */ 565d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA)); 566d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 567d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* and start the transfer */ 568d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START)); 569d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 570d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Wait for the interrupt to indicate the end of the transfer. 571d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * (PIO_DONE interrupt is set and it doesn't seem to matter 572d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * that we don't clear it) 573d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 574d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang wait_complete(base, PIO_DONE_INT); 575d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 576d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Read the ATA_DEV_RXBUF register with write data (to be 577d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * written into the device). 578d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 579d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return ATAPI_GET_DEV_RXBUF(base); 580d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 581d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 582d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 583d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 584d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Function: write_atapi_register_data 585d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 586d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Description: Writes to ATA Device Resgister 587d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 588d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 589d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 590d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void write_atapi_data(void __iomem *base, 591d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang int len, unsigned short *buf) 592d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 593d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang int i; 594d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 595d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Set transfer length to 1 */ 596d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_XFER_LEN(base, 1); 597d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 598d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_DEV_ADDR register with address of the 599d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * ATA_REG_DATA 600d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 601d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA); 602d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 603d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_CTRL register with dir set to write (1) 604d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 605d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR)); 606d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 607d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* ensure PIO DMA is not set */ 608d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA)); 609d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 610d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang for (i = 0; i < len; i++) { 611d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_DEV_TXBUF register with write data (to be 612d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * written into the device). 613d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 614d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_DEV_TXBUF(base, buf[i]); 615d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 616d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* and start the transfer */ 617d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START)); 618d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 619d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Wait for the interrupt to indicate the end of the transfer. 620d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * (We need to wait on and clear rhe ATA_DEV_INT 621d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * interrupt status) 622d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 623d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang wait_complete(base, PIO_DONE_INT); 624d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 625d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 626d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 627d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 628d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 629d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Function: read_atapi_register_data 630d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 631d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Description: Reads from ATA Device Resgister 632d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 633d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 634d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 635d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void read_atapi_data(void __iomem *base, 636d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang int len, unsigned short *buf) 637d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 638d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang int i; 639d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 640d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Set transfer length to 1 */ 641d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_XFER_LEN(base, 1); 642d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 643d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_DEV_ADDR register with address of the 644d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * ATA_REG_DATA 645d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 646d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA); 647d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 648d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_CTRL register with dir set to read (0) and 649d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 650d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR)); 651d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 652d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* ensure PIO DMA is not set */ 653d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA)); 654d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 655d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang for (i = 0; i < len; i++) { 656d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* and start the transfer */ 657d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START)); 658d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 659d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Wait for the interrupt to indicate the end of the transfer. 660d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * (PIO_DONE interrupt is set and it doesn't seem to matter 661d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * that we don't clear it) 662d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 663d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang wait_complete(base, PIO_DONE_INT); 664d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 665d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Read the ATA_DEV_RXBUF register with write data (to be 666d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * written into the device). 667d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 668d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang buf[i] = ATAPI_GET_DEV_RXBUF(base); 669d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 670d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 671d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 672d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 673d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_tf_load - send taskfile registers to host controller 674d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: Port to which output is sent 675d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @tf: ATA taskfile register set 676d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 6779363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_tf_load(). 678d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 679d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 680d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void bfin_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) 681d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 682d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 683d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; 684d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 685d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (tf->ctl != ap->last_ctl) { 686d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_CTRL, tf->ctl); 687d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ap->last_ctl = tf->ctl; 688d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ata_wait_idle(ap); 689d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 690d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 691d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (is_addr) { 692d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (tf->flags & ATA_TFLAG_LBA48) { 693d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_FEATURE, 694d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_feature); 695d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_NSECT, 696d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_nsect); 697d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_LBAL, tf->hob_lbal); 698d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_LBAM, tf->hob_lbam); 699d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_LBAH, tf->hob_lbah); 700f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(ap->dev, "hob: feat 0x%X nsect 0x%X, lba 0x%X " 701d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang "0x%X 0x%X\n", 702d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_feature, 703d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_nsect, 704d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_lbal, 705d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_lbam, 706d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_lbah); 707d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 708d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 709d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_FEATURE, tf->feature); 710d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_NSECT, tf->nsect); 711d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_LBAL, tf->lbal); 712d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_LBAM, tf->lbam); 713d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_LBAH, tf->lbah); 714f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(ap->dev, "feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", 715d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->feature, 716d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->nsect, 717d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->lbal, 718d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->lbam, 719d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->lbah); 720d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 721d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 722d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (tf->flags & ATA_TFLAG_DEVICE) { 723d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_DEVICE, tf->device); 724f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(ap->dev, "device 0x%X\n", tf->device); 725d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 726d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 727d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ata_wait_idle(ap); 728d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 729d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 730d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 731d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_check_status - Read device status reg & clear interrupt 732d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: port where the device is 733d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 734d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Note: Original code is ata_check_status(). 735d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 736d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 737d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic u8 bfin_check_status(struct ata_port *ap) 738d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 739d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 740d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return read_atapi_register(base, ATA_REG_STATUS); 741d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 742d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 743d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 744d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_tf_read - input device's ATA taskfile shadow registers 745d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: Port from which input is read 746d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @tf: ATA taskfile register set for storing input 747d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 7489363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_tf_read(). 749d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 750d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 751d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void bfin_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 752d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 753d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 754d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 755d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->command = bfin_check_status(ap); 756d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->feature = read_atapi_register(base, ATA_REG_ERR); 757d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->nsect = read_atapi_register(base, ATA_REG_NSECT); 758d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->lbal = read_atapi_register(base, ATA_REG_LBAL); 759d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->lbam = read_atapi_register(base, ATA_REG_LBAM); 760d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->lbah = read_atapi_register(base, ATA_REG_LBAH); 761d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->device = read_atapi_register(base, ATA_REG_DEVICE); 762d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 763d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (tf->flags & ATA_TFLAG_LBA48) { 764d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_CTRL, tf->ctl | ATA_HOB); 765d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_feature = read_atapi_register(base, ATA_REG_ERR); 766d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_nsect = read_atapi_register(base, ATA_REG_NSECT); 767d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_lbal = read_atapi_register(base, ATA_REG_LBAL); 768d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_lbam = read_atapi_register(base, ATA_REG_LBAM); 769d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tf->hob_lbah = read_atapi_register(base, ATA_REG_LBAH); 770d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 771d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 772d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 773d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 774d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_exec_command - issue ATA command to host controller 775d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: port to which command is being issued 776d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @tf: ATA taskfile register set 777d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 7789363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_exec_command(). 779d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 780d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 781d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void bfin_exec_command(struct ata_port *ap, 782d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang const struct ata_taskfile *tf) 783d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 784d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 785f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(ap->dev, "ata%u: cmd 0x%X\n", ap->print_id, tf->command); 786d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 787d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_CMD, tf->command); 7889363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo ata_sff_pause(ap); 789d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 790d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 791d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 792d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_check_altstatus - Read device alternate status reg 793d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: port where the device is 794d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 795d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 796d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic u8 bfin_check_altstatus(struct ata_port *ap) 797d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 798d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 799d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return read_atapi_register(base, ATA_REG_ALTSTATUS); 800d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 801d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 802d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 8039363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * bfin_dev_select - Select device 0/1 on ATA bus 804d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: ATA channel to manipulate 805d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @device: ATA device (numbered from zero) to select 806d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 8079363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_dev_select(). 808d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 809d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 8109363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heostatic void bfin_dev_select(struct ata_port *ap, unsigned int device) 811d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 812d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 813d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang u8 tmp; 814d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 815d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (device == 0) 816d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tmp = ATA_DEVICE_OBS; 817d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang else 818d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tmp = ATA_DEVICE_OBS | ATA_DEV1; 819d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 820d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_DEVICE, tmp); 8219363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo ata_sff_pause(ap); 822d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 823d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 824d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 825d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_bmdma_setup - Set up IDE DMA transaction 826d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @qc: Info associated with this ATA transaction. 827d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 828d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Note: Original code is ata_bmdma_setup(). 829d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 830d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 831d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void bfin_bmdma_setup(struct ata_queued_cmd *qc) 832d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 833d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short config = WDSIZE_16; 834d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang struct scatterlist *sg; 835ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo unsigned int si; 836d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 837f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(qc->ap->dev, "in atapi dma setup\n"); 838d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Program the ATA_CTRL register with dir */ 839d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (qc->tf.flags & ATA_TFLAG_WRITE) { 840d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* fill the ATAPI DMA controller */ 841d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang set_dma_config(CH_ATAPI_TX, config); 842d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang set_dma_x_modify(CH_ATAPI_TX, 2); 843ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 844d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang set_dma_start_addr(CH_ATAPI_TX, sg_dma_address(sg)); 845d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang set_dma_x_count(CH_ATAPI_TX, sg_dma_len(sg) >> 1); 846d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 847d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } else { 848d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang config |= WNR; 849d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* fill the ATAPI DMA controller */ 850d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang set_dma_config(CH_ATAPI_RX, config); 851d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang set_dma_x_modify(CH_ATAPI_RX, 2); 852ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 853d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang set_dma_start_addr(CH_ATAPI_RX, sg_dma_address(sg)); 854d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang set_dma_x_count(CH_ATAPI_RX, sg_dma_len(sg) >> 1); 855d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 856d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 857d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 858d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 859d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 860d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_bmdma_start - Start an IDE DMA transaction 861d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @qc: Info associated with this ATA transaction. 862d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 863d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Note: Original code is ata_bmdma_start(). 864d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 865d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 866d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void bfin_bmdma_start(struct ata_queued_cmd *qc) 867d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 868d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang struct ata_port *ap = qc->ap; 869d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 870d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang struct scatterlist *sg; 871ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo unsigned int si; 872d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 873f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(qc->ap->dev, "in atapi dma start\n"); 874d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (!(ap->udma_mask || ap->mwdma_mask)) 875d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return; 876d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 877d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* start ATAPI DMA controller*/ 878d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (qc->tf.flags & ATA_TFLAG_WRITE) { 879d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* 880d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * On blackfin arch, uncacheable memory is not 881d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * allocated with flag GFP_DMA. DMA buffer from 882d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * common kenel code should be flushed if WB 883d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * data cache is enabled. Otherwise, this loop 884d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * is an empty loop and optimized out. 885d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 886ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 887d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang flush_dcache_range(sg_dma_address(sg), 888d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang sg_dma_address(sg) + sg_dma_len(sg)); 889d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 890d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang enable_dma(CH_ATAPI_TX); 891f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(qc->ap->dev, "enable udma write\n"); 892d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 893d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Send ATA DMA write command */ 894d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_exec_command(ap, &qc->tf); 895d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 896d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* set ATA DMA write direction */ 897d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) 898d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang | XFER_DIR)); 899d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } else { 900d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang enable_dma(CH_ATAPI_RX); 901f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(qc->ap->dev, "enable udma read\n"); 902d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 903d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Send ATA DMA read command */ 904d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_exec_command(ap, &qc->tf); 905d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 906d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* set ATA DMA read direction */ 907d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) 908d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang & ~XFER_DIR)); 909d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 910d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 911d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Reset all transfer count */ 912d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | TFRCNT_RST); 913d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 914b6e7b447975b0364c3430284c7b16e2e89ccf9e9Sonic Zhang /* Set ATAPI state machine contorl in terminate sequence */ 915b6e7b447975b0364c3430284c7b16e2e89ccf9e9Sonic Zhang ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | END_ON_TERM); 916b6e7b447975b0364c3430284c7b16e2e89ccf9e9Sonic Zhang 917b6e7b447975b0364c3430284c7b16e2e89ccf9e9Sonic Zhang /* Set transfer length to buffer len */ 918ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 919d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_XFER_LEN(base, (sg_dma_len(sg) >> 1)); 920d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 921d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 922d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Enable ATA DMA operation*/ 923d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (ap->udma_mask) 924d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) 925d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang | ULTRA_START); 926d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang else 927d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) 928d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang | MULTI_START); 929d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 930d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 931d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 932d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_bmdma_stop - Stop IDE DMA transfer 933d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @qc: Command we are ending DMA for 934d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 935d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 936d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void bfin_bmdma_stop(struct ata_queued_cmd *qc) 937d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 938d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang struct ata_port *ap = qc->ap; 939d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang struct scatterlist *sg; 940ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo unsigned int si; 941d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 942f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(qc->ap->dev, "in atapi dma stop\n"); 943d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (!(ap->udma_mask || ap->mwdma_mask)) 944d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return; 945d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 946d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* stop ATAPI DMA controller*/ 947d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (qc->tf.flags & ATA_TFLAG_WRITE) 948d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang disable_dma(CH_ATAPI_TX); 949d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang else { 950d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang disable_dma(CH_ATAPI_RX); 951d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (ap->hsm_task_state & HSM_ST_LAST) { 952d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* 953d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * On blackfin arch, uncacheable memory is not 954d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * allocated with flag GFP_DMA. DMA buffer from 955d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * common kenel code should be invalidated if 956d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * data cache is enabled. Otherwise, this loop 957d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * is an empty loop and optimized out. 958d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 959ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 960d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang invalidate_dcache_range( 961d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang sg_dma_address(sg), 962d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang sg_dma_address(sg) 963d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang + sg_dma_len(sg)); 964d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 965d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 966d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 967d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 968d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 969d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 970d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_devchk - PATA device presence detection 971d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: ATA channel to examine 972d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @device: Device to examine (starting at zero) 973d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 974d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Note: Original code is ata_devchk(). 975d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 976d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 977d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic unsigned int bfin_devchk(struct ata_port *ap, 978d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned int device) 979d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 980d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 981d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang u8 nsect, lbal; 982d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 9839363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo bfin_dev_select(ap, device); 984d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 985d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_NSECT, 0x55); 986d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_LBAL, 0xaa); 987d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 988d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_NSECT, 0xaa); 989d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_LBAL, 0x55); 990d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 991d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_NSECT, 0x55); 992d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_LBAL, 0xaa); 993d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 994d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang nsect = read_atapi_register(base, ATA_REG_NSECT); 995d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang lbal = read_atapi_register(base, ATA_REG_LBAL); 996d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 997d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if ((nsect == 0x55) && (lbal == 0xaa)) 998d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 1; /* we found a device */ 999d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1000d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 0; /* nothing found */ 1001d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1002d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1003d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 1004d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_bus_post_reset - PATA device post reset 1005d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 1006d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Note: Original code is ata_bus_post_reset(). 1007d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1008d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1009d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void bfin_bus_post_reset(struct ata_port *ap, unsigned int devmask) 1010d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1011d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 1012d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned int dev0 = devmask & (1 << 0); 1013d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned int dev1 = devmask & (1 << 1); 1014341c2c958ec7bdd9f54733a8b0b432fe76842a82Tejun Heo unsigned long deadline; 1015d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1016d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* if device 0 was found in ata_devchk, wait for its 1017d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * BSY bit to clear 1018d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1019d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (dev0) 10209363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo ata_sff_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT); 1021d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1022d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* if device 1 was found in ata_devchk, wait for 1023d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * register access, then wait for BSY to clear 1024d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1025341c2c958ec7bdd9f54733a8b0b432fe76842a82Tejun Heo deadline = ata_deadline(jiffies, ATA_TMOUT_BOOT); 1026d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang while (dev1) { 1027d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang u8 nsect, lbal; 1028d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 10299363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo bfin_dev_select(ap, 1); 1030d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang nsect = read_atapi_register(base, ATA_REG_NSECT); 1031d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang lbal = read_atapi_register(base, ATA_REG_LBAL); 1032d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if ((nsect == 1) && (lbal == 1)) 1033d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang break; 1034341c2c958ec7bdd9f54733a8b0b432fe76842a82Tejun Heo if (time_after(jiffies, deadline)) { 1035d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang dev1 = 0; 1036d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang break; 1037d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 1038d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang msleep(50); /* give drive a breather */ 1039d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 1040d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (dev1) 10419363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo ata_sff_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT); 1042d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1043d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* is all this really necessary? */ 10449363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo bfin_dev_select(ap, 0); 1045d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (dev1) 10469363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo bfin_dev_select(ap, 1); 1047d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (dev0) 10489363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo bfin_dev_select(ap, 0); 1049d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1050d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1051d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 1052d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_bus_softreset - PATA device software reset 1053d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 1054d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Note: Original code is ata_bus_softreset(). 1055d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1056d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1057d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic unsigned int bfin_bus_softreset(struct ata_port *ap, 1058d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned int devmask) 1059d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1060d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 1061d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1062d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* software reset. causes dev0 to be selected */ 1063d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_CTRL, ap->ctl); 1064d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang udelay(20); 1065d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_CTRL, ap->ctl | ATA_SRST); 1066d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang udelay(20); 1067d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_CTRL, ap->ctl); 1068d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1069d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* spec mandates ">= 2ms" before checking status. 1070d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * We wait 150ms, because that was the magic delay used for 1071d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * ATAPI devices in Hale Landis's ATADRVR, for the period of time 1072d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * between when the ATA command register is written, and then 1073d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * status is checked. Because waiting for "a while" before 1074d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * checking status is fine, post SRST, we perform this magic 1075d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * delay here as well. 1076d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 1077d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Old drivers/ide uses the 2mS rule and then waits for ready 1078d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1079d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang msleep(150); 1080d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1081d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Before we perform post reset processing we want to see if 1082d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * the bus shows 0xFF because the odd clown forgets the D7 1083d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * pulldown resistor. 1084d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1085d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (bfin_check_status(ap) == 0xFF) 1086d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 0; 1087d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1088d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_bus_post_reset(ap, devmask); 1089d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1090d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 0; 1091d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1092d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1093d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 10949363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * bfin_softreset - reset host port via ATA SRST 1095d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: port to reset 1096d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @classes: resulting classes of attached devices 1097d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 10989363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_softreset(). 1099d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1100d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 11019363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heostatic int bfin_softreset(struct ata_link *link, unsigned int *classes, 11029363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo unsigned long deadline) 1103d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1104858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang struct ata_port *ap = link->ap; 1105d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; 1106d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned int devmask = 0, err_mask; 1107d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang u8 err; 1108d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1109d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* determine if device 0/1 are present */ 1110d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (bfin_devchk(ap, 0)) 1111d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang devmask |= (1 << 0); 1112d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (slave_possible && bfin_devchk(ap, 1)) 1113d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang devmask |= (1 << 1); 1114d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1115d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* select device 0 again */ 11169363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo bfin_dev_select(ap, 0); 1117d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1118d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* issue bus reset */ 1119d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang err_mask = bfin_bus_softreset(ap, devmask); 1120d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (err_mask) { 1121d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ata_port_printk(ap, KERN_ERR, "SRST failed (err_mask=0x%x)\n", 1122d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang err_mask); 1123d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return -EIO; 1124d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 1125d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1126d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* determine by signature whether we have ATA or ATAPI devices */ 11279363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo classes[0] = ata_sff_dev_classify(&ap->link.device[0], 1128858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang devmask & (1 << 0), &err); 1129d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (slave_possible && err != 0x81) 11309363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo classes[1] = ata_sff_dev_classify(&ap->link.device[1], 1131858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang devmask & (1 << 1), &err); 1132d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1133d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 0; 1134d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1135d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1136d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 1137d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_bmdma_status - Read IDE DMA status 1138d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: Port associated with this ATA transaction. 1139d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1140d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1141d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic unsigned char bfin_bmdma_status(struct ata_port *ap) 1142d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1143d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned char host_stat = 0; 1144d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 1145d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short int_status = ATAPI_GET_INT_STATUS(base); 1146d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 114730d849c95f0598309ca6451900b1fd0d2c0384e6Sonic Zhang if (ATAPI_GET_STATUS(base) & (MULTI_XFER_ON|ULTRA_XFER_ON)) 1148dc86f6d4183c79a08fa01c08dd2191895c0c7eb0sonic zhang host_stat |= ATA_DMA_ACTIVE; 114930d849c95f0598309ca6451900b1fd0d2c0384e6Sonic Zhang if (int_status & (MULTI_DONE_INT|UDMAIN_DONE_INT|UDMAOUT_DONE_INT| 115030d849c95f0598309ca6451900b1fd0d2c0384e6Sonic Zhang ATAPI_DEV_INT)) 1151dc86f6d4183c79a08fa01c08dd2191895c0c7eb0sonic zhang host_stat |= ATA_DMA_INTR; 115230d849c95f0598309ca6451900b1fd0d2c0384e6Sonic Zhang if (int_status & (MULTI_TERM_INT|UDMAIN_TERM_INT|UDMAOUT_TERM_INT)) 115330d849c95f0598309ca6451900b1fd0d2c0384e6Sonic Zhang host_stat |= ATA_DMA_ERR|ATA_DMA_INTR; 1154d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1155f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(ap->dev, "ATAPI: host_stat=0x%x\n", host_stat); 1156f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang 1157d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return host_stat; 1158d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1159d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1160d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 1161d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_data_xfer - Transfer data by PIO 1162d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @adev: device for this I/O 1163d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @buf: data buffer 1164d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @buflen: buffer length 1165d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @write_data: read/write 1166d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 11679363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_data_xfer(). 1168d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1169d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 117055dba3120fbcbea6800f9a18503d25f73212a347Tejun Heostatic unsigned int bfin_data_xfer(struct ata_device *dev, unsigned char *buf, 117155dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo unsigned int buflen, int rw) 1172d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 117355dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo struct ata_port *ap = dev->link->ap; 1174d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 117555dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo unsigned int words = buflen >> 1; 117655dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo unsigned short *buf16 = (u16 *)buf; 1177d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1178d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Transfer multiple of 2 bytes */ 117955dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo if (rw == READ) 1180d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang read_atapi_data(base, words, buf16); 118155dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo else 118255dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo write_atapi_data(base, words, buf16); 1183d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1184d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Transfer trailing 1 byte, if any. */ 1185d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (unlikely(buflen & 0x01)) { 1186d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short align_buf[1] = { 0 }; 1187d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned char *trailing_buf = buf + buflen - 1; 1188d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 118955dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo if (rw == READ) { 1190d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang read_atapi_data(base, 1, align_buf); 1191d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang memcpy(trailing_buf, align_buf, 1); 119255dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo } else { 119355dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo memcpy(align_buf, trailing_buf, 1); 119455dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo write_atapi_data(base, 1, align_buf); 1195d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 119655dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo words++; 1197d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 119855dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo 119955dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo return words << 1; 1200d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1201d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1202d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 1203d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_irq_clear - Clear ATAPI interrupt. 1204d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: Port associated with this ATA transaction. 1205d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 12069363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_irq_clear(). 1207d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1208d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1209d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void bfin_irq_clear(struct ata_port *ap) 1210d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1211d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 1212d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1213f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(ap->dev, "in atapi irq clear\n"); 1214858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT 1215858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT 1216858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT); 1217d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1218d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1219d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 1220d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_irq_on - Enable interrupts on a port. 1221d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: Port on which interrupts are enabled. 1222d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 12239363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_irq_on(). 1224d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1225d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1226d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic unsigned char bfin_irq_on(struct ata_port *ap) 1227d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1228d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 1229d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang u8 tmp; 1230d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1231f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(ap->dev, "in atapi irq on\n"); 1232d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ap->ctl &= ~ATA_NIEN; 1233d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ap->last_ctl = ap->ctl; 1234d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1235d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_CTRL, ap->ctl); 1236d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang tmp = ata_wait_idle(ap); 1237d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1238d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_irq_clear(ap); 1239d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1240d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return tmp; 1241d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1242d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1243d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 12449363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * bfin_freeze - Freeze DMA controller port 1245d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: port to freeze 1246d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 12479363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_freeze(). 1248d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1249d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 12509363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heostatic void bfin_freeze(struct ata_port *ap) 1251d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1252d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 1253d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1254f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(ap->dev, "in atapi dma freeze\n"); 1255d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ap->ctl |= ATA_NIEN; 1256d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ap->last_ctl = ap->ctl; 1257d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1258d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_CTRL, ap->ctl); 1259d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1260d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Under certain circumstances, some controllers raise IRQ on 1261d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * ATA_NIEN manipulation. Also, many controllers fail to mask 1262d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * previously pending IRQ on ATA_NIEN assertion. Clear it. 1263d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 12645682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo ap->ops->sff_check_status(ap); 1265d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1266d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_irq_clear(ap); 1267d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1268d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1269d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 12709363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * bfin_thaw - Thaw DMA controller port 1271d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: port to thaw 1272d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 12739363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_thaw(). 1274d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1275d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 12769363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heovoid bfin_thaw(struct ata_port *ap) 1277d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 127865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang dev_dbg(ap->dev, "in atapi dma thaw\n"); 1279d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_check_status(ap); 1280d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_irq_on(ap); 1281d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1282d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1283d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 12849363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * bfin_postreset - standard postreset callback 1285d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @ap: the target ata_port 1286d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @classes: classes of attached devices 1287d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 12889363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_postreset(). 1289d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1290d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 12919363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heostatic void bfin_postreset(struct ata_link *link, unsigned int *classes) 1292d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1293858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang struct ata_port *ap = link->ap; 1294d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; 1295d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1296d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* re-enable interrupts */ 1297d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang bfin_irq_on(ap); 1298d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1299d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* is double-select really necessary? */ 1300d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (classes[0] != ATA_DEV_NONE) 13019363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo bfin_dev_select(ap, 1); 1302d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (classes[1] != ATA_DEV_NONE) 13039363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo bfin_dev_select(ap, 0); 1304d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1305d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* bail out if no device is present */ 1306d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) { 1307d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return; 1308d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 1309d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1310d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* set up device control */ 1311d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang write_atapi_register(base, ATA_REG_CTRL, ap->ctl); 1312d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1313d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1314d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void bfin_port_stop(struct ata_port *ap) 1315d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1316f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(ap->dev, "in atapi port stop\n"); 1317d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (ap->udma_mask != 0 || ap->mwdma_mask != 0) { 1318d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang free_dma(CH_ATAPI_RX); 1319d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang free_dma(CH_ATAPI_TX); 1320d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 1321d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1322d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1323d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic int bfin_port_start(struct ata_port *ap) 1324d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1325f9204112586c1b9b5a5e5979d285e58a349774e0Sonic Zhang dev_dbg(ap->dev, "in atapi port start\n"); 1326d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (!(ap->udma_mask || ap->mwdma_mask)) 1327d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 0; 1328d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1329d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (request_dma(CH_ATAPI_RX, "BFIN ATAPI RX DMA") >= 0) { 1330d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (request_dma(CH_ATAPI_TX, 1331d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang "BFIN ATAPI TX DMA") >= 0) 1332d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 0; 1333d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1334d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang free_dma(CH_ATAPI_RX); 1335d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 1336d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1337d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ap->udma_mask = 0; 1338d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ap->mwdma_mask = 0; 1339d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang dev_err(ap->dev, "Unable to request ATAPI DMA!" 1340d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang " Continue in PIO mode.\n"); 1341d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1342d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 0; 1343d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1344d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 134565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhangstatic unsigned int bfin_ata_host_intr(struct ata_port *ap, 134665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang struct ata_queued_cmd *qc) 134765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang{ 134865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang struct ata_eh_info *ehi = &ap->link.eh_info; 134965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang u8 status, host_stat = 0; 135065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 135165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang VPRINTK("ata%u: protocol %d task_state %d\n", 135265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang ap->print_id, qc->tf.protocol, ap->hsm_task_state); 135365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 135465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang /* Check whether we are expecting interrupt in this state */ 135565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang switch (ap->hsm_task_state) { 135665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang case HSM_ST_FIRST: 135765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang /* Some pre-ATAPI-4 devices assert INTRQ 135865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang * at this state when ready to receive CDB. 135965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang */ 136065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 136165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang /* Check the ATA_DFLAG_CDB_INTR flag is enough here. 136265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang * The flag was turned on only for atapi devices. 136365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang * No need to check is_atapi_taskfile(&qc->tf) again. 136465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang */ 136565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) 136665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang goto idle_irq; 136765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang break; 136865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang case HSM_ST_LAST: 136965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang if (qc->tf.protocol == ATA_PROT_DMA || 137065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang qc->tf.protocol == ATAPI_PROT_DMA) { 137165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang /* check status of DMA engine */ 137265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang host_stat = ap->ops->bmdma_status(ap); 137365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang VPRINTK("ata%u: host_stat 0x%X\n", 137465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang ap->print_id, host_stat); 137565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 137665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang /* if it's not our irq... */ 137765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang if (!(host_stat & ATA_DMA_INTR)) 137865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang goto idle_irq; 137965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 138065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang /* before we do anything else, clear DMA-Start bit */ 138165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang ap->ops->bmdma_stop(qc); 138265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 138365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang if (unlikely(host_stat & ATA_DMA_ERR)) { 138465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang /* error when transfering data to/from memory */ 138565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang qc->err_mask |= AC_ERR_HOST_BUS; 138665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang ap->hsm_task_state = HSM_ST_ERR; 138765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang } 138865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang } 138965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang break; 139065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang case HSM_ST: 139165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang break; 139265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang default: 139365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang goto idle_irq; 139465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang } 139565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 139665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang /* check altstatus */ 139765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang status = ap->ops->sff_check_altstatus(ap); 139865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang if (status & ATA_BUSY) 139965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang goto busy_ata; 140065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 140165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang /* check main status, clearing INTRQ */ 140265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang status = ap->ops->sff_check_status(ap); 140365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang if (unlikely(status & ATA_BUSY)) 140465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang goto busy_ata; 140565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 140665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang /* ack bmdma irq events */ 140765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang ap->ops->sff_irq_clear(ap); 140865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 140965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang ata_sff_hsm_move(ap, qc, status, 0); 141065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 141165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA || 141265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang qc->tf.protocol == ATAPI_PROT_DMA)) 141365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat); 141465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 141565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhangbusy_ata: 141665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang return 1; /* irq handled */ 141765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 141865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhangidle_irq: 141965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang ap->stats.idle_irq++; 142065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 142165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang#ifdef ATA_IRQ_TRAP 142265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang if ((ap->stats.idle_irq % 1000) == 0) { 142365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang ap->ops->irq_ack(ap, 0); /* debug trap */ 142465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang ata_port_printk(ap, KERN_WARNING, "irq trap\n"); 142565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang return 1; 142665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang } 142765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang#endif 142865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang return 0; /* irq not handled */ 142965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang} 143065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 143165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhangstatic irqreturn_t bfin_ata_interrupt(int irq, void *dev_instance) 143265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang{ 143365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang struct ata_host *host = dev_instance; 143465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang unsigned int i; 143565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang unsigned int handled = 0; 143665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang unsigned long flags; 143765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 143865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */ 143965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang spin_lock_irqsave(&host->lock, flags); 144065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 144165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang for (i = 0; i < host->n_ports; i++) { 144265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang struct ata_port *ap; 144365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 144465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang ap = host->ports[i]; 144565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang if (ap && 144665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang !(ap->flags & ATA_FLAG_DISABLED)) { 144765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang struct ata_queued_cmd *qc; 144865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 144965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang qc = ata_qc_from_tag(ap, ap->link.active_tag); 145065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) && 145165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang (qc->flags & ATA_QCFLAG_ACTIVE)) 145265c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang handled |= bfin_ata_host_intr(ap, qc); 145365c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang } 145465c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang } 145565c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 145665c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang spin_unlock_irqrestore(&host->lock, flags); 145765c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 145865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang return IRQ_RETVAL(handled); 145965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang} 146065c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 146165c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang 1462d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic struct scsi_host_template bfin_sht = { 146368d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BASE_SHT(DRV_NAME), 1464d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .sg_tablesize = SG_NONE, 1465d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .dma_boundary = ATA_DMA_BOUNDARY, 1466d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang}; 1467d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 146865c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhangstatic struct ata_port_operations bfin_pata_ops = { 1469029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &ata_sff_port_ops, 1470029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo 1471d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .set_piomode = bfin_set_piomode, 1472d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .set_dmamode = bfin_set_dmamode, 1473d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 14745682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_tf_load = bfin_tf_load, 14755682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_tf_read = bfin_tf_read, 14765682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_exec_command = bfin_exec_command, 14775682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_check_status = bfin_check_status, 14785682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_check_altstatus = bfin_check_altstatus, 14795682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_dev_select = bfin_dev_select, 1480d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1481d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .bmdma_setup = bfin_bmdma_setup, 1482d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .bmdma_start = bfin_bmdma_start, 1483d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .bmdma_stop = bfin_bmdma_stop, 1484d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .bmdma_status = bfin_bmdma_status, 14855682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_data_xfer = bfin_data_xfer, 1486d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1487d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .qc_prep = ata_noop_qc_prep, 1488d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 14899363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo .freeze = bfin_freeze, 14909363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo .thaw = bfin_thaw, 14919363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo .softreset = bfin_softreset, 14929363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo .postreset = bfin_postreset, 1493d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 14945682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_irq_clear = bfin_irq_clear, 14955682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_irq_on = bfin_irq_on, 1496d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1497d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .port_start = bfin_port_start, 1498d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .port_stop = bfin_port_stop, 1499d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang}; 1500d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1501d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic struct ata_port_info bfin_port_info[] = { 1502d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang { 1503d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .flags = ATA_FLAG_SLAVE_POSS 1504d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang | ATA_FLAG_MMIO 1505d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang | ATA_FLAG_NO_LEGACY, 1506d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .pio_mask = 0x1f, /* pio0-4 */ 1507d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .mwdma_mask = 0, 1508d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .udma_mask = 0, 1509d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .port_ops = &bfin_pata_ops, 1510d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang }, 1511d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang}; 1512d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1513d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 1514d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_reset_controller - initialize BF54x ATAPI controller. 1515d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1516d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1517d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic int bfin_reset_controller(struct ata_host *host) 1518d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1519d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang void __iomem *base = (void __iomem *)host->ports[0]->ioaddr.ctl_addr; 1520d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang int count; 1521d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang unsigned short status; 1522d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1523d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Disable all ATAPI interrupts */ 1524d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_INT_MASK(base, 0); 1525d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang SSYNC(); 1526d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1527d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Assert the RESET signal 25us*/ 1528d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | DEV_RST); 1529d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang udelay(30); 1530d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1531d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Negate the RESET signal for 2ms*/ 1532d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) & ~DEV_RST); 1533d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang msleep(2); 1534d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1535d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Wait on Busy flag to clear */ 1536d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang count = 10000000; 1537d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang do { 1538d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang status = read_atapi_register(base, ATA_REG_STATUS); 1539f9d42491723dbb77bdc9b9dc7e096ea57d535992Roel Kluin } while (--count && (status & ATA_BUSY)); 1540d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1541d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* Enable only ATAPI Device interrupt */ 1542d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ATAPI_SET_INT_MASK(base, 1); 1543d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang SSYNC(); 1544d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1545d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return (!count); 1546d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1547d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1548d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 1549d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * atapi_io_port - define atapi peripheral port pins. 1550d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1551d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic unsigned short atapi_io_port[] = { 1552d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang P_ATAPI_RESET, 1553d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang P_ATAPI_DIOR, 1554d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang P_ATAPI_DIOW, 1555d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang P_ATAPI_CS0, 1556d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang P_ATAPI_CS1, 1557d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang P_ATAPI_DMACK, 1558d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang P_ATAPI_DMARQ, 1559d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang P_ATAPI_INTRQ, 1560d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang P_ATAPI_IORDY, 1561d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 0 1562d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang}; 1563d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1564d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 1565d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_atapi_probe - attach a bfin atapi interface 1566d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @pdev: platform device 1567d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 1568d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Register a bfin atapi interface. 1569d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 1570d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 1571d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Platform devices are expected to contain 2 resources per port: 1572d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 1573d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * - I/O Base (IORESOURCE_IO) 1574d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * - IRQ (IORESOURCE_IRQ) 1575d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 1576d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1577d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic int __devinit bfin_atapi_probe(struct platform_device *pdev) 1578d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1579d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang int board_idx = 0; 1580d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang struct resource *res; 1581d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang struct ata_host *host; 1582f88c480dac88a754f84e943cb5539d59cda3c089sonic zhang unsigned int fsclk = get_sclk(); 1583f88c480dac88a754f84e943cb5539d59cda3c089sonic zhang int udma_mode = 5; 1584d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang const struct ata_port_info *ppi[] = 1585d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang { &bfin_port_info[board_idx], NULL }; 1586d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1587d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* 1588d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Simple resource validation .. 1589d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1590d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (unlikely(pdev->num_resources != 2)) { 1591d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang dev_err(&pdev->dev, "invalid number of resources\n"); 1592d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return -EINVAL; 1593d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 1594d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1595d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* 1596d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Get the register base first 1597d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1598d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1599d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (res == NULL) 1600d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return -EINVAL; 1601d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1602ed722d3d3eb2e9ea87d9f8109c291337e79d584aAndrew Morton while (bfin_port_info[board_idx].udma_mask > 0 && 1603ed722d3d3eb2e9ea87d9f8109c291337e79d584aAndrew Morton udma_fsclk[udma_mode] > fsclk) { 1604f88c480dac88a754f84e943cb5539d59cda3c089sonic zhang udma_mode--; 1605f88c480dac88a754f84e943cb5539d59cda3c089sonic zhang bfin_port_info[board_idx].udma_mask >>= 1; 1606f88c480dac88a754f84e943cb5539d59cda3c089sonic zhang } 1607f88c480dac88a754f84e943cb5539d59cda3c089sonic zhang 1608d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang /* 1609d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * Now that that's out of the way, wire up the port.. 1610d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1611d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1); 1612d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (!host) 1613d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return -ENOMEM; 1614d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1615d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang host->ports[0]->ioaddr.ctl_addr = (void *)res->start; 1616d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1617d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (peripheral_request_list(atapi_io_port, "atapi-io-port")) { 1618d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang dev_err(&pdev->dev, "Requesting Peripherals faild\n"); 1619d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return -EFAULT; 1620d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 1621d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1622d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (bfin_reset_controller(host)) { 1623d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang peripheral_free_list(atapi_io_port); 1624d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang dev_err(&pdev->dev, "Fail to reset ATAPI device\n"); 1625d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return -EFAULT; 1626d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 1627d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1628d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang if (ata_host_activate(host, platform_get_irq(pdev, 0), 162965c0d4e54ae4b81d8c8bb685169e48306656bb5cSonic Zhang bfin_ata_interrupt, IRQF_SHARED, &bfin_sht) != 0) { 1630d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang peripheral_free_list(atapi_io_port); 1631d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang dev_err(&pdev->dev, "Fail to attach ATAPI device\n"); 1632d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return -ENODEV; 1633d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang } 1634d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 163567e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang dev_set_drvdata(&pdev->dev, host); 163667e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang 1637d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 0; 1638d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1639d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1640d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang/** 1641d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * bfin_atapi_remove - unplug a bfin atapi interface 1642d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * @pdev: platform device 1643d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * 1644d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * A bfin atapi device has been unplugged. Perform the needed 1645d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang * cleanup. Also called on module unload for any active devices. 1646d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang */ 1647d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic int __devexit bfin_atapi_remove(struct platform_device *pdev) 1648d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1649d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang struct device *dev = &pdev->dev; 1650d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang struct ata_host *host = dev_get_drvdata(dev); 1651d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1652d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang ata_host_detach(host); 165367e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang dev_set_drvdata(&pdev->dev, NULL); 1654d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1655d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang peripheral_free_list(atapi_io_port); 1656d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1657d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 0; 1658d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1659d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1660d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#ifdef CONFIG_PM 166167e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhangstatic int bfin_atapi_suspend(struct platform_device *pdev, pm_message_t state) 1662d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 166367e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang struct ata_host *host = dev_get_drvdata(&pdev->dev); 166467e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang if (host) 166567e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang return ata_host_suspend(host, state); 166667e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang else 166767e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang return 0; 1668d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1669d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 167067e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhangstatic int bfin_atapi_resume(struct platform_device *pdev) 1671d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 167267e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang struct ata_host *host = dev_get_drvdata(&pdev->dev); 167367e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang int ret; 167467e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang 167567e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang if (host) { 167667e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang ret = bfin_reset_controller(host); 167767e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang if (ret) { 167867e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang printk(KERN_ERR DRV_NAME ": Error during HW init\n"); 167967e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang return ret; 168067e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang } 168167e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang ata_host_resume(host); 168267e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang } 168367e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang 1684d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return 0; 1685d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 168667e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang#else 168767e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang#define bfin_atapi_suspend NULL 168867e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang#define bfin_atapi_resume NULL 1689d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang#endif 1690d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1691d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic struct platform_driver bfin_atapi_driver = { 1692d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .probe = bfin_atapi_probe, 1693d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .remove = __devexit_p(bfin_atapi_remove), 169467e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang .suspend = bfin_atapi_suspend, 169567e3e221d61c0e70b2f244fd921e5e601d6c7339Sonic Zhang .resume = bfin_atapi_resume, 1696d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .driver = { 1697d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .name = DRV_NAME, 1698d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang .owner = THIS_MODULE, 1699d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang }, 1700d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang}; 1701d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1702858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang#define ATAPI_MODE_SIZE 10 1703858c9c406688bc7244986b5836265071edfd1d3fSonic Zhangstatic char bfin_atapi_mode[ATAPI_MODE_SIZE]; 1704858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang 1705d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic int __init bfin_atapi_init(void) 1706d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1707d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang pr_info("register bfin atapi driver\n"); 1708858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang 1709858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang switch(bfin_atapi_mode[0]) { 1710858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang case 'p': 1711858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang case 'P': 1712858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang break; 1713858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang case 'm': 1714858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang case 'M': 1715858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang bfin_port_info[0].mwdma_mask = ATA_MWDMA2; 1716858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang break; 1717858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang default: 1718858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang bfin_port_info[0].udma_mask = ATA_UDMA5; 1719858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang }; 1720858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang 1721d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang return platform_driver_register(&bfin_atapi_driver); 1722d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1723d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1724d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangstatic void __exit bfin_atapi_exit(void) 1725d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang{ 1726d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang platform_driver_unregister(&bfin_atapi_driver); 1727d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang} 1728d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1729d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangmodule_init(bfin_atapi_init); 1730d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhangmodule_exit(bfin_atapi_exit); 1731858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang/* 1732858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang * ATAPI mode: 1733858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang * pio/PIO 1734858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang * udma/UDMA (default) 1735858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang * mwdma/MWDMA 1736858c9c406688bc7244986b5836265071edfd1d3fSonic Zhang */ 1737858c9c406688bc7244986b5836265071edfd1d3fSonic Zhangmodule_param_string(bfin_atapi_mode, bfin_atapi_mode, ATAPI_MODE_SIZE, 0); 1738d830d1731fa5906aad20c228ac8b73005b13d468Sonic Zhang 1739d830d1731fa5906aad20c228ac8b73005b13d468Sonic ZhangMODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>"); 1740d830d1731fa5906aad20c228ac8b73005b13d468Sonic ZhangMODULE_DESCRIPTION("PATA driver for blackfin 54x ATAPI controller"); 1741d830d1731fa5906aad20c228ac8b73005b13d468Sonic ZhangMODULE_LICENSE("GPL"); 1742d830d1731fa5906aad20c228ac8b73005b13d468Sonic ZhangMODULE_VERSION(DRV_VERSION); 1743458622fcdc5b316de8d74efd7e610803f0308c14Kay SieversMODULE_ALIAS("platform:" DRV_NAME); 1744