188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt/* 288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * Libata based driver for Apple "macio" family of PATA controllers 388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * 488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * Copyright 2008/2009 Benjamin Herrenschmidt, IBM Corp 588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * <benh@kernel.crashing.org> 688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * 788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * Some bits and pieces from drivers/ide/ppc/pmac.c 888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * 988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 1088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 1188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#undef DEBUG 1288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#undef DEBUG_DMA 1388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 1488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#include <linux/kernel.h> 1588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#include <linux/module.h> 1688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#include <linux/init.h> 1788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#include <linux/blkdev.h> 1888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#include <linux/ata.h> 1988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#include <linux/libata.h> 2088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#include <linux/adb.h> 2188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#include <linux/pmu.h> 2288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#include <linux/scatterlist.h> 2388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#include <linux/of.h> 245a0e3ad6af8660be21ca98a971cd00f331318c05Tejun Heo#include <linux/gfp.h> 2588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 2688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#include <scsi/scsi.h> 2788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#include <scsi/scsi_host.h> 2888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#include <scsi/scsi_device.h> 2988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 3088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#include <asm/macio.h> 3188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#include <asm/io.h> 3288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#include <asm/dbdma.h> 3388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#include <asm/pci-bridge.h> 3488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#include <asm/machdep.h> 3588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#include <asm/pmac_feature.h> 3688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#include <asm/mediabay.h> 3788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 3888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#ifdef DEBUG_DMA 3988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define dev_dbgdma(dev, format, arg...) \ 4088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_printk(KERN_DEBUG , dev , format , ## arg) 4188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#else 4288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define dev_dbgdma(dev, format, arg...) \ 4388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; }) 4488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#endif 4588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 4688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define DRV_NAME "pata_macio" 4788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define DRV_VERSION "0.9" 4888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 4988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt/* Models of macio ATA controller */ 5088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtenum { 5188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt controller_ohare, /* OHare based */ 5288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt controller_heathrow, /* Heathrow/Paddington */ 5388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt controller_kl_ata3, /* KeyLargo ATA-3 */ 5488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt controller_kl_ata4, /* KeyLargo ATA-4 */ 5588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt controller_un_ata6, /* UniNorth2 ATA-6 */ 5688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt controller_k2_ata6, /* K2 ATA-6 */ 5788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt controller_sh_ata6, /* Shasta ATA-6 */ 5888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt}; 5988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 6088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic const char* macio_ata_names[] = { 6188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt "OHare ATA", /* OHare based */ 6288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt "Heathrow ATA", /* Heathrow/Paddington */ 6388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */ 6488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */ 6588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */ 6688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */ 6788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */ 6888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt}; 6988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 7088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt/* 7188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * Extra registers, both 32-bit little-endian 7288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 7388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define IDE_TIMING_CONFIG 0x200 7488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define IDE_INTERRUPT 0x300 7588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 7688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt/* Kauai (U2) ATA has different register setup */ 7788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define IDE_KAUAI_PIO_CONFIG 0x200 7888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define IDE_KAUAI_ULTRA_CONFIG 0x210 7988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define IDE_KAUAI_POLL_CONFIG 0x220 8088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 8188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt/* 8288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * Timing configuration register definitions 8388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 8488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 8588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */ 8688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS) 8788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS) 8888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define IDE_SYSCLK_NS 30 /* 33Mhz cell */ 8988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */ 9088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 9188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt/* 133Mhz cell, found in shasta. 9288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * See comments about 100 Mhz Uninorth 2... 9388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * Note that PIO_MASK and MDMA_MASK seem to overlap, that's just 9488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * weird and I don't now why .. at this stage 9588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 9688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_133_PIOREG_PIO_MASK 0xff000fff 9788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_133_PIOREG_MDMA_MASK 0x00fff800 9888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff 9988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_133_UDMAREG_UDMA_EN 0x00000001 10088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 10188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt/* 100Mhz cell, found in Uninorth 2 and K2. It appears as a pci device 10288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * (106b/0033) on uninorth or K2 internal PCI bus and it's clock is 10388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * controlled like gem or fw. It appears to be an evolution of keylargo 10488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * ATA4 with a timing register extended to 2x32bits registers (one 10588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * for PIO & MWDMA and one for UDMA, and a similar DBDMA channel. 10688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * It has it's own local feature control register as well. 10788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * 10888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * After scratching my mind over the timing values, at least for PIO 10988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * and MDMA, I think I've figured the format of the timing register, 11088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * though I use pre-calculated tables for UDMA as usual... 11188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 11288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_100_PIO_ADDRSETUP_MASK 0xff000000 /* Size of field unknown */ 11388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_100_PIO_ADDRSETUP_SHIFT 24 11488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_100_MDMA_MASK 0x00fff000 11588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_100_MDMA_RECOVERY_MASK 0x00fc0000 11688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_100_MDMA_RECOVERY_SHIFT 18 11788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_100_MDMA_ACCESS_MASK 0x0003f000 11888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_100_MDMA_ACCESS_SHIFT 12 11988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_100_PIO_MASK 0xff000fff 12088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_100_PIO_RECOVERY_MASK 0x00000fc0 12188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_100_PIO_RECOVERY_SHIFT 6 12288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_100_PIO_ACCESS_MASK 0x0000003f 12388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_100_PIO_ACCESS_SHIFT 0 12488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 12588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff 12688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_100_UDMAREG_UDMA_EN 0x00000001 12788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 12888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 12988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on 13088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * 40 connector cable and to 4 on 80 connector one. 13188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * Clock unit is 15ns (66Mhz) 13288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * 13388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * 3 Values can be programmed: 13488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * - Write data setup, which appears to match the cycle time. They 13588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * also call it DIOW setup. 13688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * - Ready to pause time (from spec) 13788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * - Address setup. That one is weird. I don't see where exactly 13888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * it fits in UDMA cycles, I got it's name from an obscure piece 13988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * of commented out code in Darwin. They leave it to 0, we do as 14088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * well, despite a comment that would lead to think it has a 14188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * min value of 45ns. 14288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * Apple also add 60ns to the write data setup (or cycle time ?) on 14388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * reads. 14488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 14588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_66_UDMA_MASK 0xfff00000 14688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */ 14788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_66_PIO_ADDRSETUP_MASK 0xe0000000 /* Address setup */ 14888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_66_PIO_ADDRSETUP_SHIFT 29 14988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */ 15088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_66_UDMA_RDY2PAUS_SHIFT 25 15188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */ 15288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_66_UDMA_WRDATASETUP_SHIFT 21 15388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_66_MDMA_MASK 0x000ffc00 15488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_66_MDMA_RECOVERY_MASK 0x000f8000 15588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_66_MDMA_RECOVERY_SHIFT 15 15688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_66_MDMA_ACCESS_MASK 0x00007c00 15788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_66_MDMA_ACCESS_SHIFT 10 15888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_66_PIO_MASK 0xe00003ff 15988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_66_PIO_RECOVERY_MASK 0x000003e0 16088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_66_PIO_RECOVERY_SHIFT 5 16188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_66_PIO_ACCESS_MASK 0x0000001f 16288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_66_PIO_ACCESS_SHIFT 0 16388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 16488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo 16588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * Can do pio & mdma modes, clock unit is 30ns (33Mhz) 16688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * 16788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * The access time and recovery time can be programmed. Some older 16888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * Darwin code base limit OHare to 150ns cycle time. I decided to do 16988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * the same here fore safety against broken old hardware ;) 17088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * The HalfTick bit, when set, adds half a clock (15ns) to the access 17188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * time and removes one from recovery. It's not supported on KeyLargo 17288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * implementation afaik. The E bit appears to be set for PIO mode 0 and 17388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * is used to reach long timings used in this mode. 17488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 17588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_33_MDMA_MASK 0x003ff800 17688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_33_MDMA_RECOVERY_MASK 0x001f0000 17788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_33_MDMA_RECOVERY_SHIFT 16 17888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_33_MDMA_ACCESS_MASK 0x0000f800 17988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_33_MDMA_ACCESS_SHIFT 11 18088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_33_MDMA_HALFTICK 0x00200000 18188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_33_PIO_MASK 0x000007ff 18288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_33_PIO_E 0x00000400 18388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_33_PIO_RECOVERY_MASK 0x000003e0 18488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_33_PIO_RECOVERY_SHIFT 5 18588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_33_PIO_ACCESS_MASK 0x0000001f 18688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define TR_33_PIO_ACCESS_SHIFT 0 18788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 18888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt/* 18988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * Interrupt register definitions. Only present on newer cells 19088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * (Keylargo and later afaik) so we don't use it. 19188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 19288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define IDE_INTR_DMA 0x80000000 19388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define IDE_INTR_DEVICE 0x40000000 19488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 19588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt/* 19688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * FCR Register on Kauai. Not sure what bit 0x4 is ... 19788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 19888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define KAUAI_FCR_UATA_MAGIC 0x00000004 19988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define KAUAI_FCR_UATA_RESET_N 0x00000002 20088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define KAUAI_FCR_UATA_ENABLE 0x00000001 20188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 20288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 20388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt/* Allow up to 256 DBDMA commands per xfer */ 20488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define MAX_DCMDS 256 20588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 20688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt/* Don't let a DMA segment go all the way to 64K */ 20788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define MAX_DBDMA_SEG 0xff00 20888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 20988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 21088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt/* 21188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * Wait 1s for disk to answer on IDE bus after a hard reset 21288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * of the device (via GPIO/FCR). 21388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * 21488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * Some devices seem to "pollute" the bus even after dropping 21588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * the BSY bit (typically some combo drives slave on the UDMA 21688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * bus) after a hard reset. Since we hard reset all drives on 21788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * KeyLargo ATA66, we have to keep that delay around. I may end 21888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * up not hard resetting anymore on these and keep the delay only 21988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * for older interfaces instead (we have to reset when coming 22088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * from MacOS...) --BenH. 22188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 22288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#define IDE_WAKEUP_DELAY_MS 1000 22388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 22488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstruct pata_macio_timing; 22588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 22688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstruct pata_macio_priv { 22788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt int kind; 22888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt int aapl_bus_id; 22988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt int mediabay : 1; 23088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct device_node *node; 23188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct macio_dev *mdev; 23288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct pci_dev *pdev; 23388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct device *dev; 23488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt int irq; 23588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt u32 treg[2][2]; 23688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt void __iomem *tfregs; 23788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt void __iomem *kauai_fcr; 23888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct dbdma_cmd * dma_table_cpu; 23988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dma_addr_t dma_table_dma; 24088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct ata_host *host; 24188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt const struct pata_macio_timing *timings; 24288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt}; 24388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 24488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt/* Previous variants of this driver used to calculate timings 24588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * for various variants of the chip and use tables for others. 24688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * 24788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * Not only was this confusing, but in addition, it isn't clear 24888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * whether our calculation code was correct. It didn't entirely 24988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * match the darwin code and whatever documentation I could find 25088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * on these cells 25188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * 25288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * I decided to entirely rely on a table instead for this version 25388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * of the driver. Also, because I don't really care about derated 25488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * modes and really old HW other than making it work, I'm not going 25588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * to calculate / snoop timing values for something else than the 25688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * standard modes. 25788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 25888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstruct pata_macio_timing { 25988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt int mode; 26088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt u32 reg1; /* Bits to set in first timing reg */ 26188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt u32 reg2; /* Bits to set in second timing reg */ 26288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt}; 26388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 26488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic const struct pata_macio_timing pata_macio_ohare_timings[] = { 26588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_0, 0x00000526, 0, }, 26688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_1, 0x00000085, 0, }, 26788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_2, 0x00000025, 0, }, 26888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_3, 0x00000025, 0, }, 26988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_4, 0x00000025, 0, }, 27088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_MW_DMA_0, 0x00074000, 0, }, 27188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_MW_DMA_1, 0x00221000, 0, }, 27288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_MW_DMA_2, 0x00211000, 0, }, 27388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { -1, 0, 0 } 27488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt}; 27588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 27688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic const struct pata_macio_timing pata_macio_heathrow_timings[] = { 27788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_0, 0x00000526, 0, }, 27888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_1, 0x00000085, 0, }, 27988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_2, 0x00000025, 0, }, 28088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_3, 0x00000025, 0, }, 28188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_4, 0x00000025, 0, }, 28288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_MW_DMA_0, 0x00074000, 0, }, 28388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_MW_DMA_1, 0x00221000, 0, }, 28488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_MW_DMA_2, 0x00211000, 0, }, 28588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { -1, 0, 0 } 28688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt}; 28788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 28888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic const struct pata_macio_timing pata_macio_kl33_timings[] = { 28988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_0, 0x00000526, 0, }, 29088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_1, 0x00000085, 0, }, 29188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_2, 0x00000025, 0, }, 29288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_3, 0x00000025, 0, }, 29388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_4, 0x00000025, 0, }, 29488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_MW_DMA_0, 0x00084000, 0, }, 29588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_MW_DMA_1, 0x00021800, 0, }, 29688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_MW_DMA_2, 0x00011800, 0, }, 29788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { -1, 0, 0 } 29888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt}; 29988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 30088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic const struct pata_macio_timing pata_macio_kl66_timings[] = { 30188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_0, 0x0000038c, 0, }, 30288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_1, 0x0000020a, 0, }, 30388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_2, 0x00000127, 0, }, 30488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_3, 0x000000c6, 0, }, 30588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_4, 0x00000065, 0, }, 30688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_MW_DMA_0, 0x00084000, 0, }, 30788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_MW_DMA_1, 0x00029800, 0, }, 30888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_MW_DMA_2, 0x00019400, 0, }, 30988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_UDMA_0, 0x19100000, 0, }, 31088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_UDMA_1, 0x14d00000, 0, }, 31188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_UDMA_2, 0x10900000, 0, }, 31288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_UDMA_3, 0x0c700000, 0, }, 31388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_UDMA_4, 0x0c500000, 0, }, 31488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { -1, 0, 0 } 31588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt}; 31688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 31788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic const struct pata_macio_timing pata_macio_kauai_timings[] = { 31888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_0, 0x08000a92, 0, }, 31988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_1, 0x0800060f, 0, }, 32088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_2, 0x0800038b, 0, }, 32188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_3, 0x05000249, 0, }, 32288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_4, 0x04000148, 0, }, 32388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_MW_DMA_0, 0x00618000, 0, }, 32488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_MW_DMA_1, 0x00209000, 0, }, 32588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_MW_DMA_2, 0x00148000, 0, }, 32688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_UDMA_0, 0, 0x000070c1, }, 32788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_UDMA_1, 0, 0x00005d81, }, 32888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_UDMA_2, 0, 0x00004a61, }, 32988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_UDMA_3, 0, 0x00003a51, }, 33088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_UDMA_4, 0, 0x00002a31, }, 33188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_UDMA_5, 0, 0x00002921, }, 33288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { -1, 0, 0 } 33388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt}; 33488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 33588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic const struct pata_macio_timing pata_macio_shasta_timings[] = { 33688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_0, 0x0a000c97, 0, }, 33788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_1, 0x07000712, 0, }, 33888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_2, 0x040003cd, 0, }, 33988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_3, 0x0500028b, 0, }, 34088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_PIO_4, 0x0400010a, 0, }, 34188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_MW_DMA_0, 0x00820800, 0, }, 34288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_MW_DMA_1, 0x0028b000, 0, }, 34388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_MW_DMA_2, 0x001ca000, 0, }, 34488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_UDMA_0, 0, 0x00035901, }, 34588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_UDMA_1, 0, 0x000348b1, }, 34688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_UDMA_2, 0, 0x00033881, }, 34788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_UDMA_3, 0, 0x00033861, }, 34888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_UDMA_4, 0, 0x00033841, }, 34988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_UDMA_5, 0, 0x00033031, }, 35088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { XFER_UDMA_6, 0, 0x00033021, }, 35188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { -1, 0, 0 } 35288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt}; 35388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 35488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic const struct pata_macio_timing *pata_macio_find_timing( 35588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct pata_macio_priv *priv, 35688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt int mode) 35788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 35888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt int i; 35988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 36088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt for (i = 0; priv->timings[i].mode > 0; i++) { 36188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (priv->timings[i].mode == mode) 36288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return &priv->timings[i]; 36388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 36488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return NULL; 36588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 36688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 36788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 36888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic void pata_macio_apply_timings(struct ata_port *ap, unsigned int device) 36988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 37088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct pata_macio_priv *priv = ap->private_data; 37188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt void __iomem *rbase = ap->ioaddr.cmd_addr; 37288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 37388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (priv->kind == controller_sh_ata6 || 37488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->kind == controller_un_ata6 || 37588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->kind == controller_k2_ata6) { 37688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt writel(priv->treg[device][0], rbase + IDE_KAUAI_PIO_CONFIG); 37788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt writel(priv->treg[device][1], rbase + IDE_KAUAI_ULTRA_CONFIG); 37888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } else 37988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt writel(priv->treg[device][0], rbase + IDE_TIMING_CONFIG); 38088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 38188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 38288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic void pata_macio_dev_select(struct ata_port *ap, unsigned int device) 38388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 38488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ata_sff_dev_select(ap, device); 38588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 38688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Apply timings */ 38788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pata_macio_apply_timings(ap, device); 38888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 38988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 39088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic void pata_macio_set_timings(struct ata_port *ap, 39188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct ata_device *adev) 39288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 39388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct pata_macio_priv *priv = ap->private_data; 39488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt const struct pata_macio_timing *t; 39588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 39688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_dbg(priv->dev, "Set timings: DEV=%d,PIO=0x%x (%s),DMA=0x%x (%s)\n", 39788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt adev->devno, 39888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt adev->pio_mode, 39988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ata_mode_string(ata_xfer_mode2mask(adev->pio_mode)), 40088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt adev->dma_mode, 40188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ata_mode_string(ata_xfer_mode2mask(adev->dma_mode))); 40288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 40388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* First clear timings */ 40488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->treg[adev->devno][0] = priv->treg[adev->devno][1] = 0; 40588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 40688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Now get the PIO timings */ 40788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt t = pata_macio_find_timing(priv, adev->pio_mode); 40888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (t == NULL) { 40988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_warn(priv->dev, "Invalid PIO timing requested: 0x%x\n", 41088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt adev->pio_mode); 41188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt t = pata_macio_find_timing(priv, XFER_PIO_0); 41288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 41388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt BUG_ON(t == NULL); 41488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 41588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* PIO timings only ever use the first treg */ 41688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->treg[adev->devno][0] |= t->reg1; 41788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 41888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Now get DMA timings */ 41988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt t = pata_macio_find_timing(priv, adev->dma_mode); 42088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (t == NULL || (t->reg1 == 0 && t->reg2 == 0)) { 42188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_dbg(priv->dev, "DMA timing not set yet, using MW_DMA_0\n"); 42288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt t = pata_macio_find_timing(priv, XFER_MW_DMA_0); 42388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 42488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt BUG_ON(t == NULL); 42588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 42688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* DMA timings can use both tregs */ 42788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->treg[adev->devno][0] |= t->reg1; 42888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->treg[adev->devno][1] |= t->reg2; 42988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 43088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_dbg(priv->dev, " -> %08x %08x\n", 43188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->treg[adev->devno][0], 43288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->treg[adev->devno][1]); 43388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 43488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Apply to hardware */ 43588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pata_macio_apply_timings(ap, adev->devno); 43688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 43788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 43888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt/* 43988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * Blast some well known "safe" values to the timing registers at init or 44088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * wakeup from sleep time, before we do real calculation 44188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 44288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic void pata_macio_default_timings(struct pata_macio_priv *priv) 44388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 44488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt unsigned int value, value2 = 0; 44588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 44688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt switch(priv->kind) { 44788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt case controller_sh_ata6: 44888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt value = 0x0a820c97; 44988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt value2 = 0x00033031; 45088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt break; 45188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt case controller_un_ata6: 45288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt case controller_k2_ata6: 45388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt value = 0x08618a92; 45488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt value2 = 0x00002921; 45588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt break; 45688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt case controller_kl_ata4: 45788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt value = 0x0008438c; 45888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt break; 45988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt case controller_kl_ata3: 46088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt value = 0x00084526; 46188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt break; 46288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt case controller_heathrow: 46388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt case controller_ohare: 46488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt default: 46588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt value = 0x00074526; 46688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt break; 46788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 46888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->treg[0][0] = priv->treg[1][0] = value; 46988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->treg[0][1] = priv->treg[1][1] = value2; 47088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 47188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 47288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic int pata_macio_cable_detect(struct ata_port *ap) 47388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 47488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct pata_macio_priv *priv = ap->private_data; 47588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 47688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Get cable type from device-tree */ 47788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (priv->kind == controller_kl_ata4 || 47888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->kind == controller_un_ata6 || 47988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->kind == controller_k2_ata6 || 48088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->kind == controller_sh_ata6) { 48188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt const char* cable = of_get_property(priv->node, "cable-type", 48288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt NULL); 48388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct device_node *root = of_find_node_by_path("/"); 48488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt const char *model = of_get_property(root, "model", NULL); 48588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 48688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (cable && !strncmp(cable, "80-", 3)) { 48788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Some drives fail to detect 80c cable in PowerBook 48888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * These machine use proprietary short IDE cable 48988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * anyway 49088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 49188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (!strncmp(model, "PowerBook", 9)) 49288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return ATA_CBL_PATA40_SHORT; 49388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt else 49488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return ATA_CBL_PATA80; 49588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 49688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 49788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 49888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* G5's seem to have incorrect cable type in device-tree. 49988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * Let's assume they always have a 80 conductor cable, this seem to 50088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * be always the case unless the user mucked around 50188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 50288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (of_device_is_compatible(priv->node, "K2-UATA") || 50388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt of_device_is_compatible(priv->node, "shasta-ata")) 50488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return ATA_CBL_PATA80; 50588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 50688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Anything else is 40 connectors */ 50788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return ATA_CBL_PATA40; 50888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 50988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 51088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic void pata_macio_qc_prep(struct ata_queued_cmd *qc) 51188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 51288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt unsigned int write = (qc->tf.flags & ATA_TFLAG_WRITE); 51388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct ata_port *ap = qc->ap; 51488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct pata_macio_priv *priv = ap->private_data; 51588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct scatterlist *sg; 51688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct dbdma_cmd *table; 51788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt unsigned int si, pi; 51888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 51988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_dbgdma(priv->dev, "%s: qc %p flags %lx, write %d dev %d\n", 52088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt __func__, qc, qc->flags, write, qc->dev->devno); 52188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 52288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 52388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return; 52488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 52588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt table = (struct dbdma_cmd *) priv->dma_table_cpu; 52688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 52788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pi = 0; 52888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt for_each_sg(qc->sg, sg, qc->n_elem, si) { 52988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt u32 addr, sg_len, len; 53088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 53188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* determine if physical DMA addr spans 64K boundary. 53288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * Note h/w doesn't support 64-bit, so we unconditionally 53388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * truncate dma_addr_t to u32. 53488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 53588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt addr = (u32) sg_dma_address(sg); 53688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt sg_len = sg_dma_len(sg); 53788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 53888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt while (sg_len) { 53988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* table overflow should never happen */ 54088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt BUG_ON (pi++ >= MAX_DCMDS); 54188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 54288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt len = (sg_len < MAX_DBDMA_SEG) ? sg_len : MAX_DBDMA_SEG; 54388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt st_le16(&table->command, write ? OUTPUT_MORE: INPUT_MORE); 54488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt st_le16(&table->req_count, len); 54588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt st_le32(&table->phy_addr, addr); 54688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt table->cmd_dep = 0; 54788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt table->xfer_status = 0; 54888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt table->res_count = 0; 54988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt addr += len; 55088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt sg_len -= len; 55188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ++table; 55288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 55388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 55488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 55588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Should never happen according to Tejun */ 55688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt BUG_ON(!pi); 55788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 55888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Convert the last command to an input/output */ 55988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt table--; 56088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt st_le16(&table->command, write ? OUTPUT_LAST: INPUT_LAST); 56188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt table++; 56288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 56388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Add the stop command to the end of the list */ 56488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt memset(table, 0, sizeof(struct dbdma_cmd)); 56588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt st_le16(&table->command, DBDMA_STOP); 56688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 56788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_dbgdma(priv->dev, "%s: %d DMA list entries\n", __func__, pi); 56888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 56988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 57088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 57188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic void pata_macio_freeze(struct ata_port *ap) 57288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 57388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr; 57488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 57588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (dma_regs) { 57688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt unsigned int timeout = 1000000; 57788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 57888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Make sure DMA controller is stopped */ 57988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma_regs->control); 58088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt while (--timeout && (readl(&dma_regs->status) & RUN)) 58188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt udelay(1); 58288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 58388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 58488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ata_sff_freeze(ap); 58588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 58688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 58788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 58888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic void pata_macio_bmdma_setup(struct ata_queued_cmd *qc) 58988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 59088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct ata_port *ap = qc->ap; 59188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct pata_macio_priv *priv = ap->private_data; 59288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr; 59388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt int dev = qc->dev->devno; 59488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 59588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc); 59688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 59788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Make sure DMA commands updates are visible */ 59888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt writel(priv->dma_table_dma, &dma_regs->cmdptr); 59988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 60088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* On KeyLargo 66Mhz cell, we need to add 60ns to wrDataSetup on 60188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * UDMA reads 60288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 60388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (priv->kind == controller_kl_ata4 && 60488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt (priv->treg[dev][0] & TR_66_UDMA_EN)) { 60588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt void __iomem *rbase = ap->ioaddr.cmd_addr; 60688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt u32 reg = priv->treg[dev][0]; 60788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 60888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 60988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt reg += 0x00800000; 61088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt writel(reg, rbase + IDE_TIMING_CONFIG); 61188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 61288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 61388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* issue r/w command */ 61488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ap->ops->sff_exec_command(ap, &qc->tf); 61588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 61688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 61788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic void pata_macio_bmdma_start(struct ata_queued_cmd *qc) 61888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 61988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct ata_port *ap = qc->ap; 62088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct pata_macio_priv *priv = ap->private_data; 62188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr; 62288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 62388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc); 62488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 62588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt writel((RUN << 16) | RUN, &dma_regs->control); 62688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Make sure it gets to the controller right now */ 62788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt (void)readl(&dma_regs->control); 62888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 62988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 63088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic void pata_macio_bmdma_stop(struct ata_queued_cmd *qc) 63188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 63288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct ata_port *ap = qc->ap; 63388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct pata_macio_priv *priv = ap->private_data; 63488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr; 63588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt unsigned int timeout = 1000000; 63688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 63788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc); 63888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 63988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Stop the DMA engine and wait for it to full halt */ 64088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt writel (((RUN|WAKE|DEAD) << 16), &dma_regs->control); 64188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt while (--timeout && (readl(&dma_regs->status) & RUN)) 64288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt udelay(1); 64388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 64488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 64588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic u8 pata_macio_bmdma_status(struct ata_port *ap) 64688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 64788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct pata_macio_priv *priv = ap->private_data; 64888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr; 64988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt u32 dstat, rstat = ATA_DMA_INTR; 65088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt unsigned long timeout = 0; 65188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 65288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dstat = readl(&dma_regs->status); 65388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 65488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_dbgdma(priv->dev, "%s: dstat=%x\n", __func__, dstat); 65588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 65688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* We have two things to deal with here: 65788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * 65888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * - The dbdma won't stop if the command was started 65988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * but completed with an error without transferring all 66088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * datas. This happens when bad blocks are met during 66188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * a multi-block transfer. 66288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * 66388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * - The dbdma fifo hasn't yet finished flushing to 66488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * to system memory when the disk interrupt occurs. 66588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * 66688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 66788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 66888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* First check for errors */ 66988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if ((dstat & (RUN|DEAD)) != RUN) 67088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt rstat |= ATA_DMA_ERR; 67188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 67288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* If ACTIVE is cleared, the STOP command has been hit and 67388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * the transfer is complete. If not, we have to flush the 67488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * channel. 67588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 67688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if ((dstat & ACTIVE) == 0) 67788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return rstat; 67888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 67988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_dbgdma(priv->dev, "%s: DMA still active, flushing...\n", __func__); 68088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 68188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* If dbdma didn't execute the STOP command yet, the 68288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * active bit is still set. We consider that we aren't 68388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * sharing interrupts (which is hopefully the case with 68488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * those controllers) and so we just try to flush the 68588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * channel for pending data in the fifo 68688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 68788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt udelay(1); 68888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt writel((FLUSH << 16) | FLUSH, &dma_regs->control); 68988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt for (;;) { 69088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt udelay(1); 69188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dstat = readl(&dma_regs->status); 69288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if ((dstat & FLUSH) == 0) 69388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt break; 69488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (++timeout > 1000) { 69588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_warn(priv->dev, "timeout flushing DMA\n"); 69688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt rstat |= ATA_DMA_ERR; 69788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt break; 69888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 69988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 70088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return rstat; 70188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 70288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 70388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt/* port_start is when we allocate the DMA command list */ 70488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic int pata_macio_port_start(struct ata_port *ap) 70588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 70688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct pata_macio_priv *priv = ap->private_data; 70788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 70888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (ap->ioaddr.bmdma_addr == NULL) 70988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return 0; 71088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 71188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Allocate space for the DBDMA commands. 71288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * 71388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * The +2 is +1 for the stop command and +1 to allow for 71488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * aligning the start address to a multiple of 16 bytes. 71588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 71688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->dma_table_cpu = 71788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dmam_alloc_coherent(priv->dev, 71888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd), 71988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt &priv->dma_table_dma, GFP_KERNEL); 72088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (priv->dma_table_cpu == NULL) { 72188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_err(priv->dev, "Unable to allocate DMA command list\n"); 72288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ap->ioaddr.bmdma_addr = NULL; 723c7087652e1890a3feef35b30ee1d4be68e1932cdTejun Heo ap->mwdma_mask = 0; 724c7087652e1890a3feef35b30ee1d4be68e1932cdTejun Heo ap->udma_mask = 0; 72588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 72688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return 0; 72788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 72888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 72988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic void pata_macio_irq_clear(struct ata_port *ap) 73088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 73188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct pata_macio_priv *priv = ap->private_data; 73288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 73388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Nothing to do here */ 73488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 73588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_dbgdma(priv->dev, "%s\n", __func__); 73688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 73788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 73888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic void pata_macio_reset_hw(struct pata_macio_priv *priv, int resume) 73988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 74088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_dbg(priv->dev, "Enabling & resetting... \n"); 74188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 74288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (priv->mediabay) 74388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return; 74488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 74588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (priv->kind == controller_ohare && !resume) { 74688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* The code below is having trouble on some ohare machines 74788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * (timing related ?). Until I can put my hand on one of these 74888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * units, I keep the old way 74988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 75088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node, 0, 1); 75188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } else { 75288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt int rc; 75388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 75488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Reset and enable controller */ 75588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt rc = ppc_md.feature_call(PMAC_FTR_IDE_RESET, 75688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->node, priv->aapl_bus_id, 1); 75788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, 75888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->node, priv->aapl_bus_id, 1); 75988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt msleep(10); 76088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Only bother waiting if there's a reset control */ 76188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (rc == 0) { 76288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ppc_md.feature_call(PMAC_FTR_IDE_RESET, 76388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->node, priv->aapl_bus_id, 0); 76488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt msleep(IDE_WAKEUP_DELAY_MS); 76588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 76688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 76788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 76888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* If resuming a PCI device, restore the config space here */ 76988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (priv->pdev && resume) { 77088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt int rc; 77188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 77288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pci_restore_state(priv->pdev); 77388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt rc = pcim_enable_device(priv->pdev); 77488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (rc) 775a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches dev_err(&priv->pdev->dev, 776a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches "Failed to enable device after resume (%d)\n", 777a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches rc); 77888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt else 77988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pci_set_master(priv->pdev); 78088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 78188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 78288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* On Kauai, initialize the FCR. We don't perform a reset, doesn't really 78388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * seem necessary and speeds up the boot process 78488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 78588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (priv->kauai_fcr) 78688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt writel(KAUAI_FCR_UATA_MAGIC | 78788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt KAUAI_FCR_UATA_RESET_N | 78888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt KAUAI_FCR_UATA_ENABLE, priv->kauai_fcr); 78988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 79088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 79188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt/* Hook the standard slave config to fixup some HW related alignment 79288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * restrictions 79388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 79488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic int pata_macio_slave_config(struct scsi_device *sdev) 79588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 79688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct ata_port *ap = ata_shost_to_port(sdev->host); 79788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct pata_macio_priv *priv = ap->private_data; 79888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct ata_device *dev; 79988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt u16 cmd; 80088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt int rc; 80188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 80288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* First call original */ 80388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt rc = ata_scsi_slave_config(sdev); 80488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (rc) 80588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return rc; 80688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 80788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* This is lifted from sata_nv */ 80888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev = &ap->link.device[sdev->id]; 80988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 81088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* OHare has issues with non cache aligned DMA on some chipsets */ 81188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (priv->kind == controller_ohare) { 81288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt blk_queue_update_dma_alignment(sdev->request_queue, 31); 81388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt blk_queue_update_dma_pad(sdev->request_queue, 31); 81488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 81588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Tell the world about it */ 816a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches ata_dev_info(dev, "OHare alignment limits applied\n"); 81788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return 0; 81888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 81988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 82088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* We only have issues with ATAPI */ 82188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (dev->class != ATA_DEV_ATAPI) 82288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return 0; 82388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 82488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Shasta and K2 seem to have "issues" with reads ... */ 82588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (priv->kind == controller_sh_ata6 || priv->kind == controller_k2_ata6) { 82688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Allright these are bad, apply restrictions */ 82788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt blk_queue_update_dma_alignment(sdev->request_queue, 15); 82888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt blk_queue_update_dma_pad(sdev->request_queue, 15); 82988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 83088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* We enable MWI and hack cache line size directly here, this 83188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * is specific to this chipset and not normal values, we happen 83288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * to somewhat know what we are doing here (which is basically 83388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * to do the same Apple does and pray they did not get it wrong :-) 83488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 83588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt BUG_ON(!priv->pdev); 83688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pci_write_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, 0x08); 83788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pci_read_config_word(priv->pdev, PCI_COMMAND, &cmd); 83888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pci_write_config_word(priv->pdev, PCI_COMMAND, 83988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt cmd | PCI_COMMAND_INVALIDATE); 84088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 84188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Tell the world about it */ 842a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches ata_dev_info(dev, "K2/Shasta alignment limits applied\n"); 84388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 84488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 84588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return 0; 84688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 84788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 84888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#ifdef CONFIG_PM 84988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 85088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic int pata_macio_do_suspend(struct pata_macio_priv *priv, pm_message_t mesg) 85188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 85288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt int rc; 85388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 85488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* First, core libata suspend to do most of the work */ 85588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt rc = ata_host_suspend(priv->host, mesg); 85688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (rc) 85788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return rc; 85888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 85988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Restore to default timings */ 86088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pata_macio_default_timings(priv); 86188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 86288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Mask interrupt. Not strictly necessary but old driver did 86388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * it and I'd rather not change that here */ 86488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt disable_irq(priv->irq); 86588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 86688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* The media bay will handle itself just fine */ 86788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (priv->mediabay) 86888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return 0; 86988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 87088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Kauai has bus control FCRs directly here */ 87188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (priv->kauai_fcr) { 87288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt u32 fcr = readl(priv->kauai_fcr); 87388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE); 87488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt writel(fcr, priv->kauai_fcr); 87588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 87688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 87788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* For PCI, save state and disable DMA. No need to call 87888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * pci_set_power_state(), the HW doesn't do D states that 87988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * way, the platform code will take care of suspending the 88088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * ASIC properly 88188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 88288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (priv->pdev) { 88388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pci_save_state(priv->pdev); 88488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pci_disable_device(priv->pdev); 88588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 88688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 88788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Disable the bus on older machines and the cell on kauai */ 88888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node, 88988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->aapl_bus_id, 0); 89088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 89188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return 0; 89288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 89388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 89488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic int pata_macio_do_resume(struct pata_macio_priv *priv) 89588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 89688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Reset and re-enable the HW */ 89788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pata_macio_reset_hw(priv, 1); 89888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 89988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Sanitize drive timings */ 90088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pata_macio_apply_timings(priv->host->ports[0], 0); 90188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 90288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* We want our IRQ back ! */ 90388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt enable_irq(priv->irq); 90488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 90588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Let the libata core take it from there */ 90688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ata_host_resume(priv->host); 90788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 90888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return 0; 90988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 91088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 91188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#endif /* CONFIG_PM */ 91288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 91388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic struct scsi_host_template pata_macio_sht = { 91488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ATA_BASE_SHT(DRV_NAME), 91588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .sg_tablesize = MAX_DCMDS, 91688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* We may not need that strict one */ 91788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .dma_boundary = ATA_DMA_BOUNDARY, 91888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .slave_configure = pata_macio_slave_config, 91988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt}; 92088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 92188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic struct ata_port_operations pata_macio_ops = { 9228930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .inherits = &ata_bmdma_port_ops, 92388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 92488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .freeze = pata_macio_freeze, 92588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .set_piomode = pata_macio_set_timings, 92688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .set_dmamode = pata_macio_set_timings, 92788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .cable_detect = pata_macio_cable_detect, 92888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .sff_dev_select = pata_macio_dev_select, 92988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .qc_prep = pata_macio_qc_prep, 93088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .bmdma_setup = pata_macio_bmdma_setup, 93188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .bmdma_start = pata_macio_bmdma_start, 93288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .bmdma_stop = pata_macio_bmdma_stop, 93388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .bmdma_status = pata_macio_bmdma_status, 93488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .port_start = pata_macio_port_start, 93588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .sff_irq_clear = pata_macio_irq_clear, 93688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt}; 93788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 93888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic void __devinit pata_macio_invariants(struct pata_macio_priv *priv) 93988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 94088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt const int *bidp; 94188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 94288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Identify the type of controller */ 94388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (of_device_is_compatible(priv->node, "shasta-ata")) { 94488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->kind = controller_sh_ata6; 94588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->timings = pata_macio_shasta_timings; 94688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } else if (of_device_is_compatible(priv->node, "kauai-ata")) { 94788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->kind = controller_un_ata6; 94888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->timings = pata_macio_kauai_timings; 94988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } else if (of_device_is_compatible(priv->node, "K2-UATA")) { 95088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->kind = controller_k2_ata6; 95188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->timings = pata_macio_kauai_timings; 95288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } else if (of_device_is_compatible(priv->node, "keylargo-ata")) { 95388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (strcmp(priv->node->name, "ata-4") == 0) { 95488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->kind = controller_kl_ata4; 95588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->timings = pata_macio_kl66_timings; 95688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } else { 95788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->kind = controller_kl_ata3; 95888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->timings = pata_macio_kl33_timings; 95988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 96088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } else if (of_device_is_compatible(priv->node, "heathrow-ata")) { 96188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->kind = controller_heathrow; 96288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->timings = pata_macio_heathrow_timings; 96388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } else { 96488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->kind = controller_ohare; 96588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->timings = pata_macio_ohare_timings; 96688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 96788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 96888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* XXX FIXME --- setup priv->mediabay here */ 96988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 97088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Get Apple bus ID (for clock and ASIC control) */ 97188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt bidp = of_get_property(priv->node, "AAPL,bus-id", NULL); 97288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->aapl_bus_id = bidp ? *bidp : 0; 97388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 97488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Fixup missing Apple bus ID in case of media-bay */ 97588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (priv->mediabay && bidp == 0) 97688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->aapl_bus_id = 1; 97788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 97888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 97988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic void __devinit pata_macio_setup_ios(struct ata_ioports *ioaddr, 98088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt void __iomem * base, 98188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt void __iomem * dma) 98288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 98388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* cmd_addr is the base of regs for that port */ 98488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ioaddr->cmd_addr = base; 98588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 98688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* taskfile registers */ 98788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ioaddr->data_addr = base + (ATA_REG_DATA << 4); 98888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ioaddr->error_addr = base + (ATA_REG_ERR << 4); 98988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ioaddr->feature_addr = base + (ATA_REG_FEATURE << 4); 99088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ioaddr->nsect_addr = base + (ATA_REG_NSECT << 4); 99188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ioaddr->lbal_addr = base + (ATA_REG_LBAL << 4); 99288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ioaddr->lbam_addr = base + (ATA_REG_LBAM << 4); 99388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ioaddr->lbah_addr = base + (ATA_REG_LBAH << 4); 99488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ioaddr->device_addr = base + (ATA_REG_DEVICE << 4); 99588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ioaddr->status_addr = base + (ATA_REG_STATUS << 4); 99688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ioaddr->command_addr = base + (ATA_REG_CMD << 4); 99788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ioaddr->altstatus_addr = base + 0x160; 99888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ioaddr->ctl_addr = base + 0x160; 99988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ioaddr->bmdma_addr = dma; 100088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 100188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 100288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic void __devinit pmac_macio_calc_timing_masks(struct pata_macio_priv *priv, 100388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct ata_port_info *pinfo) 100488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 100588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt int i = 0; 100688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 100788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pinfo->pio_mask = 0; 100888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pinfo->mwdma_mask = 0; 100988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pinfo->udma_mask = 0; 101088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 101188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt while (priv->timings[i].mode > 0) { 101288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt unsigned int mask = 1U << (priv->timings[i].mode & 0x0f); 101388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt switch(priv->timings[i].mode & 0xf0) { 101488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt case 0x00: /* PIO */ 101588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pinfo->pio_mask |= (mask >> 8); 101688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt break; 101788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt case 0x20: /* MWDMA */ 101888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pinfo->mwdma_mask |= mask; 101988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt break; 102088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt case 0x40: /* UDMA */ 102188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pinfo->udma_mask |= mask; 102288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt break; 102388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 102488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt i++; 102588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 102688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_dbg(priv->dev, "Supported masks: PIO=%lx, MWDMA=%lx, UDMA=%lx\n", 102788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pinfo->pio_mask, pinfo->mwdma_mask, pinfo->udma_mask); 102888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 102988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 103088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic int __devinit pata_macio_common_init(struct pata_macio_priv *priv, 103188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt resource_size_t tfregs, 103288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt resource_size_t dmaregs, 103388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt resource_size_t fcregs, 103488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt unsigned long irq) 103588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 103688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct ata_port_info pinfo; 103788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt const struct ata_port_info *ppi[] = { &pinfo, NULL }; 103888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt void __iomem *dma_regs = NULL; 103988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 104088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Fill up privates with various invariants collected from the 104188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * device-tree 104288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 104388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pata_macio_invariants(priv); 104488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 104588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Make sure we have sane initial timings in the cache */ 104688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pata_macio_default_timings(priv); 104788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 104888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Not sure what the real max is but we know it's less than 64K, let's 104988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * use 64K minus 256 105088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 105188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dma_set_max_seg_size(priv->dev, MAX_DBDMA_SEG); 105288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 105388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Allocate libata host for 1 port */ 105488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt memset(&pinfo, 0, sizeof(struct ata_port_info)); 105588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pmac_macio_calc_timing_masks(priv, &pinfo); 10569cbe056f6c467e7395d5aec39aceec47812eb98eSergei Shtylyov pinfo.flags = ATA_FLAG_SLAVE_POSS; 105788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pinfo.port_ops = &pata_macio_ops; 105888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pinfo.private_data = priv; 105988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 106088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->host = ata_host_alloc_pinfo(priv->dev, ppi, 1); 106188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (priv->host == NULL) { 106288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_err(priv->dev, "Failed to allocate ATA port structure\n"); 106388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return -ENOMEM; 106488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 106588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 106688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Setup the private data in host too */ 106788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->host->private_data = priv; 106888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 106988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Map base registers */ 107088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->tfregs = devm_ioremap(priv->dev, tfregs, 0x100); 107188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (priv->tfregs == NULL) { 107288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_err(priv->dev, "Failed to map ATA ports\n"); 107388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return -ENOMEM; 107488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 107588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->host->iomap = &priv->tfregs; 107688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 107788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Map DMA regs */ 107888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (dmaregs != 0) { 107988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dma_regs = devm_ioremap(priv->dev, dmaregs, 108088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt sizeof(struct dbdma_regs)); 108188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (dma_regs == NULL) 108288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_warn(priv->dev, "Failed to map ATA DMA registers\n"); 108388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 108488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 108588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* If chip has local feature control, map those regs too */ 108688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (fcregs != 0) { 108788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->kauai_fcr = devm_ioremap(priv->dev, fcregs, 4); 108888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (priv->kauai_fcr == NULL) { 108988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_err(priv->dev, "Failed to map ATA FCR register\n"); 109088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return -ENOMEM; 109188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 109288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 109388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 109488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Setup port data structure */ 109588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pata_macio_setup_ios(&priv->host->ports[0]->ioaddr, 109688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->tfregs, dma_regs); 109788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->host->ports[0]->private_data = priv; 109888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 109988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* hard-reset the controller */ 110088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pata_macio_reset_hw(priv, 0); 110188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pata_macio_apply_timings(priv->host->ports[0], 0); 110288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 110388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Enable bus master if necessary */ 110488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (priv->pdev && dma_regs) 110588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pci_set_master(priv->pdev); 110688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 110788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_info(priv->dev, "Activating pata-macio chipset %s, Apple bus ID %d\n", 110888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt macio_ata_names[priv->kind], priv->aapl_bus_id); 110988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 111088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Start it up */ 111188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->irq = irq; 1112c3b2889424c26f3b42962b6f39aabb4f1fd1b576Tejun Heo return ata_host_activate(priv->host, irq, ata_bmdma_interrupt, 0, 111388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt &pata_macio_sht); 111488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 111588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 111688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic int __devinit pata_macio_attach(struct macio_dev *mdev, 111788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt const struct of_device_id *match) 111888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 111988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct pata_macio_priv *priv; 112088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt resource_size_t tfregs, dmaregs = 0; 112188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt unsigned long irq; 112288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt int rc; 112388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 112488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Check for broken device-trees */ 112588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (macio_resource_count(mdev) == 0) { 112688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_err(&mdev->ofdev.dev, 112788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt "No addresses for controller\n"); 112888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return -ENXIO; 112988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 113088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 113188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Enable managed resources */ 113288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt macio_enable_devres(mdev); 113388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 113488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Allocate and init private data structure */ 113588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv = devm_kzalloc(&mdev->ofdev.dev, 113688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt sizeof(struct pata_macio_priv), GFP_KERNEL); 113788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (priv == NULL) { 113888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_err(&mdev->ofdev.dev, 113988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt "Failed to allocate private memory\n"); 114088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return -ENOMEM; 114188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 114261c7a080a5a061c976988fd4b844dfb468dda255Grant Likely priv->node = of_node_get(mdev->ofdev.dev.of_node); 114388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->mdev = mdev; 114488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->dev = &mdev->ofdev.dev; 114588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 114688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Request memory resource for taskfile registers */ 114788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (macio_request_resource(mdev, 0, "pata-macio")) { 114888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_err(&mdev->ofdev.dev, 114988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt "Cannot obtain taskfile resource\n"); 115088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return -EBUSY; 115188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 115288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt tfregs = macio_resource_start(mdev, 0); 115388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 115488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Request resources for DMA registers if any */ 115588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (macio_resource_count(mdev) >= 2) { 115688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (macio_request_resource(mdev, 1, "pata-macio-dma")) 115788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_err(&mdev->ofdev.dev, 115888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt "Cannot obtain DMA resource\n"); 115988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt else 116088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dmaregs = macio_resource_start(mdev, 1); 116188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 116288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 116388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* 116488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * Fixup missing IRQ for some old implementations with broken 116588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * device-trees. 116688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * 116788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * This is a bit bogus, it should be fixed in the device-tree itself, 116888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * via the existing macio fixups, based on the type of interrupt 116988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * controller in the machine. However, I have no test HW for this case, 117088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * and this trick works well enough on those old machines... 117188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 117288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (macio_irq_count(mdev) == 0) { 117388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_warn(&mdev->ofdev.dev, 117488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt "No interrupts for controller, using 13\n"); 117588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt irq = irq_create_mapping(NULL, 13); 117688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } else 117788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt irq = macio_irq(mdev, 0); 117888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 117988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Prevvent media bay callbacks until fully registered */ 118088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt lock_media_bay(priv->mdev->media_bay); 118188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 118288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Get register addresses and call common initialization */ 118388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt rc = pata_macio_common_init(priv, 118488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt tfregs, /* Taskfile regs */ 118588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dmaregs, /* DBDMA regs */ 118688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 0, /* Feature control */ 118788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt irq); 118888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt unlock_media_bay(priv->mdev->media_bay); 118988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 119088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return rc; 119188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 119288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 119388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic int __devexit pata_macio_detach(struct macio_dev *mdev) 119488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 119588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct ata_host *host = macio_get_drvdata(mdev); 119688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct pata_macio_priv *priv = host->private_data; 119788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 119888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt lock_media_bay(priv->mdev->media_bay); 119988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 120088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Make sure the mediabay callback doesn't try to access 120188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt * dead stuff 120288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt */ 120388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->host->private_data = NULL; 120488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 120588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ata_host_detach(host); 120688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 120788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt unlock_media_bay(priv->mdev->media_bay); 120888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 120988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return 0; 121088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 121188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 121288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#ifdef CONFIG_PM 121388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 121488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic int pata_macio_suspend(struct macio_dev *mdev, pm_message_t mesg) 121588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 121688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct ata_host *host = macio_get_drvdata(mdev); 121788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 121888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return pata_macio_do_suspend(host->private_data, mesg); 121988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 122088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 122188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic int pata_macio_resume(struct macio_dev *mdev) 122288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 122388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct ata_host *host = macio_get_drvdata(mdev); 122488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 122588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return pata_macio_do_resume(host->private_data); 122688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 122788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 122888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#endif /* CONFIG_PM */ 122988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 123088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#ifdef CONFIG_PMAC_MEDIABAY 123188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic void pata_macio_mb_event(struct macio_dev* mdev, int mb_state) 123288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 123388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct ata_host *host = macio_get_drvdata(mdev); 123488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct ata_port *ap; 123588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct ata_eh_info *ehi; 123688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct ata_device *dev; 123788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt unsigned long flags; 123888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 123988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (!host || !host->private_data) 124088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return; 124188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ap = host->ports[0]; 124288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt spin_lock_irqsave(ap->lock, flags); 124388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ehi = &ap->link.eh_info; 124488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (mb_state == MB_CD) { 124588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ata_ehi_push_desc(ehi, "mediabay plug"); 124688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ata_ehi_hotplugged(ehi); 124788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ata_port_freeze(ap); 124888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } else { 124988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ata_ehi_push_desc(ehi, "mediabay unplug"); 125088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ata_for_each_dev(dev, &ap->link, ALL) 125188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev->flags |= ATA_DFLAG_DETACH; 125288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ata_port_abort(ap); 125388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 125488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt spin_unlock_irqrestore(ap->lock, flags); 125588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 125688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 125788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#endif /* CONFIG_PMAC_MEDIABAY */ 125888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 125988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 126088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic int __devinit pata_macio_pci_attach(struct pci_dev *pdev, 126188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt const struct pci_device_id *id) 126288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 126388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct pata_macio_priv *priv; 126488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct device_node *np; 126588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt resource_size_t rbase; 126688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 126788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* We cannot use a MacIO controller without its OF device node */ 126888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt np = pci_device_to_OF_node(pdev); 126988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (np == NULL) { 127088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_err(&pdev->dev, 127188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt "Cannot find OF device node for controller\n"); 127288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return -ENODEV; 127388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 127488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 127588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Check that it can be enabled */ 127688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (pcim_enable_device(pdev)) { 127788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_err(&pdev->dev, 127888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt "Cannot enable controller PCI device\n"); 127988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return -ENXIO; 128088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 128188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 128288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Allocate and init private data structure */ 128388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv = devm_kzalloc(&pdev->dev, 128488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt sizeof(struct pata_macio_priv), GFP_KERNEL); 128588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (priv == NULL) { 128688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_err(&pdev->dev, 128788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt "Failed to allocate private memory\n"); 128888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return -ENOMEM; 128988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 129088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->node = of_node_get(np); 129188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->pdev = pdev; 129288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt priv->dev = &pdev->dev; 129388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 129488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Get MMIO regions */ 129588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (pci_request_regions(pdev, "pata-macio")) { 129688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt dev_err(&pdev->dev, 129788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt "Cannot obtain PCI resources\n"); 129888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return -EBUSY; 129988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 130088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 130188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt /* Get register addresses and call common initialization */ 130288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt rbase = pci_resource_start(pdev, 0); 130388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (pata_macio_common_init(priv, 130488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt rbase + 0x2000, /* Taskfile regs */ 130588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt rbase + 0x1000, /* DBDMA regs */ 130688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt rbase, /* Feature control */ 130788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pdev->irq)) 130888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return -ENXIO; 130988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 131088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return 0; 131188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 131288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 131388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic void __devexit pata_macio_pci_detach(struct pci_dev *pdev) 131488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 131588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct ata_host *host = dev_get_drvdata(&pdev->dev); 131688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 131788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt ata_host_detach(host); 131888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 131988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 132088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#ifdef CONFIG_PM 132188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 132288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic int pata_macio_pci_suspend(struct pci_dev *pdev, pm_message_t mesg) 132388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 132488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct ata_host *host = dev_get_drvdata(&pdev->dev); 132588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 132688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return pata_macio_do_suspend(host->private_data, mesg); 132788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 132888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 132988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic int pata_macio_pci_resume(struct pci_dev *pdev) 133088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 133188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt struct ata_host *host = dev_get_drvdata(&pdev->dev); 133288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 133388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return pata_macio_do_resume(host->private_data); 133488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 133588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 133688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#endif /* CONFIG_PM */ 133788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 133888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic struct of_device_id pata_macio_match[] = 133988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 134088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { 134188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .name = "IDE", 134288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt }, 134388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { 134488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .name = "ATA", 134588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt }, 134688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { 134788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .type = "ide", 134888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt }, 134988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { 135088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .type = "ata", 135188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt }, 135288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt {}, 135388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt}; 135488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 135588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic struct macio_driver pata_macio_driver = 135688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 1357c2cdf6aba0dfcfb54be646ab630c1bccd180e890Benjamin Herrenschmidt .driver = { 1358c2cdf6aba0dfcfb54be646ab630c1bccd180e890Benjamin Herrenschmidt .name = "pata-macio", 1359c2cdf6aba0dfcfb54be646ab630c1bccd180e890Benjamin Herrenschmidt .owner = THIS_MODULE, 1360c2cdf6aba0dfcfb54be646ab630c1bccd180e890Benjamin Herrenschmidt .of_match_table = pata_macio_match, 1361c2cdf6aba0dfcfb54be646ab630c1bccd180e890Benjamin Herrenschmidt }, 136288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .probe = pata_macio_attach, 136388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .remove = pata_macio_detach, 136488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#ifdef CONFIG_PM 136588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .suspend = pata_macio_suspend, 136688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .resume = pata_macio_resume, 136788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#endif 136888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#ifdef CONFIG_PMAC_MEDIABAY 136988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .mediabay_event = pata_macio_mb_event, 137088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#endif 137188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt}; 137288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 137388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic const struct pci_device_id pata_macio_pci_match[] = { 137488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 }, 137588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 }, 137688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 }, 137788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 }, 137888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 }, 137988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt {}, 138088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt}; 138188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 138288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic struct pci_driver pata_macio_pci_driver = { 138388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .name = "pata-pci-macio", 138488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .id_table = pata_macio_pci_match, 138588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .probe = pata_macio_pci_attach, 138688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .remove = pata_macio_pci_detach, 138788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#ifdef CONFIG_PM 138888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .suspend = pata_macio_pci_suspend, 138988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .resume = pata_macio_pci_resume, 139088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt#endif 139188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .driver = { 139288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt .owner = THIS_MODULE, 139388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt }, 139488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt}; 139588358ab08944da726e948d216977ad499dfc15c6Benjamin HerrenschmidtMODULE_DEVICE_TABLE(pci, pata_macio_pci_match); 139688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 139788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 139888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic int __init pata_macio_init(void) 139988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 140088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt int rc; 140188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 140288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (!machine_is(powermac)) 140388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return -ENODEV; 140488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 140588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt rc = pci_register_driver(&pata_macio_pci_driver); 140688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (rc) 140788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return rc; 140888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt rc = macio_register_driver(&pata_macio_driver); 140988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt if (rc) { 141088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pci_unregister_driver(&pata_macio_pci_driver); 141188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return rc; 141288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt } 141388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt return 0; 141488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 141588358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 141688358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtstatic void __exit pata_macio_exit(void) 141788358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt{ 141888358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt macio_unregister_driver(&pata_macio_driver); 141988358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt pci_unregister_driver(&pata_macio_pci_driver); 142088358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt} 142188358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 142288358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtmodule_init(pata_macio_init); 142388358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidtmodule_exit(pata_macio_exit); 142488358ab08944da726e948d216977ad499dfc15c6Benjamin Herrenschmidt 142588358ab08944da726e948d216977ad499dfc15c6Benjamin HerrenschmidtMODULE_AUTHOR("Benjamin Herrenschmidt"); 142688358ab08944da726e948d216977ad499dfc15c6Benjamin HerrenschmidtMODULE_DESCRIPTION("Apple MacIO PATA driver"); 142788358ab08944da726e948d216977ad499dfc15c6Benjamin HerrenschmidtMODULE_LICENSE("GPL"); 142888358ab08944da726e948d216977ad499dfc15c6Benjamin HerrenschmidtMODULE_VERSION(DRV_VERSION); 1429