1a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/* 2a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * Support for IDE interfaces on Celleb platform 3a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 4a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * (C) Copyright 2006 TOSHIBA CORPORATION 5a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 6a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * This code is based on drivers/ata/ata_piix.c: 7a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * Copyright 2003-2005 Red Hat Inc 8a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * Copyright 2003-2005 Jeff Garzik 9a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer 10a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 11ab77163008c596aad9624ceab190d840c0143fa8Alan Cox * Copyright (C) 2003 Red Hat Inc 12a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 13a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * and drivers/ata/ahci.c: 14a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * Copyright 2004-2005 Red Hat, Inc. 15a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 16a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * and drivers/ata/libata-core.c: 17a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * Copyright 2003-2004 Red Hat, Inc. All rights reserved. 18a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * Copyright 2003-2004 Jeff Garzik 19a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 20a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * This program is free software; you can redistribute it and/or modify 21a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * it under the terms of the GNU General Public License as published by 22a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * the Free Software Foundation; either version 2 of the License, or 23a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * (at your option) any later version. 24a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 25a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * This program is distributed in the hope that it will be useful, 26a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * but WITHOUT ANY WARRANTY; without even the implied warranty of 27a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 28a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * GNU General Public License for more details. 29a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 30a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * You should have received a copy of the GNU General Public License along 31a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * with this program; if not, write to the Free Software Foundation, Inc., 32a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 33a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 34a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 35a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#include <linux/kernel.h> 36a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#include <linux/module.h> 37a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#include <linux/pci.h> 38a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#include <linux/init.h> 39a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#include <linux/blkdev.h> 40a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#include <linux/delay.h> 41a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#include <linux/device.h> 42a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#include <scsi/scsi_host.h> 43a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#include <linux/libata.h> 44a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 45a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define DRV_NAME "pata_scc" 462a3103ce4357a09c2289405f969acec0edf4398fJeff Garzik#define DRV_VERSION "0.3" 47a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 48a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4 49a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 50a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/* PCI BARs */ 51a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_CTRL_BAR 0 52a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_BMID_BAR 1 53a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 54a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/* offset of CTRL registers */ 55a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_CTL_PIOSHT 0x000 56a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_CTL_PIOCT 0x004 57a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_CTL_MDMACT 0x008 58a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_CTL_MCRCST 0x00C 59a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_CTL_SDMACT 0x010 60a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_CTL_SCRCST 0x014 61a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_CTL_UDENVT 0x018 62a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_CTL_TDVHSEL 0x020 63a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_CTL_MODEREG 0x024 64a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_CTL_ECMODE 0xF00 65a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_CTL_MAEA0 0xF50 66a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_CTL_MAEC0 0xF54 67a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_CTL_CCKCTRL 0xFF0 68a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 69a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/* offset of BMID registers */ 70a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_DMA_CMD 0x000 71a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_DMA_STATUS 0x004 72a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_DMA_TABLE_OFS 0x008 73a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_DMA_INTMASK 0x010 74a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_DMA_INTST 0x014 75a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_DMA_PTERADD 0x018 76a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_REG_CMD_ADDR 0x020 77a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_REG_DATA 0x000 78a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_REG_ERR 0x004 79a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_REG_FEATURE 0x004 80a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_REG_NSECT 0x008 81a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_REG_LBAL 0x00C 82a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_REG_LBAM 0x010 83a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_REG_LBAH 0x014 84a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_REG_DEVICE 0x018 85a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_REG_STATUS 0x01C 86a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_REG_CMD 0x01C 87a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define SCC_REG_ALTSTATUS 0x020 88a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 89a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/* register value */ 90a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define TDVHSEL_MASTER 0x00000001 91a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define TDVHSEL_SLAVE 0x00000004 92a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 93a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define MODE_JCUSFEN 0x00000080 94a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 95a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define ECMODE_VALUE 0x01 96a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 97a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define CCKCTRL_ATARESET 0x00040000 98a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define CCKCTRL_BUFCNT 0x00020000 99a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define CCKCTRL_CRST 0x00010000 100a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define CCKCTRL_OCLKEN 0x00000100 101a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define CCKCTRL_ATACLKOEN 0x00000002 102a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define CCKCTRL_LCLKEN 0x00000001 103a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 104a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define QCHCD_IOS_SS 0x00000001 105a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 106a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define QCHSD_STPDIAG 0x00020000 107a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 108a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define INTMASK_MSK 0xD1000012 109a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define INTSTS_SERROR 0x80000000 110a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define INTSTS_PRERR 0x40000000 111a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define INTSTS_RERR 0x10000000 112a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define INTSTS_ICERR 0x01000000 113a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define INTSTS_BMSINT 0x00000010 114a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define INTSTS_BMHE 0x00000008 115a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define INTSTS_IOIRQS 0x00000004 116a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define INTSTS_INTRQ 0x00000002 117a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#define INTSTS_ACTEINT 0x00000001 118a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 119a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 120a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/* PIO transfer mode table */ 121a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/* JCHST */ 122a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic const unsigned long JCHSTtbl[2][7] = { 123a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */ 124a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */ 125a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi}; 126a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 127a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/* JCHHT */ 128a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic const unsigned long JCHHTtbl[2][7] = { 129a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */ 130a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */ 131a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi}; 132a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 133a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/* JCHCT */ 134a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic const unsigned long JCHCTtbl[2][7] = { 135a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */ 136a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */ 137a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi}; 138a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 139a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/* DMA transfer mode table */ 140a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/* JCHDCTM/JCHDCTS */ 141a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic const unsigned long JCHDCTxtbl[2][7] = { 142a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */ 143a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */ 144a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi}; 145a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 146a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/* JCSTWTM/JCSTWTS */ 147a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic const unsigned long JCSTWTxtbl[2][7] = { 148a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */ 149a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */ 150a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi}; 151a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 152a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/* JCTSS */ 153a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic const unsigned long JCTSStbl[2][7] = { 154a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */ 155a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */ 156a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi}; 157a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 158a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/* JCENVT */ 159a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic const unsigned long JCENVTtbl[2][7] = { 160a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */ 161a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */ 162a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi}; 163a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 164a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/* JCACTSELS/JCACTSELM */ 165a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic const unsigned long JCACTSELtbl[2][7] = { 166a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */ 167a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */ 168a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi}; 169a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 170a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic const struct pci_device_id scc_pci_tbl[] = { 171af4d6e257dc36646bb62adececdd10ad83323788Peter Huewe { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0}, 172a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi { } /* terminate list */ 173a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi}; 174a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 175a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 176a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * scc_set_piomode - Initialize host controller PATA PIO timings 177a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @ap: Port whose timings we are configuring 178a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @adev: um 179a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 180a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * Set PIO mode for device. 181a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 182a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * LOCKING: 183a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * None (inherited from caller). 184a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 185a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 186a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic void scc_set_piomode (struct ata_port *ap, struct ata_device *adev) 187a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 188a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi unsigned int pio = adev->pio_mode - XFER_PIO_0; 189a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR]; 190a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL; 191a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *piosht_port = ctrl_base + SCC_CTL_PIOSHT; 192a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *pioct_port = ctrl_base + SCC_CTL_PIOCT; 193a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi unsigned long reg; 194a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi int offset; 195a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 196a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi reg = in_be32(cckctrl_port); 197a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (reg & CCKCTRL_ATACLKOEN) 198a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi offset = 1; /* 133MHz */ 199a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi else 200a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi offset = 0; /* 100MHz */ 201a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 202a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio]; 203a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(piosht_port, reg); 204a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi reg = JCHCTtbl[offset][pio]; 205a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(pioct_port, reg); 206a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 207a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 208a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 209a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * scc_set_dmamode - Initialize host controller PATA DMA timings 210a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @ap: Port whose timings we are configuring 211a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @adev: um 212a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 213a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * Set UDMA mode for device. 214a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 215a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * LOCKING: 216a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * None (inherited from caller). 217a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 218a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 219a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic void scc_set_dmamode (struct ata_port *ap, struct ata_device *adev) 220a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 221a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi unsigned int udma = adev->dma_mode; 222a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi unsigned int is_slave = (adev->devno != 0); 223a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi u8 speed = udma; 224a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR]; 225a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL; 226a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *mdmact_port = ctrl_base + SCC_CTL_MDMACT; 227a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *mcrcst_port = ctrl_base + SCC_CTL_MCRCST; 228a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *sdmact_port = ctrl_base + SCC_CTL_SDMACT; 229a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *scrcst_port = ctrl_base + SCC_CTL_SCRCST; 230a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *udenvt_port = ctrl_base + SCC_CTL_UDENVT; 231a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *tdvhsel_port = ctrl_base + SCC_CTL_TDVHSEL; 232a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi int offset, idx; 233a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 234a84471fe269c38ea3725345c43ad64e5f489bea2Jeff Garzik if (in_be32(cckctrl_port) & CCKCTRL_ATACLKOEN) 235a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi offset = 1; /* 133MHz */ 236a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi else 237a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi offset = 0; /* 100MHz */ 238a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 239a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (speed >= XFER_UDMA_0) 240a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi idx = speed - XFER_UDMA_0; 241a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi else 242a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return; 243a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 244a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (is_slave) { 245a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(sdmact_port, JCHDCTxtbl[offset][idx]); 246a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(scrcst_port, JCSTWTxtbl[offset][idx]); 247a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(tdvhsel_port, 248a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi (in_be32(tdvhsel_port) & ~TDVHSEL_SLAVE) | (JCACTSELtbl[offset][idx] << 2)); 249a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } else { 250a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(mdmact_port, JCHDCTxtbl[offset][idx]); 251a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(mcrcst_port, JCSTWTxtbl[offset][idx]); 252a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(tdvhsel_port, 253a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi (in_be32(tdvhsel_port) & ~TDVHSEL_MASTER) | JCACTSELtbl[offset][idx]); 254a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 255a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(udenvt_port, 256a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]); 257a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 258a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 259dcd0344775c1c0bf8ff3b9541863beea5088a7c9Akira Iguchiunsigned long scc_mode_filter(struct ata_device *adev, unsigned long mask) 260dcd0344775c1c0bf8ff3b9541863beea5088a7c9Akira Iguchi{ 261dcd0344775c1c0bf8ff3b9541863beea5088a7c9Akira Iguchi /* errata A308 workaround: limit ATAPI UDMA mode to UDMA4 */ 262dcd0344775c1c0bf8ff3b9541863beea5088a7c9Akira Iguchi if (adev->class == ATA_DEV_ATAPI && 263dcd0344775c1c0bf8ff3b9541863beea5088a7c9Akira Iguchi (mask & (0xE0 << ATA_SHIFT_UDMA))) { 264dcd0344775c1c0bf8ff3b9541863beea5088a7c9Akira Iguchi printk(KERN_INFO "%s: limit ATAPI UDMA to UDMA4\n", DRV_NAME); 265dcd0344775c1c0bf8ff3b9541863beea5088a7c9Akira Iguchi mask &= ~(0xE0 << ATA_SHIFT_UDMA); 266dcd0344775c1c0bf8ff3b9541863beea5088a7c9Akira Iguchi } 267c7087652e1890a3feef35b30ee1d4be68e1932cdTejun Heo return mask; 268dcd0344775c1c0bf8ff3b9541863beea5088a7c9Akira Iguchi} 269dcd0344775c1c0bf8ff3b9541863beea5088a7c9Akira Iguchi 270a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 271a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * scc_tf_load - send taskfile registers to host controller 272a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @ap: Port to which output is sent 273a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @tf: ATA taskfile register set 274a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 2759363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_tf_load(). 276a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 277a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 278a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic void scc_tf_load (struct ata_port *ap, const struct ata_taskfile *tf) 279a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 280a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi struct ata_ioports *ioaddr = &ap->ioaddr; 281a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; 282a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 283a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (tf->ctl != ap->last_ctl) { 284a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->ctl_addr, tf->ctl); 285a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi ap->last_ctl = tf->ctl; 286a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi ata_wait_idle(ap); 287a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 288a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 289a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { 290a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->feature_addr, tf->hob_feature); 291a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->nsect_addr, tf->hob_nsect); 292a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->lbal_addr, tf->hob_lbal); 293a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->lbam_addr, tf->hob_lbam); 294a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->lbah_addr, tf->hob_lbah); 295a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", 296a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->hob_feature, 297a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->hob_nsect, 298a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->hob_lbal, 299a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->hob_lbam, 300a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->hob_lbah); 301a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 302a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 303a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (is_addr) { 304a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->feature_addr, tf->feature); 305a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->nsect_addr, tf->nsect); 306a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->lbal_addr, tf->lbal); 307a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->lbam_addr, tf->lbam); 308a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->lbah_addr, tf->lbah); 309a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", 310a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->feature, 311a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->nsect, 312a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->lbal, 313a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->lbam, 314a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->lbah); 315a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 316a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 317a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (tf->flags & ATA_TFLAG_DEVICE) { 318a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->device_addr, tf->device); 319a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi VPRINTK("device 0x%X\n", tf->device); 320a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 321a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 322a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi ata_wait_idle(ap); 323a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 324a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 325a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 326a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * scc_check_status - Read device status reg & clear interrupt 327a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @ap: port where the device is 328a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 329a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * Note: Original code is ata_check_status(). 330a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 331a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 332a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic u8 scc_check_status (struct ata_port *ap) 333a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 334a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return in_be32(ap->ioaddr.status_addr); 335a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 336a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 337a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 338a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * scc_tf_read - input device's ATA taskfile shadow registers 339a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @ap: Port from which input is read 340a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @tf: ATA taskfile register set for storing input 341a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 3429363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_tf_read(). 343a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 344a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 345a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic void scc_tf_read (struct ata_port *ap, struct ata_taskfile *tf) 346a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 347a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi struct ata_ioports *ioaddr = &ap->ioaddr; 348a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 349a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->command = scc_check_status(ap); 350a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->feature = in_be32(ioaddr->error_addr); 351a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->nsect = in_be32(ioaddr->nsect_addr); 352a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->lbal = in_be32(ioaddr->lbal_addr); 353a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->lbam = in_be32(ioaddr->lbam_addr); 354a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->lbah = in_be32(ioaddr->lbah_addr); 355a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->device = in_be32(ioaddr->device_addr); 356a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 357a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (tf->flags & ATA_TFLAG_LBA48) { 358a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->ctl_addr, tf->ctl | ATA_HOB); 359a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->hob_feature = in_be32(ioaddr->error_addr); 360a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->hob_nsect = in_be32(ioaddr->nsect_addr); 361a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->hob_lbal = in_be32(ioaddr->lbal_addr); 362a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->hob_lbam = in_be32(ioaddr->lbam_addr); 363a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tf->hob_lbah = in_be32(ioaddr->lbah_addr); 364fe36cb53cfd82f3c0796a0826e1c9caf198c8f97Petr Vandrovec out_be32(ioaddr->ctl_addr, tf->ctl); 365fe36cb53cfd82f3c0796a0826e1c9caf198c8f97Petr Vandrovec ap->last_ctl = tf->ctl; 366a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 367a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 368a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 369a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 370a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * scc_exec_command - issue ATA command to host controller 371a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @ap: port to which command is being issued 372a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @tf: ATA taskfile register set 373a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 3749363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_exec_command(). 375a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 376a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 377a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic void scc_exec_command (struct ata_port *ap, 378a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi const struct ata_taskfile *tf) 379a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 380878d4fedab4e5eba59877b771622856495a92df4Tejun Heo DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); 381a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 382a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ap->ioaddr.command_addr, tf->command); 3839363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo ata_sff_pause(ap); 384a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 385a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 386a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 387a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * scc_check_altstatus - Read device alternate status reg 388a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @ap: port where the device is 389a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 390a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 391a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic u8 scc_check_altstatus (struct ata_port *ap) 392a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 393a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return in_be32(ap->ioaddr.altstatus_addr); 394a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 395a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 396a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 3979363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * scc_dev_select - Select device 0/1 on ATA bus 398a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @ap: ATA channel to manipulate 399a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @device: ATA device (numbered from zero) to select 400a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 4019363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_dev_select(). 402a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 403a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 4049363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heostatic void scc_dev_select (struct ata_port *ap, unsigned int device) 405a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 406a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi u8 tmp; 407a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 408a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (device == 0) 409a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tmp = ATA_DEVICE_OBS; 410a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi else 411a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi tmp = ATA_DEVICE_OBS | ATA_DEV1; 412a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 413a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ap->ioaddr.device_addr, tmp); 4149363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo ata_sff_pause(ap); 415a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 416a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 417a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 41841dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov * scc_set_devctl - Write device control reg 41941dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov * @ap: port where the device is 42041dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov * @ctl: value to write 42141dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov */ 42241dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov 42341dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyovstatic void scc_set_devctl(struct ata_port *ap, u8 ctl) 42441dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov{ 42541dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov out_be32(ap->ioaddr.ctl_addr, ctl); 42641dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov} 42741dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov 42841dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov/** 429a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * scc_bmdma_setup - Set up PCI IDE BMDMA transaction 430a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @qc: Info associated with this ATA transaction. 431a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 432a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * Note: Original code is ata_bmdma_setup(). 433a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 434a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 435a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic void scc_bmdma_setup (struct ata_queued_cmd *qc) 436a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 437a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi struct ata_port *ap = qc->ap; 438a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 439a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi u8 dmactl; 440a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *mmio = ap->ioaddr.bmdma_addr; 441a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 442a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi /* load PRD table addr */ 443f60d70113fa04e32aee2dedbf304a48469c9c45cTejun Heo out_be32(mmio + SCC_DMA_TABLE_OFS, ap->bmdma_prd_dma); 444a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 445a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi /* specify data direction, triple-check start bit is clear */ 446a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi dmactl = in_be32(mmio + SCC_DMA_CMD); 447a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); 448a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (!rw) 449a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi dmactl |= ATA_DMA_WR; 450a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(mmio + SCC_DMA_CMD, dmactl); 451a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 452a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi /* issue r/w command */ 4535682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo ap->ops->sff_exec_command(ap, &qc->tf); 454a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 455a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 456a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 457a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * scc_bmdma_start - Start a PCI IDE BMDMA transaction 458a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @qc: Info associated with this ATA transaction. 459a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 460a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * Note: Original code is ata_bmdma_start(). 461a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 462a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 463a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic void scc_bmdma_start (struct ata_queued_cmd *qc) 464a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 465a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi struct ata_port *ap = qc->ap; 466a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi u8 dmactl; 467a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *mmio = ap->ioaddr.bmdma_addr; 468a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 469a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi /* start host DMA transaction */ 470a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi dmactl = in_be32(mmio + SCC_DMA_CMD); 471a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(mmio + SCC_DMA_CMD, dmactl | ATA_DMA_START); 472a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 473a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 474a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 475a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * scc_devchk - PATA device presence detection 476a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @ap: ATA channel to examine 477a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @device: Device to examine (starting at zero) 478a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 479a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * Note: Original code is ata_devchk(). 480a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 481a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 482a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic unsigned int scc_devchk (struct ata_port *ap, 483a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi unsigned int device) 484a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 485a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi struct ata_ioports *ioaddr = &ap->ioaddr; 486a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi u8 nsect, lbal; 487a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 4885682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo ap->ops->sff_dev_select(ap, device); 489a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 490a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->nsect_addr, 0x55); 491a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->lbal_addr, 0xaa); 492a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 493a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->nsect_addr, 0xaa); 494a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->lbal_addr, 0x55); 495a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 496a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->nsect_addr, 0x55); 497a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->lbal_addr, 0xaa); 498a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 499a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi nsect = in_be32(ioaddr->nsect_addr); 500a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi lbal = in_be32(ioaddr->lbal_addr); 501a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 502a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if ((nsect == 0x55) && (lbal == 0xaa)) 503a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return 1; /* we found a device */ 504a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 505a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return 0; /* nothing found */ 506a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 507a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 508a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 509705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo * scc_wait_after_reset - wait for devices to become ready after reset 510a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 511705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo * Note: Original code is ata_sff_wait_after_reset 512a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 513a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 514fe6005b81e142c36f066b81ca85f80022c4ac979Sergei Shtylyovstatic int scc_wait_after_reset(struct ata_link *link, unsigned int devmask, 515fe6005b81e142c36f066b81ca85f80022c4ac979Sergei Shtylyov unsigned long deadline) 516a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 517705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo struct ata_port *ap = link->ap; 518a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi struct ata_ioports *ioaddr = &ap->ioaddr; 519a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi unsigned int dev0 = devmask & (1 << 0); 520a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi unsigned int dev1 = devmask & (1 << 1); 521705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo int rc, ret = 0; 522705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo 523705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo /* Spec mandates ">= 2ms" before checking status. We wait 524705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo * 150ms, because that was the magic delay used for ATAPI 525705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo * devices in Hale Landis's ATADRVR, for the period of time 526705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo * between when the ATA command register is written, and then 527705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo * status is checked. Because waiting for "a while" before 528705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo * checking status is fine, post SRST, we perform this magic 529705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo * delay here as well. 530705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo * 531705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo * Old drivers/ide uses the 2mS rule and then waits for ready. 532705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo */ 53397750cebb3000a9cc08f8ce8dc8c7143be7d7201Tejun Heo ata_msleep(ap, 150); 534a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 535705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo /* always check readiness of the master device */ 536705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo rc = ata_sff_wait_ready(link, deadline); 537705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo /* -ENODEV means the odd clown forgot the D7 pulldown resistor 538705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo * and TF status is 0xff, bail out on it too. 539a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 540705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo if (rc) 541705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo return rc; 542a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 543705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo /* if device 1 was found in ata_devchk, wait for register 544705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo * access briefly, then wait for BSY to clear. 545a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 546705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo if (dev1) { 547705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo int i; 548a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 5495682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo ap->ops->sff_dev_select(ap, 1); 550705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo 551705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo /* Wait for register access. Some ATAPI devices fail 552705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo * to set nsect/lbal after reset, so don't waste too 553705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo * much time on it. We're gonna wait for !BSY anyway. 554705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo */ 555705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo for (i = 0; i < 2; i++) { 556705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo u8 nsect, lbal; 557705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo 558705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo nsect = in_be32(ioaddr->nsect_addr); 559705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo lbal = in_be32(ioaddr->lbal_addr); 560705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo if ((nsect == 1) && (lbal == 1)) 561705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo break; 56297750cebb3000a9cc08f8ce8dc8c7143be7d7201Tejun Heo ata_msleep(ap, 50); /* give drive a breather */ 563705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo } 564705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo 565705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo rc = ata_sff_wait_ready(link, deadline); 566705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo if (rc) { 567705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo if (rc != -ENODEV) 568705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo return rc; 569705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo ret = rc; 570705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo } 5717e068376c5128db2a342fa659a6dfa1488adc135Tony Breeds } 572a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 573a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi /* is all this really necessary? */ 5745682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo ap->ops->sff_dev_select(ap, 0); 575a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (dev1) 5765682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo ap->ops->sff_dev_select(ap, 1); 577a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (dev0) 5785682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo ap->ops->sff_dev_select(ap, 0); 5797e068376c5128db2a342fa659a6dfa1488adc135Tony Breeds 580705e76beb90b97421e1f61e857c4246799781bb5Tejun Heo return ret; 581a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 582a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 583a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 584a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * scc_bus_softreset - PATA device software reset 585a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 586a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * Note: Original code is ata_bus_softreset(). 587a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 588a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 5897e068376c5128db2a342fa659a6dfa1488adc135Tony Breedsstatic unsigned int scc_bus_softreset(struct ata_port *ap, unsigned int devmask, 5907e068376c5128db2a342fa659a6dfa1488adc135Tony Breeds unsigned long deadline) 591a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 592a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi struct ata_ioports *ioaddr = &ap->ioaddr; 593a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 594878d4fedab4e5eba59877b771622856495a92df4Tejun Heo DPRINTK("ata%u: bus reset via SRST\n", ap->print_id); 595a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 596a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi /* software reset. causes dev0 to be selected */ 597a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->ctl_addr, ap->ctl); 598a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi udelay(20); 599a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->ctl_addr, ap->ctl | ATA_SRST); 600a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi udelay(20); 601a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ioaddr->ctl_addr, ap->ctl); 602a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 603e50e3ce5e70e36e6069a8cc8292df76058fa9e23Stephen Rothwell scc_wait_after_reset(&ap->link, devmask, deadline); 604a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 605a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return 0; 606a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 607a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 608a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 6099363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * scc_softreset - reset host port via ATA SRST 610a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @ap: port to reset 611a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @classes: resulting classes of attached devices 6127e068376c5128db2a342fa659a6dfa1488adc135Tony Breeds * @deadline: deadline jiffies for the operation 613a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 6149363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_softreset(). 615a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 616a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 6179363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heostatic int scc_softreset(struct ata_link *link, unsigned int *classes, 6189363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo unsigned long deadline) 619a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 620b90fe23bd51c6b1c298159591c833bdd24f55002Satyam Sharma struct ata_port *ap = link->ap; 621a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; 622a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi unsigned int devmask = 0, err_mask; 623a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi u8 err; 624a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 625a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi DPRINTK("ENTER\n"); 626a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 627a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi /* determine if device 0/1 are present */ 628a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (scc_devchk(ap, 0)) 629a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi devmask |= (1 << 0); 630a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (slave_possible && scc_devchk(ap, 1)) 631a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi devmask |= (1 << 1); 632a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 633a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi /* select device 0 again */ 6345682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo ap->ops->sff_dev_select(ap, 0); 635a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 636a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi /* issue bus reset */ 637a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi DPRINTK("about to softreset, devmask=%x\n", devmask); 6387e068376c5128db2a342fa659a6dfa1488adc135Tony Breeds err_mask = scc_bus_softreset(ap, devmask, deadline); 639a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (err_mask) { 640a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches ata_port_err(ap, "SRST failed (err_mask=0x%x)\n", err_mask); 641a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return -EIO; 642a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 643a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 644a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi /* determine by signature whether we have ATA or ATAPI devices */ 6459363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo classes[0] = ata_sff_dev_classify(&ap->link.device[0], 6463f19859ee95a38c066a0420eb8a30c76ecd67a42Tejun Heo devmask & (1 << 0), &err); 647a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (slave_possible && err != 0x81) 6489363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo classes[1] = ata_sff_dev_classify(&ap->link.device[1], 6493f19859ee95a38c066a0420eb8a30c76ecd67a42Tejun Heo devmask & (1 << 1), &err); 650a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 651a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]); 652a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return 0; 653a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 654a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 655a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 656a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * scc_bmdma_stop - Stop PCI IDE BMDMA transfer 657a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @qc: Command we are ending DMA for 658a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 659a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 660a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic void scc_bmdma_stop (struct ata_queued_cmd *qc) 661a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 662a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi struct ata_port *ap = qc->ap; 663a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR]; 664a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *bmid_base = ap->host->iomap[SCC_BMID_BAR]; 665a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi u32 reg; 666a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 667a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi while (1) { 668a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi reg = in_be32(bmid_base + SCC_DMA_INTST); 669a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 670a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (reg & INTSTS_SERROR) { 671a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi printk(KERN_WARNING "%s: SERROR\n", DRV_NAME); 672a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(bmid_base + SCC_DMA_INTST, INTSTS_SERROR|INTSTS_BMSINT); 673a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(bmid_base + SCC_DMA_CMD, 674a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START); 675a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi continue; 676a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 677a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 678a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (reg & INTSTS_PRERR) { 679a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi u32 maea0, maec0; 680a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi maea0 = in_be32(ctrl_base + SCC_CTL_MAEA0); 681a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi maec0 = in_be32(ctrl_base + SCC_CTL_MAEC0); 682a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", DRV_NAME, maea0, maec0); 683a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(bmid_base + SCC_DMA_INTST, INTSTS_PRERR|INTSTS_BMSINT); 684a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(bmid_base + SCC_DMA_CMD, 685a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START); 686a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi continue; 687a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 688a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 689a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (reg & INTSTS_RERR) { 690a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi printk(KERN_WARNING "%s: Response Error\n", DRV_NAME); 691a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(bmid_base + SCC_DMA_INTST, INTSTS_RERR|INTSTS_BMSINT); 692a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(bmid_base + SCC_DMA_CMD, 693a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START); 694a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi continue; 695a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 696a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 697a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (reg & INTSTS_ICERR) { 698a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(bmid_base + SCC_DMA_CMD, 699a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START); 700a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi printk(KERN_WARNING "%s: Illegal Configuration\n", DRV_NAME); 701a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ICERR|INTSTS_BMSINT); 702a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi continue; 703a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 704a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 705a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (reg & INTSTS_BMSINT) { 706a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi unsigned int classes; 707341c2c958ec7bdd9f54733a8b0b432fe76842a82Tejun Heo unsigned long deadline = ata_deadline(jiffies, ATA_TMOUT_BOOT); 708a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi printk(KERN_WARNING "%s: Internal Bus Error\n", DRV_NAME); 709a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMSINT); 710a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi /* TBD: SW reset */ 7119363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo scc_softreset(&ap->link, &classes, deadline); 712a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi continue; 713a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 714a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 715a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (reg & INTSTS_BMHE) { 716a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMHE); 717a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi continue; 718a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 719a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 720a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (reg & INTSTS_ACTEINT) { 721a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ACTEINT); 722a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi continue; 723a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 724a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 725a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (reg & INTSTS_IOIRQS) { 726a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(bmid_base + SCC_DMA_INTST, INTSTS_IOIRQS); 727a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi continue; 728a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 729a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi break; 730a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 731a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 732a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi /* clear start/stop bit */ 733a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(bmid_base + SCC_DMA_CMD, 734a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START); 735a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 736a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 737a57c1bade5a0ee5cd8b74502db9cbebb7f5780b2Alan Cox ata_sff_dma_pause(ap); /* dummy read */ 738a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 739a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 740a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 741a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * scc_bmdma_status - Read PCI IDE BMDMA status 742a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @ap: Port associated with this ATA transaction. 743a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 744a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 745a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic u8 scc_bmdma_status (struct ata_port *ap) 746a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 747a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *mmio = ap->ioaddr.bmdma_addr; 748fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi u8 host_stat = in_be32(mmio + SCC_DMA_STATUS); 749fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi u32 int_status = in_be32(mmio + SCC_DMA_INTST); 750b90fe23bd51c6b1c298159591c833bdd24f55002Satyam Sharma struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 751fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi static int retry = 0; 752fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi 753fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi /* return if IOS_SS is cleared */ 754fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi if (!(in_be32(mmio + SCC_DMA_CMD) & ATA_DMA_START)) 755fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi return host_stat; 756fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi 757fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi /* errata A252,A308 workaround: Step4 */ 758a57c1bade5a0ee5cd8b74502db9cbebb7f5780b2Alan Cox if ((scc_check_altstatus(ap) & ATA_ERR) 759a57c1bade5a0ee5cd8b74502db9cbebb7f5780b2Alan Cox && (int_status & INTSTS_INTRQ)) 760fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi return (host_stat | ATA_DMA_INTR); 761fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi 762fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi /* errata A308 workaround Step5 */ 763fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi if (int_status & INTSTS_IOIRQS) { 764fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi host_stat |= ATA_DMA_INTR; 765fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi 766fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi /* We don't check ATAPI DMA because it is limited to UDMA4 */ 767fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi if ((qc->tf.protocol == ATA_PROT_DMA && 768fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi qc->dev->xfer_mode > XFER_UDMA_4)) { 769fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi if (!(int_status & INTSTS_ACTEINT)) { 770dcd0344775c1c0bf8ff3b9541863beea5088a7c9Akira Iguchi printk(KERN_WARNING "ata%u: operation failed (transfer data loss)\n", 771dcd0344775c1c0bf8ff3b9541863beea5088a7c9Akira Iguchi ap->print_id); 772fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi host_stat |= ATA_DMA_ERR; 773fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi if (retry++) 774dcd0344775c1c0bf8ff3b9541863beea5088a7c9Akira Iguchi ap->udma_mask &= ~(1 << qc->dev->xfer_mode); 775fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi } else 776fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi retry = 0; 777fae57d348379861f115fe1e586a1e0902b71ae9eAkira Iguchi } 778a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 779a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 780a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return host_stat; 781a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 782a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 783a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 784a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * scc_data_xfer - Transfer data by PIO 78555dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo * @dev: device for this I/O 786a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @buf: data buffer 787a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @buflen: buffer length 78855dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo * @rw: read/write 789a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 7909363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_data_xfer(). 791a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 792a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 79355dba3120fbcbea6800f9a18503d25f73212a347Tejun Heostatic unsigned int scc_data_xfer (struct ata_device *dev, unsigned char *buf, 79455dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo unsigned int buflen, int rw) 795a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 79655dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo struct ata_port *ap = dev->link->ap; 797a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi unsigned int words = buflen >> 1; 798a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi unsigned int i; 799826cd156de6cea1e4982f32238077215cfa4ae63Al Viro __le16 *buf16 = (__le16 *) buf; 800a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *mmio = ap->ioaddr.data_addr; 801a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 802a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi /* Transfer multiple of 2 bytes */ 80355dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo if (rw == READ) 804a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi for (i = 0; i < words; i++) 805826cd156de6cea1e4982f32238077215cfa4ae63Al Viro buf16[i] = cpu_to_le16(in_be32(mmio)); 80655dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo else 80755dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo for (i = 0; i < words; i++) 808826cd156de6cea1e4982f32238077215cfa4ae63Al Viro out_be32(mmio, le16_to_cpu(buf16[i])); 809a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 810a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi /* Transfer trailing 1 byte, if any. */ 811a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (unlikely(buflen & 0x01)) { 812826cd156de6cea1e4982f32238077215cfa4ae63Al Viro __le16 align_buf[1] = { 0 }; 813a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi unsigned char *trailing_buf = buf + buflen - 1; 814a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 81555dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo if (rw == READ) { 816826cd156de6cea1e4982f32238077215cfa4ae63Al Viro align_buf[0] = cpu_to_le16(in_be32(mmio)); 817a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi memcpy(trailing_buf, align_buf, 1); 81855dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo } else { 81955dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo memcpy(align_buf, trailing_buf, 1); 820826cd156de6cea1e4982f32238077215cfa4ae63Al Viro out_be32(mmio, le16_to_cpu(align_buf[0])); 821a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 82255dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo words++; 823a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 82455dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo 82555dba3120fbcbea6800f9a18503d25f73212a347Tejun Heo return words << 1; 826a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 827a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 828a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 8299363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * scc_postreset - standard postreset callback 830a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @ap: the target ata_port 831a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @classes: classes of attached devices 832a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 8339363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * Note: Original code is ata_sff_postreset(). 834a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 835a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 8369363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heostatic void scc_postreset(struct ata_link *link, unsigned int *classes) 837a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 838b90fe23bd51c6b1c298159591c833bdd24f55002Satyam Sharma struct ata_port *ap = link->ap; 839b90fe23bd51c6b1c298159591c833bdd24f55002Satyam Sharma 840a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi DPRINTK("ENTER\n"); 841a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 842a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi /* is double-select really necessary? */ 843a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (classes[0] != ATA_DEV_NONE) 8445682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo ap->ops->sff_dev_select(ap, 1); 845a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (classes[1] != ATA_DEV_NONE) 8465682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo ap->ops->sff_dev_select(ap, 0); 847a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 848a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi /* bail out if no device is present */ 849a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) { 850a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi DPRINTK("EXIT, no device\n"); 851a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return; 852a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 853a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 854a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi /* set up device control */ 855ec86c81dfcc52e313920621b1d1e92343a842afeSergei Shtylyov out_be32(ap->ioaddr.ctl_addr, ap->ctl); 856a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 857a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi DPRINTK("EXIT\n"); 858a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 859a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 860a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 8619363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo * scc_irq_clear - Clear PCI IDE BMDMA interrupt. 862a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @ap: Port associated with this ATA transaction. 863a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 86437f65b8bc262a5ae4c8e58be92fe3032f0aaaf04Tejun Heo * Note: Original code is ata_bmdma_irq_clear(). 865a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 866a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 8679363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heostatic void scc_irq_clear (struct ata_port *ap) 868a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 869a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *mmio = ap->ioaddr.bmdma_addr; 870a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 871a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (!mmio) 872a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return; 873a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 874a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(mmio + SCC_DMA_STATUS, in_be32(mmio + SCC_DMA_STATUS)); 875a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 876a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 877a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 878a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * scc_port_start - Set port up for dma. 879a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @ap: Port to initialize 880a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 881c7087652e1890a3feef35b30ee1d4be68e1932cdTejun Heo * Allocate space for PRD table using ata_bmdma_port_start(). 882a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * Set PRD table address for PTERADD. (PRD Transfer End Read) 883a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 884a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 885a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic int scc_port_start (struct ata_port *ap) 886a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 887a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *mmio = ap->ioaddr.bmdma_addr; 888a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi int rc; 889a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 890c7087652e1890a3feef35b30ee1d4be68e1932cdTejun Heo rc = ata_bmdma_port_start(ap); 891a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (rc) 892a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return rc; 893a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 894f60d70113fa04e32aee2dedbf304a48469c9c45cTejun Heo out_be32(mmio + SCC_DMA_PTERADD, ap->bmdma_prd_dma); 895a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return 0; 896a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 897a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 898a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 899a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * scc_port_stop - Undo scc_port_start() 900a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @ap: Port to shut down 901a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 902a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * Reset PTERADD. 903a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 904a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 905a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic void scc_port_stop (struct ata_port *ap) 906a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 907a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *mmio = ap->ioaddr.bmdma_addr; 908a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 909a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(mmio + SCC_DMA_PTERADD, 0); 910a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 911a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 912a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic struct scsi_host_template scc_sht = { 91368d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BMDMA_SHT(DRV_NAME), 914a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi}; 915a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 916c1796d9850aaa97ee7492d090499b5508971514bTejun Heostatic struct ata_port_operations scc_pata_ops = { 917029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &ata_bmdma_port_ops, 918029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo 919a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi .set_piomode = scc_set_piomode, 920a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi .set_dmamode = scc_set_dmamode, 921dcd0344775c1c0bf8ff3b9541863beea5088a7c9Akira Iguchi .mode_filter = scc_mode_filter, 922a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 9235682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_tf_load = scc_tf_load, 9245682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_tf_read = scc_tf_read, 9255682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_exec_command = scc_exec_command, 9265682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_check_status = scc_check_status, 9275682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_check_altstatus = scc_check_altstatus, 9285682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_dev_select = scc_dev_select, 92941dec29bcb05eb8ec396f70ce791c6e3e4ce4712Sergei Shtylyov .sff_set_devctl = scc_set_devctl, 930a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 931a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi .bmdma_setup = scc_bmdma_setup, 932a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi .bmdma_start = scc_bmdma_start, 933a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi .bmdma_stop = scc_bmdma_stop, 934a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi .bmdma_status = scc_bmdma_status, 9355682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_data_xfer = scc_data_xfer, 936a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 9379f8abf8248f8b90532a201845654d467f4388474Bartlomiej Zolnierkiewicz .cable_detect = ata_cable_80wire, 9389363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo .softreset = scc_softreset, 9399363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo .postreset = scc_postreset, 940a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 9415682ed33aae05d10a25c95633ef9d9c062825888Tejun Heo .sff_irq_clear = scc_irq_clear, 942a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 943a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi .port_start = scc_port_start, 944a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi .port_stop = scc_port_stop, 945a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi}; 946a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 947a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic struct ata_port_info scc_port_info[] = { 948a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi { 9499cbe056f6c467e7395d5aec39aceec47812eb98eSergei Shtylyov .flags = ATA_FLAG_SLAVE_POSS, 95014bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .pio_mask = ATA_PIO4, 95114bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø /* No MWDMA */ 952a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi .udma_mask = ATA_UDMA6, 953a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi .port_ops = &scc_pata_ops, 954a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi }, 955a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi}; 956a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 957a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 958a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * scc_reset_controller - initialize SCC PATA controller. 959a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 960a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 9615d728824efeda61d304153bfcf1378a3c18b7d70Tejun Heostatic int scc_reset_controller(struct ata_host *host) 962a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 9635d728824efeda61d304153bfcf1378a3c18b7d70Tejun Heo void __iomem *ctrl_base = host->iomap[SCC_CTRL_BAR]; 9645d728824efeda61d304153bfcf1378a3c18b7d70Tejun Heo void __iomem *bmid_base = host->iomap[SCC_BMID_BAR]; 965a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL; 966a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *mode_port = ctrl_base + SCC_CTL_MODEREG; 967a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *ecmode_port = ctrl_base + SCC_CTL_ECMODE; 968a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *intmask_port = bmid_base + SCC_DMA_INTMASK; 969a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi void __iomem *dmastatus_port = bmid_base + SCC_DMA_STATUS; 970a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi u32 reg = 0; 971a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 972a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(cckctrl_port, reg); 973a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi reg |= CCKCTRL_ATACLKOEN; 974a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(cckctrl_port, reg); 975a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN; 976a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(cckctrl_port, reg); 977a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi reg |= CCKCTRL_CRST; 978a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(cckctrl_port, reg); 979a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 980a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi for (;;) { 981a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi reg = in_be32(cckctrl_port); 982a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (reg & CCKCTRL_CRST) 983a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi break; 984a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi udelay(5000); 985a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 986a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 987a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi reg |= CCKCTRL_ATARESET; 988a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(cckctrl_port, reg); 989a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(ecmode_port, ECMODE_VALUE); 990a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(mode_port, MODE_JCUSFEN); 991a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi out_be32(intmask_port, INTMASK_MSK); 992a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 993a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (in_be32(dmastatus_port) & QCHSD_STPDIAG) { 994a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi printk(KERN_WARNING "%s: failed to detect 80c cable. (PDIAG# is high)\n", DRV_NAME); 995a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return -EIO; 996a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi } 997a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 998a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return 0; 999a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 1000a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 1001a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 1002a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * scc_setup_ports - initialize ioaddr with SCC PATA port offsets. 1003a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @ioaddr: IO address structure to be initialized 1004a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @base: base address of BMID region 1005a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 1006a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 1007a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic void scc_setup_ports (struct ata_ioports *ioaddr, void __iomem *base) 1008a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 1009a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi ioaddr->cmd_addr = base + SCC_REG_CMD_ADDR; 1010a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi ioaddr->altstatus_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS; 1011a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi ioaddr->ctl_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS; 1012a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi ioaddr->bmdma_addr = base; 1013a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi ioaddr->data_addr = ioaddr->cmd_addr + SCC_REG_DATA; 1014a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi ioaddr->error_addr = ioaddr->cmd_addr + SCC_REG_ERR; 1015a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi ioaddr->feature_addr = ioaddr->cmd_addr + SCC_REG_FEATURE; 1016a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi ioaddr->nsect_addr = ioaddr->cmd_addr + SCC_REG_NSECT; 1017a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi ioaddr->lbal_addr = ioaddr->cmd_addr + SCC_REG_LBAL; 1018a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi ioaddr->lbam_addr = ioaddr->cmd_addr + SCC_REG_LBAM; 1019a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi ioaddr->lbah_addr = ioaddr->cmd_addr + SCC_REG_LBAH; 1020a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi ioaddr->device_addr = ioaddr->cmd_addr + SCC_REG_DEVICE; 1021a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi ioaddr->status_addr = ioaddr->cmd_addr + SCC_REG_STATUS; 1022a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi ioaddr->command_addr = ioaddr->cmd_addr + SCC_REG_CMD; 1023a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 1024a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 10255d728824efeda61d304153bfcf1378a3c18b7d70Tejun Heostatic int scc_host_init(struct ata_host *host) 1026a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 10275d728824efeda61d304153bfcf1378a3c18b7d70Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 1028a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi int rc; 1029a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 10305d728824efeda61d304153bfcf1378a3c18b7d70Tejun Heo rc = scc_reset_controller(host); 1031a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (rc) 1032a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return rc; 1033a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 1034a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 1035a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (rc) 1036a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return rc; 1037a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 1038a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (rc) 1039a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return rc; 1040a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 10415d728824efeda61d304153bfcf1378a3c18b7d70Tejun Heo scc_setup_ports(&host->ports[0]->ioaddr, host->iomap[SCC_BMID_BAR]); 1042a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 1043a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi pci_set_master(pdev); 1044a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 1045a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return 0; 1046a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 1047a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 1048a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi/** 1049a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * scc_init_one - Register SCC PATA device with kernel services 1050a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @pdev: PCI device to register 1051a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * @ent: Entry in scc_pci_tbl matching with @pdev 1052a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 1053a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * LOCKING: 1054a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * Inherited from PCI layer (may sleep). 1055a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * 1056a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * RETURNS: 1057a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi * Zero on success, or -ERRNO value. 1058a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi */ 1059a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 1060a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic int scc_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 1061a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 1062a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi unsigned int board_idx = (unsigned int) ent->driver_data; 10635d728824efeda61d304153bfcf1378a3c18b7d70Tejun Heo const struct ata_port_info *ppi[] = { &scc_port_info[board_idx], NULL }; 10640397bad5b413226b8f55f599b185ab506d13b078Alexey Dobriyan struct ata_host *host; 1065a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi int rc; 1066a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 106706296a1e684bcd40b9a28d5d8030809e4295528bJoe Perches ata_print_version_once(&pdev->dev, DRV_VERSION); 1068a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 10690397bad5b413226b8f55f599b185ab506d13b078Alexey Dobriyan host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1); 10705d728824efeda61d304153bfcf1378a3c18b7d70Tejun Heo if (!host) 10715d728824efeda61d304153bfcf1378a3c18b7d70Tejun Heo return -ENOMEM; 10725d728824efeda61d304153bfcf1378a3c18b7d70Tejun Heo 1073a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi rc = pcim_enable_device(pdev); 1074a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (rc) 1075a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return rc; 1076a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 1077a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi rc = pcim_iomap_regions(pdev, (1 << SCC_CTRL_BAR) | (1 << SCC_BMID_BAR), DRV_NAME); 1078a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (rc == -EBUSY) 1079a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi pcim_pin_device(pdev); 1080a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (rc) 1081a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return rc; 10825d728824efeda61d304153bfcf1378a3c18b7d70Tejun Heo host->iomap = pcim_iomap_table(pdev); 1083a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 1084cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo ata_port_pbar_desc(host->ports[0], SCC_CTRL_BAR, -1, "ctrl"); 1085cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo ata_port_pbar_desc(host->ports[0], SCC_BMID_BAR, -1, "bmid"); 1086cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 10875d728824efeda61d304153bfcf1378a3c18b7d70Tejun Heo rc = scc_host_init(host); 1088a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (rc) 1089a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return rc; 1090a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 1091c3b2889424c26f3b42962b6f39aabb4f1fd1b576Tejun Heo return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, 10929363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo IRQF_SHARED, &scc_sht); 1093a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 1094a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 1095a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic struct pci_driver scc_pci_driver = { 1096a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi .name = DRV_NAME, 1097a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi .id_table = scc_pci_tbl, 1098a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi .probe = scc_init_one, 1099a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi .remove = ata_pci_remove_one, 1100a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#ifdef CONFIG_PM 1101a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi .suspend = ata_pci_device_suspend, 1102a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi .resume = ata_pci_device_resume, 1103a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi#endif 1104a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi}; 1105a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 1106a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic int __init scc_init (void) 1107a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 1108a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi int rc; 1109a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 1110a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi DPRINTK("pci_register_driver\n"); 1111a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi rc = pci_register_driver(&scc_pci_driver); 1112a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi if (rc) 1113a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return rc; 1114a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 1115a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi DPRINTK("done\n"); 1116a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi return 0; 1117a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 1118a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 1119a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchistatic void __exit scc_exit (void) 1120a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi{ 1121a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi pci_unregister_driver(&scc_pci_driver); 1122a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi} 1123a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 1124a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchimodule_init(scc_init); 1125a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchimodule_exit(scc_exit); 1126a619f981b477035027dd27dfbee6148b4cd4a83cAkira Iguchi 1127a619f981b477035027dd27dfbee6148b4cd4a83cAkira IguchiMODULE_AUTHOR("Toshiba corp"); 1128a619f981b477035027dd27dfbee6148b4cd4a83cAkira IguchiMODULE_DESCRIPTION("SCSI low-level driver for Toshiba SCC PATA controller"); 1129a619f981b477035027dd27dfbee6148b4cd4a83cAkira IguchiMODULE_LICENSE("GPL"); 1130a619f981b477035027dd27dfbee6148b4cd4a83cAkira IguchiMODULE_DEVICE_TABLE(pci, scc_pci_tbl); 1131a619f981b477035027dd27dfbee6148b4cd4a83cAkira IguchiMODULE_VERSION(DRV_VERSION); 1132