pata_serverworks.c revision 029cfd6b74fc5c517865fad78cf4a3ea8d9b664a
1/* 2 * pata_serverworks.c - Serverworks PATA for new ATA layer 3 * (C) 2005 Red Hat Inc 4 * Alan Cox <alan@redhat.com> 5 * 6 * based upon 7 * 8 * serverworks.c 9 * 10 * Copyright (C) 1998-2000 Michel Aubry 11 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz 12 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 13 * Portions copyright (c) 2001 Sun Microsystems 14 * 15 * 16 * RCC/ServerWorks IDE driver for Linux 17 * 18 * OSB4: `Open South Bridge' IDE Interface (fn 1) 19 * supports UDMA mode 2 (33 MB/s) 20 * 21 * CSB5: `Champion South Bridge' IDE Interface (fn 1) 22 * all revisions support UDMA mode 4 (66 MB/s) 23 * revision A2.0 and up support UDMA mode 5 (100 MB/s) 24 * 25 * *** The CSB5 does not provide ANY register *** 26 * *** to detect 80-conductor cable presence. *** 27 * 28 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel) 29 * 30 * Documentation: 31 * Available under NDA only. Errata info very hard to get. 32 */ 33 34#include <linux/kernel.h> 35#include <linux/module.h> 36#include <linux/pci.h> 37#include <linux/init.h> 38#include <linux/blkdev.h> 39#include <linux/delay.h> 40#include <scsi/scsi_host.h> 41#include <linux/libata.h> 42 43#define DRV_NAME "pata_serverworks" 44#define DRV_VERSION "0.4.3" 45 46#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */ 47#define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */ 48 49/* Seagate Barracuda ATA IV Family drives in UDMA mode 5 50 * can overrun their FIFOs when used with the CSB5 */ 51 52static const char *csb_bad_ata100[] = { 53 "ST320011A", 54 "ST340016A", 55 "ST360021A", 56 "ST380021A", 57 NULL 58}; 59 60/** 61 * dell_cable - Dell serverworks cable detection 62 * @ap: ATA port to do cable detect 63 * 64 * Dell hide the 40/80 pin select for their interfaces in the top two 65 * bits of the subsystem ID. 66 */ 67 68static int dell_cable(struct ata_port *ap) { 69 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 70 71 if (pdev->subsystem_device & (1 << (ap->port_no + 14))) 72 return ATA_CBL_PATA80; 73 return ATA_CBL_PATA40; 74} 75 76/** 77 * sun_cable - Sun Cobalt 'Alpine' cable detection 78 * @ap: ATA port to do cable select 79 * 80 * Cobalt CSB5 IDE hides the 40/80pin in the top two bits of the 81 * subsystem ID the same as dell. We could use one function but we may 82 * need to extend the Dell one in future 83 */ 84 85static int sun_cable(struct ata_port *ap) { 86 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 87 88 if (pdev->subsystem_device & (1 << (ap->port_no + 14))) 89 return ATA_CBL_PATA80; 90 return ATA_CBL_PATA40; 91} 92 93/** 94 * osb4_cable - OSB4 cable detect 95 * @ap: ATA port to check 96 * 97 * The OSB4 isn't UDMA66 capable so this is easy 98 */ 99 100static int osb4_cable(struct ata_port *ap) { 101 return ATA_CBL_PATA40; 102} 103 104/** 105 * csb_cable - CSB5/6 cable detect 106 * @ap: ATA port to check 107 * 108 * Serverworks default arrangement is to use the drive side detection 109 * only. 110 */ 111 112static int csb_cable(struct ata_port *ap) { 113 return ATA_CBL_PATA_UNK; 114} 115 116struct sv_cable_table { 117 int device; 118 int subvendor; 119 int (*cable_detect)(struct ata_port *ap); 120}; 121 122/* 123 * Note that we don't copy the old serverworks code because the old 124 * code contains obvious mistakes 125 */ 126 127static struct sv_cable_table cable_detect[] = { 128 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_DELL, dell_cable }, 129 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_VENDOR_ID_DELL, dell_cable }, 130 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_SUN, sun_cable }, 131 { PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, osb4_cable }, 132 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, csb_cable }, 133 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, csb_cable }, 134 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, csb_cable }, 135 { PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, csb_cable }, 136 { } 137}; 138 139/** 140 * serverworks_cable_detect - cable detection 141 * @ap: ATA port 142 * @deadline: deadline jiffies for the operation 143 * 144 * Perform cable detection according to the device and subvendor 145 * identifications 146 */ 147 148static int serverworks_cable_detect(struct ata_port *ap) 149{ 150 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 151 struct sv_cable_table *cb = cable_detect; 152 153 while(cb->device) { 154 if (cb->device == pdev->device && 155 (cb->subvendor == pdev->subsystem_vendor || 156 cb->subvendor == PCI_ANY_ID)) { 157 return cb->cable_detect(ap); 158 } 159 cb++; 160 } 161 162 BUG(); 163 return -1; /* kill compiler warning */ 164} 165 166/** 167 * serverworks_is_csb - Check for CSB or OSB 168 * @pdev: PCI device to check 169 * 170 * Returns true if the device being checked is known to be a CSB 171 * series device. 172 */ 173 174static u8 serverworks_is_csb(struct pci_dev *pdev) 175{ 176 switch (pdev->device) { 177 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: 178 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: 179 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: 180 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE: 181 return 1; 182 default: 183 break; 184 } 185 return 0; 186} 187 188/** 189 * serverworks_osb4_filter - mode selection filter 190 * @adev: ATA device 191 * @mask: Mask of proposed modes 192 * 193 * Filter the offered modes for the device to apply controller 194 * specific rules. OSB4 requires no UDMA for disks due to a FIFO 195 * bug we hit. 196 */ 197 198static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask) 199{ 200 if (adev->class == ATA_DEV_ATA) 201 mask &= ~ATA_MASK_UDMA; 202 return ata_pci_default_filter(adev, mask); 203} 204 205 206/** 207 * serverworks_csb_filter - mode selection filter 208 * @adev: ATA device 209 * @mask: Mask of proposed modes 210 * 211 * Check the blacklist and disable UDMA5 if matched 212 */ 213 214static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask) 215{ 216 const char *p; 217 char model_num[ATA_ID_PROD_LEN + 1]; 218 int i; 219 220 /* Disk, UDMA */ 221 if (adev->class != ATA_DEV_ATA) 222 return ata_pci_default_filter(adev, mask); 223 224 /* Actually do need to check */ 225 ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num)); 226 227 for (i = 0; (p = csb_bad_ata100[i]) != NULL; i++) { 228 if (!strcmp(p, model_num)) 229 mask &= ~(0xE0 << ATA_SHIFT_UDMA); 230 } 231 return ata_pci_default_filter(adev, mask); 232} 233 234/** 235 * serverworks_set_piomode - set initial PIO mode data 236 * @ap: ATA interface 237 * @adev: ATA device 238 * 239 * Program the OSB4/CSB5 timing registers for PIO. The PIO register 240 * load is done as a simple lookup. 241 */ 242static void serverworks_set_piomode(struct ata_port *ap, struct ata_device *adev) 243{ 244 static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; 245 int offset = 1 + 2 * ap->port_no - adev->devno; 246 int devbits = (2 * ap->port_no + adev->devno) * 4; 247 u16 csb5_pio; 248 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 249 int pio = adev->pio_mode - XFER_PIO_0; 250 251 pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]); 252 253 /* The OSB4 just requires the timing but the CSB series want the 254 mode number as well */ 255 if (serverworks_is_csb(pdev)) { 256 pci_read_config_word(pdev, 0x4A, &csb5_pio); 257 csb5_pio &= ~(0x0F << devbits); 258 pci_write_config_byte(pdev, 0x4A, csb5_pio | (pio << devbits)); 259 } 260} 261 262/** 263 * serverworks_set_dmamode - set initial DMA mode data 264 * @ap: ATA interface 265 * @adev: ATA device 266 * 267 * Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5 268 * chipset. The MWDMA mode values are pulled from a lookup table 269 * while the chipset uses mode number for UDMA. 270 */ 271 272static void serverworks_set_dmamode(struct ata_port *ap, struct ata_device *adev) 273{ 274 static const u8 dma_mode[] = { 0x77, 0x21, 0x20 }; 275 int offset = 1 + 2 * ap->port_no - adev->devno; 276 int devbits = 2 * ap->port_no + adev->devno; 277 u8 ultra; 278 u8 ultra_cfg; 279 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 280 281 pci_read_config_byte(pdev, 0x54, &ultra_cfg); 282 pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra); 283 ultra &= ~(0x0F << (adev->devno * 4)); 284 285 if (adev->dma_mode >= XFER_UDMA_0) { 286 pci_write_config_byte(pdev, 0x44 + offset, 0x20); 287 288 ultra |= (adev->dma_mode - XFER_UDMA_0) 289 << (adev->devno * 4); 290 ultra_cfg |= (1 << devbits); 291 } else { 292 pci_write_config_byte(pdev, 0x44 + offset, 293 dma_mode[adev->dma_mode - XFER_MW_DMA_0]); 294 ultra_cfg &= ~(1 << devbits); 295 } 296 pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra); 297 pci_write_config_byte(pdev, 0x54, ultra_cfg); 298} 299 300static struct scsi_host_template serverworks_sht = { 301 ATA_BMDMA_SHT(DRV_NAME), 302}; 303 304static struct ata_port_operations serverworks_osb4_port_ops = { 305 .inherits = &ata_bmdma_port_ops, 306 .cable_detect = serverworks_cable_detect, 307 .mode_filter = serverworks_osb4_filter, 308 .set_piomode = serverworks_set_piomode, 309 .set_dmamode = serverworks_set_dmamode, 310}; 311 312static struct ata_port_operations serverworks_csb_port_ops = { 313 .inherits = &serverworks_osb4_port_ops, 314 .mode_filter = serverworks_csb_filter, 315}; 316 317static int serverworks_fixup_osb4(struct pci_dev *pdev) 318{ 319 u32 reg; 320 struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, 321 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL); 322 if (isa_dev) { 323 pci_read_config_dword(isa_dev, 0x64, ®); 324 reg &= ~0x00002000; /* disable 600ns interrupt mask */ 325 if (!(reg & 0x00004000)) 326 printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n"); 327 reg |= 0x00004000; /* enable UDMA/33 support */ 328 pci_write_config_dword(isa_dev, 0x64, reg); 329 pci_dev_put(isa_dev); 330 return 0; 331 } 332 printk(KERN_WARNING "ata_serverworks: Unable to find bridge.\n"); 333 return -ENODEV; 334} 335 336static int serverworks_fixup_csb(struct pci_dev *pdev) 337{ 338 u8 btr; 339 340 /* Third Channel Test */ 341 if (!(PCI_FUNC(pdev->devfn) & 1)) { 342 struct pci_dev * findev = NULL; 343 u32 reg4c = 0; 344 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, 345 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL); 346 if (findev) { 347 pci_read_config_dword(findev, 0x4C, ®4c); 348 reg4c &= ~0x000007FF; 349 reg4c |= 0x00000040; 350 reg4c |= 0x00000020; 351 pci_write_config_dword(findev, 0x4C, reg4c); 352 pci_dev_put(findev); 353 } 354 } else { 355 struct pci_dev * findev = NULL; 356 u8 reg41 = 0; 357 358 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, 359 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL); 360 if (findev) { 361 pci_read_config_byte(findev, 0x41, ®41); 362 reg41 &= ~0x40; 363 pci_write_config_byte(findev, 0x41, reg41); 364 pci_dev_put(findev); 365 } 366 } 367 /* setup the UDMA Control register 368 * 369 * 1. clear bit 6 to enable DMA 370 * 2. enable DMA modes with bits 0-1 371 * 00 : legacy 372 * 01 : udma2 373 * 10 : udma2/udma4 374 * 11 : udma2/udma4/udma5 375 */ 376 pci_read_config_byte(pdev, 0x5A, &btr); 377 btr &= ~0x40; 378 if (!(PCI_FUNC(pdev->devfn) & 1)) 379 btr |= 0x2; 380 else 381 btr |= (pdev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2; 382 pci_write_config_byte(pdev, 0x5A, btr); 383 384 return btr; 385} 386 387static void serverworks_fixup_ht1000(struct pci_dev *pdev) 388{ 389 u8 btr; 390 /* Setup HT1000 SouthBridge Controller - Single Channel Only */ 391 pci_read_config_byte(pdev, 0x5A, &btr); 392 btr &= ~0x40; 393 btr |= 0x3; 394 pci_write_config_byte(pdev, 0x5A, btr); 395} 396 397 398static int serverworks_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 399{ 400 static const struct ata_port_info info[4] = { 401 { /* OSB4 */ 402 .sht = &serverworks_sht, 403 .flags = ATA_FLAG_SLAVE_POSS, 404 .pio_mask = 0x1f, 405 .mwdma_mask = 0x07, 406 .udma_mask = 0x07, 407 .port_ops = &serverworks_osb4_port_ops 408 }, { /* OSB4 no UDMA */ 409 .sht = &serverworks_sht, 410 .flags = ATA_FLAG_SLAVE_POSS, 411 .pio_mask = 0x1f, 412 .mwdma_mask = 0x07, 413 .udma_mask = 0x00, 414 .port_ops = &serverworks_osb4_port_ops 415 }, { /* CSB5 */ 416 .sht = &serverworks_sht, 417 .flags = ATA_FLAG_SLAVE_POSS, 418 .pio_mask = 0x1f, 419 .mwdma_mask = 0x07, 420 .udma_mask = ATA_UDMA4, 421 .port_ops = &serverworks_csb_port_ops 422 }, { /* CSB5 - later revisions*/ 423 .sht = &serverworks_sht, 424 .flags = ATA_FLAG_SLAVE_POSS, 425 .pio_mask = 0x1f, 426 .mwdma_mask = 0x07, 427 .udma_mask = ATA_UDMA5, 428 .port_ops = &serverworks_csb_port_ops 429 } 430 }; 431 const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL }; 432 int rc; 433 434 rc = pcim_enable_device(pdev); 435 if (rc) 436 return rc; 437 438 /* Force master latency timer to 64 PCI clocks */ 439 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40); 440 441 /* OSB4 : South Bridge and IDE */ 442 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { 443 /* Select non UDMA capable OSB4 if we can't do fixups */ 444 if ( serverworks_fixup_osb4(pdev) < 0) 445 ppi[0] = &info[1]; 446 } 447 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */ 448 else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) || 449 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || 450 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) { 451 452 /* If the returned btr is the newer revision then 453 select the right info block */ 454 if (serverworks_fixup_csb(pdev) == 3) 455 ppi[0] = &info[3]; 456 457 /* Is this the 3rd channel CSB6 IDE ? */ 458 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) 459 ppi[1] = &ata_dummy_port_info; 460 } 461 /* setup HT1000E */ 462 else if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) 463 serverworks_fixup_ht1000(pdev); 464 465 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) 466 ata_pci_clear_simplex(pdev); 467 468 return ata_pci_init_one(pdev, ppi); 469} 470 471#ifdef CONFIG_PM 472static int serverworks_reinit_one(struct pci_dev *pdev) 473{ 474 struct ata_host *host = dev_get_drvdata(&pdev->dev); 475 int rc; 476 477 rc = ata_pci_device_do_resume(pdev); 478 if (rc) 479 return rc; 480 481 /* Force master latency timer to 64 PCI clocks */ 482 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40); 483 484 switch (pdev->device) { 485 case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE: 486 serverworks_fixup_osb4(pdev); 487 break; 488 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: 489 ata_pci_clear_simplex(pdev); 490 /* fall through */ 491 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: 492 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: 493 serverworks_fixup_csb(pdev); 494 break; 495 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE: 496 serverworks_fixup_ht1000(pdev); 497 break; 498 } 499 500 ata_host_resume(host); 501 return 0; 502} 503#endif 504 505static const struct pci_device_id serverworks[] = { 506 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0}, 507 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2}, 508 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2}, 509 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2}, 510 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2}, 511 512 { }, 513}; 514 515static struct pci_driver serverworks_pci_driver = { 516 .name = DRV_NAME, 517 .id_table = serverworks, 518 .probe = serverworks_init_one, 519 .remove = ata_pci_remove_one, 520#ifdef CONFIG_PM 521 .suspend = ata_pci_device_suspend, 522 .resume = serverworks_reinit_one, 523#endif 524}; 525 526static int __init serverworks_init(void) 527{ 528 return pci_register_driver(&serverworks_pci_driver); 529} 530 531static void __exit serverworks_exit(void) 532{ 533 pci_unregister_driver(&serverworks_pci_driver); 534} 535 536MODULE_AUTHOR("Alan Cox"); 537MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6"); 538MODULE_LICENSE("GPL"); 539MODULE_DEVICE_TABLE(pci, serverworks); 540MODULE_VERSION(DRV_VERSION); 541 542module_init(serverworks_init); 543module_exit(serverworks_exit); 544