pdc_adma.c revision fc4712d12e332a46f200b9ba641855182df282c0
1/* 2 * pdc_adma.c - Pacific Digital Corporation ADMA 3 * 4 * Maintained by: Mark Lord <mlord@pobox.com> 5 * 6 * Copyright 2005 Mark Lord 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; see the file COPYING. If not, write to 20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 21 * 22 * 23 * libata documentation is available via 'make {ps|pdf}docs', 24 * as Documentation/DocBook/libata.* 25 * 26 * 27 * Supports ATA disks in single-packet ADMA mode. 28 * Uses PIO for everything else. 29 * 30 * TODO: Use ADMA transfers for ATAPI devices, when possible. 31 * This requires careful attention to a number of quirks of the chip. 32 * 33 */ 34 35#include <linux/kernel.h> 36#include <linux/module.h> 37#include <linux/pci.h> 38#include <linux/init.h> 39#include <linux/blkdev.h> 40#include <linux/delay.h> 41#include <linux/interrupt.h> 42#include <linux/device.h> 43#include <scsi/scsi_host.h> 44#include <linux/libata.h> 45 46#define DRV_NAME "pdc_adma" 47#define DRV_VERSION "1.0" 48 49/* macro to calculate base address for ATA regs */ 50#define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40)) 51 52/* macro to calculate base address for ADMA regs */ 53#define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20)) 54 55/* macro to obtain addresses from ata_port */ 56#define ADMA_PORT_REGS(ap) \ 57 ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no) 58 59enum { 60 ADMA_MMIO_BAR = 4, 61 62 ADMA_PORTS = 2, 63 ADMA_CPB_BYTES = 40, 64 ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16, 65 ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES, 66 67 ADMA_DMA_BOUNDARY = 0xffffffff, 68 69 /* global register offsets */ 70 ADMA_MODE_LOCK = 0x00c7, 71 72 /* per-channel register offsets */ 73 ADMA_CONTROL = 0x0000, /* ADMA control */ 74 ADMA_STATUS = 0x0002, /* ADMA status */ 75 ADMA_CPB_COUNT = 0x0004, /* CPB count */ 76 ADMA_CPB_CURRENT = 0x000c, /* current CPB address */ 77 ADMA_CPB_NEXT = 0x000c, /* next CPB address */ 78 ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */ 79 ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */ 80 ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */ 81 82 /* ADMA_CONTROL register bits */ 83 aNIEN = (1 << 8), /* irq mask: 1==masked */ 84 aGO = (1 << 7), /* packet trigger ("Go!") */ 85 aRSTADM = (1 << 5), /* ADMA logic reset */ 86 aPIOMD4 = 0x0003, /* PIO mode 4 */ 87 88 /* ADMA_STATUS register bits */ 89 aPSD = (1 << 6), 90 aUIRQ = (1 << 4), 91 aPERR = (1 << 0), 92 93 /* CPB bits */ 94 cDONE = (1 << 0), 95 cATERR = (1 << 3), 96 97 cVLD = (1 << 0), 98 cDAT = (1 << 2), 99 cIEN = (1 << 3), 100 101 /* PRD bits */ 102 pORD = (1 << 4), 103 pDIRO = (1 << 5), 104 pEND = (1 << 7), 105 106 /* ATA register flags */ 107 rIGN = (1 << 5), 108 rEND = (1 << 7), 109 110 /* ATA register addresses */ 111 ADMA_REGS_CONTROL = 0x0e, 112 ADMA_REGS_SECTOR_COUNT = 0x12, 113 ADMA_REGS_LBA_LOW = 0x13, 114 ADMA_REGS_LBA_MID = 0x14, 115 ADMA_REGS_LBA_HIGH = 0x15, 116 ADMA_REGS_DEVICE = 0x16, 117 ADMA_REGS_COMMAND = 0x17, 118 119 /* PCI device IDs */ 120 board_1841_idx = 0, /* ADMA 2-port controller */ 121}; 122 123typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t; 124 125struct adma_port_priv { 126 u8 *pkt; 127 dma_addr_t pkt_dma; 128 adma_state_t state; 129}; 130 131static int adma_ata_init_one(struct pci_dev *pdev, 132 const struct pci_device_id *ent); 133static int adma_port_start(struct ata_port *ap); 134static void adma_port_stop(struct ata_port *ap); 135static void adma_qc_prep(struct ata_queued_cmd *qc); 136static unsigned int adma_qc_issue(struct ata_queued_cmd *qc); 137static int adma_check_atapi_dma(struct ata_queued_cmd *qc); 138static void adma_freeze(struct ata_port *ap); 139static void adma_thaw(struct ata_port *ap); 140static int adma_prereset(struct ata_link *link, unsigned long deadline); 141 142static struct scsi_host_template adma_ata_sht = { 143 ATA_BASE_SHT(DRV_NAME), 144 .sg_tablesize = LIBATA_MAX_PRD, 145 .dma_boundary = ADMA_DMA_BOUNDARY, 146}; 147 148static struct ata_port_operations adma_ata_ops = { 149 .inherits = &ata_sff_port_ops, 150 151 .check_atapi_dma = adma_check_atapi_dma, 152 .qc_prep = adma_qc_prep, 153 .qc_issue = adma_qc_issue, 154 155 .freeze = adma_freeze, 156 .thaw = adma_thaw, 157 .prereset = adma_prereset, 158 159 .port_start = adma_port_start, 160 .port_stop = adma_port_stop, 161}; 162 163static struct ata_port_info adma_port_info[] = { 164 /* board_1841_idx */ 165 { 166 .flags = ATA_FLAG_SLAVE_POSS | 167 ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO | 168 ATA_FLAG_PIO_POLLING, 169 .pio_mask = 0x10, /* pio4 */ 170 .udma_mask = ATA_UDMA4, 171 .port_ops = &adma_ata_ops, 172 }, 173}; 174 175static const struct pci_device_id adma_ata_pci_tbl[] = { 176 { PCI_VDEVICE(PDC, 0x1841), board_1841_idx }, 177 178 { } /* terminate list */ 179}; 180 181static struct pci_driver adma_ata_pci_driver = { 182 .name = DRV_NAME, 183 .id_table = adma_ata_pci_tbl, 184 .probe = adma_ata_init_one, 185 .remove = ata_pci_remove_one, 186}; 187 188static int adma_check_atapi_dma(struct ata_queued_cmd *qc) 189{ 190 return 1; /* ATAPI DMA not yet supported */ 191} 192 193static void adma_reset_engine(struct ata_port *ap) 194{ 195 void __iomem *chan = ADMA_PORT_REGS(ap); 196 197 /* reset ADMA to idle state */ 198 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL); 199 udelay(2); 200 writew(aPIOMD4, chan + ADMA_CONTROL); 201 udelay(2); 202} 203 204static void adma_reinit_engine(struct ata_port *ap) 205{ 206 struct adma_port_priv *pp = ap->private_data; 207 void __iomem *chan = ADMA_PORT_REGS(ap); 208 209 /* mask/clear ATA interrupts */ 210 writeb(ATA_NIEN, ap->ioaddr.ctl_addr); 211 ata_check_status(ap); 212 213 /* reset the ADMA engine */ 214 adma_reset_engine(ap); 215 216 /* set in-FIFO threshold to 0x100 */ 217 writew(0x100, chan + ADMA_FIFO_IN); 218 219 /* set CPB pointer */ 220 writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT); 221 222 /* set out-FIFO threshold to 0x100 */ 223 writew(0x100, chan + ADMA_FIFO_OUT); 224 225 /* set CPB count */ 226 writew(1, chan + ADMA_CPB_COUNT); 227 228 /* read/discard ADMA status */ 229 readb(chan + ADMA_STATUS); 230} 231 232static inline void adma_enter_reg_mode(struct ata_port *ap) 233{ 234 void __iomem *chan = ADMA_PORT_REGS(ap); 235 236 writew(aPIOMD4, chan + ADMA_CONTROL); 237 readb(chan + ADMA_STATUS); /* flush */ 238} 239 240static void adma_freeze(struct ata_port *ap) 241{ 242 void __iomem *chan = ADMA_PORT_REGS(ap); 243 244 /* mask/clear ATA interrupts */ 245 writeb(ATA_NIEN, ap->ioaddr.ctl_addr); 246 ata_check_status(ap); 247 248 /* reset ADMA to idle state */ 249 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL); 250 udelay(2); 251 writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL); 252 udelay(2); 253} 254 255static void adma_thaw(struct ata_port *ap) 256{ 257 adma_reinit_engine(ap); 258} 259 260static int adma_prereset(struct ata_link *link, unsigned long deadline) 261{ 262 struct ata_port *ap = link->ap; 263 struct adma_port_priv *pp = ap->private_data; 264 265 if (pp->state != adma_state_idle) /* healthy paranoia */ 266 pp->state = adma_state_mmio; 267 adma_reinit_engine(ap); 268 269 return ata_std_prereset(link, deadline); 270} 271 272static int adma_fill_sg(struct ata_queued_cmd *qc) 273{ 274 struct scatterlist *sg; 275 struct ata_port *ap = qc->ap; 276 struct adma_port_priv *pp = ap->private_data; 277 u8 *buf = pp->pkt, *last_buf = NULL; 278 int i = (2 + buf[3]) * 8; 279 u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0); 280 unsigned int si; 281 282 for_each_sg(qc->sg, sg, qc->n_elem, si) { 283 u32 addr; 284 u32 len; 285 286 addr = (u32)sg_dma_address(sg); 287 *(__le32 *)(buf + i) = cpu_to_le32(addr); 288 i += 4; 289 290 len = sg_dma_len(sg) >> 3; 291 *(__le32 *)(buf + i) = cpu_to_le32(len); 292 i += 4; 293 294 last_buf = &buf[i]; 295 buf[i++] = pFLAGS; 296 buf[i++] = qc->dev->dma_mode & 0xf; 297 buf[i++] = 0; /* pPKLW */ 298 buf[i++] = 0; /* reserved */ 299 300 *(__le32 *)(buf + i) = 301 (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4); 302 i += 4; 303 304 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4, 305 (unsigned long)addr, len); 306 } 307 308 if (likely(last_buf)) 309 *last_buf |= pEND; 310 311 return i; 312} 313 314static void adma_qc_prep(struct ata_queued_cmd *qc) 315{ 316 struct adma_port_priv *pp = qc->ap->private_data; 317 u8 *buf = pp->pkt; 318 u32 pkt_dma = (u32)pp->pkt_dma; 319 int i = 0; 320 321 VPRINTK("ENTER\n"); 322 323 adma_enter_reg_mode(qc->ap); 324 if (qc->tf.protocol != ATA_PROT_DMA) { 325 ata_qc_prep(qc); 326 return; 327 } 328 329 buf[i++] = 0; /* Response flags */ 330 buf[i++] = 0; /* reserved */ 331 buf[i++] = cVLD | cDAT | cIEN; 332 i++; /* cLEN, gets filled in below */ 333 334 *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */ 335 i += 4; /* cNCPB */ 336 i += 4; /* cPRD, gets filled in below */ 337 338 buf[i++] = 0; /* reserved */ 339 buf[i++] = 0; /* reserved */ 340 buf[i++] = 0; /* reserved */ 341 buf[i++] = 0; /* reserved */ 342 343 /* ATA registers; must be a multiple of 4 */ 344 buf[i++] = qc->tf.device; 345 buf[i++] = ADMA_REGS_DEVICE; 346 if ((qc->tf.flags & ATA_TFLAG_LBA48)) { 347 buf[i++] = qc->tf.hob_nsect; 348 buf[i++] = ADMA_REGS_SECTOR_COUNT; 349 buf[i++] = qc->tf.hob_lbal; 350 buf[i++] = ADMA_REGS_LBA_LOW; 351 buf[i++] = qc->tf.hob_lbam; 352 buf[i++] = ADMA_REGS_LBA_MID; 353 buf[i++] = qc->tf.hob_lbah; 354 buf[i++] = ADMA_REGS_LBA_HIGH; 355 } 356 buf[i++] = qc->tf.nsect; 357 buf[i++] = ADMA_REGS_SECTOR_COUNT; 358 buf[i++] = qc->tf.lbal; 359 buf[i++] = ADMA_REGS_LBA_LOW; 360 buf[i++] = qc->tf.lbam; 361 buf[i++] = ADMA_REGS_LBA_MID; 362 buf[i++] = qc->tf.lbah; 363 buf[i++] = ADMA_REGS_LBA_HIGH; 364 buf[i++] = 0; 365 buf[i++] = ADMA_REGS_CONTROL; 366 buf[i++] = rIGN; 367 buf[i++] = 0; 368 buf[i++] = qc->tf.command; 369 buf[i++] = ADMA_REGS_COMMAND | rEND; 370 371 buf[3] = (i >> 3) - 2; /* cLEN */ 372 *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */ 373 374 i = adma_fill_sg(qc); 375 wmb(); /* flush PRDs and pkt to memory */ 376#if 0 377 /* dump out CPB + PRDs for debug */ 378 { 379 int j, len = 0; 380 static char obuf[2048]; 381 for (j = 0; j < i; ++j) { 382 len += sprintf(obuf+len, "%02x ", buf[j]); 383 if ((j & 7) == 7) { 384 printk("%s\n", obuf); 385 len = 0; 386 } 387 } 388 if (len) 389 printk("%s\n", obuf); 390 } 391#endif 392} 393 394static inline void adma_packet_start(struct ata_queued_cmd *qc) 395{ 396 struct ata_port *ap = qc->ap; 397 void __iomem *chan = ADMA_PORT_REGS(ap); 398 399 VPRINTK("ENTER, ap %p\n", ap); 400 401 /* fire up the ADMA engine */ 402 writew(aPIOMD4 | aGO, chan + ADMA_CONTROL); 403} 404 405static unsigned int adma_qc_issue(struct ata_queued_cmd *qc) 406{ 407 struct adma_port_priv *pp = qc->ap->private_data; 408 409 switch (qc->tf.protocol) { 410 case ATA_PROT_DMA: 411 pp->state = adma_state_pkt; 412 adma_packet_start(qc); 413 return 0; 414 415 case ATAPI_PROT_DMA: 416 BUG(); 417 break; 418 419 default: 420 break; 421 } 422 423 pp->state = adma_state_mmio; 424 return ata_qc_issue_prot(qc); 425} 426 427static inline unsigned int adma_intr_pkt(struct ata_host *host) 428{ 429 unsigned int handled = 0, port_no; 430 431 for (port_no = 0; port_no < host->n_ports; ++port_no) { 432 struct ata_port *ap = host->ports[port_no]; 433 struct adma_port_priv *pp; 434 struct ata_queued_cmd *qc; 435 void __iomem *chan = ADMA_PORT_REGS(ap); 436 u8 status = readb(chan + ADMA_STATUS); 437 438 if (status == 0) 439 continue; 440 handled = 1; 441 adma_enter_reg_mode(ap); 442 if (ap->flags & ATA_FLAG_DISABLED) 443 continue; 444 pp = ap->private_data; 445 if (!pp || pp->state != adma_state_pkt) 446 continue; 447 qc = ata_qc_from_tag(ap, ap->link.active_tag); 448 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { 449 if (status & aPERR) 450 qc->err_mask |= AC_ERR_HOST_BUS; 451 else if ((status & (aPSD | aUIRQ))) 452 qc->err_mask |= AC_ERR_OTHER; 453 454 if (pp->pkt[0] & cATERR) 455 qc->err_mask |= AC_ERR_DEV; 456 else if (pp->pkt[0] != cDONE) 457 qc->err_mask |= AC_ERR_OTHER; 458 459 if (!qc->err_mask) 460 ata_qc_complete(qc); 461 else { 462 struct ata_eh_info *ehi = &ap->link.eh_info; 463 ata_ehi_clear_desc(ehi); 464 ata_ehi_push_desc(ehi, 465 "ADMA-status 0x%02X", status); 466 ata_ehi_push_desc(ehi, 467 "pkt[0] 0x%02X", pp->pkt[0]); 468 469 if (qc->err_mask == AC_ERR_DEV) 470 ata_port_abort(ap); 471 else 472 ata_port_freeze(ap); 473 } 474 } 475 } 476 return handled; 477} 478 479static inline unsigned int adma_intr_mmio(struct ata_host *host) 480{ 481 unsigned int handled = 0, port_no; 482 483 for (port_no = 0; port_no < host->n_ports; ++port_no) { 484 struct ata_port *ap; 485 ap = host->ports[port_no]; 486 if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) { 487 struct ata_queued_cmd *qc; 488 struct adma_port_priv *pp = ap->private_data; 489 if (!pp || pp->state != adma_state_mmio) 490 continue; 491 qc = ata_qc_from_tag(ap, ap->link.active_tag); 492 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { 493 494 /* check main status, clearing INTRQ */ 495 u8 status = ata_check_status(ap); 496 if ((status & ATA_BUSY)) 497 continue; 498 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n", 499 ap->print_id, qc->tf.protocol, status); 500 501 /* complete taskfile transaction */ 502 pp->state = adma_state_idle; 503 qc->err_mask |= ac_err_mask(status); 504 if (!qc->err_mask) 505 ata_qc_complete(qc); 506 else { 507 struct ata_eh_info *ehi = 508 &ap->link.eh_info; 509 ata_ehi_clear_desc(ehi); 510 ata_ehi_push_desc(ehi, 511 "status 0x%02X", status); 512 513 if (qc->err_mask == AC_ERR_DEV) 514 ata_port_abort(ap); 515 else 516 ata_port_freeze(ap); 517 } 518 handled = 1; 519 } 520 } 521 } 522 return handled; 523} 524 525static irqreturn_t adma_intr(int irq, void *dev_instance) 526{ 527 struct ata_host *host = dev_instance; 528 unsigned int handled = 0; 529 530 VPRINTK("ENTER\n"); 531 532 spin_lock(&host->lock); 533 handled = adma_intr_pkt(host) | adma_intr_mmio(host); 534 spin_unlock(&host->lock); 535 536 VPRINTK("EXIT\n"); 537 538 return IRQ_RETVAL(handled); 539} 540 541static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base) 542{ 543 port->cmd_addr = 544 port->data_addr = base + 0x000; 545 port->error_addr = 546 port->feature_addr = base + 0x004; 547 port->nsect_addr = base + 0x008; 548 port->lbal_addr = base + 0x00c; 549 port->lbam_addr = base + 0x010; 550 port->lbah_addr = base + 0x014; 551 port->device_addr = base + 0x018; 552 port->status_addr = 553 port->command_addr = base + 0x01c; 554 port->altstatus_addr = 555 port->ctl_addr = base + 0x038; 556} 557 558static int adma_port_start(struct ata_port *ap) 559{ 560 struct device *dev = ap->host->dev; 561 struct adma_port_priv *pp; 562 int rc; 563 564 rc = ata_port_start(ap); 565 if (rc) 566 return rc; 567 adma_enter_reg_mode(ap); 568 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 569 if (!pp) 570 return -ENOMEM; 571 pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma, 572 GFP_KERNEL); 573 if (!pp->pkt) 574 return -ENOMEM; 575 /* paranoia? */ 576 if ((pp->pkt_dma & 7) != 0) { 577 printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n", 578 (u32)pp->pkt_dma); 579 return -ENOMEM; 580 } 581 memset(pp->pkt, 0, ADMA_PKT_BYTES); 582 ap->private_data = pp; 583 adma_reinit_engine(ap); 584 return 0; 585} 586 587static void adma_port_stop(struct ata_port *ap) 588{ 589 adma_reset_engine(ap); 590} 591 592static void adma_host_init(struct ata_host *host, unsigned int chip_id) 593{ 594 unsigned int port_no; 595 596 /* enable/lock aGO operation */ 597 writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK); 598 599 /* reset the ADMA logic */ 600 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) 601 adma_reset_engine(host->ports[port_no]); 602} 603 604static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base) 605{ 606 int rc; 607 608 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 609 if (rc) { 610 dev_printk(KERN_ERR, &pdev->dev, 611 "32-bit DMA enable failed\n"); 612 return rc; 613 } 614 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 615 if (rc) { 616 dev_printk(KERN_ERR, &pdev->dev, 617 "32-bit consistent DMA enable failed\n"); 618 return rc; 619 } 620 return 0; 621} 622 623static int adma_ata_init_one(struct pci_dev *pdev, 624 const struct pci_device_id *ent) 625{ 626 static int printed_version; 627 unsigned int board_idx = (unsigned int) ent->driver_data; 628 const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL }; 629 struct ata_host *host; 630 void __iomem *mmio_base; 631 int rc, port_no; 632 633 if (!printed_version++) 634 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 635 636 /* alloc host */ 637 host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS); 638 if (!host) 639 return -ENOMEM; 640 641 /* acquire resources and fill host */ 642 rc = pcim_enable_device(pdev); 643 if (rc) 644 return rc; 645 646 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) 647 return -ENODEV; 648 649 rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME); 650 if (rc) 651 return rc; 652 host->iomap = pcim_iomap_table(pdev); 653 mmio_base = host->iomap[ADMA_MMIO_BAR]; 654 655 rc = adma_set_dma_masks(pdev, mmio_base); 656 if (rc) 657 return rc; 658 659 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) { 660 struct ata_port *ap = host->ports[port_no]; 661 void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no); 662 unsigned int offset = port_base - mmio_base; 663 664 adma_ata_setup_port(&ap->ioaddr, port_base); 665 666 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio"); 667 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port"); 668 } 669 670 /* initialize adapter */ 671 adma_host_init(host, board_idx); 672 673 pci_set_master(pdev); 674 return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED, 675 &adma_ata_sht); 676} 677 678static int __init adma_ata_init(void) 679{ 680 return pci_register_driver(&adma_ata_pci_driver); 681} 682 683static void __exit adma_ata_exit(void) 684{ 685 pci_unregister_driver(&adma_ata_pci_driver); 686} 687 688MODULE_AUTHOR("Mark Lord"); 689MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver"); 690MODULE_LICENSE("GPL"); 691MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl); 692MODULE_VERSION(DRV_VERSION); 693 694module_init(adma_ata_init); 695module_exit(adma_ata_exit); 696