120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * sata_mv.c - Marvell SATA support 320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * Copyright 2008-2009: Marvell Corporation, all rights reserved. 58b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * Copyright 2005: EMC Corporation, all rights reserved. 6e2b1be56c5656902744c2b52e8304126a40bb609Jeff Garzik * Copyright 2005 Red Hat, Inc. All rights reserved. 720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 840f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * Originally written by Brett Russ. 940f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>. 1040f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * 1120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 1220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is free software; you can redistribute it and/or modify 1420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * it under the terms of the GNU General Public License as published by 1520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * the Free Software Foundation; version 2 of the License. 1620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is distributed in the hope that it will be useful, 1820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * but WITHOUT ANY WARRANTY; without even the implied warranty of 1920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 2020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * GNU General Public License for more details. 2120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * You should have received a copy of the GNU General Public License 2320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * along with this program; if not, write to the Free Software 2420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 2520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 284a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik/* 2985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * sata_mv TODO list: 3085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Develop a low-power-consumption strategy, and implement it. 3285afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 332b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds. 3485afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3585afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> [Experiment, Marvell value added] Is it possible to use target 3685afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * mode to cross-connect two Linux boxes with Marvell cards? If so, 3785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * creating LibATA target mode support would be very interesting. 3885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * Target mode, for those without docs, is the ability to directly 4085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * connect two SATA ports. 4185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord */ 424a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 4365ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord/* 4465ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * 80x1-B2 errata PCI#11: 4565ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * 4665ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * Users of the 6041/6081 Rev.B2 chips (current is C0) 4765ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * should be careful to insert those cards only onto PCI-X bus #0, 4865ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * and only in device slots 0..7, not higher. The chips may not 4965ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * work correctly otherwise (note: this is a pretty rare condition). 5065ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord */ 5165ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord 5220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/kernel.h> 5320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/module.h> 5420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/pci.h> 5520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/init.h> 5620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/blkdev.h> 5720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/delay.h> 5820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/interrupt.h> 598d8b60046d6a2328ca4b9031b4948084f775f607Andrew Morton#include <linux/dmapool.h> 6020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/dma-mapping.h> 61a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik#include <linux/device.h> 62c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#include <linux/clk.h> 63f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/platform_device.h> 64f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/ata_platform.h> 6515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#include <linux/mbus.h> 66c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord#include <linux/bitops.h> 675a0e3ad6af8660be21ca98a971cd00f331318c05Tejun Heo#include <linux/gfp.h> 6820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <scsi/scsi_host.h> 69193515d51ccb363165d6b09e9ba5c21089e34badJeff Garzik#include <scsi/scsi_cmnd.h> 706c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik#include <scsi/scsi_device.h> 7120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/libata.h> 7220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#define DRV_NAME "sata_mv" 74cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord#define DRV_VERSION "1.28" 7520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7640f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord/* 7740f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * module options 7840f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord */ 7940f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord 8040f21b1124a9552bc093469280eb8239dc5f73d7Mark Lordstatic int msi; 8140f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord#ifdef CONFIG_PCI 8240f21b1124a9552bc093469280eb8239dc5f73d7Mark Lordmodule_param(msi, int, S_IRUGO); 8340f21b1124a9552bc093469280eb8239dc5f73d7Mark LordMODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 8440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord#endif 8540f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord 862b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic int irq_coalescing_io_count; 872b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordmodule_param(irq_coalescing_io_count, int, S_IRUGO); 882b748a0a344847fe6b924407bbe153e1878c9f09Mark LordMODULE_PARM_DESC(irq_coalescing_io_count, 892b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord "IRQ coalescing I/O count threshold (0..255)"); 902b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 912b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic int irq_coalescing_usecs; 922b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordmodule_param(irq_coalescing_usecs, int, S_IRUGO); 932b748a0a344847fe6b924407bbe153e1878c9f09Mark LordMODULE_PARM_DESC(irq_coalescing_usecs, 942b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord "IRQ coalescing time threshold in usecs"); 952b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 9620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russenum { 9720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* BAR's are enumerated in terms of pci_resource_start() terms */ 9820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 9920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IO_BAR = 2, /* offset 0x18: IO space */ 10020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 10120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 10220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 10320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 10420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1052b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */ 1062b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */ 1072b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */ 1082b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord MAX_COAL_IO_COUNT = 255, /* completed I/O count */ 1092b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 11020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_BASE = 0, 111615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 1122b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 1132b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Per-chip ("all ports") interrupt coalescing feature. 1142b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * This is only for GEN_II / GEN_IIE hardware. 1152b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * 1162b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Coalescing defers the interrupt until either the IO_THRESHOLD 1172b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. 1182b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 119cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord COAL_REG_BASE = 0x18000, 120cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08), 1212b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */ 1222b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 123cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc), 124cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0), 1252b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 1262b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 1272b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Registers for the (unused here) transaction coalescing feature: 1282b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 129cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88), 130cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c), 1312b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 132cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATAHC0_REG_BASE = 0x20000, 133cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord FLASH_CTL = 0x1046c, 134cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord GPIO_PORT_CTL = 0x104f0, 135cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord RESET_CFG = 0x180d8, 13620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 13720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 13820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 13920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 14020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 14120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 14231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH = 32, 14331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 14431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* CRQB needs alignment on a 1KB boundary. Size == 1KB 14631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * CRPB needs alignment on a 256B boundary. Size == 256B 14731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 14831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 14931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 15031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 151da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord MV_MAX_SG_CT = 256, 15231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 15331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 154352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ 15520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_HC_SHIFT = 2, 156352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ 157352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ 158352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ 15920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 16020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Host Flags */ 16120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 1627bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 1639cbe056f6c467e7395d5aec39aceec47812eb98eSergei Shtylyov MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_POLLING, 164ad3aef51e17b9c6a90a9014805f1645e8e441c17Mark Lord 16591b1a84c10869e2e46a576e5367de3166bff8eccMark Lord MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI, 16620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 16740f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ | 16840f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA, 16991b1a84c10869e2e46a576e5367de3166bff8eccMark Lord 17091b1a84c10869e2e46a576e5367de3166bff8eccMark Lord MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN, 171ad3aef51e17b9c6a90a9014805f1645e8e441c17Mark Lord 17231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_FLAG_READ = (1 << 0), 17331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_TAG_SHIFT = 1, 174c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 175e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 176c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 17731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_ADDR_SHIFT = 8, 17831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_CS = (0x2 << 11), 17931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_LAST = (1 << 15), 18031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 18131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRPB_FLAG_STATUS_SHIFT = 8, 182c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 183c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 18431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 18531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EPRD_FLAG_END_OF_TBL = (1 << 31), 18631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 18720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* PCI interface registers */ 18820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 189cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_COMMAND = 0xc00, 190cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */ 191cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */ 19231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 193cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_MAIN_CMD_STS = 0xd30, 19420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ STOP_PCI_MASTER = (1 << 2), 19520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MASTER_EMPTY = (1 << 3), 19620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GLOB_SFT_RST = (1 << 4), 19720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 198cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_MODE = 0xd00, 1998e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_MODE_MASK = 0x30, 2008e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 201522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 202522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_DISC_TIMER = 0xd04, 203522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MSI_TRIGGER = 0xc38, 204522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_SERR_MASK = 0xc28, 205cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_XBAR_TMOUT = 0x1d04, 206522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 207522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 208522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_ATTRIBUTE = 0x1d48, 209522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_COMMAND = 0x1d50, 210522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 211cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_IRQ_CAUSE = 0x1d58, 212cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_IRQ_MASK = 0x1d5c, 21320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 21420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 215cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCIE_IRQ_CAUSE = 0x1900, 216cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCIE_IRQ_MASK = 0x1910, 217646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 21802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 2197368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */ 220cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_HC_MAIN_IRQ_CAUSE = 0x1d60, 221cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_HC_MAIN_IRQ_MASK = 0x1d64, 222cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SOC_HC_MAIN_IRQ_CAUSE = 0x20020, 223cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SOC_HC_MAIN_IRQ_MASK = 0x20024, 22440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord ERR_IRQ = (1 << 0), /* shift by (2 * port #) */ 22540f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord DONE_IRQ = (1 << 1), /* shift by (2 * port #) */ 22620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 22720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 2282b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */ 2292b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */ 23020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_ERR = (1 << 18), 23140f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */ 23240f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */ 23340f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */ 23440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */ 23540f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */ 23620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GPIO_INT = (1 << 22), 23720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SELF_INT = (1 << 23), 23820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TWSI_INT = (1 << 24), 23920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 240fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 241e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 24220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 24320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATAHC registers */ 244cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord HC_CFG = 0x00, 24520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 246cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord HC_IRQ_CAUSE = 0x14, 247352fab701ca4753dd005b67ce5e512be944eb591Mark Lord DMA_IRQ = (1 << 0), /* shift by port # */ 248352fab701ca4753dd005b67ce5e512be944eb591Mark Lord HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ 24920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ DEV_IRQ = (1 << 8), /* shift by port # */ 25020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2512b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 2522b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Per-HC (Host-Controller) interrupt coalescing feature. 2532b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * This is present on all chip generations. 2542b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * 2552b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Coalescing defers the interrupt until either the IO_THRESHOLD 2562b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. 2572b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 258cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord HC_IRQ_COAL_IO_THRESHOLD = 0x000c, 259cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord HC_IRQ_COAL_TIME_THRESHOLD = 0x0010, 2602b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 261cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SOC_LED_CTRL = 0x2c, 262000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */ 263000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */ 264000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord /* with dev activity LED */ 265000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 26620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Shadow block registers */ 267cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SHD_BLK = 0x100, 268cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */ 26920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 27020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATA registers */ 271cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_STATUS = 0x300, /* ctrl, err regs follow status */ 272cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_ACTIVE = 0x350, 273cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord FIS_IRQ_CAUSE = 0x364, 274cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */ 27517c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 276cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord LTMODE = 0x30c, /* requires read-after-write */ 27717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 27817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 279cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PHY_MODE2 = 0x330, 28047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik PHY_MODE3 = 0x310, 281cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord 282cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PHY_MODE4 = 0x314, /* requires read-after-write */ 283ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */ 284ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */ 285ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */ 286ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */ 287ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord 288cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_IFCTL = 0x344, 289cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_TESTCTL = 0x348, 290cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_IFSTAT = 0x34c, 291cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord VENDOR_UNIQUE_FIS = 0x35c, 29217c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 293cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord FISCFG = 0x360, 2948e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */ 2958e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 29617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 29729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr PHY_MODE9_GEN2 = 0x398, 29829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr PHY_MODE9_GEN1 = 0x39c, 29929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr PHYCFG_OFS = 0x3a0, /* only in 65n devices */ 30029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 301c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_MODE = 0x74, 302cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV5_LTMODE = 0x30, 303cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV5_PHY_CTL = 0x0C, 304cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_IFCFG = 0x050, 305bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 306bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_M2_PREAMP_MASK = 0x7e0, 30720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Port registers */ 309cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_CFG = 0, 3100c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 3110c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 3120c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 3130c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 3140c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 315e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 316e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 31720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 318cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_ERR_IRQ_CAUSE = 0x8, 319cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_ERR_IRQ_MASK = 0xc, 3206c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 3216c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 3226c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV = (1 << 2), /* device error */ 3236c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 3246c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 3256c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 326c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 327c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 3286c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 329c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 3306c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 3316c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 3326c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 3336c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 334646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3356c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 336646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 337646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 338646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 339646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 340646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3416c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 342646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3436c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 344646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 345646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 346646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 347646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 348646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 349646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3506c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 351646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3526c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 353c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_OVERRUN_5 = (1 << 5), 354c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_UNDERRUN_5 = (1 << 6), 355646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 356646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 357646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 | 358646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 | 35985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord EDMA_ERR_LNK_CTRL_TX, 360646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 361bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 362bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 363bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 364bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 365bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SERR | 366bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS | 3676c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 368bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 369bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 370bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY | 371bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_CTRL_RX_2 | 372bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_RX | 373bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_TX | 374bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_TRANS_PROTO, 375e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 376bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 377bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 378bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 379bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 380bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_OVERRUN_5 | 381bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_UNDERRUN_5 | 382bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS_5 | 3836c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 384bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 385bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 386bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY, 38720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 388cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_REQ_Q_BASE_HI = 0x10, 389cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */ 39031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 391cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_REQ_Q_OUT_PTR = 0x18, 39231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_PTR_SHIFT = 5, 39331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 394cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_RSP_Q_BASE_HI = 0x1c, 395cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_RSP_Q_IN_PTR = 0x20, 396cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */ 39731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_PTR_SHIFT = 3, 39831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 399cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_CMD = 0x28, /* EDMA command register */ 4000ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_EN = (1 << 0), /* enable EDMA */ 4010ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 4028e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */ 4038e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 404cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_STATUS = 0x30, /* EDMA engine status */ 4058e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */ 4068e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */ 40720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 408cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_IORDY_TMOUT = 0x34, 409cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_ARB_CFG = 0x38, 4108e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 411cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */ 412cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */ 413da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 414cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord BMDMA_CMD = 0x224, /* bmdma command register */ 415cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord BMDMA_STATUS = 0x228, /* bmdma status register */ 416cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */ 417cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */ 418da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 41931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Host private flags (hp_flags) */ 42031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_HP_FLAG_MSI = (1 << 0), 42147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB0 = (1 << 1), 42247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB2 = (1 << 2), 42347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1B2 = (1 << 3), 42447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1C0 = (1 << 4), 4250ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 4260ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 4270ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 42802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 429616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ 4301f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */ 431000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */ 43220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 43331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Port private flags (pp_flags) */ 4340ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 435721091685f853ba4e6c49f26f989db0b1a811250Mark Lord MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 43600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */ 43729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */ 438d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */ 43920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 44020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 441ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 442ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 443e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 4448e7decdb8b132ee970a2636931b7653dec6af472Mark Lord#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) 4451f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC) 446bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 44715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 44815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_BASE(i) (0x20034 + ((i) << 4)) 44915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 450095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzikenum { 451baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik /* DMA boundary 0xffff is required by the s/g splitting 452baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik * we need on /length/ in mv_fill-sg(). 453baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik */ 454baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik MV_DMA_BOUNDARY = 0xffffU, 455095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 4560ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* mask of register bits containing lower 32 bits 4570ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik * of EDMA request queue DMA address 4580ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik */ 459095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 460095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 4610ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* ditto, for response queue */ 462095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 463095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik}; 464095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 465522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikenum chip_type { 466522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_504x, 467522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_508x, 468522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_5080, 469522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_604x, 470522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_608x, 471e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_6042, 472e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_7042, 473f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara chip_soc, 474522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik}; 475522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 47631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ReQuest Block: 32B */ 47731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crqb { 478e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr; 479e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr_hi; 480e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ctrl_flags; 481e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ata_cmd[11]; 48231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 48320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 484e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstruct mv_crqb_iie { 485e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 486e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 487e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags; 488e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 len; 489e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 ata_cmd[4]; 490e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 491e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 49231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ResPonse Block: 8B */ 49331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crpb { 494e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 id; 495e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 flags; 496e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 tmstmp; 49720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 49820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 49931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 50031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_sg { 501e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 502e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags_size; 503e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 504e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 reserved; 50531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 50620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 50708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord/* 50808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * We keep a local cache of a few frequently accessed port 50908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * registers here, to avoid having to read them (very slow) 51008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * when switching between EDMA and non-EDMA modes. 51108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord */ 51208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstruct mv_cached_regs { 51308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 fiscfg; 51408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 ltmode; 51508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 haltcond; 516c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord u32 unknown_rsvd; 51708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord}; 51808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 51931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_port_priv { 52031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crqb *crqb; 52131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crqb_dma; 52231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crpb *crpb; 52331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crpb_dma; 524eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 525eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 526bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 527bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int req_idx; 528bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int resp_idx; 529bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 53031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 pp_flags; 53108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord struct mv_cached_regs cached; 53229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int delayed_eh_pmp_map; 53331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 53431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 535bca1c4eb9411533d613123618c0d127fae532595Jeff Garzikstruct mv_port_signal { 536bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 amps; 537bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 pre; 538bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik}; 539bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 54002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lordstruct mv_host_priv { 54102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 hp_flags; 5421bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bishara unsigned int board_idx; 54396e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord u32 main_irq_mask; 54402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_port_signal signal[8]; 54502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord const struct mv_hw_ops *ops; 546f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports; 547f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *base; 5487368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_cause_addr; 5497368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_mask_addr; 550cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 irq_cause_offset; 551cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 irq_mask_offset; 55202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 unmask_all_irqs; 553c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara 554c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#if defined(CONFIG_HAVE_CLK) 555c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara struct clk *clk; 556c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#endif 557da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord /* 558da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * These consistent DMA memory pools give us guaranteed 559da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * alignment for hardware-accessed data structures, 560da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * and less memory waste in accomplishing the alignment. 561da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord */ 562da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crqb_pool; 563da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crpb_pool; 564da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *sg_tbl_pool; 56502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord}; 56602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 56747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstruct mv_hw_ops { 5682a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 5692a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 57047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 57147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 57247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 573c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 574c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 575522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 5767bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 57747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 57847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 57982ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 58082ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 58182ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 58282ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 58331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap); 58431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap); 5853e4a139107e497a741c26f8a377a10f214d63ec1Mark Lordstatic int mv_qc_defer(struct ata_queued_cmd *qc); 58631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc); 587e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc); 5889a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 589a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 590a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo unsigned long deadline); 591bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap); 592bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap); 593f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *dev); 59420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 5952a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5962a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 59747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 59847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 59947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 600c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 601c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 602522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 6037bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 60447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 6052a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 6062a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 60747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 60847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 60947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 610c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 611c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 612522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 613f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 614f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 615f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 616f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 617f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 618f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc); 619f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 620f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 621f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 62229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayrstatic void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, 62329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr void __iomem *mmio, unsigned int port); 6247bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 625e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 626c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no); 627e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap); 628b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio); 62900b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma); 63047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 631e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp); 632e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 633e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 634e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 635e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 63629d187bb1e30682e228ce461c487d78d945c3e4fMark Lordstatic void mv_pmp_error_handler(struct ata_port *ap); 6374c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic void mv_process_crpb_entries(struct ata_port *ap, 6384c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp); 63947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 640da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_sff_irq_clear(struct ata_port *ap); 641da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic int mv_check_atapi_dma(struct ata_queued_cmd *qc); 642da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_setup(struct ata_queued_cmd *qc); 643da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_start(struct ata_queued_cmd *qc); 644da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_stop(struct ata_queued_cmd *qc); 645da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic u8 mv_bmdma_status(struct ata_port *ap); 646d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lordstatic u8 mv_sff_check_status(struct ata_port *ap); 647da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 648eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 649eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * because we have to allow room for worst case splitting of 650eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * PRDs for 64K boundaries in mv_fill_sg(). 651eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 652c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv5_sht = { 65368d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BASE_SHT(DRV_NAME), 654baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 655c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .dma_boundary = MV_DMA_BOUNDARY, 656c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik}; 657c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 658c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv6_sht = { 65968d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_NCQ_SHT(DRV_NAME), 660138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .can_queue = MV_MAX_Q_DEPTH - 1, 661baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 66220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .dma_boundary = MV_DMA_BOUNDARY, 66320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 66420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 665029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv5_ops = { 666029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &ata_sff_port_ops, 667c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 668c96f1732e25362d10ee7bcac1df8412a2e6b7d23Alan Cox .lost_interrupt = ATA_OP_NULL, 669c96f1732e25362d10ee7bcac1df8412a2e6b7d23Alan Cox 6703e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord .qc_defer = mv_qc_defer, 671c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_prep = mv_qc_prep, 672c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_issue = mv_qc_issue, 673c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 674bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .freeze = mv_eh_freeze, 675bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .thaw = mv_eh_thaw, 676a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .hardreset = mv_hardreset, 677bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 678c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_read = mv5_scr_read, 679c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_write = mv5_scr_write, 680c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 681c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_start = mv_port_start, 682c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_stop = mv_port_stop, 683c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik}; 684c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 685029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv6_ops = { 6868930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .inherits = &ata_bmdma_port_ops, 6878930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo 6888930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .lost_interrupt = ATA_OP_NULL, 6898930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo 6908930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .qc_defer = mv_qc_defer, 6918930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .qc_prep = mv_qc_prep, 6928930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .qc_issue = mv_qc_issue, 6938930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo 694f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord .dev_config = mv6_dev_config, 69520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 6968930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .freeze = mv_eh_freeze, 6978930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .thaw = mv_eh_thaw, 6988930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .hardreset = mv_hardreset, 6998930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .softreset = mv_softreset, 700e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_hardreset = mv_pmp_hardreset, 701e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_softreset = mv_softreset, 70229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord .error_handler = mv_pmp_error_handler, 703da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 7048930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .scr_read = mv_scr_read, 7058930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .scr_write = mv_scr_write, 7068930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo 70740f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord .sff_check_status = mv_sff_check_status, 708da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .sff_irq_clear = mv_sff_irq_clear, 709da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .check_atapi_dma = mv_check_atapi_dma, 710da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_setup = mv_bmdma_setup, 711da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_start = mv_bmdma_start, 712da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_stop = mv_bmdma_stop, 713da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_status = mv_bmdma_status, 7148930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo 7158930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .port_start = mv_port_start, 7168930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .port_stop = mv_port_stop, 71720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 71820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 719029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv_iie_ops = { 720029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv6_ops, 721029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .dev_config = ATA_OP_NULL, 722e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .qc_prep = mv_qc_prep_iie, 723e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 724e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 72598ac62defe529d04a192688f40d801a2d8fbcf98Arjan van de Venstatic const struct ata_port_info mv_port_info[] = { 72620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_504x */ 72791b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_I_FLAGS, 728c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 729bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 730c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 73120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 73220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_508x */ 73391b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 734c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 735bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 736c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 73720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 73847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik { /* chip_5080 */ 73991b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 740c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 741bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 742c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 74347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik }, 74420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_604x */ 74591b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_II_FLAGS, 746c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 747bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 748c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 74920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 75020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_608x */ 75191b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC, 752c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 753bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 754c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 75520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 756e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_6042 */ 75791b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_IIE_FLAGS, 758c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 759bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 760e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 761e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 762e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_7042 */ 76391b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_IIE_FLAGS, 764c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 765bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 766e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 767e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 768f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { /* chip_soc */ 76991b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_IIE_FLAGS, 770c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 77117c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .udma_mask = ATA_UDMA6, 77217c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .port_ops = &mv_iie_ops, 773f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 77420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 77520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7763b7d697dfb7d03edb87e50b743a7ecff029618e9Jeff Garzikstatic const struct pci_device_id mv_pci_tbl[] = { 7772d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 7782d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 7792d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 7802d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 78146c5784c8fa736c2bb42fe681189b86e99abdc2eMark Lord /* RocketRAID 1720/174x have different identifiers */ 78246c5784c8fa736c2bb42fe681189b86e99abdc2eMark Lord { PCI_VDEVICE(TTI, 0x1720), chip_6042 }, 7834462254ac6be9150aae87d54d388fc348d6fceadMark Lord { PCI_VDEVICE(TTI, 0x1740), chip_6042 }, 7844462254ac6be9150aae87d54d388fc348d6fceadMark Lord { PCI_VDEVICE(TTI, 0x1742), chip_6042 }, 7852d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 7862d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 7872d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 7882d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 7892d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 7902d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 7912d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 7922d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 7932d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 794d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger /* Adaptec 1430SA */ 795d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 796d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger 79702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Marvell 7042 support */ 7986a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 7996a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom 80002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Highpoint RocketRAID PCIe series */ 80102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 80202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 80302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 8042d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { } /* terminate list */ 80520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 80620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 80747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv5xxx_ops = { 80847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv5_phy_errata, 80947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv5_enable_leds, 81047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv5_read_preamp, 81147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv5_reset_hc, 812522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv5_reset_flash, 813522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv5_reset_bus, 81447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 81547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 81647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv6xxx_ops = { 81747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv6_phy_errata, 81847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv6_enable_leds, 81947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv6_read_preamp, 82047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv6_reset_hc, 821522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv6_reset_flash, 822522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv_reset_pci_bus, 82347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 82447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 825f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic const struct mv_hw_ops mv_soc_ops = { 826f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .phy_errata = mv6_phy_errata, 827f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .enable_leds = mv_soc_enable_leds, 828f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .read_preamp = mv_soc_read_preamp, 829f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_hc = mv_soc_reset_hc, 830f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_flash = mv_soc_reset_flash, 831f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_bus = mv_soc_reset_bus, 832f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 833f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 83429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayrstatic const struct mv_hw_ops mv_soc_65n_ops = { 83529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr .phy_errata = mv_soc_65n_phy_errata, 83629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr .enable_leds = mv_soc_enable_leds, 83729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr .reset_hc = mv_soc_reset_hc, 83829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr .reset_flash = mv_soc_reset_flash, 83929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr .reset_bus = mv_soc_reset_bus, 84029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr}; 84129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 84220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 84320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Functions 84420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 84520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 84620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void writelfl(unsigned long data, void __iomem *addr) 84720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 84820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writel(data, addr); 84920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ (void) readl(addr); /* flush to avoid PCI posted write */ 85020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 85120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 852c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hc_from_port(unsigned int port) 853c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 854c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port >> MV_PORT_HC_SHIFT; 855c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 856c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 857c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hardport_from_port(unsigned int port) 858c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 859c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port & MV_PORT_MASK; 860c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 861c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 8621cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord/* 8631cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Consolidate some rather tricky bit shift calculations. 8641cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * This is hot-path stuff, so not a function. 8651cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Simple code, with two return values, so macro rather than inline. 8661cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 8671cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * port is the sole input, in range 0..7. 8687368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * shift is one output, for use with main_irq_cause / main_irq_mask registers. 8697368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * hardport is the other output, in range 0..3. 8701cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 8711cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Note that port and hardport may be the same variable in some cases. 8721cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord */ 8731cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ 8741cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord{ \ 8751cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift = mv_hc_from_port(port) * HC_SHIFT; \ 8761cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord hardport = mv_hardport_from_port(port); \ 8771cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift += hardport * 2; \ 8781cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord} 8791cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord 880352fab701ca4753dd005b67ce5e512be944eb591Mark Lordstatic inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 881352fab701ca4753dd005b67ce5e512be944eb591Mark Lord{ 882cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 883352fab701ca4753dd005b67ce5e512be944eb591Mark Lord} 884352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 885c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline void __iomem *mv_hc_base_from_port(void __iomem *base, 886c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 887c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 888c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base(base, mv_hc_from_port(port)); 889c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 890c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 89120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 89220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 893c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base_from_port(base, port) + 8948b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik MV_SATAHC_ARBTR_REG_SZ + 895c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 89620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 89720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 898e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 899e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord{ 900e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 901e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 902e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 903e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord return hc_mmio + ofs; 904e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord} 905e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 906f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic inline void __iomem *mv_host_base(struct ata_host *host) 907f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 908f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 909f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return hpriv->base; 910f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 911f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 91220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_ap_base(struct ata_port *ap) 91320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 914f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return mv_port_base(mv_host_base(ap->host), ap->port_no); 91520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 91620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 917cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic inline int mv_get_hc_count(unsigned long port_flags) 91831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 919cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 92031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 92131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 92208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord/** 92308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * mv_save_cached_regs - (re-)initialize cached port registers 92408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @ap: the port whose registers we are caching 92508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * 92608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * Initialize the local cache of port registers, 92708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * so that reading them over and over again can 92808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * be avoided on the hotter paths of this driver. 92908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * This saves a few microseconds each time we switch 93008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * to/from EDMA mode to perform (eg.) a drive cache flush. 93108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord */ 93208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstatic void mv_save_cached_regs(struct ata_port *ap) 93308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord{ 93408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 93508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord struct mv_port_priv *pp = ap->private_data; 93608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 937cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord pp->cached.fiscfg = readl(port_mmio + FISCFG); 938cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord pp->cached.ltmode = readl(port_mmio + LTMODE); 939cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND); 940cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD); 94108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord} 94208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 94308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord/** 94408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * mv_write_cached_reg - write to a cached port register 94508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @addr: hardware address of the register 94608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @old: pointer to cached value of the register 94708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @new: new value for the register 94808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * 94908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * Write a new value to a cached register, 95008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * but only if the value is different from before. 95108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord */ 95208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstatic inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new) 95308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord{ 95408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord if (new != *old) { 95512f3b6d7551306c00cf834540a33184de67c9187Mark Lord unsigned long laddr; 95608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord *old = new; 95712f3b6d7551306c00cf834540a33184de67c9187Mark Lord /* 95812f3b6d7551306c00cf834540a33184de67c9187Mark Lord * Workaround for 88SX60x1-B2 FEr SATA#13: 95912f3b6d7551306c00cf834540a33184de67c9187Mark Lord * Read-after-write is needed to prevent generating 64-bit 96012f3b6d7551306c00cf834540a33184de67c9187Mark Lord * write cycles on the PCI bus for SATA interface registers 96112f3b6d7551306c00cf834540a33184de67c9187Mark Lord * at offsets ending in 0x4 or 0xc. 96212f3b6d7551306c00cf834540a33184de67c9187Mark Lord * 96312f3b6d7551306c00cf834540a33184de67c9187Mark Lord * Looks like a lot of fuss, but it avoids an unnecessary 96412f3b6d7551306c00cf834540a33184de67c9187Mark Lord * +1 usec read-after-write delay for unaffected registers. 96512f3b6d7551306c00cf834540a33184de67c9187Mark Lord */ 96612f3b6d7551306c00cf834540a33184de67c9187Mark Lord laddr = (long)addr & 0xffff; 96712f3b6d7551306c00cf834540a33184de67c9187Mark Lord if (laddr >= 0x300 && laddr <= 0x33c) { 96812f3b6d7551306c00cf834540a33184de67c9187Mark Lord laddr &= 0x000f; 96912f3b6d7551306c00cf834540a33184de67c9187Mark Lord if (laddr == 0x4 || laddr == 0xc) { 97012f3b6d7551306c00cf834540a33184de67c9187Mark Lord writelfl(new, addr); /* read after write */ 97112f3b6d7551306c00cf834540a33184de67c9187Mark Lord return; 97212f3b6d7551306c00cf834540a33184de67c9187Mark Lord } 97312f3b6d7551306c00cf834540a33184de67c9187Mark Lord } 97412f3b6d7551306c00cf834540a33184de67c9187Mark Lord writel(new, addr); /* unaffected by the errata */ 97508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord } 97608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord} 97708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 978c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic void mv_set_edma_ptrs(void __iomem *port_mmio, 979c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_host_priv *hpriv, 980c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp) 981c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik{ 982bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 index; 983bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 984c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 985c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize request queue 986c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 987fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 988fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 989bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 990c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crqb_dma & 0x3ff); 991cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI); 992bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 993cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + EDMA_REQ_Q_IN_PTR); 994cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR); 995c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 996c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 997c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize response queue 998c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 999fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 1000fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; 1001bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1002c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crpb_dma & 0xff); 1003cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI); 1004cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR); 1005bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 1006cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + EDMA_RSP_Q_OUT_PTR); 1007c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik} 1008c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 10092b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv) 10102b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord{ 10112b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 10122b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * When writing to the main_irq_mask in hardware, 10132b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * we must ensure exclusivity between the interrupt coalescing bits 10142b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * and the corresponding individual port DONE_IRQ bits. 10152b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * 10162b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Note that this register is really an "IRQ enable" register, 10172b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * not an "IRQ mask" register as Marvell's naming might suggest. 10182b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 10192b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE)) 10202b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mask &= ~DONE_IRQ_0_3; 10212b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE)) 10222b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mask &= ~DONE_IRQ_4_7; 10232b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord writelfl(mask, hpriv->main_irq_mask_addr); 10242b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord} 10252b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 1026c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lordstatic void mv_set_main_irq_mask(struct ata_host *host, 1027c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 disable_bits, u32 enable_bits) 1028c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord{ 1029c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord struct mv_host_priv *hpriv = host->private_data; 1030c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 old_mask, new_mask; 1031c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 103296e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord old_mask = hpriv->main_irq_mask; 1033c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord new_mask = (old_mask & ~disable_bits) | enable_bits; 103496e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord if (new_mask != old_mask) { 103596e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord hpriv->main_irq_mask = new_mask; 10362b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_write_main_irq_mask(new_mask, hpriv); 103796e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord } 1038c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord} 1039c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 1040c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lordstatic void mv_enable_port_irqs(struct ata_port *ap, 1041c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int port_bits) 1042c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord{ 1043c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int shift, hardport, port = ap->port_no; 1044c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 disable_bits, enable_bits; 1045c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 1046c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 1047c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 1048c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord disable_bits = (DONE_IRQ | ERR_IRQ) << shift; 1049c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord enable_bits = port_bits << shift; 1050c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); 1051c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord} 1052c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 105300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_clear_and_enable_port_irqs(struct ata_port *ap, 105400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord void __iomem *port_mmio, 105500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord unsigned int port_irqs) 105600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord{ 105700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 105800b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord int hardport = mv_hardport_from_port(ap->port_no); 105900b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port( 106000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_host_base(ap->host), ap->port_no); 106100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord u32 hc_irq_cause; 106200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 106300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord /* clear EDMA event indicators, if any */ 1064cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 106500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 106600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord /* clear pending irq events */ 106700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 1068cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); 106900b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 107000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord /* clear FIS IRQ Cause */ 107100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord if (IS_GEN_IIE(hpriv)) 1072cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, port_mmio + FIS_IRQ_CAUSE); 107300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 107400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_enable_port_irqs(ap, port_irqs); 107500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord} 107600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 10772b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic void mv_set_irq_coalescing(struct ata_host *host, 10782b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord unsigned int count, unsigned int usecs) 10792b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord{ 10802b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord struct mv_host_priv *hpriv = host->private_data; 10812b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord void __iomem *mmio = hpriv->base, *hc_mmio; 10822b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord u32 coal_enable = 0; 10832b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord unsigned long flags; 10846abf4678261218938ccdac90767d34ce9937634fMark Lord unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC; 10852b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 10862b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord ALL_PORTS_COAL_DONE; 10872b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 10882b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* Disable IRQ coalescing if either threshold is zero */ 10892b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (!usecs || !count) { 10902b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord clks = count = 0; 10912b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } else { 10922b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* Respect maximum limits of the hardware */ 10932b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord clks = usecs * COAL_CLOCKS_PER_USEC; 10942b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (clks > MAX_COAL_TIME_THRESHOLD) 10952b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord clks = MAX_COAL_TIME_THRESHOLD; 10962b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (count > MAX_COAL_IO_COUNT) 10972b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord count = MAX_COAL_IO_COUNT; 10982b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } 10992b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 11002b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord spin_lock_irqsave(&host->lock, flags); 11016abf4678261218938ccdac90767d34ce9937634fMark Lord mv_set_main_irq_mask(host, coal_disable, 0); 11022b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 11036abf4678261218938ccdac90767d34ce9937634fMark Lord if (is_dual_hc && !IS_GEN_I(hpriv)) { 11042b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 11056abf4678261218938ccdac90767d34ce9937634fMark Lord * GEN_II/GEN_IIE with dual host controllers: 11066abf4678261218938ccdac90767d34ce9937634fMark Lord * one set of global thresholds for the entire chip. 11072b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 1108cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD); 1109cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(count, mmio + IRQ_COAL_IO_THRESHOLD); 11102b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* clear leftover coal IRQ bit */ 1111cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); 11126abf4678261218938ccdac90767d34ce9937634fMark Lord if (count) 11136abf4678261218938ccdac90767d34ce9937634fMark Lord coal_enable = ALL_PORTS_COAL_DONE; 11146abf4678261218938ccdac90767d34ce9937634fMark Lord clks = count = 0; /* force clearing of regular regs below */ 11152b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } 11166abf4678261218938ccdac90767d34ce9937634fMark Lord 11172b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 11182b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * All chips: independent thresholds for each HC on the chip. 11192b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 11202b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord hc_mmio = mv_hc_base_from_port(mmio, 0); 1121cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); 1122cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); 1123cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); 11246abf4678261218938ccdac90767d34ce9937634fMark Lord if (count) 11256abf4678261218938ccdac90767d34ce9937634fMark Lord coal_enable |= PORTS_0_3_COAL_DONE; 11266abf4678261218938ccdac90767d34ce9937634fMark Lord if (is_dual_hc) { 11272b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC); 1128cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); 1129cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); 1130cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); 11316abf4678261218938ccdac90767d34ce9937634fMark Lord if (count) 11326abf4678261218938ccdac90767d34ce9937634fMark Lord coal_enable |= PORTS_4_7_COAL_DONE; 11332b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } 11342b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 11356abf4678261218938ccdac90767d34ce9937634fMark Lord mv_set_main_irq_mask(host, 0, coal_enable); 11362b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord spin_unlock_irqrestore(&host->lock, flags); 11372b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord} 11382b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 113905b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 114000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord * mv_start_edma - Enable eDMA engine 114105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @base: port base address 114205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pp: port private data 114305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 1144beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * Verify the local cache of the eDMA state is accurate with a 1145beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * WARN_ON. 114605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 114705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 114805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 114905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 115000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio, 1151721091685f853ba4e6c49f26f989db0b1a811250Mark Lord struct mv_port_priv *pp, u8 protocol) 115220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1153721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int want_ncq = (protocol == ATA_PROT_NCQ); 1154721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1155721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 1156721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 1157721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq != using_ncq) 1158b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 1159721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } 1160c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 11610c58912e192fc3a4835d772aafa40b72552b819fMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 11620c58912e192fc3a4835d772aafa40b72552b819fMark Lord 116300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_edma_cfg(ap, want_ncq, 1); 11640c58912e192fc3a4835d772aafa40b72552b819fMark Lord 1165f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord mv_set_edma_ptrs(port_mmio, hpriv, pp); 116600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ); 1167bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1168cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(EDMA_EN, port_mmio + EDMA_CMD); 1169afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 1170afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 117120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 117220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 11739b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lordstatic void mv_wait_for_edma_empty_idle(struct ata_port *ap) 11749b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord{ 11759b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 11769b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE); 11779b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const int per_loop = 5, timeout = (15 * 1000 / per_loop); 11789b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord int i; 11799b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 11809b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord /* 11819b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord * Wait for the EDMA engine to finish transactions in progress. 1182c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * No idea what a good "timeout" value might be, but measurements 1183c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * indicate that it often requires hundreds of microseconds 1184c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * with two drives in-use. So we use the 15msec value above 1185c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * as a rough guess at what even more drives might require. 11869b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord */ 11879b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord for (i = 0; i < timeout; ++i) { 1188cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 edma_stat = readl(port_mmio + EDMA_STATUS); 11899b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord if ((edma_stat & empty_idle) == empty_idle) 11909b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord break; 11919b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord udelay(per_loop); 11929b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord } 1193a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches /* ata_port_info(ap, "%s: %u+ usecs\n", __func__, i); */ 11949b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord} 11959b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 119605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1197e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * mv_stop_edma_engine - Disable eDMA engine 1198b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * @port_mmio: io base address 119905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 120005b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 120105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 120205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 1203b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio) 120420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1205b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord int i; 120631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1207b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Disable eDMA. The disable bit auto clears. */ 1208cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(EDMA_DS, port_mmio + EDMA_CMD); 12098b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 1210b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Wait for the chip to confirm eDMA is off. */ 1211b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord for (i = 10000; i > 0; i--) { 1212cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 reg = readl(port_mmio + EDMA_CMD); 12134537deb5e90b717a725b3d74b58b4bb1d28443d0Jeff Garzik if (!(reg & EDMA_EN)) 1214b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 1215b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord udelay(10); 121631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 1217b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 121820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 121920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1220e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap) 12210ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik{ 1222b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord void __iomem *port_mmio = mv_ap_base(ap); 1223b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 122466e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord int err = 0; 12250ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 1226b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 1227b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 1228b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 12299b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord mv_wait_for_edma_empty_idle(ap); 1230b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (mv_stop_edma_engine(port_mmio)) { 1231a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches ata_port_err(ap, "Unable to stop eDMA\n"); 123266e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord err = -EIO; 1233b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord } 123466e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord mv_edma_cfg(ap, 0, 0); 123566e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord return err; 12360ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik} 12370ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 12388a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#ifdef ATA_DEBUG 123931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_mem(void __iomem *start, unsigned bytes) 124020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 124131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 124231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 124331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%p: ", start + b); 124431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 12452dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", readl(start + b)); 124631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 124731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 124831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 124931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 125031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 12518a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#endif 12528a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik 125331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 125431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 125531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 125631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 125731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 dw; 125831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 125931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%02x: ", b); 126031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 12612dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik (void) pci_read_config_dword(pdev, b, &dw); 12622dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", dw); 126331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 126431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 126531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 126631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 126731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 126831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 126931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_all_regs(void __iomem *mmio_base, int port, 127031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct pci_dev *pdev) 127131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 127231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 12738b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik void __iomem *hc_base = mv_hc_base(mmio_base, 127431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port >> MV_PORT_HC_SHIFT); 127531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_base; 127631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int start_port, num_ports, p, start_hc, num_hcs, hc; 127731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 127831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (0 > port) { 127931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = start_port = 0; 128031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = 8; /* shld be benign for 4 port devs */ 128131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_hcs = 2; 128231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } else { 128331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = port >> MV_PORT_HC_SHIFT; 128431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_port = port; 128531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = num_hcs = 1; 128631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 12878b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik DPRINTK("All registers for port(s) %u-%u:\n", start_port, 128831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports > 1 ? num_ports - 1 : start_port); 128931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 129031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (NULL != pdev) { 129131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI config space regs:\n"); 129231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 129331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 129431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI regs:\n"); 129531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xc00, 0x3c); 129631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xd00, 0x34); 129731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xf00, 0x4); 129831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0x1d00, 0x6c); 129931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 1300d220c37e0a3c9a47ae00e87e044d963b3ea040bcDan Aloni hc_base = mv_hc_base(mmio_base, hc); 130131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("HC regs (HC %i):\n", hc); 130231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(hc_base, 0x1c); 130331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 130431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (p = start_port; p < start_port + num_ports; p++) { 130531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port_base = mv_port_base(mmio_base, p); 13062dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("EDMA regs (port %i):\n", p); 130731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base, 0x54); 13082dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("SATA regs (port %i):\n", p); 130931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base+0x300, 0x60); 131031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 131131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 131220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 131320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 131420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic unsigned int mv_scr_offset(unsigned int sc_reg_in) 131520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 131620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs; 131720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 131820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ switch (sc_reg_in) { 131920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_STATUS: 132020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_CONTROL: 132120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ERROR: 1322cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ofs = SATA_STATUS + (sc_reg_in * sizeof(u32)); 132320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 132420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ACTIVE: 1325cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ofs = SATA_ACTIVE; /* active is not with the others */ 132620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 132720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ default: 132820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = 0xffffffffU; 132920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 133020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 133120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return ofs; 133220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 133320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 133482ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 133520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 133620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 133720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1338da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 133982ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo *val = readl(mv_ap_base(link->ap) + ofs); 1340da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1341da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1342da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 134320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 134420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 134582ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 134620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 134720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 134820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1349da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 13502009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord void __iomem *addr = mv_ap_base(link->ap) + ofs; 13512009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord if (sc_reg_in == SCR_CONTROL) { 13522009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord /* 13532009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * Workaround for 88SX60x1 FEr SATA#26: 13542009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * 135525985edcedea6396277003854657b5f3cb31a628Lucas De Marchi * COMRESETs have to take care not to accidentally 13562009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * put the drive to sleep when writing SCR_CONTROL. 13572009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * Setting bits 12..15 prevents this problem. 13582009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * 13592009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * So if we see an outbound COMMRESET, set those bits. 13602009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * Ditto for the followup write that clears the reset. 13612009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * 13622009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * The proprietary driver does this for 13632009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * all chip versions, and so do we. 13642009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord */ 13652009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1) 13662009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord val |= 0xf000; 13672009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord } 13682009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord writelfl(val, addr); 1369da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1370da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1371da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 137220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 137320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1374f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *adev) 1375f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord{ 1376f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord /* 1377e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Deal with Gen-II ("mv6") hardware quirks/restrictions: 1378e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * 1379e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Gen-II does not support NCQ over a port multiplier 1380e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * (no FIS-based switching). 1381f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord */ 1382e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (adev->flags & ATA_DFLAG_NCQ) { 1383352fab701ca4753dd005b67ce5e512be944eb591Mark Lord if (sata_pmp_attached(adev->link->ap)) { 1384e49856d82a887ce365637176f9f99ab68076eae8Mark Lord adev->flags &= ~ATA_DFLAG_NCQ; 1385a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches ata_dev_info(adev, 1386352fab701ca4753dd005b67ce5e512be944eb591Mark Lord "NCQ disabled for command-based switching\n"); 1387352fab701ca4753dd005b67ce5e512be944eb591Mark Lord } 1388e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 1389f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1390f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 13913e4a139107e497a741c26f8a377a10f214d63ec1Mark Lordstatic int mv_qc_defer(struct ata_queued_cmd *qc) 13923e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord{ 13933e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct ata_link *link = qc->dev->link; 13943e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct ata_port *ap = link->ap; 13953e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct mv_port_priv *pp = ap->private_data; 13963e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 13973e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord /* 139829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * Don't allow new commands if we're in a delayed EH state 139929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * for NCQ and/or FIS-based switching. 140029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord */ 140129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 140229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord return ATA_DEFER_PORT; 1403159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou 1404159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou /* PIO commands need exclusive link: no other commands [DMA or PIO] 1405159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou * can run concurrently. 1406159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou * set excl_link when we want to send a PIO command in DMA mode 1407159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou * or a non-NCQ command in NCQ mode. 1408159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou * When we receive a command from that link, and there are no 1409159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou * outstanding commands, mark a flag to clear excl_link and let 1410159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou * the command go through. 1411159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou */ 1412159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou if (unlikely(ap->excl_link)) { 1413159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou if (link == ap->excl_link) { 1414159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou if (ap->nr_active_links) 1415159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou return ATA_DEFER_PORT; 1416159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou qc->flags |= ATA_QCFLAG_CLEAR_EXCL; 1417159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou return 0; 1418159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou } else 1419159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou return ATA_DEFER_PORT; 1420159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou } 1421159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou 142229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord /* 14233e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * If the port is completely idle, then allow the new qc. 14243e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord */ 14253e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (ap->nr_active_links == 0) 14263e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return 0; 14273e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 14284bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo /* 14294bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * The port is operating in host queuing mode (EDMA) with NCQ 14304bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * enabled, allow multiple NCQ commands. EDMA also allows 14314bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * queueing multiple DMA commands but libata core currently 14324bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * doesn't allow it. 14334bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo */ 14344bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) && 1435159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) { 1436159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou if (ata_is_ncq(qc->tf.protocol)) 1437159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou return 0; 1438159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou else { 1439159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou ap->excl_link = link; 1440159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou return ATA_DEFER_PORT; 1441159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou } 1442159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou } 14434bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo 14443e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return ATA_DEFER_PORT; 14453e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord} 14463e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 144708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstatic void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs) 1448e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 144908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord struct mv_port_priv *pp = ap->private_data; 145008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord void __iomem *port_mmio; 145100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 145208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg; 145308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 ltmode, *old_ltmode = &pp->cached.ltmode; 145408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 haltcond, *old_haltcond = &pp->cached.haltcond; 145500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 145608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord ltmode = *old_ltmode & ~LTMODE_BIT8; 145708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord haltcond = *old_haltcond | EDMA_ERR_DEV; 145800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 145900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (want_fbs) { 146008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC; 146108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord ltmode = *old_ltmode | LTMODE_BIT8; 14624c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (want_ncq) 146308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord haltcond &= ~EDMA_ERR_DEV; 14644c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord else 146508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord fiscfg |= FISCFG_WAIT_DEV_ERR; 146608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord } else { 146708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR); 1468e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 146900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 147008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord port_mmio = mv_ap_base(ap); 1471cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg); 1472cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode); 1473cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond); 1474f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1475f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 1476dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lordstatic void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq) 1477dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord{ 1478dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1479dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord u32 old, new; 1480dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord 1481dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord /* workaround for 88SX60x1 FEr SATA#25 (part 1) */ 1482cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord old = readl(hpriv->base + GPIO_PORT_CTL); 1483dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord if (want_ncq) 1484dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord new = old | (1 << 22); 1485dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord else 1486dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord new = old & ~(1 << 22); 1487dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord if (new != old) 1488cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(new, hpriv->base + GPIO_PORT_CTL); 1489dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord} 1490dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord 1491c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord/** 149240f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma 149340f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * @ap: Port being initialized 1494c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * 1495c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * There are two DMA modes on these chips: basic DMA, and EDMA. 1496c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * 1497c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * Bit-0 of the "EDMA RESERVED" register enables/disables use 1498c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * of basic DMA on the GEN_IIE versions of the chips. 1499c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * 1500c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * This bit survives EDMA resets, and must be set for basic DMA 1501c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * to function, and should be cleared when EDMA is active. 1502c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord */ 1503c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lordstatic void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma) 1504c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord{ 1505c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord struct mv_port_priv *pp = ap->private_data; 1506c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord u32 new, *old = &pp->cached.unknown_rsvd; 1507c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord 1508c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord if (enable_bmdma) 1509c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord new = *old | 1; 1510c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord else 1511c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord new = *old & ~1; 1512cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new); 1513c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord} 1514c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord 1515000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord/* 1516000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * SOC chips have an issue whereby the HDD LEDs don't always blink 1517000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * during I/O when NCQ is enabled. Enabling a special "LED blink" mode 1518000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * of the SOC takes care of it, generating a steady blink rate when 1519000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * any drive on the chip is active. 1520000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * 1521000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * Unfortunately, the blink mode is a global hardware setting for the SOC, 1522000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * so we must use it whenever at least one port on the SOC has NCQ enabled. 1523000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * 1524000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * We turn "LED blink" off when NCQ is not in use anywhere, because the normal 1525000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * LED operation works then, and provides better (more accurate) feedback. 1526000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * 1527000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * Note that this code assumes that an SOC never has more than one HC onboard. 1528000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord */ 1529000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lordstatic void mv_soc_led_blink_enable(struct ata_port *ap) 1530000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord{ 1531000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct ata_host *host = ap->host; 1532000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct mv_host_priv *hpriv = host->private_data; 1533000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord void __iomem *hc_mmio; 1534000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord u32 led_ctrl; 1535000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1536000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN) 1537000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord return; 1538000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN; 1539000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); 1540cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord led_ctrl = readl(hc_mmio + SOC_LED_CTRL); 1541cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); 1542000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord} 1543000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1544000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lordstatic void mv_soc_led_blink_disable(struct ata_port *ap) 1545000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord{ 1546000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct ata_host *host = ap->host; 1547000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct mv_host_priv *hpriv = host->private_data; 1548000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord void __iomem *hc_mmio; 1549000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord u32 led_ctrl; 1550000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord unsigned int port; 1551000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1552000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)) 1553000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord return; 1554000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1555000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord /* disable led-blink only if no ports are using NCQ */ 1556000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord for (port = 0; port < hpriv->n_ports; port++) { 1557000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct ata_port *this_ap = host->ports[port]; 1558000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct mv_port_priv *pp = this_ap->private_data; 1559000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1560000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 1561000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord return; 1562000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord } 1563000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1564000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN; 1565000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); 1566cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord led_ctrl = readl(hc_mmio + SOC_LED_CTRL); 1567cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); 1568000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord} 1569000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 157000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma) 1571e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 15720c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 cfg; 1573e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_port_priv *pp = ap->private_data; 1574e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1575e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1576e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1577e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* set up non-NCQ EDMA configuration */ 15780c58912e192fc3a4835d772aafa40b72552b819fMark Lord cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 1579d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= 1580d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 1581e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 15820c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (IS_GEN_I(hpriv)) 1583e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 8); /* enab config burst size mask */ 1584e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1585dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord else if (IS_GEN_II(hpriv)) { 1586e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1587dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord mv_60x1_errata_sata25(ap, want_ncq); 1588e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1589dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord } else if (IS_GEN_IIE(hpriv)) { 159000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord int want_fbs = sata_pmp_attached(ap); 159100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord /* 159200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * Possible future enhancement: 159300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * 159400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * The chip can use FBS with non-NCQ, if we allow it, 159500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * But first we need to have the error handling in place 159600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * for this mode (datasheet section 7.3.15.4.2.3). 159700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * So disallow non-NCQ FBS for now. 159800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord */ 159900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord want_fbs &= want_ncq; 160000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 160108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_config_fbs(ap, want_ncq, want_fbs); 160200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 160300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (want_fbs) { 160400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord pp->pp_flags |= MV_PP_FLAG_FBS_EN; 160500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ 160600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord } 160700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 1608e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 160900b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord if (want_edma) { 161000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord cfg |= (1 << 22); /* enab 4-entry host queue cache */ 161100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord if (!IS_SOC(hpriv)) 161200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord cfg |= (1 << 18); /* enab early completion */ 161300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord } 1614616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (hpriv->hp_flags & MV_HP_CUT_THROUGH) 1615616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ 1616c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord mv_bmdma_enable_iie(ap, !want_edma); 1617000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1618000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (IS_SOC(hpriv)) { 1619000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (want_ncq) 1620000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord mv_soc_led_blink_enable(ap); 1621000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord else 1622000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord mv_soc_led_blink_disable(ap); 1623000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord } 1624e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 1625e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1626721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq) { 1627721091685f853ba4e6c49f26f989db0b1a811250Mark Lord cfg |= EDMA_CFG_NCQ; 1628721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 162900b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord } 1630721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1631cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(cfg, port_mmio + EDMA_CFG); 1632e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1633e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1634da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordstatic void mv_port_free_dma_mem(struct ata_port *ap) 1635da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord{ 1636da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1637da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_port_priv *pp = ap->private_data; 1638eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord int tag; 1639da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1640da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crqb) { 1641da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1642da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = NULL; 1643da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1644da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crpb) { 1645da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1646da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = NULL; 1647da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1648eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1649eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1650eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we have one unique sg_tbl per NCQ tag. 1651eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1652eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1653eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (pp->sg_tbl[tag]) { 1654eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) 1655eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_pool_free(hpriv->sg_tbl_pool, 1656eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag], 1657eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag]); 1658eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = NULL; 1659eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1660da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1661da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord} 1662da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 166305b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 166405b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_start - Port specific init/start routine. 166505b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 166605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 166705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Allocate and point to DMA memory, init port private memory, 166805b308e1df6d9d673daedb517969241f41278b52Brett Russ * zero indices. 166905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 167005b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 167105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 167205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 167331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap) 167431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1675cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct device *dev = ap->host->dev; 1676cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 167731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp; 1678933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord unsigned long flags; 1679dde2020754aeb14e17052d61784dcb37f252aac2James Bottomley int tag; 168031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 168124dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 16826037d6bbdff65eb5a84fe35e140f4da4f7cc103aJeff Garzik if (!pp) 168324dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return -ENOMEM; 1684da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord ap->private_data = pp; 168531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1686da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1687da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crqb) 1688da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 1689da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crqb, 0, MV_CRQB_Q_SZ); 169031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1691da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1692da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crpb) 1693da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord goto out_port_free_dma_mem; 1694da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crpb, 0, MV_CRPB_Q_SZ); 169531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 16963bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */ 16973bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) 16983bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord ap->flags |= ATA_FLAG_AN; 1699eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1700eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1701eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we need one unique sg_tbl per NCQ tag. 1702eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1703eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1704eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) { 1705eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1706eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1707eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (!pp->sg_tbl[tag]) 1708eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord goto out_port_free_dma_mem; 1709eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } else { 1710eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = pp->sg_tbl[0]; 1711eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1712eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1713eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1714933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord 1715933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_lock_irqsave(ap->lock, flags); 171608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_save_cached_regs(ap); 171766e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord mv_edma_cfg(ap, 0, 0); 1718933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_unlock_irqrestore(ap->lock, flags); 1719933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord 172031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 1721da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1722da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordout_port_free_dma_mem: 1723da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 1724da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 172531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 172631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 172705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 172805b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_stop - Port specific cleanup/stop routine. 172905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 173005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 173105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Stop DMA, cleanup port memory. 173205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 173305b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 1734cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine uses the host lock to protect the DMA stop. 173505b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 173631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap) 173731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1738933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord unsigned long flags; 1739933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord 1740933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_lock_irqsave(ap->lock, flags); 1741e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma(ap); 174288e675e193159b9891c1c576de4348eaf490f5d0Mark Lord mv_enable_port_irqs(ap, 0); 1743933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_unlock_irqrestore(ap->lock, flags); 1744da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 174531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 174631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 174705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 174805b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 174905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command whose SG list to source from 175005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 175105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Populate the SG list and mark the last entry. 175205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 175305b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 175405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 175505b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 17566c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzikstatic void mv_fill_sg(struct ata_queued_cmd *qc) 175731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 175831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = qc->ap->private_data; 1759972c26bdd6b58e7534473c4f7928584578cf43f4Jeff Garzik struct scatterlist *sg; 17603be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik struct mv_sg *mv_sg, *last_sg = NULL; 1761ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo unsigned int si; 176231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1763eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord mv_sg = pp->sg_tbl[qc->tag]; 1764ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 1765d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik dma_addr_t addr = sg_dma_address(sg); 1766d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik u32 sg_len = sg_dma_len(sg); 176722374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 17684007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson while (sg_len) { 17694007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 offset = addr & 0xffff; 17704007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 len = sg_len; 177122374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 177232cd11a61007511ddb38783deec8bb1aa6735789Mark Lord if (offset + len > 0x10000) 17734007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson len = 0x10000 - offset; 17744007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 17754007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 17764007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 17776c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik mv_sg->flags_size = cpu_to_le32(len & 0xffff); 177832cd11a61007511ddb38783deec8bb1aa6735789Mark Lord mv_sg->reserved = 0; 17794007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 17804007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson sg_len -= len; 17814007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson addr += len; 17824007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 17833be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg = mv_sg; 17844007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg++; 17854007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson } 178631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 17873be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik 17883be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik if (likely(last_sg)) 17893be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 179032cd11a61007511ddb38783deec8bb1aa6735789Mark Lord mb(); /* ensure data structure is visible to the chipset */ 179131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 179231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 17935796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzikstatic void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 179431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1795559eedad7f7764dacca33980127b4615011230e4Mark Lord u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 179631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ (last ? CRQB_CMD_LAST : 0); 1797559eedad7f7764dacca33980127b4615011230e4Mark Lord *cmdw = cpu_to_le16(tmp); 179831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 179931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 180005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1801da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_sff_irq_clear - Clear hardware interrupt after DMA. 1802da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @ap: Port associated with this ATA transaction. 1803da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1804da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * We need this only for ATAPI bmdma transactions, 1805da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * as otherwise we experience spurious interrupts 1806da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * after libata-sff handles the bmdma interrupts. 1807da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1808da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_sff_irq_clear(struct ata_port *ap) 1809da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1810da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ); 1811da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1812da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1813da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1814da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA. 1815da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to check for chipset/DMA compatibility. 1816da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1817da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * The bmdma engines cannot handle speculative data sizes 1818da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * (bytecount under/over flow). So only allow DMA for 1819da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * data transfer commands with known data sizes. 1820da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1821da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1822da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1823da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1824da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic int mv_check_atapi_dma(struct ata_queued_cmd *qc) 1825da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1826da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct scsi_cmnd *scmd = qc->scsicmd; 1827da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1828da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord if (scmd) { 1829da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord switch (scmd->cmnd[0]) { 1830da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case READ_6: 1831da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case READ_10: 1832da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case READ_12: 1833da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case WRITE_6: 1834da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case WRITE_10: 1835da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case WRITE_12: 1836da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case GPCMD_READ_CD: 1837da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case GPCMD_SEND_DVD_STRUCTURE: 1838da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case GPCMD_SEND_CUE_SHEET: 1839da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord return 0; /* DMA is safe */ 1840da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord } 1841da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord } 1842da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord return -EOPNOTSUPP; /* use PIO instead */ 1843da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1844da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1845da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1846da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_setup - Set up BMDMA transaction 1847da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to prepare DMA for. 1848da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1849da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1850da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1851da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1852da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_setup(struct ata_queued_cmd *qc) 1853da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1854da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct ata_port *ap = qc->ap; 1855da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1856da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct mv_port_priv *pp = ap->private_data; 1857da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1858da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord mv_fill_sg(qc); 1859da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1860da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* clear all DMA cmd bits */ 1861cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0, port_mmio + BMDMA_CMD); 1862da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1863da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* load PRD table addr. */ 1864da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16, 1865cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + BMDMA_PRD_HIGH); 1866da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord writelfl(pp->sg_tbl_dma[qc->tag], 1867cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + BMDMA_PRD_LOW); 1868da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1869da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* issue r/w command */ 1870da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord ap->ops->sff_exec_command(ap, &qc->tf); 1871da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1872da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1873da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1874da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_start - Start a BMDMA transaction 1875da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to start DMA on. 1876da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1877da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1878da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1879da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1880da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_start(struct ata_queued_cmd *qc) 1881da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1882da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct ata_port *ap = qc->ap; 1883da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1884da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 1885da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START; 1886da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1887da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* start host DMA transaction */ 1888cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(cmd, port_mmio + BMDMA_CMD); 1889da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1890da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1891da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1892da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_stop - Stop BMDMA transfer 1893da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to stop DMA on. 1894da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1895da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Clears the ATA_DMA_START flag in the bmdma control register 1896da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1897da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1898da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1899da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 190044b733809a5aba7f6b15a548d31a56d25bf3851cMark Lordstatic void mv_bmdma_stop_ap(struct ata_port *ap) 1901da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1902da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1903da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord u32 cmd; 1904da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1905da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* clear start/stop bit */ 1906cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord cmd = readl(port_mmio + BMDMA_CMD); 190744b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord if (cmd & ATA_DMA_START) { 190844b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord cmd &= ~ATA_DMA_START; 190944b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord writelfl(cmd, port_mmio + BMDMA_CMD); 191044b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord 191144b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 191244b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord ata_sff_dma_pause(ap); 191344b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord } 191444b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord} 1915da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 191644b733809a5aba7f6b15a548d31a56d25bf3851cMark Lordstatic void mv_bmdma_stop(struct ata_queued_cmd *qc) 191744b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord{ 191844b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord mv_bmdma_stop_ap(qc->ap); 1919da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1920da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1921da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1922da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_status - Read BMDMA status 1923da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @ap: port for which to retrieve DMA status. 1924da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1925da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Read and return equivalent of the sff BMDMA status register. 1926da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1927da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1928da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1929da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1930da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic u8 mv_bmdma_status(struct ata_port *ap) 1931da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1932da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1933da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord u32 reg, status; 1934da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1935da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* 1936da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Other bits are valid only if ATA_DMA_ACTIVE==0, 1937da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * and the ATA_DMA_INTR bit doesn't exist. 1938da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1939cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord reg = readl(port_mmio + BMDMA_STATUS); 1940da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord if (reg & ATA_DMA_ACTIVE) 1941da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord status = ATA_DMA_ACTIVE; 194244b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord else if (reg & ATA_DMA_ERR) 1943da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR; 194444b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord else { 194544b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord /* 194644b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord * Just because DMA_ACTIVE is 0 (DMA completed), 194744b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord * this does _not_ mean the device is "done". 194844b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord * So we should not yet be signalling ATA_DMA_INTR 194944b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord * in some cases. Eg. DSM/TRIM, and perhaps others. 195044b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord */ 195144b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord mv_bmdma_stop_ap(ap); 195244b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY) 195344b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord status = 0; 195444b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord else 195544b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord status = ATA_DMA_INTR; 195644b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord } 1957da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord return status; 1958da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1959da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1960299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lordstatic void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc) 1961299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord{ 1962299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord struct ata_taskfile *tf = &qc->tf; 1963299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord /* 1964299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * Workaround for 88SX60x1 FEr SATA#24. 1965299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * 1966299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * Chip may corrupt WRITEs if multi_count >= 4kB. 1967299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * Note that READs are unaffected. 1968299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * 1969299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * It's not clear if this errata really means "4K bytes", 1970299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * or if it always happens for multi_count > 7 1971299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * regardless of device sector_size. 1972299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * 1973299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * So, for safety, any write with multi_count > 7 1974299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * gets converted here into a regular PIO write instead: 1975299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord */ 1976299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) { 1977299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord if (qc->dev->multi_count > 7) { 1978299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord switch (tf->command) { 1979299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_CMD_WRITE_MULTI: 1980299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord tf->command = ATA_CMD_PIO_WRITE; 1981299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord break; 1982299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_CMD_WRITE_MULTI_FUA_EXT: 1983299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord tf->flags &= ~ATA_TFLAG_FUA; /* ugh */ 1984299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord /* fall through */ 1985299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_CMD_WRITE_MULTI_EXT: 1986299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord tf->command = ATA_CMD_PIO_WRITE_EXT; 1987299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord break; 1988299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord } 1989299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord } 1990299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord } 1991299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord} 1992299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord 1993da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 199405b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_prep - Host specific command preparation. 199505b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to prepare 199605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 199705b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 199805b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it handles prep of the CRQB 199905b308e1df6d9d673daedb517969241f41278b52Brett Russ * (command request block), does some sanity checking, and calls 200005b308e1df6d9d673daedb517969241f41278b52Brett Russ * the SG load routine. 200105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 200205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 200305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 200405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 200531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc) 200631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 200731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_port *ap = qc->ap; 200831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = ap->private_data; 2009e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 *cw; 20108d2b450d0f9233f221d545f26720eebbc468e857Mark Lord struct ata_taskfile *tf = &qc->tf; 201131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u16 flags = 0; 2012a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 201331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2014299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord switch (tf->protocol) { 2015299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_PROT_DMA: 201644b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord if (tf->command == ATA_CMD_DSM) 201744b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord return; 201844b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord /* fall-thru */ 2019299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_PROT_NCQ: 2020299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord break; /* continue below */ 2021299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_PROT_PIO: 2022299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord mv_rw_multi_errata_sata24(qc); 202331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 2024299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord default: 2025299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord return; 2026299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord } 202720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 202831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Fill in command request block 202931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 20308d2b450d0f9233f221d545f26720eebbc468e857Mark Lord if (!(tf->flags & ATA_TFLAG_WRITE)) 203131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= CRQB_FLAG_READ; 2032beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 203331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= qc->tag << CRQB_TAG_SHIFT; 2034e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 203531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2036bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 2037fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 2038a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 2039a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr = 2040eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 2041a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr_hi = 2042eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 2043a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 204431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2045a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord cw = &pp->crqb[in_index].ata_cmd[0]; 204631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 204725985edcedea6396277003854657b5f3cb31a628Lucas De Marchi /* Sadly, the CRQB cannot accommodate all registers--there are 204831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * only 11 bytes...so we must pick and choose required 204931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * registers based on the command. So, we drop feature and 205031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * hob_feature for [RW] DMA commands, but they are needed for 2051cd12e1f7a2c28917c89d65c0d4a52d3919b4c125Mark Lord * NCQ. NCQ will drop hob_nsect, which is not needed there 2052cd12e1f7a2c28917c89d65c0d4a52d3919b4c125Mark Lord * (nsect is used only for the tag; feat/hob_feat hold true nsect). 205320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 205431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ switch (tf->command) { 205531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ: 205631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ_EXT: 205731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE: 205831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE_EXT: 2059c15d85c8f3f73b5f20aae7928e25b6996f16b328Jens Axboe case ATA_CMD_WRITE_FUA_EXT: 206031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 206131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 206231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_READ: 206331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_WRITE: 20648b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 206531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 206631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 206731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ default: 206831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* The only other commands EDMA supports in non-queued and 206931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 207031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * of which are defined/used by Linux. If we get here, this 207131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * driver needs work. 207231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * 207331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * FIXME: modify libata to give qc_prep a return value and 207431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * return error here. 207531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 207631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ BUG_ON(tf->command); 207731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 207831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 207931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 208031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 208131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 208231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 208331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 208431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 208531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 208631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 208731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 208831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2089e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 2090e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 2091e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik mv_fill_sg(qc); 2092e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 2093e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2094e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik/** 2095e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * mv_qc_prep_iie - Host specific command preparation. 2096e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * @qc: queued command to prepare 2097e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 2098e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * This routine simply redirects to the general purpose routine 2099e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * if command is not DMA. Else, it handles prep of the CRQB 2100e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * (command request block), does some sanity checking, and calls 2101e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * the SG load routine. 2102e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 2103e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * LOCKING: 2104e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * Inherited from caller. 2105e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik */ 2106e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc) 2107e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 2108e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_port *ap = qc->ap; 2109e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_port_priv *pp = ap->private_data; 2110e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_crqb_iie *crqb; 21118d2b450d0f9233f221d545f26720eebbc468e857Mark Lord struct ata_taskfile *tf = &qc->tf; 2112a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 2113e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik u32 flags = 0; 2114e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 21158d2b450d0f9233f221d545f26720eebbc468e857Mark Lord if ((tf->protocol != ATA_PROT_DMA) && 21168d2b450d0f9233f221d545f26720eebbc468e857Mark Lord (tf->protocol != ATA_PROT_NCQ)) 2117e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 211844b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord if (tf->command == ATA_CMD_DSM) 211944b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord return; /* use bmdma for this */ 2120e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2121e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* Fill in Gen IIE command request block */ 21228d2b450d0f9233f221d545f26720eebbc468e857Mark Lord if (!(tf->flags & ATA_TFLAG_WRITE)) 2123e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= CRQB_FLAG_READ; 2124e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2125beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 2126e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= qc->tag << CRQB_TAG_SHIFT; 21278c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord flags |= qc->tag << CRQB_HOSTQ_SHIFT; 2128e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 2129e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2130bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 2131fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 2132a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 2133a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 2134eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 2135eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 2136e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->flags = cpu_to_le32(flags); 2137e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2138e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[0] = cpu_to_le32( 2139e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->command << 16) | 2140e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->feature << 24) 2141e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2142e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[1] = cpu_to_le32( 2143e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbal << 0) | 2144e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbam << 8) | 2145e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbah << 16) | 2146e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->device << 24) 2147e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2148e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[2] = cpu_to_le32( 2149e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbal << 0) | 2150e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbam << 8) | 2151e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbah << 16) | 2152e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_feature << 24) 2153e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2154e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[3] = cpu_to_le32( 2155e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->nsect << 0) | 2156e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_nsect << 8) 2157e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2158e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2159e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 216031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 216131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_fill_sg(qc); 216231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 216331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 216405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2165d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * mv_sff_check_status - fetch device status, if valid 2166d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * @ap: ATA port to fetch status from 2167d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * 2168d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * When using command issue via mv_qc_issue_fis(), 2169d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * the initial ATA_BUSY state does not show up in the 2170d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * ATA status (shadow) register. This can confuse libata! 2171d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * 2172d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * So we have a hook here to fake ATA_BUSY for that situation, 2173d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * until the first time a BUSY, DRQ, or ERR bit is seen. 2174d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * 2175d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * The rest of the time, it simply returns the ATA status register. 2176d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord */ 2177d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lordstatic u8 mv_sff_check_status(struct ata_port *ap) 2178d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord{ 2179d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord u8 stat = ioread8(ap->ioaddr.status_addr); 2180d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord struct mv_port_priv *pp = ap->private_data; 2181d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord 2182d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) { 2183d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) 2184d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; 2185d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord else 2186d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord stat = ATA_BUSY; 2187d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord } 2188d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord return stat; 2189d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord} 2190d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord 2191d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord/** 219270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register 219370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * @fis: fis to be sent 219470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * @nwords: number of 32-bit words in the fis 219570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 219670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lordstatic unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords) 219770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord{ 219870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 219970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord u32 ifctl, old_ifctl, ifstat; 220070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord int i, timeout = 200, final_word = nwords - 1; 220170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 220270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Initiate FIS transmission mode */ 2203cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord old_ifctl = readl(port_mmio + SATA_IFCTL); 220470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ifctl = 0x100 | (old_ifctl & 0xf); 2205cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(ifctl, port_mmio + SATA_IFCTL); 220670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 220770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Send all words of the FIS except for the final word */ 220870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord for (i = 0; i < final_word; ++i) 2209cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS); 221070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 221170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Flag end-of-transmission, and then send the final word */ 2212cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL); 2213cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS); 221470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 221570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* 221670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Wait for FIS transmission to complete. 221770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * This typically takes just a single iteration. 221870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 221970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord do { 2220cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ifstat = readl(port_mmio + SATA_IFSTAT); 222170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } while (!(ifstat & 0x1000) && --timeout); 222270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 222370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Restore original port configuration */ 2224cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(old_ifctl, port_mmio + SATA_IFCTL); 222570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 222670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* See if it worked */ 222770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if ((ifstat & 0x3000) != 0x1000) { 2228a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches ata_port_warn(ap, "%s transmission error, ifstat=%08x\n", 2229a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches __func__, ifstat); 223070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return AC_ERR_OTHER; 223170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } 223270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return 0; 223370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord} 223470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 223570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord/** 223670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * mv_qc_issue_fis - Issue a command directly as a FIS 223770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * @qc: queued command to start 223870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 223970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Note that the ATA shadow registers are not updated 224070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * after command issue, so the device will appear "READY" 224170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * if polled, even while it is BUSY processing the command. 224270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 224370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * So we use a status hook to fake ATA_BUSY until the drive changes state. 224470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 224570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Note: we don't get updated shadow regs on *completion* 224670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * of non-data commands. So avoid sending them via this function, 224770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * as they will appear to have completed immediately. 224870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 224970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * GEN_IIE has special registers that we could get the result tf from, 225070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * but earlier chipsets do not. For now, we ignore those registers. 225170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 225270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lordstatic unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc) 225370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord{ 225470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct ata_port *ap = qc->ap; 225570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct mv_port_priv *pp = ap->private_data; 225670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct ata_link *link = qc->dev->link; 225770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord u32 fis[5]; 225870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord int err = 0; 225970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 226070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis); 22614c4a90fd2b9d1f5c0d33df3fcfaa8a3dae9abc53Thiago Farina err = mv_send_fis(ap, fis, ARRAY_SIZE(fis)); 226270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (err) 226370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return err; 226470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 226570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord switch (qc->tf.protocol) { 226670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord case ATAPI_PROT_PIO: 226770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; 226870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* fall through */ 226970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord case ATAPI_PROT_NODATA: 227070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST_FIRST; 227170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord break; 227270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord case ATA_PROT_PIO: 227370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; 227470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (qc->tf.flags & ATA_TFLAG_WRITE) 227570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST_FIRST; 227670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord else 227770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST; 227870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord break; 227970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord default: 228070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST_LAST; 228170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord break; 228270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } 228370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 228470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (qc->tf.flags & ATA_TFLAG_POLLING) 2285ea3c64506ea7965f86f030155e6fdef381de10e2Gwendal Grignou ata_sff_queue_pio_task(link, 0); 228670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return 0; 228770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord} 228870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 228970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord/** 229005b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_issue - Initiate a command to the host 229105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to start 229205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 229305b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 229405b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it sanity checks our local 229505b308e1df6d9d673daedb517969241f41278b52Brett Russ * caches of the request producer/consumer indices then enables 229605b308e1df6d9d673daedb517969241f41278b52Brett Russ * DMA and bumps the request producer index. 229705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 229805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 229905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 230005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 23019a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 230231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 2303f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord static int limit_warnings = 10; 2304c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct ata_port *ap = qc->ap; 2305c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 2306c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp = ap->private_data; 2307bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 in_index; 230842ed893d8011264f9945c2f54055b47c298ac53eMark Lord unsigned int port_irqs; 2309f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord 2310d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */ 2311d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord 2312f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord switch (qc->tf.protocol) { 2313f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATA_PROT_DMA: 231444b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord if (qc->tf.command == ATA_CMD_DSM) { 231544b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */ 231644b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord return AC_ERR_OTHER; 231744b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord break; /* use bmdma for this */ 231844b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord } 231944b733809a5aba7f6b15a548d31a56d25bf3851cMark Lord /* fall thru */ 2320f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATA_PROT_NCQ: 2321f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord mv_start_edma(ap, port_mmio, pp, qc->tf.protocol); 2322f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2323f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 2324f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord 2325f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord /* Write the request in pointer to kick the EDMA to life */ 2326f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 2327cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + EDMA_REQ_Q_IN_PTR); 2328f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord return 0; 232931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2330f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATA_PROT_PIO: 2331c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord /* 2332c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * Errata SATA#16, SATA#24: warn if multiple DRQs expected. 2333c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * 2334c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * Someday, we might implement special polling workarounds 2335c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * for these, but it all seems rather unnecessary since we 2336c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * normally use only DMA for commands which transfer more 2337c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * than a single block of data. 2338c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * 2339c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * Much of the time, this could just work regardless. 2340c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * So for now, just log the incident, and allow the attempt. 2341c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord */ 2342c7843e8f565f624b0cff7cad1370fad4cb84dfbcMark Lord if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) { 2343c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord --limit_warnings; 2344a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches ata_link_warn(qc->dev->link, DRV_NAME 2345a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches ": attempting PIO w/multiple DRQ: " 2346a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches "this may fail due to h/w errata\n"); 2347c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord } 2348f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord /* drop through */ 234942ed893d8011264f9945c2f54055b47c298ac53eMark Lord case ATA_PROT_NODATA: 2350f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATAPI_PROT_PIO: 235142ed893d8011264f9945c2f54055b47c298ac53eMark Lord case ATAPI_PROT_NODATA: 235242ed893d8011264f9945c2f54055b47c298ac53eMark Lord if (ap->flags & ATA_FLAG_PIO_POLLING) 235342ed893d8011264f9945c2f54055b47c298ac53eMark Lord qc->tf.flags |= ATA_TFLAG_POLLING; 235442ed893d8011264f9945c2f54055b47c298ac53eMark Lord break; 235531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 235642ed893d8011264f9945c2f54055b47c298ac53eMark Lord 235742ed893d8011264f9945c2f54055b47c298ac53eMark Lord if (qc->tf.flags & ATA_TFLAG_POLLING) 235842ed893d8011264f9945c2f54055b47c298ac53eMark Lord port_irqs = ERR_IRQ; /* mask device interrupt when polling */ 235942ed893d8011264f9945c2f54055b47c298ac53eMark Lord else 236042ed893d8011264f9945c2f54055b47c298ac53eMark Lord port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */ 236142ed893d8011264f9945c2f54055b47c298ac53eMark Lord 236242ed893d8011264f9945c2f54055b47c298ac53eMark Lord /* 236342ed893d8011264f9945c2f54055b47c298ac53eMark Lord * We're about to send a non-EDMA capable command to the 236442ed893d8011264f9945c2f54055b47c298ac53eMark Lord * port. Turn off EDMA so there won't be problems accessing 236542ed893d8011264f9945c2f54055b47c298ac53eMark Lord * shadow block, etc registers. 236642ed893d8011264f9945c2f54055b47c298ac53eMark Lord */ 236742ed893d8011264f9945c2f54055b47c298ac53eMark Lord mv_stop_edma(ap); 236842ed893d8011264f9945c2f54055b47c298ac53eMark Lord mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs); 236942ed893d8011264f9945c2f54055b47c298ac53eMark Lord mv_pmp_select(ap, qc->dev->link->pmp); 237070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 237170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (qc->tf.command == ATA_CMD_READ_LOG_EXT) { 237270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 237370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* 237470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Workaround for 88SX60x1 FEr SATA#25 (part 2). 237540f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * 237670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * After any NCQ error, the READ_LOG_EXT command 237770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * from libata-eh *must* use mv_qc_issue_fis(). 237870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Otherwise it might fail, due to chip errata. 237970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 238070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Rather than special-case it, we'll just *always* 238170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * use this method here for READ_LOG_EXT, making for 238270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * easier testing. 238370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 238470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (IS_GEN_II(hpriv)) 238570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return mv_qc_issue_fis(qc); 238670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } 2387360ff7833098e944e5003618b03894251e937802Tejun Heo return ata_bmdma_qc_issue(qc); 238831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 238931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 23908f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lordstatic struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) 23918f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 23928f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct mv_port_priv *pp = ap->private_data; 23938f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc; 23948f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 23958f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 23968f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord return NULL; 23978f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord qc = ata_qc_from_tag(ap, ap->link.active_tag); 23983e4ec3443f70fbe144799ccf0b1c3797f78d1715Tejun Heo if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING)) 23993e4ec3443f70fbe144799ccf0b1c3797f78d1715Tejun Heo return qc; 24003e4ec3443f70fbe144799ccf0b1c3797f78d1715Tejun Heo return NULL; 24018f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 24028f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 240329d187bb1e30682e228ce461c487d78d945c3e4fMark Lordstatic void mv_pmp_error_handler(struct ata_port *ap) 240429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord{ 240529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int pmp, pmp_map; 240629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord struct mv_port_priv *pp = ap->private_data; 240729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord 240829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { 240929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord /* 241029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * Perform NCQ error analysis on failed PMPs 241129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * before we freeze the port entirely. 241229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * 241329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * The failed PMPs are marked earlier by mv_pmp_eh_prep(). 241429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord */ 241529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pmp_map = pp->delayed_eh_pmp_map; 241629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; 241729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord for (pmp = 0; pmp_map != 0; pmp++) { 241829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int this_pmp = (1 << pmp); 241929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pmp_map & this_pmp) { 242029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord struct ata_link *link = &ap->pmp_link[pmp]; 242129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pmp_map &= ~this_pmp; 242229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord ata_eh_analyze_ncq_error(link); 242329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 242429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 242529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord ata_port_freeze(ap); 242629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 242729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord sata_pmp_error_handler(ap); 242829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord} 242929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord 24304c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic unsigned int mv_get_err_pmp_map(struct ata_port *ap) 24314c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 24324c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 24334c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 2434cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord return readl(port_mmio + SATA_TESTCTL) >> 16; 24354c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 24364c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24374c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map) 24384c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 24394c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct ata_eh_info *ehi; 24404c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int pmp; 24414c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24424c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 24434c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Initialize EH info for PMPs which saw device errors 24444c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 24454c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi = &ap->link.eh_info; 24464c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord for (pmp = 0; pmp_map != 0; pmp++) { 24474c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int this_pmp = (1 << pmp); 24484c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pmp_map & this_pmp) { 24494c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct ata_link *link = &ap->pmp_link[pmp]; 24504c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24514c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pmp_map &= ~this_pmp; 24524c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi = &link->eh_info; 24534c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_ehi_clear_desc(ehi); 24544c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_ehi_push_desc(ehi, "dev err"); 24554c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi->err_mask |= AC_ERR_DEV; 24564c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi->action |= ATA_EH_RESET; 24574c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_link_abort(link); 24584c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24594c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24604c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 24614c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 246206aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lordstatic int mv_req_q_empty(struct ata_port *ap) 246306aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord{ 246406aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 246506aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord u32 in_ptr, out_ptr; 246606aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord 2467cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR) 246806aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2469cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR) 247006aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 247106aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord return (in_ptr == out_ptr); /* 1 == queue_is_empty */ 247206aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord} 247306aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord 24744c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_fbs_ncq_dev_err(struct ata_port *ap) 24754c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 24764c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp = ap->private_data; 24774c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord int failed_links; 24784c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int old_map, new_map; 24794c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24804c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 24814c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device error during FBS+NCQ operation: 24824c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 24834c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Set a port flag to prevent further I/O being enqueued. 24844c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Leave the EDMA running to drain outstanding commands from this port. 24854c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Perform the post-mortem/EH only when all responses are complete. 24864c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2). 24874c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 24884c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { 24894c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; 24904c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->delayed_eh_pmp_map = 0; 24914c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24924c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord old_map = pp->delayed_eh_pmp_map; 24934c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord new_map = old_map | mv_get_err_pmp_map(ap); 24944c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24954c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (old_map != new_map) { 24964c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->delayed_eh_pmp_map = new_map; 24974c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_pmp_eh_prep(ap, new_map & ~old_map); 24984c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 2499c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord failed_links = hweight16(new_map); 25004c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 2501a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches ata_port_info(ap, 2502a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches "%s: pmp_map=%04x qc_map=%04x failed_links=%d nr_active_links=%d\n", 2503a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches __func__, pp->delayed_eh_pmp_map, 2504a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches ap->qc_active, failed_links, 2505a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches ap->nr_active_links); 25064c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 250706aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { 25084c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_process_crpb_entries(ap, pp); 25094c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_stop_edma(ap); 25104c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_eh_freeze(ap); 2511a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches ata_port_info(ap, "%s: done\n", __func__); 25124c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 1; /* handled */ 25134c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 2514a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches ata_port_info(ap, "%s: waiting\n", __func__); 25154c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 1; /* handled */ 25164c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 25174c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 25184c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap) 25194c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 25204c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 25214c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Possible future enhancement: 25224c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 25234c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * FBS+non-NCQ operation is not yet implemented. 25244c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * See related notes in mv_edma_cfg(). 25254c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 25264c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device error during FBS+non-NCQ operation: 25274c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 25284c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * We need to snapshot the shadow registers for each failed command. 25294c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3). 25304c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 25314c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 25324c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 25334c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 25344c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause) 25354c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 25364c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp = ap->private_data; 25374c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 25384c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 25394c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* EDMA was not active: not handled */ 25404c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) 25414c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* FBS was not active: not handled */ 25424c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 25434c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(edma_err_cause & EDMA_ERR_DEV)) 25444c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* non DEV error: not handled */ 25454c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT; 25464c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS)) 25474c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* other problems: not handled */ 25484c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 25494c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { 25504c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 25514c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * EDMA should NOT have self-disabled for this case. 25524c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * If it did, then something is wrong elsewhere, 25534c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * and we cannot handle it here. 25544c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 25554c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & EDMA_ERR_SELF_DIS) { 2556a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n", 2557a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches __func__, edma_err_cause, pp->pp_flags); 25584c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 25594c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 25604c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return mv_handle_fbs_ncq_dev_err(ap); 25614c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } else { 25624c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 25634c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * EDMA should have self-disabled for this case. 25644c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * If it did not, then something is wrong elsewhere, 25654c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * and we cannot handle it here. 25664c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 25674c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) { 2568a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n", 2569a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches __func__, edma_err_cause, pp->pp_flags); 25704c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 25714c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 25724c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return mv_handle_fbs_non_ncq_dev_err(ap); 25734c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 25744c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 25754c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 25764c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 2577a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lordstatic void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled) 25788f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 25798f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_eh_info *ehi = &ap->link.eh_info; 2580a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord char *when = "idle"; 25818f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 25828f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_ehi_clear_desc(ehi); 25833e4ec3443f70fbe144799ccf0b1c3797f78d1715Tejun Heo if (edma_was_enabled) { 2584a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "EDMA enabled"; 25858f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } else { 25868f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 25878f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 2588a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "polling"; 25898f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } 2590a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when); 25918f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->err_mask |= AC_ERR_OTHER; 25928f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->action |= ATA_EH_RESET; 25938f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_port_freeze(ap); 25948f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 25958f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 259605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 259705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_err_intr - Handle error interrupts on the port 259805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 259905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 26008d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Most cases require a full reset of the chip's state machine, 26018d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * which also performs a COMRESET. 26028d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Also, if the port disabled DMA, update our cached copy to match. 260305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 260405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 260505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 260605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 260737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lordstatic void mv_err_intr(struct ata_port *ap) 260831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 260931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 2610bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 edma_err_cause, eh_freeze_mask, serr = 0; 2611e40060772d85f3534d3d517197696e24bb01f45bMark Lord u32 fis_cause = 0; 2612bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 2613bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2614bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int action = 0, err_mask = 0; 26159af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_eh_info *ehi = &ap->link.eh_info; 261637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord struct ata_queued_cmd *qc; 261737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord int abort = 0; 261820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 26198d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord /* 262037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Read and clear the SError and err_cause bits. 2621e40060772d85f3534d3d517197696e24bb01f45bMark Lord * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear 2622e40060772d85f3534d3d517197696e24bb01f45bMark Lord * the FIS_IRQ_CAUSE register before clearing edma_err_cause. 26238d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord */ 262437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord sata_scr_read(&ap->link, SCR_ERROR, &serr); 262537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 262637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord 2627cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE); 2628e40060772d85f3534d3d517197696e24bb01f45bMark Lord if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2629cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord fis_cause = readl(port_mmio + FIS_IRQ_CAUSE); 2630cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE); 2631e40060772d85f3534d3d517197696e24bb01f45bMark Lord } 2632cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE); 2633bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 26344c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & EDMA_ERR_DEV) { 26354c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 26364c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device errors during FIS-based switching operation 26374c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * require special handling. 26384c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 26394c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (mv_handle_dev_err(ap, edma_err_cause)) 26404c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return; 26414c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 26424c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 264337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord qc = mv_get_active_qc(ap); 264437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_clear_desc(ehi); 264537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x", 264637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord edma_err_cause, pp->pp_flags); 2647e40060772d85f3534d3d517197696e24bb01f45bMark Lord 2648c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2649e40060772d85f3534d3d517197696e24bb01f45bMark Lord ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause); 2650cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord if (fis_cause & FIS_IRQ_CAUSE_AN) { 2651c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord u32 ec = edma_err_cause & 2652c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT); 2653c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord sata_async_notification(ap); 2654c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord if (!ec) 2655c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord return; /* Just an AN; no need for the nukes */ 2656c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord ata_ehi_push_desc(ehi, "SDB notify"); 2657c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord } 2658c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord } 2659bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 2660352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * All generations share these EDMA error cause bits: 2661bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 266237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (edma_err_cause & EDMA_ERR_DEV) { 2663bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_DEV; 266437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord action |= ATA_EH_RESET; 266537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_push_desc(ehi, "dev error"); 266637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 2667bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 26686c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 2669bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR)) { 2670bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_ATA_BUS; 2671cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2672b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "parity error"); 2673bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2674bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 2675bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_hotplugged(ehi); 2676bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 2677b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo "dev disconnect" : "dev connect"); 2678cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2679bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2680bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2681352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 2682352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Gen-I has a different SELF_DIS bit, 2683352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * different FREEZE bits, and no SERR bit: 2684352fab701ca4753dd005b67ce5e512be944eb591Mark Lord */ 2685ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) { 2686bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE_5; 2687bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 2688bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2689b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 2690bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2691bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 2692bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE; 2693bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS) { 2694bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2695b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 2696bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2697bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SERR) { 26988d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord ata_ehi_push_desc(ehi, "SError=%08x", serr); 26998d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord err_mask |= AC_ERR_ATA_BUS; 2700cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2701bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2702afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 270320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2704bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!err_mask) { 2705bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_OTHER; 2706cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2707bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2708bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2709bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->serror |= serr; 2710bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->action |= action; 2711bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2712bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 2713bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 2714bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 2715bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 2716bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 271737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (err_mask == AC_ERR_DEV) { 271837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* 271937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Cannot do ata_port_freeze() here, 272037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * because it would kill PIO access, 272137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * which is needed for further diagnosis. 272237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord */ 272337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord mv_eh_freeze(ap); 272437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord abort = 1; 272537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } else if (edma_err_cause & eh_freeze_mask) { 272637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* 272737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Note to self: ata_port_freeze() calls ata_port_abort() 272837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord */ 2729bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 273037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } else { 273137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord abort = 1; 273237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 273337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord 273437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (abort) { 273537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (qc) 273637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_link_abort(qc->dev->link); 273737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord else 273837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_port_abort(ap); 273937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 2740bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2741bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 27421aadf5c3bbbbb0db09dcb5aa26c61326e0d3e9e7Tejun Heostatic bool mv_process_crpb_response(struct ata_port *ap, 2743fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response, unsigned int tag, int ncq_enabled) 2744fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord{ 2745752e386c247664152f2cce37915d1f50631d7f42Tejun Heo u8 ata_status; 2746752e386c247664152f2cce37915d1f50631d7f42Tejun Heo u16 edma_status = le16_to_cpu(response->flags); 2747752e386c247664152f2cce37915d1f50631d7f42Tejun Heo 2748752e386c247664152f2cce37915d1f50631d7f42Tejun Heo /* 2749752e386c247664152f2cce37915d1f50631d7f42Tejun Heo * edma_status from a response queue entry: 2750752e386c247664152f2cce37915d1f50631d7f42Tejun Heo * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only). 2751752e386c247664152f2cce37915d1f50631d7f42Tejun Heo * MSB is saved ATA status from command completion. 2752752e386c247664152f2cce37915d1f50631d7f42Tejun Heo */ 2753752e386c247664152f2cce37915d1f50631d7f42Tejun Heo if (!ncq_enabled) { 2754752e386c247664152f2cce37915d1f50631d7f42Tejun Heo u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; 2755752e386c247664152f2cce37915d1f50631d7f42Tejun Heo if (err_cause) { 2756752e386c247664152f2cce37915d1f50631d7f42Tejun Heo /* 2757752e386c247664152f2cce37915d1f50631d7f42Tejun Heo * Error will be seen/handled by 2758752e386c247664152f2cce37915d1f50631d7f42Tejun Heo * mv_err_intr(). So do nothing at all here. 2759752e386c247664152f2cce37915d1f50631d7f42Tejun Heo */ 27601aadf5c3bbbbb0db09dcb5aa26c61326e0d3e9e7Tejun Heo return false; 2761752e386c247664152f2cce37915d1f50631d7f42Tejun Heo } 2762fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2763752e386c247664152f2cce37915d1f50631d7f42Tejun Heo ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; 2764752e386c247664152f2cce37915d1f50631d7f42Tejun Heo if (!ac_err_mask(ata_status)) 27651aadf5c3bbbbb0db09dcb5aa26c61326e0d3e9e7Tejun Heo return true; 2766752e386c247664152f2cce37915d1f50631d7f42Tejun Heo /* else: leave it for mv_err_intr() */ 27671aadf5c3bbbbb0db09dcb5aa26c61326e0d3e9e7Tejun Heo return false; 2768fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord} 2769fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 2770fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) 2771bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2772bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 2773bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2774fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u32 in_index; 2775bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik bool work_done = false; 27761aadf5c3bbbbb0db09dcb5aa26c61326e0d3e9e7Tejun Heo u32 done_mask = 0; 2777fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); 2778bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2779fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Get the hardware queue position index */ 2780cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR) 2781bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2782bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2783fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Process new responses from since the last time we looked */ 2784fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord while (in_index != pp->resp_idx) { 27856c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik unsigned int tag; 2786fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response = &pp->crpb[pp->resp_idx]; 2787bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2788fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2789bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2790fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (IS_GEN_I(hpriv)) { 2791fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 50xx: no NCQ, only one command active at a time */ 27929af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo tag = ap->link.active_tag; 2793fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 2794fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Gen II/IIE: get command tag from CRPB entry */ 2795fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord tag = le16_to_cpu(response->id) & 0x1f; 2796bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 27971aadf5c3bbbbb0db09dcb5aa26c61326e0d3e9e7Tejun Heo if (mv_process_crpb_response(ap, response, tag, ncq_enabled)) 27981aadf5c3bbbbb0db09dcb5aa26c61326e0d3e9e7Tejun Heo done_mask |= 1 << tag; 2799bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik work_done = true; 2800bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2801bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 28021aadf5c3bbbbb0db09dcb5aa26c61326e0d3e9e7Tejun Heo if (work_done) { 28031aadf5c3bbbbb0db09dcb5aa26c61326e0d3e9e7Tejun Heo ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask); 28041aadf5c3bbbbb0db09dcb5aa26c61326e0d3e9e7Tejun Heo 28051aadf5c3bbbbb0db09dcb5aa26c61326e0d3e9e7Tejun Heo /* Update the software queue position index in hardware */ 2806bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 2807fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), 2808cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + EDMA_RSP_Q_OUT_PTR); 28091aadf5c3bbbbb0db09dcb5aa26c61326e0d3e9e7Tejun Heo } 281020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 281120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2812a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lordstatic void mv_port_intr(struct ata_port *ap, u32 port_cause) 2813a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord{ 2814a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord struct mv_port_priv *pp; 2815a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord int edma_was_enabled; 2816a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord 2817a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2818a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Grab a snapshot of the EDMA_EN flag setting, 2819a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * so that we have a consistent view for this port, 2820a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * even if something we call of our routines changes it. 2821a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2822a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord pp = ap->private_data; 2823a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); 2824a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2825a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Process completed CRPB response(s) before other events. 2826a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2827a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (edma_was_enabled && (port_cause & DONE_IRQ)) { 2828a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_process_crpb_entries(ap, pp); 28294c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 28304c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_handle_fbs_ncq_dev_err(ap); 2831a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2832a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2833a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Handle chip-reported errors, or continue on to handle PIO. 2834a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2835a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (unlikely(port_cause & ERR_IRQ)) { 2836a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_err_intr(ap); 2837a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } else if (!edma_was_enabled) { 2838a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord struct ata_queued_cmd *qc = mv_get_active_qc(ap); 2839a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (qc) 2840c3b2889424c26f3b42962b6f39aabb4f1fd1b576Tejun Heo ata_bmdma_port_intr(ap, qc); 2841a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord else 2842a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_unexpected_intr(ap, edma_was_enabled); 2843a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2844a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord} 2845a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord 284605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 284705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_host_intr - Handle all interrupts on the given host controller 2848cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * @host: host specific structure 28497368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * @main_irq_cause: Main interrupt cause register for the chip. 285005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 285105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 285205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 285305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 28547368f91926a2870a8c3f9546d86535ce71ae0757Mark Lordstatic int mv_host_intr(struct ata_host *host, u32 main_irq_cause) 285520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2856f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 2857eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord void __iomem *mmio = hpriv->base, *hc_mmio; 2858a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0, port; 285920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 28602b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* If asserted, clear the "all ports" IRQ coalescing bit */ 28612b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (main_irq_cause & ALL_PORTS_COAL_DONE) 2862cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); 28632b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 2864a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord for (port = 0; port < hpriv->n_ports; port++) { 2865cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_port *ap = host->ports[port]; 2866eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord unsigned int p, shift, hardport, port_cause; 2867eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord 2868a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2869a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord /* 2870eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * Each hc within the host has its own hc_irq_cause register, 2871eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * where the interrupting ports bits get ack'd. 2872a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord */ 2873eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (hardport == 0) { /* first port on this hc ? */ 2874eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND; 2875eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord u32 port_mask, ack_irqs; 2876eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord /* 2877eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * Skip this entire hc if nothing pending for any ports 2878eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord */ 2879eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (!hc_cause) { 2880eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord port += MV_PORTS_PER_HC - 1; 2881eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord continue; 2882eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord } 2883eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord /* 2884eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * We don't need/want to read the hc_irq_cause register, 2885eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * because doing so hurts performance, and 2886eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * main_irq_cause already gives us everything we need. 2887eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * 2888eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * But we do have to *write* to the hc_irq_cause to ack 2889eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * the ports that we are handling this time through. 2890eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * 2891eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * This requires that we create a bitmap for those 2892eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * ports which interrupted us, and use that bitmap 2893eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * to ack (only) those ports via hc_irq_cause. 2894eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord */ 2895eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord ack_irqs = 0; 28962b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (hc_cause & PORTS_0_3_COAL_DONE) 28972b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord ack_irqs = HC_COAL_IRQ; 2898eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord for (p = 0; p < MV_PORTS_PER_HC; ++p) { 2899eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if ((port + p) >= hpriv->n_ports) 2900eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord break; 2901eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2); 2902eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (hc_cause & port_mask) 2903eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord ack_irqs |= (DMA_IRQ | DEV_IRQ) << p; 2904eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord } 2905a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord hc_mmio = mv_hc_base_from_port(mmio, port); 2906cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE); 2907a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = 1; 2908a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord } 29098f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord /* 2910a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Handle interrupts signalled for this port: 29118f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord */ 2912a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ); 2913a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (port_cause) 2914a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_port_intr(ap, port_cause); 291520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 2916a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return handled; 291720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 291820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2919a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lordstatic int mv_pci_error(struct ata_host *host, void __iomem *mmio) 2920bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 292102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 2922bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_port *ap; 2923bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 2924bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_eh_info *ehi; 2925bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int i, err_mask, printed = 0; 2926bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 err_cause; 2927bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2928cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord err_cause = readl(mmio + hpriv->irq_cause_offset); 2929bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2930a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause); 2931bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2932bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik DPRINTK("All regs @ PCI error\n"); 2933bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 2934bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2935cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, mmio + hpriv->irq_cause_offset); 2936bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2937bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik for (i = 0; i < host->n_ports; i++) { 2938bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ap = host->ports[i]; 2939936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo if (!ata_link_offline(&ap->link)) { 29409af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo ehi = &ap->link.eh_info; 2941bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 2942bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!printed++) 2943bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, 2944bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik "PCI err cause 0x%08x", err_cause); 2945bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_HOST_BUS; 2946cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo ehi->action = ATA_EH_RESET; 29479af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 2948bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 2949bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 2950bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 2951bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 2952bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2953bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 2954bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2955bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2956a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return 1; /* handled */ 2957bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2958bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 295905b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2960c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * mv_interrupt - Main interrupt event handler 296105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @irq: unused 296205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @dev_instance: private data; in this case the host structure 296305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 296405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read the read only register to determine if any host 296505b308e1df6d9d673daedb517969241f41278b52Brett Russ * controllers have pending interrupts. If so, call lower level 296605b308e1df6d9d673daedb517969241f41278b52Brett Russ * routine to handle. Also check for PCI errors which are only 296705b308e1df6d9d673daedb517969241f41278b52Brett Russ * reported here. 296805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 29698b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * LOCKING: 2970cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine holds the host lock while processing pending 297105b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts. 297205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 29737d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t mv_interrupt(int irq, void *dev_instance) 297420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2975cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = dev_instance; 2976f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 2977a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0; 29786d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI; 297996e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord u32 main_irq_cause, pending_irqs; 298020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2981646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord spin_lock(&host->lock); 29826d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 29836d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord /* for MSI: block new interrupts while in here */ 29846d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord if (using_msi) 29852b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_write_main_irq_mask(0, hpriv); 29866d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 29877368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_cause = readl(hpriv->main_irq_cause_addr); 298896e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord pending_irqs = main_irq_cause & hpriv->main_irq_mask; 2989352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 2990352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Deal with cases where we either have nothing pending, or have read 2991352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * a bogus register value which can indicate HW removal or PCI fault. 299220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2993a44253d24a97ec3efe601267274a5fb64d8696c1Mark Lord if (pending_irqs && main_irq_cause != 0xffffffffU) { 29941f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv))) 2995a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = mv_pci_error(host, hpriv->base); 2996a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord else 2997a44253d24a97ec3efe601267274a5fb64d8696c1Mark Lord handled = mv_host_intr(host, pending_irqs); 2998bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 29996d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 30006d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord /* for MSI: unmask; interrupt cause bits will retrigger now */ 30016d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord if (using_msi) 30022b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv); 30036d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 30049d51af7bd2f1d730cb6eeeb9ff837e3441ad4e07Mark Lord spin_unlock(&host->lock); 30059d51af7bd2f1d730cb6eeeb9ff837e3441ad4e07Mark Lord 300620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return IRQ_RETVAL(handled); 300720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 300820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3009c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic unsigned int mv5_scr_offset(unsigned int sc_reg_in) 3010c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 3011c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs; 3012c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3013c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik switch (sc_reg_in) { 3014c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_STATUS: 3015c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_ERROR: 3016c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_CONTROL: 3017c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = sc_reg_in * sizeof(u32); 3018c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 3019c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik default: 3020c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = 0xffffffffU; 3021c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 3022c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 3023c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return ofs; 3024c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3025c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 302682ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 3027c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 302882ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo struct mv_host_priv *hpriv = link->ap->host->private_data; 3029f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 303082ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 3031c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 3032c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3033da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 3034da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(addr + ofs); 3035da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 3036da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 3037da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 3038c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3039c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 304082ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 3041c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 304282ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo struct mv_host_priv *hpriv = link->ap->host->private_data; 3043f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 304482ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 3045c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 3046c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3047da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 30480d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo writelfl(val, addr + ofs); 3049da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 3050da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 3051da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 3052c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3053c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 30547bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 3055522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 30567bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara struct pci_dev *pdev = to_pci_dev(host->dev); 3057522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik int early_5080; 3058522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 305944c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 3060522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3061522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik if (!early_5080) { 3062522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 3063522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= (1 << 0); 3064522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 3065522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik } 3066522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 30677bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara mv_reset_pci_bus(host, mmio); 3068522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 3069522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3070522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 3071522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 3072cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x0fcfffff, mmio + FLASH_CTL); 3073522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 3074522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 307547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 3076ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 3077ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 3078c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 3079c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 3080c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3081c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 3082c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3083c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 3084c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 3085ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3086ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 308747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 3088ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 3089522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp; 3090522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3091cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0, mmio + GPIO_PORT_CTL); 3092522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3093522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 3094522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3095522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 3096522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= ~(1 << 0); 3097522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 3098ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3099ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 31002a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 31012a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 3102bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 3103c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, port); 3104c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 3105c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 3106c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 3107c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3108c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik if (fix_apm_sq) { 3109cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(phy_mmio + MV5_LTMODE); 3110c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= (1 << 19); 3111cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(tmp, phy_mmio + MV5_LTMODE); 3112c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3113cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(phy_mmio + MV5_PHY_CTL); 3114c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~0x3; 3115c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x1; 3116cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(tmp, phy_mmio + MV5_PHY_CTL); 3117c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 3118c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3119c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 3120c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~mask; 3121c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].pre; 3122c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].amps; 3123c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_MODE); 3124bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 3125bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3126c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3127c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 3128c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, port_mmio + (reg)) 3129c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 3130c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 3131c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 3132c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 3133c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3134e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 3135c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3136c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x028); /* command */ 3137cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x11f, port_mmio + EDMA_CFG); 3138c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x004); /* timer */ 3139c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x008); /* irq err cause */ 3140c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); /* irq err mask */ 3141c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); /* rq bah */ 3142c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); /* rq inp */ 3143c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); /* rq outp */ 3144c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x01c); /* respq bah */ 3145c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x024); /* respq outp */ 3146c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x020); /* respq inp */ 3147c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x02c); /* test control */ 3148cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 3149c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3150c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 3151c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3152c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, hc_mmio + (reg)) 3153c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3154c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc) 315547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik{ 3156c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 3157c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 3158c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3159c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); 3160c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); 3161c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); 3162c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); 3163c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3164c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(hc_mmio + 0x20); 3165c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= 0x1c1c1c1c; 3166c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x03030303; 3167c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, hc_mmio + 0x20); 3168c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3169c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 3170c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3171c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3172c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 3173c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 3174c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc, port; 3175c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3176c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (hc = 0; hc < n_hc; hc++) { 3177c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (port = 0; port < MV_PORTS_PER_HC; port++) 3178c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_hc_port(hpriv, mmio, 3179c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (hc * MV_PORTS_PER_HC) + port); 3180c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3181c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_one_hc(hpriv, mmio, hc); 3182c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 3183c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3184c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return 0; 318547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik} 318647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 3187101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 3188101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#define ZERO(reg) writel(0, mmio + (reg)) 31897bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 3190101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 319102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 3192101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 3193101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3194cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(mmio + MV_PCI_MODE); 3195101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0xff00ffff; 3196cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(tmp, mmio + MV_PCI_MODE); 3197101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3198101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_DISC_TIMER); 3199101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_MSI_TRIGGER); 3200cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); 3201101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_SERR_MASK); 3202cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ZERO(hpriv->irq_cause_offset); 3203cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ZERO(hpriv->irq_mask_offset); 3204101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_LOW_ADDRESS); 3205101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_HIGH_ADDRESS); 3206101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_ATTRIBUTE); 3207101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_COMMAND); 3208101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 3209101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 3210101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3211101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 3212101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 3213101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 3214101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3215101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik mv5_reset_flash(hpriv, mmio); 3216101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3217cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(mmio + GPIO_PORT_CTL); 3218101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0x3; 3219101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp |= (1 << 5) | (1 << 6); 3220cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(tmp, mmio + GPIO_PORT_CTL); 3221101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 3222101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3223101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik/** 3224101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * mv6_reset_hc - Perform the 6xxx global soft reset 3225101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * @mmio: base address of the HBA 3226101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 3227101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * This routine only applies to 6xxx parts. 3228101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 3229101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * LOCKING: 3230101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * Inherited from caller. 3231101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 3232c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3233c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 3234101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 3235cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord void __iomem *reg = mmio + PCI_MAIN_CMD_STS; 3236101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik int i, rc = 0; 3237101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 t; 3238101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3239101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* Following procedure defined in PCI "main command and status 3240101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * register" table. 3241101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 3242101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 3243101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | STOP_PCI_MASTER, reg); 3244101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3245101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik for (i = 0; i < 1000; i++) { 3246101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 3247101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 32482dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik if (PCI_MASTER_EMPTY & t) 3249101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik break; 3250101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3251101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(PCI_MASTER_EMPTY & t)) { 3252101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 3253101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 3254101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 3255101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3256101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3257101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* set reset */ 3258101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 3259101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 3260101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | GLOB_SFT_RST, reg); 3261101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 3262101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 3263101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 3264101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3265101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(GLOB_SFT_RST & t)) { 3266101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 3267101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 3268101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 3269101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3270101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3271101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 3272101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 3273101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 3274101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 3275101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 3276101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 3277101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while ((GLOB_SFT_RST & t) && (i-- > 0)); 3278101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3279101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (GLOB_SFT_RST & t) { 3280101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 3281101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 3282101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3283101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikdone: 3284101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik return rc; 3285101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 3286101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 328747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 3288ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 3289ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 3290ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *port_mmio; 3291ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik u32 tmp; 3292ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3293cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(mmio + RESET_CFG); 3294ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik if ((tmp & (1 << 0)) == 0) { 329547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->signal[idx].amps = 0x7 << 8; 3296ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = 0x1 << 5; 3297ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik return; 3298ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik } 3299ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3300ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik port_mmio = mv_port_base(mmio, idx); 3301ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(port_mmio + PHY_MODE2); 3302ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3303ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3304ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3305ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3306ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 330747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 3308ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 3309cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x00000060, mmio + GPIO_PORT_CTL); 3310ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3311ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3312c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 33132a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 3314bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 3315c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 3316c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3317bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 331847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik int fix_phy_mode2 = 331947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 3320bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik int fix_phy_mode4 = 332147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 33228c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord u32 m2, m3; 332347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 332447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (fix_phy_mode2) { 332547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 332647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 332747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 |= (1 << 31); 332847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 332947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 333047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 333147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 333247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 333347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~((1 << 16) | (1 << 31)); 333447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 333547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 333647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 333747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 333847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 33398c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord /* 33408c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord * Gen-II/IIe PHY_MODE3 errata RM#2: 33418c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord * Achieves better receiver noise performance than the h/w default: 33428c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord */ 33438c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord m3 = readl(port_mmio + PHY_MODE3); 33448c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord m3 = (m3 & 0x1f) | (0x5555601 << 5); 3345bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 33460388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord /* Guideline 88F5182 (GL# SATA-S11) */ 33470388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord if (IS_SOC(hpriv)) 33480388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord m3 &= ~0x1c; 33490388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord 3350bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (fix_phy_mode4) { 3351ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord u32 m4 = readl(port_mmio + PHY_MODE4); 3352ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord /* 3353ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * Enforce reserved-bit restrictions on GenIIe devices only. 3354ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * For earlier chipsets, force only the internal config field 3355ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * (workaround for errata FEr SATA#10 part 1). 3356ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord */ 33578c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord if (IS_GEN_IIE(hpriv)) 3358ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES; 3359ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord else 3360ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE; 33618c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord writel(m4, port_mmio + PHY_MODE4); 3362bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3363b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord /* 3364b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * Workaround for 60x1-B2 errata SATA#13: 3365b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3, 3366b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * so we must always rewrite PHY_MODE3 after PHY_MODE4. 3367ba68460b8e019dfd9c73ab69f5ed163a8b24e296Mark Lord * Or ensure we use writelfl() when writing PHY_MODE4. 3368b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord */ 3369b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord writel(m3, port_mmio + PHY_MODE3); 3370bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3371bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik /* Revert values of pre-emphasis and signal amps to the saved ones */ 3372bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 3373bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3374bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 &= ~MV_M2_PREAMP_MASK; 33752a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].amps; 33762a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].pre; 337747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 3378bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3379e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* according to mvSata 3.6.1, some IIE values are fixed */ 3380e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (IS_GEN_IIE(hpriv)) { 3381e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 &= ~0xC30FF01F; 3382e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 |= 0x0000900F; 3383e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 3384e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 3385bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 3386bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 3387bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3388f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* TODO: use the generic LED interface to configure the SATA Presence */ 3389f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* & Acitivy LEDs on the board */ 3390f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 3391f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3392f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3393f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 3394f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3395f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3396f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 3397f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3398f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3399f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio; 3400f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara u32 tmp; 3401f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3402f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara port_mmio = mv_port_base(mmio, idx); 3403f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(port_mmio + PHY_MODE2); 3404f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3405f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3406f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3407f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3408f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3409f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 3410f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, port_mmio + (reg)) 3411f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 3412f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int port) 3413f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3414f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio = mv_port_base(mmio, port); 3415f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3416e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 3417f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3418f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x028); /* command */ 3419cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x101f, port_mmio + EDMA_CFG); 3420f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x004); /* timer */ 3421f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x008); /* irq err cause */ 3422f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); /* irq err mask */ 3423f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); /* rq bah */ 3424f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); /* rq inp */ 3425f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x018); /* rq outp */ 3426f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x01c); /* respq bah */ 3427f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x024); /* respq outp */ 3428f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x020); /* respq inp */ 3429f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x02c); /* test control */ 3430d7b0c143693bcbf391d2be235e150b97bfd8f9baSaeed Bishara writel(0x800, port_mmio + EDMA_IORDY_TMOUT); 3431f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3432f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3433f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 3434f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3435f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, hc_mmio + (reg)) 3436f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 3437f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3438f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3439f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *hc_mmio = mv_hc_base(mmio, 0); 3440f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3441f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); 3442f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); 3443f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); 3444f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3445f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3446f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3447f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 3448f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3449f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 3450f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc) 3451f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3452f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int port; 3453f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3454f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara for (port = 0; port < hpriv->n_ports; port++) 3455f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_hc_port(hpriv, mmio, port); 3456f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3457f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_one_hc(hpriv, mmio); 3458f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3459f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 3460f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3461f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3462f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 3463f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3464f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3465f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 3466f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3467f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3468f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 3469f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3470f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 3471f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3472f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 347329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayrstatic void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, 347429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr void __iomem *mmio, unsigned int port) 347529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr{ 347629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr void __iomem *port_mmio = mv_port_base(mmio, port); 347729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr u32 reg; 347829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 347929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg = readl(port_mmio + PHY_MODE3); 348029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */ 348129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg |= (0x1 << 27); 348229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */ 348329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg |= (0x1 << 29); 348429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr writel(reg, port_mmio + PHY_MODE3); 348529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 348629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg = readl(port_mmio + PHY_MODE4); 348729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */ 348829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg |= (0x1 << 16); 348929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr writel(reg, port_mmio + PHY_MODE4); 349029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 349129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg = readl(port_mmio + PHY_MODE9_GEN2); 349229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */ 349329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg |= 0x8; 349429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */ 349529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr writel(reg, port_mmio + PHY_MODE9_GEN2); 349629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 349729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg = readl(port_mmio + PHY_MODE9_GEN1); 349829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */ 349929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg |= 0x8; 350029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */ 350129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr writel(reg, port_mmio + PHY_MODE9_GEN1); 350229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr} 350329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 350429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr/** 350529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr * soc_is_65 - check if the soc is 65 nano device 350629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr * 350729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr * Detect the type of the SoC, this is done by reading the PHYCFG_OFS 350829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr * register, this register should contain non-zero value and it exists only 350929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr * in the 65 nano devices, when reading it from older devices we get 0. 351029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr */ 351129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayrstatic bool soc_is_65n(struct mv_host_priv *hpriv) 351229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr{ 351329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr void __iomem *port0_mmio = mv_port_base(hpriv->base, 0); 351429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 351529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr if (readl(port0_mmio + PHYCFG_OFS)) 351629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr return true; 351729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr return false; 351829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr} 351929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 35208e7decdb8b132ee970a2636931b7653dec6af472Mark Lordstatic void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) 3521b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord{ 3522cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 ifcfg = readl(port_mmio + SATA_IFCFG); 3523b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 35248e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */ 3525b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (want_gen2i) 35268e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg |= (1 << 7); /* enable gen2i speed */ 3527cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(ifcfg, port_mmio + SATA_IFCFG); 3528b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord} 3529b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 3530e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 3531c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no) 3532c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 3533c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port_no); 3534c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 35358e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* 35368e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * The datasheet warns against setting EDMA_RESET when EDMA is active 35378e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * (but doesn't say what the problem might be). So we first try 35388e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * to disable the EDMA engine before doing the EDMA_RESET operation. 35398e7decdb8b132ee970a2636931b7653dec6af472Mark Lord */ 35400d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord mv_stop_edma_engine(port_mmio); 3541cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD); 3542c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3543b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (!IS_GEN_I(hpriv)) { 35448e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* Enable 3.0gb/s link speed: this survives EDMA_RESET */ 35458e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(port_mmio, 1); 3546c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 3547b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord /* 35488e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * Strobing EDMA_RESET here causes a hard reset of the SATA transport, 3549b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * link, and physical layers. It resets all SATA interface registers 3550cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord * (except for SATA_IFCFG), and issues a COMRESET to the dev. 3551c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik */ 3552cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD); 3553b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord udelay(25); /* allow reset propagation */ 3554cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, port_mmio + EDMA_CMD); 3555c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3556c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->ops->phy_errata(hpriv, mmio, port_no); 3557c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3558ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) 3559c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mdelay(1); 3560c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3561c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3562e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp) 356320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 3564e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (sata_pmp_supported(ap)) { 3565e49856d82a887ce365637176f9f99ab68076eae8Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 3566cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 reg = readl(port_mmio + SATA_IFCTL); 3567e49856d82a887ce365637176f9f99ab68076eae8Mark Lord int old = reg & 0xf; 356822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 3569e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (old != pmp) { 3570e49856d82a887ce365637176f9f99ab68076eae8Mark Lord reg = (reg & ~0xf) | pmp; 3571cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(reg, port_mmio + SATA_IFCTL); 3572e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 357322374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik } 357420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 357520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3576e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 3577e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 357822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik{ 3579e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 3580e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return sata_std_hardreset(link, class, deadline); 3581e49856d82a887ce365637176f9f99ab68076eae8Mark Lord} 3582bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3583e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 3584e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 3585e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 3586e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 3587e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return ata_sff_softreset(link, class, deadline); 358822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik} 358922374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 3590cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 3591bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned long deadline) 359231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 3593cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo struct ata_port *ap = link->ap; 3594bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 3595b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 3596f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 35970d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord int rc, attempts = 0, extra = 0; 35980d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord u32 sstatus; 35990d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord bool online; 360031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3601e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, ap->port_no); 3602b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 3603d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= 3604d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 3605bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 36060d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Workaround for errata FEr SATA#10 (part 2) */ 36070d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord do { 360817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord const unsigned long *timing = 360917c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord sata_ehc_deb_timing(&link->eh_context); 3610bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 361117c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord rc = sata_link_hardreset(link, timing, deadline + extra, 361217c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord &online, NULL); 36139dcffd99d0b1c0c1b8b2c0f85d240e791eca1055Mark Lord rc = online ? -EAGAIN : rc; 361417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord if (rc) 36150d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord return rc; 36160d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord sata_scr_read(link, SCR_STATUS, &sstatus); 36170d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 36180d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Force 1.5gb/s link speed and try again */ 36198e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(mv_ap_base(ap), 0); 36200d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (time_after(jiffies + HZ, deadline)) 36210d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord extra = HZ; /* only extend it once, max */ 36220d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } 36230d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); 362408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_save_cached_regs(ap); 362566e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord mv_edma_cfg(ap, 0, 0); 3626bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 362717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord return rc; 3628bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 3629bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3630bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap) 3631bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 36321cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord mv_stop_edma(ap); 3633c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_enable_port_irqs(ap, 0); 3634bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 3635bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3636bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap) 3637bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 3638f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 3639c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int port = ap->port_no; 3640c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int hardport = mv_hardport_from_port(port); 36411cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); 3642bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 3643c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 hc_irq_cause; 3644bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3645bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA errors on this port */ 3646cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 3647bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3648bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear pending irq events */ 3649cae6edc3b5a536119374a5439d9b253cb26f05e1Mark Lord hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 3650cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); 3651bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 365288e675e193159b9891c1c576de4348eaf490f5d0Mark Lord mv_enable_port_irqs(ap, ERR_IRQ); 365331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 365431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 365505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 365605b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_init - Perform some early initialization on a single port. 365705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port: libata data structure storing shadow register addresses 365805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port_mmio: base address of the port 365905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 366005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Initialize shadow register mmio addresses, clear outstanding 366105b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts on the port, and unmask interrupts for the future 366205b308e1df6d9d673daedb517969241f41278b52Brett Russ * start of the port. 366305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 366405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 366505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 366605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 366731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 366820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 3669cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord void __iomem *serr, *shd_base = port_mmio + SHD_BLK; 367031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 36718b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik /* PIO related setup 367231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 367331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 36748b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->error_addr = 367531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 367631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 367731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 367831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 367931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 368031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 36818b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->status_addr = 368231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 368331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* special case: control/altstatus doesn't have ATA_REG_ address */ 3684cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST; 368531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 368631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding port interrupt conditions */ 3687cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord serr = port_mmio + mv_scr_offset(SCR_ERROR); 3688cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(readl(serr), serr); 3689cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 369031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3691646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord /* unmask all non-transient EDMA error interrupts */ 3692cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK); 369320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 36948b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 3695cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(port_mmio + EDMA_CFG), 3696cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(port_mmio + EDMA_ERR_IRQ_CAUSE), 3697cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(port_mmio + EDMA_ERR_IRQ_MASK)); 369820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 369920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3700616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic unsigned int mv_in_pcix_mode(struct ata_host *host) 3701616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 3702616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 3703616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 3704616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 3705616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 37061f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (IS_SOC(hpriv) || !IS_PCIE(hpriv)) 3707616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not PCI-X capable */ 3708cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord reg = readl(mmio + MV_PCI_MODE); 3709616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if ((reg & MV_PCI_MODE_MASK) == 0) 3710616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* conventional PCI mode */ 3711616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* chip is in PCI-X mode */ 3712616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 3713616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 3714616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic int mv_pci_cut_through_okay(struct ata_host *host) 3715616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 3716616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 3717616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 3718616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 3719616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 3720616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (!mv_in_pcix_mode(host)) { 3721cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord reg = readl(mmio + MV_PCI_COMMAND); 3722cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord if (reg & MV_PCI_COMMAND_MRDTRIG) 3723616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not okay */ 3724616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord } 3725616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* okay */ 3726616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 3727616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 372865ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lordstatic void mv_60x1b2_errata_pci7(struct ata_host *host) 372965ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord{ 373065ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord struct mv_host_priv *hpriv = host->private_data; 373165ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord void __iomem *mmio = hpriv->base; 373265ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord 373365ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord /* workaround for 60x1-B2 errata PCI#7 */ 373465ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord if (mv_in_pcix_mode(host)) { 3735cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 reg = readl(mmio + MV_PCI_COMMAND); 3736cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND); 373765ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord } 373865ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord} 373965ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord 37404447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_chip_id(struct ata_host *host, unsigned int board_idx) 3741bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 37424447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 37434447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 3744bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 3745bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 37465796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik switch (board_idx) { 374747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case chip_5080: 374847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 3749ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 375047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 375144c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 375247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x1: 375347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 375447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 375547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 375647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 375747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 375847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 3759a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches dev_warn(&pdev->dev, 3760a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches "Applying 50XXB2 workarounds to unknown rev\n"); 376147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 376247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 376347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 376447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 376547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 3766bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_504x: 3767bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_508x: 376847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 3769ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 3770bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 377144c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 377247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x0: 377347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 377447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 377547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 377647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 377747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 377847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 3779a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches dev_warn(&pdev->dev, 3780a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches "Applying B2 workarounds to unknown rev\n"); 378147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 378247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 3783bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3784bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3785bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3786bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_604x: 3787bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_608x: 378847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv6xxx_ops; 3789ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_II; 379047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 379144c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 379247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x7: 379365ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord mv_60x1b2_errata_pci7(host); 379447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 379547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 379647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x9: 379747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3798bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3799bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 3800a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches dev_warn(&pdev->dev, 3801a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches "Applying B2 workarounds to unknown rev\n"); 380247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 3803bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3804bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3805bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3806bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3807e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_7042: 3808616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH; 3809306b30f74d37f289033c696285e07ce0158a5d7bMark Lord if (pdev->vendor == PCI_VENDOR_ID_TTI && 3810306b30f74d37f289033c696285e07ce0158a5d7bMark Lord (pdev->device == 0x2300 || pdev->device == 0x2310)) 3811306b30f74d37f289033c696285e07ce0158a5d7bMark Lord { 38124e5200334e03e5620aa19d538300c13db270a063Mark Lord /* 38134e5200334e03e5620aa19d538300c13db270a063Mark Lord * Highpoint RocketRAID PCIe 23xx series cards: 38144e5200334e03e5620aa19d538300c13db270a063Mark Lord * 38154e5200334e03e5620aa19d538300c13db270a063Mark Lord * Unconfigured drives are treated as "Legacy" 38164e5200334e03e5620aa19d538300c13db270a063Mark Lord * by the BIOS, and it overwrites sector 8 with 38174e5200334e03e5620aa19d538300c13db270a063Mark Lord * a "Lgcy" metadata block prior to Linux boot. 38184e5200334e03e5620aa19d538300c13db270a063Mark Lord * 38194e5200334e03e5620aa19d538300c13db270a063Mark Lord * Configured drives (RAID or JBOD) leave sector 8 38204e5200334e03e5620aa19d538300c13db270a063Mark Lord * alone, but instead overwrite a high numbered 38214e5200334e03e5620aa19d538300c13db270a063Mark Lord * sector for the RAID metadata. This sector can 38224e5200334e03e5620aa19d538300c13db270a063Mark Lord * be determined exactly, by truncating the physical 38234e5200334e03e5620aa19d538300c13db270a063Mark Lord * drive capacity to a nice even GB value. 38244e5200334e03e5620aa19d538300c13db270a063Mark Lord * 38254e5200334e03e5620aa19d538300c13db270a063Mark Lord * RAID metadata is at: (dev->n_sectors & ~0xfffff) 38264e5200334e03e5620aa19d538300c13db270a063Mark Lord * 38274e5200334e03e5620aa19d538300c13db270a063Mark Lord * Warn the user, lest they think we're just buggy. 38284e5200334e03e5620aa19d538300c13db270a063Mark Lord */ 38294e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 38304e5200334e03e5620aa19d538300c13db270a063Mark Lord " BIOS CORRUPTS DATA on all attached drives," 38314e5200334e03e5620aa19d538300c13db270a063Mark Lord " regardless of if/how they are configured." 38324e5200334e03e5620aa19d538300c13db270a063Mark Lord " BEWARE!\n"); 38334e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": For data safety, do not" 38344e5200334e03e5620aa19d538300c13db270a063Mark Lord " use sectors 8-9 on \"Legacy\" drives," 38354e5200334e03e5620aa19d538300c13db270a063Mark Lord " and avoid the final two gigabytes on" 38364e5200334e03e5620aa19d538300c13db270a063Mark Lord " all RocketRAID BIOS initialized drives.\n"); 3837306b30f74d37f289033c696285e07ce0158a5d7bMark Lord } 38388e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* drop through */ 3839e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_6042: 3840e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hpriv->ops = &mv6xxx_ops; 3841e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_GEN_IIE; 3842616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (board_idx == chip_6042 && mv_pci_cut_through_okay(host)) 3843616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_CUT_THROUGH; 3844e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 384544c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 38465cf73bfb061552aa18d816d2859409be9ace5306Mark Lord case 0x2: /* Rev.B0: the first/only public release */ 3847e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3848e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3849e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik default: 3850a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches dev_warn(&pdev->dev, 3851a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches "Applying 60X1C0 workarounds to unknown rev\n"); 3852e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3853e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3854e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 3855e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3856f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara case chip_soc: 385729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr if (soc_is_65n(hpriv)) 385829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr hpriv->ops = &mv_soc_65n_ops; 385929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr else 386029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr hpriv->ops = &mv_soc_ops; 3861eb3a55a9f43f0f8e770c2abf70e65bdda2d5ff1eSaeed Bishara hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE | 3862eb3a55a9f43f0f8e770c2abf70e65bdda2d5ff1eSaeed Bishara MV_HP_ERRATA_60X1C0; 3863f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara break; 3864e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 3865bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 3866a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches dev_err(host->dev, "BUG: invalid board index %u\n", board_idx); 3867bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 1; 3868bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3869bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3870bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik hpriv->hp_flags = hp_flags; 387102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord if (hp_flags & MV_HP_PCIE) { 3872cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->irq_cause_offset = PCIE_IRQ_CAUSE; 3873cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->irq_mask_offset = PCIE_IRQ_MASK; 387402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 387502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } else { 3876cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->irq_cause_offset = PCI_IRQ_CAUSE; 3877cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->irq_mask_offset = PCI_IRQ_MASK; 387802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 387902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } 3880bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3881bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 0; 3882bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 3883bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 388405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 388547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik * mv_init_host - Perform some early initialization of the host. 38864447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to initialize 388705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 388805b308e1df6d9d673daedb517969241f41278b52Brett Russ * If possible, do an early global reset of the host. Then do 388905b308e1df6d9d673daedb517969241f41278b52Brett Russ * our port init and clear/unmask all/relevant host interrupts. 389005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 389105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 389205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 389305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 38941bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bisharastatic int mv_init_host(struct ata_host *host) 389520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 389620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ int rc = 0, n_hc, port, hc; 38974447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 3898f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 389947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 39001bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bishara rc = mv_chip_id(host, hpriv->board_idx); 3901bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (rc) 3902352fab701ca4753dd005b67ce5e512be944eb591Mark Lord goto done; 3903f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 39041f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (IS_SOC(hpriv)) { 3905cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE; 3906cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK; 39071f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord } else { 3908cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE; 3909cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK; 3910f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 3911352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 39125d0fb2e730e2085021cf5c8b6d14983e92aea75bThomas Reitmayr /* initialize shadow irq mask with register's value */ 39135d0fb2e730e2085021cf5c8b6d14983e92aea75bThomas Reitmayr hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr); 39145d0fb2e730e2085021cf5c8b6d14983e92aea75bThomas Reitmayr 3915352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* global interrupt mask: 0 == mask everything */ 3916c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_set_main_irq_mask(host, ~0, 0); 3917bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 39184447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_hc = mv_get_hc_count(host->ports[0]->flags); 3919bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 39204447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) 392129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr if (hpriv->ops->read_preamp) 392229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr hpriv->ops->read_preamp(hpriv, port, mmio); 392320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3924c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 392547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (rc) 392620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ goto done; 392720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3928522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik hpriv->ops->reset_flash(hpriv, mmio); 39297bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara hpriv->ops->reset_bus(host, mmio); 393047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->enable_leds(hpriv, mmio); 393120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 39324447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) { 3933cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo struct ata_port *ap = host->ports[port]; 39342a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 3935cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 3936cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo mv_port_init(&ap->ioaddr, port_mmio); 393720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 393820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 393920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hc; hc++) { 394031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 394131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 394231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 394331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ "(before clear)=0x%08x\n", hc, 3944cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(hc_mmio + HC_CFG), 3945cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(hc_mmio + HC_IRQ_CAUSE)); 394631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 394731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding hc interrupt conditions */ 3948cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, hc_mmio + HC_IRQ_CAUSE); 394920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 395020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 395144c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord if (!IS_SOC(hpriv)) { 395244c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord /* Clear any currently outstanding host interrupt conditions */ 3953cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, mmio + hpriv->irq_cause_offset); 395431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 395544c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord /* and unmask interrupt generation for host regs */ 3956cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset); 395744c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord } 395851de32d200b21333950abc52ea1e589bc4eecef7Mark Lord 39596be96ac15e4d913e1f48299db083ada5321803b2Mark Lord /* 39606be96ac15e4d913e1f48299db083ada5321803b2Mark Lord * enable only global host interrupts for now. 39616be96ac15e4d913e1f48299db083ada5321803b2Mark Lord * The per-port interrupts get done later as ports are set up. 39626be96ac15e4d913e1f48299db083ada5321803b2Mark Lord */ 39636be96ac15e4d913e1f48299db083ada5321803b2Mark Lord mv_set_main_irq_mask(host, 0, PCI_ERR); 39642b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_set_irq_coalescing(host, irq_coalescing_io_count, 39652b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord irq_coalescing_usecs); 3966f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharadone: 3967f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3968f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3969fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik 3970fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradleystatic int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 3971fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley{ 3972fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 3973fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRQB_Q_SZ, 0); 3974fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crqb_pool) 3975fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3976fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3977fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 3978fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRPB_Q_SZ, 0); 3979fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crpb_pool) 3980fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3981fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3982fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 3983fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_SG_TBL_SZ, 0); 3984fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->sg_tbl_pool) 3985fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3986fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3987fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return 0; 3988fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley} 3989fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 399015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhekstatic void mv_conf_mbus_windows(struct mv_host_priv *hpriv, 399163a9332b232bdab0df6ef18a9f39e8d58a82bda4Andrew Lunn const struct mbus_dram_target_info *dram) 399215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek{ 399315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek int i; 399415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 399515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < 4; i++) { 399615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_CTRL(i)); 399715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_BASE(i)); 399815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 399915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 400015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < dram->num_cs; i++) { 400163a9332b232bdab0df6ef18a9f39e8d58a82bda4Andrew Lunn const struct mbus_dram_window *cs = dram->cs + i; 400215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 400315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(((cs->size - 1) & 0xffff0000) | 400415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (cs->mbus_attr << 8) | 400515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (dram->mbus_dram_target_id << 4) | 1, 400615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek hpriv->base + WINDOW_CTRL(i)); 400715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(cs->base, hpriv->base + WINDOW_BASE(i)); 400815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 400915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek} 401015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 4011f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/** 4012f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_probe - handle a positive probe of an soc Marvell 4013f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * host 4014f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device found 4015f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 4016f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * LOCKING: 4017f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Inherited from caller. 4018f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 4019f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev) 4020f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 4021f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct mv_sata_platform_data *mv_platform_data; 402263a9332b232bdab0df6ef18a9f39e8d58a82bda4Andrew Lunn const struct mbus_dram_target_info *dram; 4023f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct ata_port_info *ppi[] = 4024f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { &mv_port_info[chip_soc], NULL }; 4025f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host; 4026f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv; 4027f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct resource *res; 402899b80e97710ae2e53c951acfdd956e9f38e36646Dan Carpenter int n_ports = 0; 402999b80e97710ae2e53c951acfdd956e9f38e36646Dan Carpenter int rc; 403020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 403106296a1e684bcd40b9a28d5d8030809e4295528bJoe Perches ata_print_version_once(&pdev->dev, DRV_VERSION); 4032bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 4033f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 4034f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Simple resource validation .. 4035f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 4036f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (unlikely(pdev->num_resources != 2)) { 4037f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_err(&pdev->dev, "invalid number of resources\n"); 4038f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 4039f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 4040f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4041f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 4042f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Get the register base first 4043f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 4044f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4045f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (res == NULL) 4046f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 4047f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4048f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* allocate host */ 4049f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_platform_data = pdev->dev.platform_data; 4050f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara n_ports = mv_platform_data->n_ports; 4051f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4052f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 4053f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 4054f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4055f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!host || !hpriv) 4056f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -ENOMEM; 4057f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->private_data = hpriv; 4058f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 40591bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bishara hpriv->board_idx = chip_soc; 4060f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4061f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->iomap = NULL; 4062f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara hpriv->base = devm_ioremap(&pdev->dev, res->start, 4063041b5eac254107cd3ba60034c38a411531cc64eeJulia Lawall resource_size(res)); 4064cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->base -= SATAHC0_REG_BASE; 4065f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4066c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#if defined(CONFIG_HAVE_CLK) 4067c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara hpriv->clk = clk_get(&pdev->dev, NULL); 4068c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara if (IS_ERR(hpriv->clk)) 4069c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara dev_notice(&pdev->dev, "cannot get clkdev\n"); 4070c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara else 4071c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara clk_enable(hpriv->clk); 4072c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#endif 4073c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara 407415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek /* 407515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek * (Re-)program MBUS remapping windows if we are asked to. 407615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek */ 407763a9332b232bdab0df6ef18a9f39e8d58a82bda4Andrew Lunn dram = mv_mbus_dram_info(); 407863a9332b232bdab0df6ef18a9f39e8d58a82bda4Andrew Lunn if (dram) 407963a9332b232bdab0df6ef18a9f39e8d58a82bda4Andrew Lunn mv_conf_mbus_windows(hpriv, dram); 408015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 4081fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley rc = mv_create_dma_pools(hpriv, &pdev->dev); 4082fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (rc) 4083c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara goto err; 4084fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 4085f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* initialize adapter */ 40861bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bishara rc = mv_init_host(host); 4087f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc) 4088c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara goto err; 4089f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4090a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches dev_info(&pdev->dev, "slots %u ports %d\n", 4091a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches (unsigned)MV_MAX_Q_DEPTH, host->n_ports); 4092f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4093c00a4c9d247a3a24190d2f27ab9b23424d8b082cSergei Shtylyov rc = ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, 4094c00a4c9d247a3a24190d2f27ab9b23424d8b082cSergei Shtylyov IRQF_SHARED, &mv6_sht); 4095c00a4c9d247a3a24190d2f27ab9b23424d8b082cSergei Shtylyov if (!rc) 4096c00a4c9d247a3a24190d2f27ab9b23424d8b082cSergei Shtylyov return 0; 4097c00a4c9d247a3a24190d2f27ab9b23424d8b082cSergei Shtylyov 4098c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bisharaerr: 4099c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#if defined(CONFIG_HAVE_CLK) 4100c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara if (!IS_ERR(hpriv->clk)) { 4101c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara clk_disable(hpriv->clk); 4102c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara clk_put(hpriv->clk); 4103c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara } 4104c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#endif 4105c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara 4106c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara return rc; 4107f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 4108f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4109f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* 4110f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 4111f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_remove - unplug a platform interface 4112f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device 4113f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 4114f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * A platform bus SATA device has been unplugged. Perform the needed 4115f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * cleanup. Also called on module unload for any active devices. 4116f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 4117f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev) 4118f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 4119d86619211ed3cdf4f6abff984774b65314aba0feSergei Shtylyov struct ata_host *host = platform_get_drvdata(pdev); 4120c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#if defined(CONFIG_HAVE_CLK) 4121c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 4122c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#endif 4123f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_host_detach(host); 4124c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara 4125c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#if defined(CONFIG_HAVE_CLK) 4126c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara if (!IS_ERR(hpriv->clk)) { 4127c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara clk_disable(hpriv->clk); 4128c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara clk_put(hpriv->clk); 4129c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara } 4130c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#endif 4131f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 413220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 413320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 41346481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara#ifdef CONFIG_PM 41356481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bisharastatic int mv_platform_suspend(struct platform_device *pdev, pm_message_t state) 41366481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara{ 4137d86619211ed3cdf4f6abff984774b65314aba0feSergei Shtylyov struct ata_host *host = platform_get_drvdata(pdev); 41386481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara if (host) 41396481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara return ata_host_suspend(host, state); 41406481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara else 41416481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara return 0; 41426481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara} 41436481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara 41446481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bisharastatic int mv_platform_resume(struct platform_device *pdev) 41456481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara{ 4146d86619211ed3cdf4f6abff984774b65314aba0feSergei Shtylyov struct ata_host *host = platform_get_drvdata(pdev); 414763a9332b232bdab0df6ef18a9f39e8d58a82bda4Andrew Lunn const struct mbus_dram_target_info *dram; 41486481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara int ret; 41496481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara 41506481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara if (host) { 41516481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 415263a9332b232bdab0df6ef18a9f39e8d58a82bda4Andrew Lunn 41536481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara /* 41546481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara * (Re-)program MBUS remapping windows if we are asked to. 41556481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara */ 415663a9332b232bdab0df6ef18a9f39e8d58a82bda4Andrew Lunn dram = mv_mbus_dram_info(); 415763a9332b232bdab0df6ef18a9f39e8d58a82bda4Andrew Lunn if (dram) 415863a9332b232bdab0df6ef18a9f39e8d58a82bda4Andrew Lunn mv_conf_mbus_windows(hpriv, dram); 41596481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara 41606481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara /* initialize adapter */ 41611bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bishara ret = mv_init_host(host); 41626481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara if (ret) { 41636481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara printk(KERN_ERR DRV_NAME ": Error during HW init\n"); 41646481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara return ret; 41656481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara } 41666481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara ata_host_resume(host); 41676481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara } 41686481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara 41696481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara return 0; 41706481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara} 41716481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara#else 41726481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara#define mv_platform_suspend NULL 41736481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara#define mv_platform_resume NULL 41746481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara#endif 41756481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara 4176f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic struct platform_driver mv_platform_driver = { 4177f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_platform_probe, 4178f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .remove = __devexit_p(mv_platform_remove), 41796481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara .suspend = mv_platform_suspend, 41806481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara .resume = mv_platform_resume, 4181f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .driver = { 4182f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .name = DRV_NAME, 4183f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .owner = THIS_MODULE, 4184f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 4185f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 4186f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4187f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 41887bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 4189f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 4190f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent); 4191b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara#ifdef CONFIG_PM 4192b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bisharastatic int mv_pci_device_resume(struct pci_dev *pdev); 4193b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara#endif 4194f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 41957bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 41967bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic struct pci_driver mv_pci_driver = { 41977bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .name = DRV_NAME, 41987bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .id_table = mv_pci_tbl, 4199f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_pci_init_one, 42007bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .remove = ata_pci_remove_one, 4201b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara#ifdef CONFIG_PM 4202b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara .suspend = ata_pci_device_suspend, 4203b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara .resume = mv_pci_device_resume, 4204b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara#endif 4205b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara 42067bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara}; 42077bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 42087bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* move to PCI layer or libata core? */ 42097bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int pci_go_64(struct pci_dev *pdev) 42107bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara{ 42117bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc; 42127bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 42136a35528a8346f6e6fd32ed7e51f04d1fa4ca2c01Yang Hongyang if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 42146a35528a8346f6e6fd32ed7e51f04d1fa4ca2c01Yang Hongyang rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 42157bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 4216284901a90a9e0b812ca3f5f852cbbfb60d10249dYang Hongyang rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 42177bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 4218a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches dev_err(&pdev->dev, 4219a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches "64-bit DMA enable failed\n"); 42207bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 42217bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 42227bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 42237bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } else { 4224284901a90a9e0b812ca3f5f852cbbfb60d10249dYang Hongyang rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 42257bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 4226a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches dev_err(&pdev->dev, "32-bit DMA enable failed\n"); 42277bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 42287bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 4229284901a90a9e0b812ca3f5f852cbbfb60d10249dYang Hongyang rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 42307bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 4231a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches dev_err(&pdev->dev, 4232a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches "32-bit consistent DMA enable failed\n"); 42337bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 42347bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 42357bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 42367bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 42377bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 42387bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara} 42397bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 424005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 424105b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_print_info - Dump key info to kernel log for perusal. 42424447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to print info about 424305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 424405b308e1df6d9d673daedb517969241f41278b52Brett Russ * FIXME: complete this. 424505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 424605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 424705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 424805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 42494447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic void mv_print_info(struct ata_host *host) 425031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 42514447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 42524447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 425344c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok u8 scc; 4254c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik const char *scc_s, *gen; 425531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 425631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Use this to determine the HW stepping of the chip so we know 425731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * what errata to workaround 425831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 425931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 426031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (scc == 0) 426131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "SCSI"; 426231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else if (scc == 0x01) 426331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "RAID"; 426431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else 4265c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik scc_s = "?"; 4266c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik 4267c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik if (IS_GEN_I(hpriv)) 4268c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "I"; 4269c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_II(hpriv)) 4270c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "II"; 4271c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_IIE(hpriv)) 4272c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "IIE"; 4273c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else 4274c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "?"; 427531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 4276a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches dev_info(&pdev->dev, "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 4277a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 4278a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 427931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 428031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 428105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 4282f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_pci_init_one - handle a positive probe of a PCI Marvell host 428305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pdev: PCI device found 428405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ent: PCI device ID entry for the matched host 428505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 428605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 428705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 428805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 4289f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 4290f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent) 429120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 429220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int board_idx = (unsigned int)ent->driver_data; 42934447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 42944447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct ata_host *host; 42954447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv; 4296c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara int n_ports, port, rc; 429720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 429806296a1e684bcd40b9a28d5d8030809e4295528bJoe Perches ata_print_version_once(&pdev->dev, DRV_VERSION); 429920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 43004447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* allocate host */ 43014447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 43024447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 43034447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 43044447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 43054447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (!host || !hpriv) 43064447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return -ENOMEM; 43074447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->private_data = hpriv; 4308f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 43091bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bishara hpriv->board_idx = board_idx; 43104447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 43114447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* acquire resources */ 431224dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo rc = pcim_enable_device(pdev); 431324dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 431420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return rc; 431520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 43160d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 43170d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc == -EBUSY) 431824dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pcim_pin_device(pdev); 43190d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc) 432024dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 43214447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->iomap = pcim_iomap_table(pdev); 4322f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base = host->iomap[MV_PRIMARY_BAR]; 432320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4324d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik rc = pci_go_64(pdev); 4325d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik if (rc) 4326d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik return rc; 4327d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik 4328da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord rc = mv_create_dma_pools(hpriv, &pdev->dev); 4329da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (rc) 4330da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return rc; 4331da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 4332c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara for (port = 0; port < host->n_ports; port++) { 4333c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara struct ata_port *ap = host->ports[port]; 4334c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara void __iomem *port_mmio = mv_port_base(hpriv->base, port); 4335c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara unsigned int offset = port_mmio - hpriv->base; 4336c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara 4337c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 4338c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 4339c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara } 4340c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara 434120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* initialize adapter */ 43421bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bishara rc = mv_init_host(host); 434324dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 434424dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 434520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 43466d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord /* Enable message-switched interrupts, if requested */ 43476d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord if (msi && pci_enable_msi(pdev) == 0) 43486d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord hpriv->hp_flags |= MV_HP_FLAG_MSI; 434920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 435031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 43514447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo mv_print_info(host); 435220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 43534447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo pci_set_master(pdev); 4354ea8b4db97aa41a66c05daa4055a1974692ccd52dJeff Garzik pci_try_set_mwi(pdev); 43554447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 4356c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 435720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 4358b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara 4359b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara#ifdef CONFIG_PM 4360b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bisharastatic int mv_pci_device_resume(struct pci_dev *pdev) 4361b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara{ 4362d86619211ed3cdf4f6abff984774b65314aba0feSergei Shtylyov struct ata_host *host = pci_get_drvdata(pdev); 4363b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara int rc; 4364b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara 4365b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara rc = ata_pci_device_do_resume(pdev); 4366b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara if (rc) 4367b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara return rc; 4368b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara 4369b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara /* initialize adapter */ 4370b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara rc = mv_init_host(host); 4371b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara if (rc) 4372b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara return rc; 4373b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara 4374b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara ata_host_resume(host); 4375b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara 4376b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara return 0; 4377b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara} 4378b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara#endif 43797bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 438020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4381f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev); 4382f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev); 4383f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 438420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic int __init mv_init(void) 438520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 43867bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc = -ENODEV; 43877bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 43887bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_register_driver(&mv_pci_driver); 4389f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 4390f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 4391f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#endif 4392f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = platform_driver_register(&mv_platform_driver); 4393f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4394f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#ifdef CONFIG_PCI 4395f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 4396f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara pci_unregister_driver(&mv_pci_driver); 43977bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 43987bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 439920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 440020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 440120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic void __exit mv_exit(void) 440220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 44037bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 440420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ pci_unregister_driver(&mv_pci_driver); 44057bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 4406f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara platform_driver_unregister(&mv_platform_driver); 440720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 440820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 440920f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_AUTHOR("Brett Russ"); 441020f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 441120f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_LICENSE("GPL"); 441220f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DEVICE_TABLE(pci, mv_pci_tbl); 441320f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_VERSION(DRV_VERSION); 441417c5aab5b34e351531466e35b154ca86db7d46a9Mark LordMODULE_ALIAS("platform:" DRV_NAME); 441520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 441620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_init(mv_init); 441720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_exit(mv_exit); 4418