sata_mv.c revision 041b5eac254107cd3ba60034c38a411531cc64ee
120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * sata_mv.c - Marvell SATA support 320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * Copyright 2008-2009: Marvell Corporation, all rights reserved. 58b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * Copyright 2005: EMC Corporation, all rights reserved. 6e2b1be56c5656902744c2b52e8304126a40bb609Jeff Garzik * Copyright 2005 Red Hat, Inc. All rights reserved. 720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 840f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * Originally written by Brett Russ. 940f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>. 1040f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * 1120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 1220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is free software; you can redistribute it and/or modify 1420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * it under the terms of the GNU General Public License as published by 1520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * the Free Software Foundation; version 2 of the License. 1620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is distributed in the hope that it will be useful, 1820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * but WITHOUT ANY WARRANTY; without even the implied warranty of 1920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 2020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * GNU General Public License for more details. 2120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * You should have received a copy of the GNU General Public License 2320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * along with this program; if not, write to the Free Software 2420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 2520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 284a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik/* 2985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * sata_mv TODO list: 3085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Develop a low-power-consumption strategy, and implement it. 3285afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 332b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds. 3485afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3585afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> [Experiment, Marvell value added] Is it possible to use target 3685afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * mode to cross-connect two Linux boxes with Marvell cards? If so, 3785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * creating LibATA target mode support would be very interesting. 3885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * Target mode, for those without docs, is the ability to directly 4085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * connect two SATA ports. 4185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord */ 424a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 4365ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord/* 4465ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * 80x1-B2 errata PCI#11: 4565ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * 4665ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * Users of the 6041/6081 Rev.B2 chips (current is C0) 4765ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * should be careful to insert those cards only onto PCI-X bus #0, 4865ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * and only in device slots 0..7, not higher. The chips may not 4965ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * work correctly otherwise (note: this is a pretty rare condition). 5065ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord */ 5165ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord 5220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/kernel.h> 5320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/module.h> 5420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/pci.h> 5520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/init.h> 5620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/blkdev.h> 5720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/delay.h> 5820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/interrupt.h> 598d8b60046d6a2328ca4b9031b4948084f775f607Andrew Morton#include <linux/dmapool.h> 6020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/dma-mapping.h> 61a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik#include <linux/device.h> 62f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/platform_device.h> 63f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/ata_platform.h> 6415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#include <linux/mbus.h> 65c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord#include <linux/bitops.h> 6620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <scsi/scsi_host.h> 67193515d51ccb363165d6b09e9ba5c21089e34badJeff Garzik#include <scsi/scsi_cmnd.h> 686c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik#include <scsi/scsi_device.h> 6920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/libata.h> 7020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#define DRV_NAME "sata_mv" 72cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord#define DRV_VERSION "1.28" 7320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord/* 7540f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * module options 7640f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord */ 7740f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord 7840f21b1124a9552bc093469280eb8239dc5f73d7Mark Lordstatic int msi; 7940f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord#ifdef CONFIG_PCI 8040f21b1124a9552bc093469280eb8239dc5f73d7Mark Lordmodule_param(msi, int, S_IRUGO); 8140f21b1124a9552bc093469280eb8239dc5f73d7Mark LordMODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 8240f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord#endif 8340f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord 842b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic int irq_coalescing_io_count; 852b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordmodule_param(irq_coalescing_io_count, int, S_IRUGO); 862b748a0a344847fe6b924407bbe153e1878c9f09Mark LordMODULE_PARM_DESC(irq_coalescing_io_count, 872b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord "IRQ coalescing I/O count threshold (0..255)"); 882b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 892b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic int irq_coalescing_usecs; 902b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordmodule_param(irq_coalescing_usecs, int, S_IRUGO); 912b748a0a344847fe6b924407bbe153e1878c9f09Mark LordMODULE_PARM_DESC(irq_coalescing_usecs, 922b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord "IRQ coalescing time threshold in usecs"); 932b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 9420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russenum { 9520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* BAR's are enumerated in terms of pci_resource_start() terms */ 9620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 9720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IO_BAR = 2, /* offset 0x18: IO space */ 9820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 9920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 10020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 10120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 10220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1032b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */ 1042b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */ 1052b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */ 1062b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord MAX_COAL_IO_COUNT = 255, /* completed I/O count */ 1072b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 10820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_BASE = 0, 109615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 1102b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 1112b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Per-chip ("all ports") interrupt coalescing feature. 1122b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * This is only for GEN_II / GEN_IIE hardware. 1132b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * 1142b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Coalescing defers the interrupt until either the IO_THRESHOLD 1152b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. 1162b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 117cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord COAL_REG_BASE = 0x18000, 118cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08), 1192b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */ 1202b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 121cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc), 122cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0), 1232b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 1242b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 1252b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Registers for the (unused here) transaction coalescing feature: 1262b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 127cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88), 128cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c), 1292b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 130cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATAHC0_REG_BASE = 0x20000, 131cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord FLASH_CTL = 0x1046c, 132cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord GPIO_PORT_CTL = 0x104f0, 133cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord RESET_CFG = 0x180d8, 13420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 13520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 13620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 13720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 13820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 13920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 14031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH = 32, 14131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 14231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* CRQB needs alignment on a 1KB boundary. Size == 1KB 14431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * CRPB needs alignment on a 256B boundary. Size == 256B 14531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 14631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 14731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 14831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 149da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord MV_MAX_SG_CT = 256, 15031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 15131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 152352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ 15320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_HC_SHIFT = 2, 154352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ 155352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ 156352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ 15720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 15820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Host Flags */ 15920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 1607bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 161c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 16291b1a84c10869e2e46a576e5367de3166bff8eccMark Lord ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING, 163ad3aef51e17b9c6a90a9014805f1645e8e441c17Mark Lord 16491b1a84c10869e2e46a576e5367de3166bff8eccMark Lord MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI, 16520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 16640f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ | 16740f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA, 16891b1a84c10869e2e46a576e5367de3166bff8eccMark Lord 16991b1a84c10869e2e46a576e5367de3166bff8eccMark Lord MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN, 170ad3aef51e17b9c6a90a9014805f1645e8e441c17Mark Lord 17131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_FLAG_READ = (1 << 0), 17231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_TAG_SHIFT = 1, 173c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 174e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 175c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 17631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_ADDR_SHIFT = 8, 17731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_CS = (0x2 << 11), 17831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_LAST = (1 << 15), 17931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 18031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRPB_FLAG_STATUS_SHIFT = 8, 181c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 182c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 18331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 18431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EPRD_FLAG_END_OF_TBL = (1 << 31), 18531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 18620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* PCI interface registers */ 18720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 188cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_COMMAND = 0xc00, 189cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */ 190cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */ 19131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 192cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_MAIN_CMD_STS = 0xd30, 19320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ STOP_PCI_MASTER = (1 << 2), 19420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MASTER_EMPTY = (1 << 3), 19520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GLOB_SFT_RST = (1 << 4), 19620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 197cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_MODE = 0xd00, 1988e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_MODE_MASK = 0x30, 1998e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 200522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 201522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_DISC_TIMER = 0xd04, 202522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MSI_TRIGGER = 0xc38, 203522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_SERR_MASK = 0xc28, 204cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_XBAR_TMOUT = 0x1d04, 205522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 206522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 207522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_ATTRIBUTE = 0x1d48, 208522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_COMMAND = 0x1d50, 209522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 210cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_IRQ_CAUSE = 0x1d58, 211cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_IRQ_MASK = 0x1d5c, 21220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 21320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 214cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCIE_IRQ_CAUSE = 0x1900, 215cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCIE_IRQ_MASK = 0x1910, 216646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 21702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 2187368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */ 219cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_HC_MAIN_IRQ_CAUSE = 0x1d60, 220cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_HC_MAIN_IRQ_MASK = 0x1d64, 221cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SOC_HC_MAIN_IRQ_CAUSE = 0x20020, 222cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SOC_HC_MAIN_IRQ_MASK = 0x20024, 22340f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord ERR_IRQ = (1 << 0), /* shift by (2 * port #) */ 22440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord DONE_IRQ = (1 << 1), /* shift by (2 * port #) */ 22520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 22620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 2272b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */ 2282b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */ 22920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_ERR = (1 << 18), 23040f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */ 23140f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */ 23240f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */ 23340f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */ 23440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */ 23520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GPIO_INT = (1 << 22), 23620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SELF_INT = (1 << 23), 23720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TWSI_INT = (1 << 24), 23820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 239fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 240e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 24120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 24220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATAHC registers */ 243cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord HC_CFG = 0x00, 24420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 245cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord HC_IRQ_CAUSE = 0x14, 246352fab701ca4753dd005b67ce5e512be944eb591Mark Lord DMA_IRQ = (1 << 0), /* shift by port # */ 247352fab701ca4753dd005b67ce5e512be944eb591Mark Lord HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ 24820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ DEV_IRQ = (1 << 8), /* shift by port # */ 24920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2502b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 2512b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Per-HC (Host-Controller) interrupt coalescing feature. 2522b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * This is present on all chip generations. 2532b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * 2542b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Coalescing defers the interrupt until either the IO_THRESHOLD 2552b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. 2562b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 257cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord HC_IRQ_COAL_IO_THRESHOLD = 0x000c, 258cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord HC_IRQ_COAL_TIME_THRESHOLD = 0x0010, 2592b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 260cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SOC_LED_CTRL = 0x2c, 261000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */ 262000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */ 263000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord /* with dev activity LED */ 264000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 26520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Shadow block registers */ 266cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SHD_BLK = 0x100, 267cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */ 26820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 26920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATA registers */ 270cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_STATUS = 0x300, /* ctrl, err regs follow status */ 271cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_ACTIVE = 0x350, 272cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord FIS_IRQ_CAUSE = 0x364, 273cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */ 27417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 275cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord LTMODE = 0x30c, /* requires read-after-write */ 27617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 27717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 278cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PHY_MODE2 = 0x330, 27947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik PHY_MODE3 = 0x310, 280cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord 281cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PHY_MODE4 = 0x314, /* requires read-after-write */ 282ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */ 283ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */ 284ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */ 285ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */ 286ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord 287cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_IFCTL = 0x344, 288cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_TESTCTL = 0x348, 289cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_IFSTAT = 0x34c, 290cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord VENDOR_UNIQUE_FIS = 0x35c, 29117c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 292cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord FISCFG = 0x360, 2938e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */ 2948e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 29517c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 29629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr PHY_MODE9_GEN2 = 0x398, 29729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr PHY_MODE9_GEN1 = 0x39c, 29829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr PHYCFG_OFS = 0x3a0, /* only in 65n devices */ 29929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 300c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_MODE = 0x74, 301cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV5_LTMODE = 0x30, 302cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV5_PHY_CTL = 0x0C, 303cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_IFCFG = 0x050, 304bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 305bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_M2_PREAMP_MASK = 0x7e0, 30620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Port registers */ 308cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_CFG = 0, 3090c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 3100c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 3110c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 3120c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 3130c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 314e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 315e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 31620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 317cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_ERR_IRQ_CAUSE = 0x8, 318cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_ERR_IRQ_MASK = 0xc, 3196c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 3206c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 3216c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV = (1 << 2), /* device error */ 3226c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 3236c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 3246c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 325c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 326c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 3276c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 328c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 3296c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 3306c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 3316c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 3326c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 333646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3346c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 335646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 336646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 337646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 338646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 339646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3406c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 341646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3426c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 343646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 344646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 345646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 346646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 347646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 348646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3496c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 350646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3516c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 352c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_OVERRUN_5 = (1 << 5), 353c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_UNDERRUN_5 = (1 << 6), 354646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 355646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 356646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 | 357646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 | 35885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord EDMA_ERR_LNK_CTRL_TX, 359646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 360bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 361bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 362bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 363bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 364bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SERR | 365bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS | 3666c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 367bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 368bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 369bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY | 370bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_CTRL_RX_2 | 371bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_RX | 372bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_TX | 373bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_TRANS_PROTO, 374e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 375bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 376bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 377bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 378bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 379bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_OVERRUN_5 | 380bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_UNDERRUN_5 | 381bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS_5 | 3826c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 383bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 384bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 385bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY, 38620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 387cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_REQ_Q_BASE_HI = 0x10, 388cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */ 38931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 390cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_REQ_Q_OUT_PTR = 0x18, 39131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_PTR_SHIFT = 5, 39231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 393cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_RSP_Q_BASE_HI = 0x1c, 394cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_RSP_Q_IN_PTR = 0x20, 395cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */ 39631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_PTR_SHIFT = 3, 39731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 398cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_CMD = 0x28, /* EDMA command register */ 3990ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_EN = (1 << 0), /* enable EDMA */ 4000ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 4018e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */ 4028e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 403cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_STATUS = 0x30, /* EDMA engine status */ 4048e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */ 4058e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */ 40620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 407cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_IORDY_TMOUT = 0x34, 408cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_ARB_CFG = 0x38, 4098e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 410cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */ 411cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */ 412da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 413cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord BMDMA_CMD = 0x224, /* bmdma command register */ 414cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord BMDMA_STATUS = 0x228, /* bmdma status register */ 415cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */ 416cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */ 417da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 41831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Host private flags (hp_flags) */ 41931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_HP_FLAG_MSI = (1 << 0), 42047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB0 = (1 << 1), 42147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB2 = (1 << 2), 42247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1B2 = (1 << 3), 42347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1C0 = (1 << 4), 4240ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 4250ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 4260ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 42702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 428616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ 4291f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */ 430000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */ 43120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 43231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Port private flags (pp_flags) */ 4330ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 434721091685f853ba4e6c49f26f989db0b1a811250Mark Lord MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 43500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */ 43629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */ 437d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */ 43820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 43920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 440ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 441ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 442e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 4438e7decdb8b132ee970a2636931b7653dec6af472Mark Lord#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) 4441f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC) 445bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 44615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 44715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_BASE(i) (0x20034 + ((i) << 4)) 44815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 449095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzikenum { 450baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik /* DMA boundary 0xffff is required by the s/g splitting 451baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik * we need on /length/ in mv_fill-sg(). 452baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik */ 453baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik MV_DMA_BOUNDARY = 0xffffU, 454095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 4550ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* mask of register bits containing lower 32 bits 4560ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik * of EDMA request queue DMA address 4570ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik */ 458095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 459095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 4600ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* ditto, for response queue */ 461095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 462095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik}; 463095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 464522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikenum chip_type { 465522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_504x, 466522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_508x, 467522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_5080, 468522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_604x, 469522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_608x, 470e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_6042, 471e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_7042, 472f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara chip_soc, 473522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik}; 474522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 47531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ReQuest Block: 32B */ 47631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crqb { 477e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr; 478e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr_hi; 479e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ctrl_flags; 480e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ata_cmd[11]; 48131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 48220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 483e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstruct mv_crqb_iie { 484e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 485e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 486e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags; 487e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 len; 488e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 ata_cmd[4]; 489e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 490e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 49131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ResPonse Block: 8B */ 49231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crpb { 493e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 id; 494e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 flags; 495e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 tmstmp; 49620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 49720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 49831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 49931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_sg { 500e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 501e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags_size; 502e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 503e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 reserved; 50431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 50520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 50608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord/* 50708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * We keep a local cache of a few frequently accessed port 50808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * registers here, to avoid having to read them (very slow) 50908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * when switching between EDMA and non-EDMA modes. 51008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord */ 51108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstruct mv_cached_regs { 51208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 fiscfg; 51308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 ltmode; 51408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 haltcond; 515c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord u32 unknown_rsvd; 51608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord}; 51708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 51831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_port_priv { 51931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crqb *crqb; 52031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crqb_dma; 52131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crpb *crpb; 52231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crpb_dma; 523eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 524eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 525bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 526bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int req_idx; 527bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int resp_idx; 528bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 52931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 pp_flags; 53008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord struct mv_cached_regs cached; 53129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int delayed_eh_pmp_map; 53231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 53331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 534bca1c4eb9411533d613123618c0d127fae532595Jeff Garzikstruct mv_port_signal { 535bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 amps; 536bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 pre; 537bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik}; 538bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 53902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lordstruct mv_host_priv { 54002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 hp_flags; 54196e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord u32 main_irq_mask; 54202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_port_signal signal[8]; 54302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord const struct mv_hw_ops *ops; 544f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports; 545f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *base; 5467368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_cause_addr; 5477368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_mask_addr; 548cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 irq_cause_offset; 549cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 irq_mask_offset; 55002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 unmask_all_irqs; 551da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord /* 552da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * These consistent DMA memory pools give us guaranteed 553da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * alignment for hardware-accessed data structures, 554da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * and less memory waste in accomplishing the alignment. 555da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord */ 556da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crqb_pool; 557da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crpb_pool; 558da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *sg_tbl_pool; 55902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord}; 56002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 56147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstruct mv_hw_ops { 5622a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 5632a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 56447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 56547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 56647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 567c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 568c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 569522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 5707bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 57147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 57247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 57382ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 57482ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 57582ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 57682ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 57731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap); 57831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap); 5793e4a139107e497a741c26f8a377a10f214d63ec1Mark Lordstatic int mv_qc_defer(struct ata_queued_cmd *qc); 58031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc); 581e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc); 5829a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 583a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 584a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo unsigned long deadline); 585bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap); 586bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap); 587f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *dev); 58820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 5892a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5902a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 59147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 59247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 59347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 594c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 595c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 596522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 5977bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 59847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 5992a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 6002a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 60147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 60247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 60347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 604c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 605c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 606522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 607f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 608f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 609f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 610f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 611f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 612f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc); 613f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 614f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 615f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 61629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayrstatic void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, 61729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr void __iomem *mmio, unsigned int port); 6187bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 619e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 620c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no); 621e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap); 622b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio); 62300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma); 62447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 625e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp); 626e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 627e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 628e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 629e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 63029d187bb1e30682e228ce461c487d78d945c3e4fMark Lordstatic void mv_pmp_error_handler(struct ata_port *ap); 6314c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic void mv_process_crpb_entries(struct ata_port *ap, 6324c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp); 63347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 634da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_sff_irq_clear(struct ata_port *ap); 635da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic int mv_check_atapi_dma(struct ata_queued_cmd *qc); 636da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_setup(struct ata_queued_cmd *qc); 637da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_start(struct ata_queued_cmd *qc); 638da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_stop(struct ata_queued_cmd *qc); 639da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic u8 mv_bmdma_status(struct ata_port *ap); 640d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lordstatic u8 mv_sff_check_status(struct ata_port *ap); 641da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 642eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 643eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * because we have to allow room for worst case splitting of 644eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * PRDs for 64K boundaries in mv_fill_sg(). 645eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 646c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv5_sht = { 64768d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BASE_SHT(DRV_NAME), 648baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 649c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .dma_boundary = MV_DMA_BOUNDARY, 650c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik}; 651c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 652c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv6_sht = { 65368d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_NCQ_SHT(DRV_NAME), 654138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .can_queue = MV_MAX_Q_DEPTH - 1, 655baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 65620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .dma_boundary = MV_DMA_BOUNDARY, 65720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 65820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 659029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv5_ops = { 660029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &ata_sff_port_ops, 661c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 662c96f1732e25362d10ee7bcac1df8412a2e6b7d23Alan Cox .lost_interrupt = ATA_OP_NULL, 663c96f1732e25362d10ee7bcac1df8412a2e6b7d23Alan Cox 6643e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord .qc_defer = mv_qc_defer, 665c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_prep = mv_qc_prep, 666c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_issue = mv_qc_issue, 667c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 668bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .freeze = mv_eh_freeze, 669bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .thaw = mv_eh_thaw, 670a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .hardreset = mv_hardreset, 671a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .error_handler = ata_std_error_handler, /* avoid SFF EH */ 672029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .post_internal_cmd = ATA_OP_NULL, 673bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 674c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_read = mv5_scr_read, 675c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_write = mv5_scr_write, 676c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 677c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_start = mv_port_start, 678c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_stop = mv_port_stop, 679c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik}; 680c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 681029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv6_ops = { 682029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv5_ops, 683f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord .dev_config = mv6_dev_config, 68420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_read = mv_scr_read, 68520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_write = mv_scr_write, 68620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 687e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_hardreset = mv_pmp_hardreset, 688e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_softreset = mv_softreset, 689e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .softreset = mv_softreset, 69029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord .error_handler = mv_pmp_error_handler, 691da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 69240f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord .sff_check_status = mv_sff_check_status, 693da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .sff_irq_clear = mv_sff_irq_clear, 694da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .check_atapi_dma = mv_check_atapi_dma, 695da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_setup = mv_bmdma_setup, 696da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_start = mv_bmdma_start, 697da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_stop = mv_bmdma_stop, 698da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_status = mv_bmdma_status, 69920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 70020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 701029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv_iie_ops = { 702029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv6_ops, 703029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .dev_config = ATA_OP_NULL, 704e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .qc_prep = mv_qc_prep_iie, 705e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 706e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 70798ac62defe529d04a192688f40d801a2d8fbcf98Arjan van de Venstatic const struct ata_port_info mv_port_info[] = { 70820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_504x */ 70991b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_I_FLAGS, 710c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 711bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 712c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 71320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 71420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_508x */ 71591b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 716c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 717bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 718c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 71920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 72047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik { /* chip_5080 */ 72191b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 722c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 723bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 724c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 72547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik }, 72620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_604x */ 72791b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_II_FLAGS, 728c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 729bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 730c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 73120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 73220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_608x */ 73391b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC, 734c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 735bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 736c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 73720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 738e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_6042 */ 73991b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_IIE_FLAGS, 740c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 741bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 742e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 743e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 744e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_7042 */ 74591b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_IIE_FLAGS, 746c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 747bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 748e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 749e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 750f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { /* chip_soc */ 75191b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_IIE_FLAGS, 752c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 75317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .udma_mask = ATA_UDMA6, 75417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .port_ops = &mv_iie_ops, 755f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 75620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 75720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7583b7d697dfb7d03edb87e50b743a7ecff029618e9Jeff Garzikstatic const struct pci_device_id mv_pci_tbl[] = { 7592d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 7602d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 7612d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 7622d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 76346c5784c8fa736c2bb42fe681189b86e99abdc2eMark Lord /* RocketRAID 1720/174x have different identifiers */ 76446c5784c8fa736c2bb42fe681189b86e99abdc2eMark Lord { PCI_VDEVICE(TTI, 0x1720), chip_6042 }, 7654462254ac6be9150aae87d54d388fc348d6fceadMark Lord { PCI_VDEVICE(TTI, 0x1740), chip_6042 }, 7664462254ac6be9150aae87d54d388fc348d6fceadMark Lord { PCI_VDEVICE(TTI, 0x1742), chip_6042 }, 7672d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 7682d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 7692d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 7702d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 7712d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 7722d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 7732d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 7742d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 7752d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 776d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger /* Adaptec 1430SA */ 777d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 778d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger 77902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Marvell 7042 support */ 7806a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 7816a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom 78202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Highpoint RocketRAID PCIe series */ 78302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 78402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 78502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 7862d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { } /* terminate list */ 78720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 78820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 78947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv5xxx_ops = { 79047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv5_phy_errata, 79147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv5_enable_leds, 79247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv5_read_preamp, 79347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv5_reset_hc, 794522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv5_reset_flash, 795522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv5_reset_bus, 79647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 79747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 79847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv6xxx_ops = { 79947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv6_phy_errata, 80047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv6_enable_leds, 80147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv6_read_preamp, 80247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv6_reset_hc, 803522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv6_reset_flash, 804522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv_reset_pci_bus, 80547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 80647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 807f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic const struct mv_hw_ops mv_soc_ops = { 808f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .phy_errata = mv6_phy_errata, 809f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .enable_leds = mv_soc_enable_leds, 810f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .read_preamp = mv_soc_read_preamp, 811f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_hc = mv_soc_reset_hc, 812f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_flash = mv_soc_reset_flash, 813f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_bus = mv_soc_reset_bus, 814f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 815f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 81629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayrstatic const struct mv_hw_ops mv_soc_65n_ops = { 81729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr .phy_errata = mv_soc_65n_phy_errata, 81829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr .enable_leds = mv_soc_enable_leds, 81929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr .reset_hc = mv_soc_reset_hc, 82029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr .reset_flash = mv_soc_reset_flash, 82129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr .reset_bus = mv_soc_reset_bus, 82229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr}; 82329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 82420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 82520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Functions 82620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 82720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 82820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void writelfl(unsigned long data, void __iomem *addr) 82920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 83020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writel(data, addr); 83120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ (void) readl(addr); /* flush to avoid PCI posted write */ 83220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 83320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 834c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hc_from_port(unsigned int port) 835c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 836c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port >> MV_PORT_HC_SHIFT; 837c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 838c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 839c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hardport_from_port(unsigned int port) 840c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 841c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port & MV_PORT_MASK; 842c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 843c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 8441cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord/* 8451cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Consolidate some rather tricky bit shift calculations. 8461cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * This is hot-path stuff, so not a function. 8471cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Simple code, with two return values, so macro rather than inline. 8481cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 8491cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * port is the sole input, in range 0..7. 8507368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * shift is one output, for use with main_irq_cause / main_irq_mask registers. 8517368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * hardport is the other output, in range 0..3. 8521cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 8531cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Note that port and hardport may be the same variable in some cases. 8541cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord */ 8551cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ 8561cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord{ \ 8571cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift = mv_hc_from_port(port) * HC_SHIFT; \ 8581cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord hardport = mv_hardport_from_port(port); \ 8591cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift += hardport * 2; \ 8601cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord} 8611cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord 862352fab701ca4753dd005b67ce5e512be944eb591Mark Lordstatic inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 863352fab701ca4753dd005b67ce5e512be944eb591Mark Lord{ 864cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 865352fab701ca4753dd005b67ce5e512be944eb591Mark Lord} 866352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 867c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline void __iomem *mv_hc_base_from_port(void __iomem *base, 868c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 869c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 870c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base(base, mv_hc_from_port(port)); 871c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 872c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 87320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 87420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 875c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base_from_port(base, port) + 8768b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik MV_SATAHC_ARBTR_REG_SZ + 877c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 87820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 87920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 880e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 881e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord{ 882e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 883e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 884e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 885e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord return hc_mmio + ofs; 886e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord} 887e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 888f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic inline void __iomem *mv_host_base(struct ata_host *host) 889f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 890f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 891f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return hpriv->base; 892f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 893f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 89420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_ap_base(struct ata_port *ap) 89520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 896f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return mv_port_base(mv_host_base(ap->host), ap->port_no); 89720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 89820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 899cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic inline int mv_get_hc_count(unsigned long port_flags) 90031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 901cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 90231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 90331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 90408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord/** 90508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * mv_save_cached_regs - (re-)initialize cached port registers 90608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @ap: the port whose registers we are caching 90708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * 90808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * Initialize the local cache of port registers, 90908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * so that reading them over and over again can 91008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * be avoided on the hotter paths of this driver. 91108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * This saves a few microseconds each time we switch 91208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * to/from EDMA mode to perform (eg.) a drive cache flush. 91308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord */ 91408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstatic void mv_save_cached_regs(struct ata_port *ap) 91508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord{ 91608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 91708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord struct mv_port_priv *pp = ap->private_data; 91808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 919cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord pp->cached.fiscfg = readl(port_mmio + FISCFG); 920cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord pp->cached.ltmode = readl(port_mmio + LTMODE); 921cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND); 922cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD); 92308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord} 92408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 92508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord/** 92608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * mv_write_cached_reg - write to a cached port register 92708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @addr: hardware address of the register 92808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @old: pointer to cached value of the register 92908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @new: new value for the register 93008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * 93108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * Write a new value to a cached register, 93208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * but only if the value is different from before. 93308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord */ 93408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstatic inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new) 93508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord{ 93608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord if (new != *old) { 93712f3b6d7551306c00cf834540a33184de67c9187Mark Lord unsigned long laddr; 93808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord *old = new; 93912f3b6d7551306c00cf834540a33184de67c9187Mark Lord /* 94012f3b6d7551306c00cf834540a33184de67c9187Mark Lord * Workaround for 88SX60x1-B2 FEr SATA#13: 94112f3b6d7551306c00cf834540a33184de67c9187Mark Lord * Read-after-write is needed to prevent generating 64-bit 94212f3b6d7551306c00cf834540a33184de67c9187Mark Lord * write cycles on the PCI bus for SATA interface registers 94312f3b6d7551306c00cf834540a33184de67c9187Mark Lord * at offsets ending in 0x4 or 0xc. 94412f3b6d7551306c00cf834540a33184de67c9187Mark Lord * 94512f3b6d7551306c00cf834540a33184de67c9187Mark Lord * Looks like a lot of fuss, but it avoids an unnecessary 94612f3b6d7551306c00cf834540a33184de67c9187Mark Lord * +1 usec read-after-write delay for unaffected registers. 94712f3b6d7551306c00cf834540a33184de67c9187Mark Lord */ 94812f3b6d7551306c00cf834540a33184de67c9187Mark Lord laddr = (long)addr & 0xffff; 94912f3b6d7551306c00cf834540a33184de67c9187Mark Lord if (laddr >= 0x300 && laddr <= 0x33c) { 95012f3b6d7551306c00cf834540a33184de67c9187Mark Lord laddr &= 0x000f; 95112f3b6d7551306c00cf834540a33184de67c9187Mark Lord if (laddr == 0x4 || laddr == 0xc) { 95212f3b6d7551306c00cf834540a33184de67c9187Mark Lord writelfl(new, addr); /* read after write */ 95312f3b6d7551306c00cf834540a33184de67c9187Mark Lord return; 95412f3b6d7551306c00cf834540a33184de67c9187Mark Lord } 95512f3b6d7551306c00cf834540a33184de67c9187Mark Lord } 95612f3b6d7551306c00cf834540a33184de67c9187Mark Lord writel(new, addr); /* unaffected by the errata */ 95708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord } 95808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord} 95908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 960c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic void mv_set_edma_ptrs(void __iomem *port_mmio, 961c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_host_priv *hpriv, 962c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp) 963c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik{ 964bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 index; 965bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 966c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 967c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize request queue 968c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 969fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 970fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 971bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 972c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crqb_dma & 0x3ff); 973cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI); 974bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 975cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + EDMA_REQ_Q_IN_PTR); 976cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR); 977c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 978c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 979c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize response queue 980c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 981fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 982fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; 983bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 984c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crpb_dma & 0xff); 985cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI); 986cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR); 987bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 988cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + EDMA_RSP_Q_OUT_PTR); 989c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik} 990c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 9912b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv) 9922b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord{ 9932b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 9942b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * When writing to the main_irq_mask in hardware, 9952b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * we must ensure exclusivity between the interrupt coalescing bits 9962b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * and the corresponding individual port DONE_IRQ bits. 9972b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * 9982b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Note that this register is really an "IRQ enable" register, 9992b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * not an "IRQ mask" register as Marvell's naming might suggest. 10002b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 10012b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE)) 10022b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mask &= ~DONE_IRQ_0_3; 10032b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE)) 10042b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mask &= ~DONE_IRQ_4_7; 10052b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord writelfl(mask, hpriv->main_irq_mask_addr); 10062b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord} 10072b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 1008c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lordstatic void mv_set_main_irq_mask(struct ata_host *host, 1009c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 disable_bits, u32 enable_bits) 1010c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord{ 1011c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord struct mv_host_priv *hpriv = host->private_data; 1012c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 old_mask, new_mask; 1013c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 101496e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord old_mask = hpriv->main_irq_mask; 1015c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord new_mask = (old_mask & ~disable_bits) | enable_bits; 101696e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord if (new_mask != old_mask) { 101796e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord hpriv->main_irq_mask = new_mask; 10182b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_write_main_irq_mask(new_mask, hpriv); 101996e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord } 1020c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord} 1021c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 1022c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lordstatic void mv_enable_port_irqs(struct ata_port *ap, 1023c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int port_bits) 1024c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord{ 1025c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int shift, hardport, port = ap->port_no; 1026c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 disable_bits, enable_bits; 1027c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 1028c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 1029c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 1030c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord disable_bits = (DONE_IRQ | ERR_IRQ) << shift; 1031c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord enable_bits = port_bits << shift; 1032c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); 1033c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord} 1034c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 103500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_clear_and_enable_port_irqs(struct ata_port *ap, 103600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord void __iomem *port_mmio, 103700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord unsigned int port_irqs) 103800b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord{ 103900b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 104000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord int hardport = mv_hardport_from_port(ap->port_no); 104100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port( 104200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_host_base(ap->host), ap->port_no); 104300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord u32 hc_irq_cause; 104400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 104500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord /* clear EDMA event indicators, if any */ 1046cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 104700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 104800b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord /* clear pending irq events */ 104900b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 1050cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); 105100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 105200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord /* clear FIS IRQ Cause */ 105300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord if (IS_GEN_IIE(hpriv)) 1054cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, port_mmio + FIS_IRQ_CAUSE); 105500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 105600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_enable_port_irqs(ap, port_irqs); 105700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord} 105800b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 10592b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic void mv_set_irq_coalescing(struct ata_host *host, 10602b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord unsigned int count, unsigned int usecs) 10612b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord{ 10622b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord struct mv_host_priv *hpriv = host->private_data; 10632b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord void __iomem *mmio = hpriv->base, *hc_mmio; 10642b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord u32 coal_enable = 0; 10652b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord unsigned long flags; 10666abf4678261218938ccdac90767d34ce9937634fMark Lord unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC; 10672b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 10682b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord ALL_PORTS_COAL_DONE; 10692b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 10702b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* Disable IRQ coalescing if either threshold is zero */ 10712b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (!usecs || !count) { 10722b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord clks = count = 0; 10732b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } else { 10742b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* Respect maximum limits of the hardware */ 10752b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord clks = usecs * COAL_CLOCKS_PER_USEC; 10762b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (clks > MAX_COAL_TIME_THRESHOLD) 10772b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord clks = MAX_COAL_TIME_THRESHOLD; 10782b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (count > MAX_COAL_IO_COUNT) 10792b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord count = MAX_COAL_IO_COUNT; 10802b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } 10812b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 10822b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord spin_lock_irqsave(&host->lock, flags); 10836abf4678261218938ccdac90767d34ce9937634fMark Lord mv_set_main_irq_mask(host, coal_disable, 0); 10842b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 10856abf4678261218938ccdac90767d34ce9937634fMark Lord if (is_dual_hc && !IS_GEN_I(hpriv)) { 10862b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 10876abf4678261218938ccdac90767d34ce9937634fMark Lord * GEN_II/GEN_IIE with dual host controllers: 10886abf4678261218938ccdac90767d34ce9937634fMark Lord * one set of global thresholds for the entire chip. 10892b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 1090cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD); 1091cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(count, mmio + IRQ_COAL_IO_THRESHOLD); 10922b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* clear leftover coal IRQ bit */ 1093cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); 10946abf4678261218938ccdac90767d34ce9937634fMark Lord if (count) 10956abf4678261218938ccdac90767d34ce9937634fMark Lord coal_enable = ALL_PORTS_COAL_DONE; 10966abf4678261218938ccdac90767d34ce9937634fMark Lord clks = count = 0; /* force clearing of regular regs below */ 10972b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } 10986abf4678261218938ccdac90767d34ce9937634fMark Lord 10992b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 11002b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * All chips: independent thresholds for each HC on the chip. 11012b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 11022b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord hc_mmio = mv_hc_base_from_port(mmio, 0); 1103cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); 1104cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); 1105cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); 11066abf4678261218938ccdac90767d34ce9937634fMark Lord if (count) 11076abf4678261218938ccdac90767d34ce9937634fMark Lord coal_enable |= PORTS_0_3_COAL_DONE; 11086abf4678261218938ccdac90767d34ce9937634fMark Lord if (is_dual_hc) { 11092b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC); 1110cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); 1111cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); 1112cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); 11136abf4678261218938ccdac90767d34ce9937634fMark Lord if (count) 11146abf4678261218938ccdac90767d34ce9937634fMark Lord coal_enable |= PORTS_4_7_COAL_DONE; 11152b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } 11162b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 11176abf4678261218938ccdac90767d34ce9937634fMark Lord mv_set_main_irq_mask(host, 0, coal_enable); 11182b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord spin_unlock_irqrestore(&host->lock, flags); 11192b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord} 11202b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 112105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 112200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord * mv_start_edma - Enable eDMA engine 112305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @base: port base address 112405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pp: port private data 112505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 1126beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * Verify the local cache of the eDMA state is accurate with a 1127beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * WARN_ON. 112805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 112905b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 113005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 113105b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 113200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio, 1133721091685f853ba4e6c49f26f989db0b1a811250Mark Lord struct mv_port_priv *pp, u8 protocol) 113420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1135721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int want_ncq = (protocol == ATA_PROT_NCQ); 1136721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1137721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 1138721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 1139721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq != using_ncq) 1140b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 1141721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } 1142c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 11430c58912e192fc3a4835d772aafa40b72552b819fMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 11440c58912e192fc3a4835d772aafa40b72552b819fMark Lord 114500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_edma_cfg(ap, want_ncq, 1); 11460c58912e192fc3a4835d772aafa40b72552b819fMark Lord 1147f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord mv_set_edma_ptrs(port_mmio, hpriv, pp); 114800b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ); 1149bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1150cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(EDMA_EN, port_mmio + EDMA_CMD); 1151afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 1152afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 115320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 115420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 11559b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lordstatic void mv_wait_for_edma_empty_idle(struct ata_port *ap) 11569b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord{ 11579b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 11589b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE); 11599b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const int per_loop = 5, timeout = (15 * 1000 / per_loop); 11609b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord int i; 11619b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 11629b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord /* 11639b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord * Wait for the EDMA engine to finish transactions in progress. 1164c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * No idea what a good "timeout" value might be, but measurements 1165c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * indicate that it often requires hundreds of microseconds 1166c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * with two drives in-use. So we use the 15msec value above 1167c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * as a rough guess at what even more drives might require. 11689b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord */ 11699b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord for (i = 0; i < timeout; ++i) { 1170cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 edma_stat = readl(port_mmio + EDMA_STATUS); 11719b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord if ((edma_stat & empty_idle) == empty_idle) 11729b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord break; 11739b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord udelay(per_loop); 11749b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord } 11759b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */ 11769b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord} 11779b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 117805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1179e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * mv_stop_edma_engine - Disable eDMA engine 1180b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * @port_mmio: io base address 118105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 118205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 118305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 118405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 1185b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio) 118620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1187b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord int i; 118831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1189b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Disable eDMA. The disable bit auto clears. */ 1190cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(EDMA_DS, port_mmio + EDMA_CMD); 11918b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 1192b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Wait for the chip to confirm eDMA is off. */ 1193b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord for (i = 10000; i > 0; i--) { 1194cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 reg = readl(port_mmio + EDMA_CMD); 11954537deb5e90b717a725b3d74b58b4bb1d28443d0Jeff Garzik if (!(reg & EDMA_EN)) 1196b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 1197b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord udelay(10); 119831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 1199b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 120020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 120120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1202e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap) 12030ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik{ 1204b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord void __iomem *port_mmio = mv_ap_base(ap); 1205b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 120666e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord int err = 0; 12070ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 1208b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 1209b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 1210b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 12119b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord mv_wait_for_edma_empty_idle(ap); 1212b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (mv_stop_edma_engine(port_mmio)) { 1213b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); 121466e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord err = -EIO; 1215b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord } 121666e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord mv_edma_cfg(ap, 0, 0); 121766e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord return err; 12180ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik} 12190ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 12208a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#ifdef ATA_DEBUG 122131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_mem(void __iomem *start, unsigned bytes) 122220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 122331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 122431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 122531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%p: ", start + b); 122631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 12272dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", readl(start + b)); 122831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 122931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 123031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 123131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 123231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 12338a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#endif 12348a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik 123531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 123631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 123731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 123831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 123931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 dw; 124031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 124131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%02x: ", b); 124231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 12432dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik (void) pci_read_config_dword(pdev, b, &dw); 12442dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", dw); 124531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 124631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 124731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 124831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 124931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 125031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 125131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_all_regs(void __iomem *mmio_base, int port, 125231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct pci_dev *pdev) 125331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 125431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 12558b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik void __iomem *hc_base = mv_hc_base(mmio_base, 125631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port >> MV_PORT_HC_SHIFT); 125731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_base; 125831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int start_port, num_ports, p, start_hc, num_hcs, hc; 125931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 126031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (0 > port) { 126131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = start_port = 0; 126231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = 8; /* shld be benign for 4 port devs */ 126331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_hcs = 2; 126431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } else { 126531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = port >> MV_PORT_HC_SHIFT; 126631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_port = port; 126731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = num_hcs = 1; 126831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 12698b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik DPRINTK("All registers for port(s) %u-%u:\n", start_port, 127031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports > 1 ? num_ports - 1 : start_port); 127131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 127231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (NULL != pdev) { 127331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI config space regs:\n"); 127431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 127531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 127631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI regs:\n"); 127731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xc00, 0x3c); 127831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xd00, 0x34); 127931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xf00, 0x4); 128031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0x1d00, 0x6c); 128131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 1282d220c37e0a3c9a47ae00e87e044d963b3ea040bcDan Aloni hc_base = mv_hc_base(mmio_base, hc); 128331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("HC regs (HC %i):\n", hc); 128431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(hc_base, 0x1c); 128531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 128631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (p = start_port; p < start_port + num_ports; p++) { 128731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port_base = mv_port_base(mmio_base, p); 12882dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("EDMA regs (port %i):\n", p); 128931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base, 0x54); 12902dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("SATA regs (port %i):\n", p); 129131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base+0x300, 0x60); 129231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 129331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 129420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 129520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 129620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic unsigned int mv_scr_offset(unsigned int sc_reg_in) 129720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 129820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs; 129920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 130020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ switch (sc_reg_in) { 130120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_STATUS: 130220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_CONTROL: 130320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ERROR: 1304cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ofs = SATA_STATUS + (sc_reg_in * sizeof(u32)); 130520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 130620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ACTIVE: 1307cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ofs = SATA_ACTIVE; /* active is not with the others */ 130820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 130920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ default: 131020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = 0xffffffffU; 131120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 131220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 131320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return ofs; 131420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 131520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 131682ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 131720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 131820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 131920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1320da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 132182ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo *val = readl(mv_ap_base(link->ap) + ofs); 1322da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1323da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1324da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 132520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 132620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 132782ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 132820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 132920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 133020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1331da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 13322009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord void __iomem *addr = mv_ap_base(link->ap) + ofs; 13332009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord if (sc_reg_in == SCR_CONTROL) { 13342009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord /* 13352009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * Workaround for 88SX60x1 FEr SATA#26: 13362009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * 13372009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * COMRESETs have to take care not to accidently 13382009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * put the drive to sleep when writing SCR_CONTROL. 13392009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * Setting bits 12..15 prevents this problem. 13402009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * 13412009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * So if we see an outbound COMMRESET, set those bits. 13422009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * Ditto for the followup write that clears the reset. 13432009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * 13442009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * The proprietary driver does this for 13452009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * all chip versions, and so do we. 13462009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord */ 13472009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1) 13482009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord val |= 0xf000; 13492009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord } 13502009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord writelfl(val, addr); 1351da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1352da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1353da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 135420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 135520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1356f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *adev) 1357f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord{ 1358f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord /* 1359e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Deal with Gen-II ("mv6") hardware quirks/restrictions: 1360e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * 1361e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Gen-II does not support NCQ over a port multiplier 1362e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * (no FIS-based switching). 1363f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord */ 1364e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (adev->flags & ATA_DFLAG_NCQ) { 1365352fab701ca4753dd005b67ce5e512be944eb591Mark Lord if (sata_pmp_attached(adev->link->ap)) { 1366e49856d82a887ce365637176f9f99ab68076eae8Mark Lord adev->flags &= ~ATA_DFLAG_NCQ; 1367352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ata_dev_printk(adev, KERN_INFO, 1368352fab701ca4753dd005b67ce5e512be944eb591Mark Lord "NCQ disabled for command-based switching\n"); 1369352fab701ca4753dd005b67ce5e512be944eb591Mark Lord } 1370e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 1371f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1372f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 13733e4a139107e497a741c26f8a377a10f214d63ec1Mark Lordstatic int mv_qc_defer(struct ata_queued_cmd *qc) 13743e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord{ 13753e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct ata_link *link = qc->dev->link; 13763e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct ata_port *ap = link->ap; 13773e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct mv_port_priv *pp = ap->private_data; 13783e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 13793e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord /* 138029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * Don't allow new commands if we're in a delayed EH state 138129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * for NCQ and/or FIS-based switching. 138229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord */ 138329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 138429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord return ATA_DEFER_PORT; 138529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord /* 13863e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * If the port is completely idle, then allow the new qc. 13873e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord */ 13883e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (ap->nr_active_links == 0) 13893e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return 0; 13903e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 13914bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo /* 13924bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * The port is operating in host queuing mode (EDMA) with NCQ 13934bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * enabled, allow multiple NCQ commands. EDMA also allows 13944bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * queueing multiple DMA commands but libata core currently 13954bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * doesn't allow it. 13964bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo */ 13974bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) && 13984bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol)) 13994bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo return 0; 14004bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo 14013e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return ATA_DEFER_PORT; 14023e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord} 14033e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 140408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstatic void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs) 1405e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 140608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord struct mv_port_priv *pp = ap->private_data; 140708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord void __iomem *port_mmio; 140800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 140908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg; 141008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 ltmode, *old_ltmode = &pp->cached.ltmode; 141108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 haltcond, *old_haltcond = &pp->cached.haltcond; 141200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 141308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord ltmode = *old_ltmode & ~LTMODE_BIT8; 141408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord haltcond = *old_haltcond | EDMA_ERR_DEV; 141500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 141600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (want_fbs) { 141708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC; 141808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord ltmode = *old_ltmode | LTMODE_BIT8; 14194c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (want_ncq) 142008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord haltcond &= ~EDMA_ERR_DEV; 14214c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord else 142208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord fiscfg |= FISCFG_WAIT_DEV_ERR; 142308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord } else { 142408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR); 1425e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 142600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 142708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord port_mmio = mv_ap_base(ap); 1428cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg); 1429cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode); 1430cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond); 1431f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1432f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 1433dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lordstatic void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq) 1434dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord{ 1435dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1436dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord u32 old, new; 1437dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord 1438dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord /* workaround for 88SX60x1 FEr SATA#25 (part 1) */ 1439cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord old = readl(hpriv->base + GPIO_PORT_CTL); 1440dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord if (want_ncq) 1441dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord new = old | (1 << 22); 1442dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord else 1443dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord new = old & ~(1 << 22); 1444dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord if (new != old) 1445cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(new, hpriv->base + GPIO_PORT_CTL); 1446dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord} 1447dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord 1448c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord/** 144940f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma 145040f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * @ap: Port being initialized 1451c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * 1452c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * There are two DMA modes on these chips: basic DMA, and EDMA. 1453c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * 1454c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * Bit-0 of the "EDMA RESERVED" register enables/disables use 1455c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * of basic DMA on the GEN_IIE versions of the chips. 1456c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * 1457c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * This bit survives EDMA resets, and must be set for basic DMA 1458c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * to function, and should be cleared when EDMA is active. 1459c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord */ 1460c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lordstatic void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma) 1461c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord{ 1462c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord struct mv_port_priv *pp = ap->private_data; 1463c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord u32 new, *old = &pp->cached.unknown_rsvd; 1464c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord 1465c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord if (enable_bmdma) 1466c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord new = *old | 1; 1467c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord else 1468c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord new = *old & ~1; 1469cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new); 1470c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord} 1471c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord 1472000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord/* 1473000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * SOC chips have an issue whereby the HDD LEDs don't always blink 1474000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * during I/O when NCQ is enabled. Enabling a special "LED blink" mode 1475000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * of the SOC takes care of it, generating a steady blink rate when 1476000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * any drive on the chip is active. 1477000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * 1478000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * Unfortunately, the blink mode is a global hardware setting for the SOC, 1479000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * so we must use it whenever at least one port on the SOC has NCQ enabled. 1480000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * 1481000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * We turn "LED blink" off when NCQ is not in use anywhere, because the normal 1482000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * LED operation works then, and provides better (more accurate) feedback. 1483000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * 1484000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * Note that this code assumes that an SOC never has more than one HC onboard. 1485000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord */ 1486000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lordstatic void mv_soc_led_blink_enable(struct ata_port *ap) 1487000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord{ 1488000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct ata_host *host = ap->host; 1489000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct mv_host_priv *hpriv = host->private_data; 1490000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord void __iomem *hc_mmio; 1491000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord u32 led_ctrl; 1492000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1493000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN) 1494000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord return; 1495000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN; 1496000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); 1497cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord led_ctrl = readl(hc_mmio + SOC_LED_CTRL); 1498cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); 1499000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord} 1500000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1501000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lordstatic void mv_soc_led_blink_disable(struct ata_port *ap) 1502000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord{ 1503000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct ata_host *host = ap->host; 1504000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct mv_host_priv *hpriv = host->private_data; 1505000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord void __iomem *hc_mmio; 1506000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord u32 led_ctrl; 1507000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord unsigned int port; 1508000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1509000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)) 1510000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord return; 1511000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1512000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord /* disable led-blink only if no ports are using NCQ */ 1513000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord for (port = 0; port < hpriv->n_ports; port++) { 1514000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct ata_port *this_ap = host->ports[port]; 1515000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct mv_port_priv *pp = this_ap->private_data; 1516000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1517000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 1518000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord return; 1519000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord } 1520000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1521000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN; 1522000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); 1523cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord led_ctrl = readl(hc_mmio + SOC_LED_CTRL); 1524cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); 1525000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord} 1526000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 152700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma) 1528e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 15290c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 cfg; 1530e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_port_priv *pp = ap->private_data; 1531e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1532e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1533e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1534e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* set up non-NCQ EDMA configuration */ 15350c58912e192fc3a4835d772aafa40b72552b819fMark Lord cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 1536d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= 1537d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 1538e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 15390c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (IS_GEN_I(hpriv)) 1540e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 8); /* enab config burst size mask */ 1541e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1542dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord else if (IS_GEN_II(hpriv)) { 1543e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1544dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord mv_60x1_errata_sata25(ap, want_ncq); 1545e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1546dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord } else if (IS_GEN_IIE(hpriv)) { 154700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord int want_fbs = sata_pmp_attached(ap); 154800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord /* 154900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * Possible future enhancement: 155000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * 155100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * The chip can use FBS with non-NCQ, if we allow it, 155200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * But first we need to have the error handling in place 155300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * for this mode (datasheet section 7.3.15.4.2.3). 155400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * So disallow non-NCQ FBS for now. 155500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord */ 155600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord want_fbs &= want_ncq; 155700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 155808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_config_fbs(ap, want_ncq, want_fbs); 155900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 156000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (want_fbs) { 156100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord pp->pp_flags |= MV_PP_FLAG_FBS_EN; 156200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ 156300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord } 156400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 1565e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 156600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord if (want_edma) { 156700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord cfg |= (1 << 22); /* enab 4-entry host queue cache */ 156800b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord if (!IS_SOC(hpriv)) 156900b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord cfg |= (1 << 18); /* enab early completion */ 157000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord } 1571616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (hpriv->hp_flags & MV_HP_CUT_THROUGH) 1572616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ 1573c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord mv_bmdma_enable_iie(ap, !want_edma); 1574000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1575000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (IS_SOC(hpriv)) { 1576000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (want_ncq) 1577000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord mv_soc_led_blink_enable(ap); 1578000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord else 1579000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord mv_soc_led_blink_disable(ap); 1580000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord } 1581e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 1582e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1583721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq) { 1584721091685f853ba4e6c49f26f989db0b1a811250Mark Lord cfg |= EDMA_CFG_NCQ; 1585721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 158600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord } 1587721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1588cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(cfg, port_mmio + EDMA_CFG); 1589e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1590e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1591da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordstatic void mv_port_free_dma_mem(struct ata_port *ap) 1592da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord{ 1593da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1594da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_port_priv *pp = ap->private_data; 1595eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord int tag; 1596da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1597da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crqb) { 1598da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1599da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = NULL; 1600da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1601da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crpb) { 1602da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1603da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = NULL; 1604da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1605eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1606eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1607eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we have one unique sg_tbl per NCQ tag. 1608eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1609eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1610eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (pp->sg_tbl[tag]) { 1611eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) 1612eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_pool_free(hpriv->sg_tbl_pool, 1613eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag], 1614eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag]); 1615eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = NULL; 1616eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1617da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1618da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord} 1619da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 162005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 162105b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_start - Port specific init/start routine. 162205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 162305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 162405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Allocate and point to DMA memory, init port private memory, 162505b308e1df6d9d673daedb517969241f41278b52Brett Russ * zero indices. 162605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 162705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 162805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 162905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 163031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap) 163131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1632cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct device *dev = ap->host->dev; 1633cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 163431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp; 1635933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord unsigned long flags; 1636dde2020754aeb14e17052d61784dcb37f252aac2James Bottomley int tag; 163731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 163824dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 16396037d6bbdff65eb5a84fe35e140f4da4f7cc103aJeff Garzik if (!pp) 164024dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return -ENOMEM; 1641da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord ap->private_data = pp; 164231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1643da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1644da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crqb) 1645da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 1646da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crqb, 0, MV_CRQB_Q_SZ); 164731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1648da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1649da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crpb) 1650da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord goto out_port_free_dma_mem; 1651da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crpb, 0, MV_CRPB_Q_SZ); 165231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 16533bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */ 16543bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) 16553bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord ap->flags |= ATA_FLAG_AN; 1656eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1657eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1658eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we need one unique sg_tbl per NCQ tag. 1659eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1660eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1661eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) { 1662eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1663eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1664eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (!pp->sg_tbl[tag]) 1665eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord goto out_port_free_dma_mem; 1666eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } else { 1667eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = pp->sg_tbl[0]; 1668eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1669eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1670eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1671933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord 1672933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_lock_irqsave(ap->lock, flags); 167308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_save_cached_regs(ap); 167466e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord mv_edma_cfg(ap, 0, 0); 1675933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_unlock_irqrestore(ap->lock, flags); 1676933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord 167731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 1678da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1679da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordout_port_free_dma_mem: 1680da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 1681da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 168231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 168331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 168405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 168505b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_stop - Port specific cleanup/stop routine. 168605b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 168705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 168805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Stop DMA, cleanup port memory. 168905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 169005b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 1691cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine uses the host lock to protect the DMA stop. 169205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 169331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap) 169431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1695933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord unsigned long flags; 1696933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord 1697933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_lock_irqsave(ap->lock, flags); 1698e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma(ap); 169988e675e193159b9891c1c576de4348eaf490f5d0Mark Lord mv_enable_port_irqs(ap, 0); 1700933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_unlock_irqrestore(ap->lock, flags); 1701da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 170231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 170331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 170405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 170505b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 170605b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command whose SG list to source from 170705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 170805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Populate the SG list and mark the last entry. 170905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 171005b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 171105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 171205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 17136c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzikstatic void mv_fill_sg(struct ata_queued_cmd *qc) 171431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 171531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = qc->ap->private_data; 1716972c26bdd6b58e7534473c4f7928584578cf43f4Jeff Garzik struct scatterlist *sg; 17173be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik struct mv_sg *mv_sg, *last_sg = NULL; 1718ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo unsigned int si; 171931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1720eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord mv_sg = pp->sg_tbl[qc->tag]; 1721ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 1722d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik dma_addr_t addr = sg_dma_address(sg); 1723d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik u32 sg_len = sg_dma_len(sg); 172422374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 17254007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson while (sg_len) { 17264007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 offset = addr & 0xffff; 17274007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 len = sg_len; 172822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 172932cd11a61007511ddb38783deec8bb1aa6735789Mark Lord if (offset + len > 0x10000) 17304007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson len = 0x10000 - offset; 17314007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 17324007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 17334007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 17346c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik mv_sg->flags_size = cpu_to_le32(len & 0xffff); 173532cd11a61007511ddb38783deec8bb1aa6735789Mark Lord mv_sg->reserved = 0; 17364007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 17374007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson sg_len -= len; 17384007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson addr += len; 17394007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 17403be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg = mv_sg; 17414007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg++; 17424007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson } 174331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 17443be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik 17453be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik if (likely(last_sg)) 17463be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 174732cd11a61007511ddb38783deec8bb1aa6735789Mark Lord mb(); /* ensure data structure is visible to the chipset */ 174831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 174931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 17505796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzikstatic void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 175131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1752559eedad7f7764dacca33980127b4615011230e4Mark Lord u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 175331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ (last ? CRQB_CMD_LAST : 0); 1754559eedad7f7764dacca33980127b4615011230e4Mark Lord *cmdw = cpu_to_le16(tmp); 175531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 175631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 175705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1758da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_sff_irq_clear - Clear hardware interrupt after DMA. 1759da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @ap: Port associated with this ATA transaction. 1760da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1761da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * We need this only for ATAPI bmdma transactions, 1762da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * as otherwise we experience spurious interrupts 1763da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * after libata-sff handles the bmdma interrupts. 1764da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1765da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_sff_irq_clear(struct ata_port *ap) 1766da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1767da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ); 1768da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1769da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1770da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1771da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA. 1772da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to check for chipset/DMA compatibility. 1773da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1774da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * The bmdma engines cannot handle speculative data sizes 1775da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * (bytecount under/over flow). So only allow DMA for 1776da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * data transfer commands with known data sizes. 1777da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1778da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1779da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1780da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1781da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic int mv_check_atapi_dma(struct ata_queued_cmd *qc) 1782da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1783da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct scsi_cmnd *scmd = qc->scsicmd; 1784da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1785da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord if (scmd) { 1786da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord switch (scmd->cmnd[0]) { 1787da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case READ_6: 1788da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case READ_10: 1789da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case READ_12: 1790da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case WRITE_6: 1791da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case WRITE_10: 1792da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case WRITE_12: 1793da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case GPCMD_READ_CD: 1794da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case GPCMD_SEND_DVD_STRUCTURE: 1795da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case GPCMD_SEND_CUE_SHEET: 1796da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord return 0; /* DMA is safe */ 1797da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord } 1798da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord } 1799da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord return -EOPNOTSUPP; /* use PIO instead */ 1800da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1801da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1802da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1803da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_setup - Set up BMDMA transaction 1804da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to prepare DMA for. 1805da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1806da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1807da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1808da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1809da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_setup(struct ata_queued_cmd *qc) 1810da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1811da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct ata_port *ap = qc->ap; 1812da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1813da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct mv_port_priv *pp = ap->private_data; 1814da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1815da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord mv_fill_sg(qc); 1816da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1817da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* clear all DMA cmd bits */ 1818cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0, port_mmio + BMDMA_CMD); 1819da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1820da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* load PRD table addr. */ 1821da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16, 1822cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + BMDMA_PRD_HIGH); 1823da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord writelfl(pp->sg_tbl_dma[qc->tag], 1824cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + BMDMA_PRD_LOW); 1825da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1826da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* issue r/w command */ 1827da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord ap->ops->sff_exec_command(ap, &qc->tf); 1828da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1829da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1830da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1831da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_start - Start a BMDMA transaction 1832da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to start DMA on. 1833da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1834da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1835da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1836da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1837da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_start(struct ata_queued_cmd *qc) 1838da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1839da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct ata_port *ap = qc->ap; 1840da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1841da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 1842da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START; 1843da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1844da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* start host DMA transaction */ 1845cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(cmd, port_mmio + BMDMA_CMD); 1846da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1847da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1848da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1849da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_stop - Stop BMDMA transfer 1850da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to stop DMA on. 1851da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1852da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Clears the ATA_DMA_START flag in the bmdma control register 1853da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1854da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1855da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1856da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1857da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_stop(struct ata_queued_cmd *qc) 1858da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1859da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct ata_port *ap = qc->ap; 1860da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1861da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord u32 cmd; 1862da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1863da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* clear start/stop bit */ 1864cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord cmd = readl(port_mmio + BMDMA_CMD); 1865da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord cmd &= ~ATA_DMA_START; 1866cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(cmd, port_mmio + BMDMA_CMD); 1867da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1868da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 1869da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord ata_sff_dma_pause(ap); 1870da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1871da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1872da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1873da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_status - Read BMDMA status 1874da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @ap: port for which to retrieve DMA status. 1875da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1876da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Read and return equivalent of the sff BMDMA status register. 1877da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1878da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1879da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1880da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1881da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic u8 mv_bmdma_status(struct ata_port *ap) 1882da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1883da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1884da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord u32 reg, status; 1885da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1886da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* 1887da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Other bits are valid only if ATA_DMA_ACTIVE==0, 1888da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * and the ATA_DMA_INTR bit doesn't exist. 1889da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1890cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord reg = readl(port_mmio + BMDMA_STATUS); 1891da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord if (reg & ATA_DMA_ACTIVE) 1892da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord status = ATA_DMA_ACTIVE; 1893da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord else 1894da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR; 1895da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord return status; 1896da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1897da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1898299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lordstatic void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc) 1899299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord{ 1900299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord struct ata_taskfile *tf = &qc->tf; 1901299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord /* 1902299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * Workaround for 88SX60x1 FEr SATA#24. 1903299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * 1904299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * Chip may corrupt WRITEs if multi_count >= 4kB. 1905299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * Note that READs are unaffected. 1906299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * 1907299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * It's not clear if this errata really means "4K bytes", 1908299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * or if it always happens for multi_count > 7 1909299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * regardless of device sector_size. 1910299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * 1911299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * So, for safety, any write with multi_count > 7 1912299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * gets converted here into a regular PIO write instead: 1913299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord */ 1914299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) { 1915299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord if (qc->dev->multi_count > 7) { 1916299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord switch (tf->command) { 1917299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_CMD_WRITE_MULTI: 1918299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord tf->command = ATA_CMD_PIO_WRITE; 1919299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord break; 1920299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_CMD_WRITE_MULTI_FUA_EXT: 1921299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord tf->flags &= ~ATA_TFLAG_FUA; /* ugh */ 1922299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord /* fall through */ 1923299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_CMD_WRITE_MULTI_EXT: 1924299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord tf->command = ATA_CMD_PIO_WRITE_EXT; 1925299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord break; 1926299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord } 1927299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord } 1928299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord } 1929299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord} 1930299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord 1931da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 193205b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_prep - Host specific command preparation. 193305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to prepare 193405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 193505b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 193605b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it handles prep of the CRQB 193705b308e1df6d9d673daedb517969241f41278b52Brett Russ * (command request block), does some sanity checking, and calls 193805b308e1df6d9d673daedb517969241f41278b52Brett Russ * the SG load routine. 193905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 194005b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 194105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 194205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 194331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc) 194431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 194531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_port *ap = qc->ap; 194631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = ap->private_data; 1947e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 *cw; 19488d2b450d0f9233f221d545f26720eebbc468e857Mark Lord struct ata_taskfile *tf = &qc->tf; 194931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u16 flags = 0; 1950a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 195131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1952299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord switch (tf->protocol) { 1953299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_PROT_DMA: 1954299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_PROT_NCQ: 1955299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord break; /* continue below */ 1956299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_PROT_PIO: 1957299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord mv_rw_multi_errata_sata24(qc); 195831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 1959299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord default: 1960299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord return; 1961299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord } 196220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 196331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Fill in command request block 196431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 19658d2b450d0f9233f221d545f26720eebbc468e857Mark Lord if (!(tf->flags & ATA_TFLAG_WRITE)) 196631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= CRQB_FLAG_READ; 1967beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 196831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= qc->tag << CRQB_TAG_SHIFT; 1969e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 197031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1971bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1972fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 1973a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1974a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr = 1975eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1976a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr_hi = 1977eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1978a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 197931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1980a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord cw = &pp->crqb[in_index].ata_cmd[0]; 198131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 198231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Sadly, the CRQB cannot accomodate all registers--there are 198331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * only 11 bytes...so we must pick and choose required 198431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * registers based on the command. So, we drop feature and 198531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * hob_feature for [RW] DMA commands, but they are needed for 1986cd12e1f7a2c28917c89d65c0d4a52d3919b4c125Mark Lord * NCQ. NCQ will drop hob_nsect, which is not needed there 1987cd12e1f7a2c28917c89d65c0d4a52d3919b4c125Mark Lord * (nsect is used only for the tag; feat/hob_feat hold true nsect). 198820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 198931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ switch (tf->command) { 199031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ: 199131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ_EXT: 199231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE: 199331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE_EXT: 1994c15d85c8f3f73b5f20aae7928e25b6996f16b328Jens Axboe case ATA_CMD_WRITE_FUA_EXT: 199531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 199631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 199731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_READ: 199831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_WRITE: 19998b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 200031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 200131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 200231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ default: 200331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* The only other commands EDMA supports in non-queued and 200431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 200531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * of which are defined/used by Linux. If we get here, this 200631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * driver needs work. 200731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * 200831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * FIXME: modify libata to give qc_prep a return value and 200931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * return error here. 201031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 201131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ BUG_ON(tf->command); 201231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 201331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 201431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 201531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 201631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 201731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 201831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 201931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 202031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 202131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 202231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 202331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2024e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 2025e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 2026e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik mv_fill_sg(qc); 2027e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 2028e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2029e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik/** 2030e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * mv_qc_prep_iie - Host specific command preparation. 2031e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * @qc: queued command to prepare 2032e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 2033e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * This routine simply redirects to the general purpose routine 2034e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * if command is not DMA. Else, it handles prep of the CRQB 2035e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * (command request block), does some sanity checking, and calls 2036e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * the SG load routine. 2037e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 2038e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * LOCKING: 2039e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * Inherited from caller. 2040e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik */ 2041e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc) 2042e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 2043e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_port *ap = qc->ap; 2044e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_port_priv *pp = ap->private_data; 2045e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_crqb_iie *crqb; 20468d2b450d0f9233f221d545f26720eebbc468e857Mark Lord struct ata_taskfile *tf = &qc->tf; 2047a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 2048e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik u32 flags = 0; 2049e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 20508d2b450d0f9233f221d545f26720eebbc468e857Mark Lord if ((tf->protocol != ATA_PROT_DMA) && 20518d2b450d0f9233f221d545f26720eebbc468e857Mark Lord (tf->protocol != ATA_PROT_NCQ)) 2052e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 2053e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2054e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* Fill in Gen IIE command request block */ 20558d2b450d0f9233f221d545f26720eebbc468e857Mark Lord if (!(tf->flags & ATA_TFLAG_WRITE)) 2056e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= CRQB_FLAG_READ; 2057e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2058beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 2059e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= qc->tag << CRQB_TAG_SHIFT; 20608c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord flags |= qc->tag << CRQB_HOSTQ_SHIFT; 2061e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 2062e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2063bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 2064fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 2065a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 2066a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 2067eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 2068eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 2069e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->flags = cpu_to_le32(flags); 2070e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2071e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[0] = cpu_to_le32( 2072e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->command << 16) | 2073e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->feature << 24) 2074e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2075e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[1] = cpu_to_le32( 2076e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbal << 0) | 2077e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbam << 8) | 2078e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbah << 16) | 2079e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->device << 24) 2080e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2081e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[2] = cpu_to_le32( 2082e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbal << 0) | 2083e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbam << 8) | 2084e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbah << 16) | 2085e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_feature << 24) 2086e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2087e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[3] = cpu_to_le32( 2088e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->nsect << 0) | 2089e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_nsect << 8) 2090e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2091e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2092e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 209331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 209431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_fill_sg(qc); 209531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 209631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 209705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2098d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * mv_sff_check_status - fetch device status, if valid 2099d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * @ap: ATA port to fetch status from 2100d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * 2101d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * When using command issue via mv_qc_issue_fis(), 2102d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * the initial ATA_BUSY state does not show up in the 2103d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * ATA status (shadow) register. This can confuse libata! 2104d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * 2105d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * So we have a hook here to fake ATA_BUSY for that situation, 2106d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * until the first time a BUSY, DRQ, or ERR bit is seen. 2107d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * 2108d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * The rest of the time, it simply returns the ATA status register. 2109d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord */ 2110d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lordstatic u8 mv_sff_check_status(struct ata_port *ap) 2111d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord{ 2112d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord u8 stat = ioread8(ap->ioaddr.status_addr); 2113d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord struct mv_port_priv *pp = ap->private_data; 2114d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord 2115d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) { 2116d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) 2117d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; 2118d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord else 2119d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord stat = ATA_BUSY; 2120d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord } 2121d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord return stat; 2122d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord} 2123d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord 2124d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord/** 212570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register 212670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * @fis: fis to be sent 212770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * @nwords: number of 32-bit words in the fis 212870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 212970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lordstatic unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords) 213070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord{ 213170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 213270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord u32 ifctl, old_ifctl, ifstat; 213370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord int i, timeout = 200, final_word = nwords - 1; 213470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 213570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Initiate FIS transmission mode */ 2136cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord old_ifctl = readl(port_mmio + SATA_IFCTL); 213770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ifctl = 0x100 | (old_ifctl & 0xf); 2138cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(ifctl, port_mmio + SATA_IFCTL); 213970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 214070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Send all words of the FIS except for the final word */ 214170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord for (i = 0; i < final_word; ++i) 2142cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS); 214370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 214470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Flag end-of-transmission, and then send the final word */ 2145cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL); 2146cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS); 214770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 214870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* 214970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Wait for FIS transmission to complete. 215070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * This typically takes just a single iteration. 215170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 215270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord do { 2153cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ifstat = readl(port_mmio + SATA_IFSTAT); 215470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } while (!(ifstat & 0x1000) && --timeout); 215570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 215670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Restore original port configuration */ 2157cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(old_ifctl, port_mmio + SATA_IFCTL); 215870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 215970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* See if it worked */ 216070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if ((ifstat & 0x3000) != 0x1000) { 216170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ata_port_printk(ap, KERN_WARNING, 216270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord "%s transmission error, ifstat=%08x\n", 216370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord __func__, ifstat); 216470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return AC_ERR_OTHER; 216570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } 216670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return 0; 216770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord} 216870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 216970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord/** 217070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * mv_qc_issue_fis - Issue a command directly as a FIS 217170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * @qc: queued command to start 217270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 217370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Note that the ATA shadow registers are not updated 217470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * after command issue, so the device will appear "READY" 217570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * if polled, even while it is BUSY processing the command. 217670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 217770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * So we use a status hook to fake ATA_BUSY until the drive changes state. 217870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 217970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Note: we don't get updated shadow regs on *completion* 218070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * of non-data commands. So avoid sending them via this function, 218170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * as they will appear to have completed immediately. 218270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 218370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * GEN_IIE has special registers that we could get the result tf from, 218470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * but earlier chipsets do not. For now, we ignore those registers. 218570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 218670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lordstatic unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc) 218770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord{ 218870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct ata_port *ap = qc->ap; 218970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct mv_port_priv *pp = ap->private_data; 219070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct ata_link *link = qc->dev->link; 219170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord u32 fis[5]; 219270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord int err = 0; 219370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 219470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis); 219570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord err = mv_send_fis(ap, fis, sizeof(fis) / sizeof(fis[0])); 219670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (err) 219770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return err; 219870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 219970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord switch (qc->tf.protocol) { 220070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord case ATAPI_PROT_PIO: 220170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; 220270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* fall through */ 220370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord case ATAPI_PROT_NODATA: 220470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST_FIRST; 220570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord break; 220670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord case ATA_PROT_PIO: 220770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; 220870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (qc->tf.flags & ATA_TFLAG_WRITE) 220970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST_FIRST; 221070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord else 221170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST; 221270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord break; 221370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord default: 221470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST_LAST; 221570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord break; 221670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } 221770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 221870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (qc->tf.flags & ATA_TFLAG_POLLING) 221970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ata_pio_queue_task(ap, qc, 0); 222070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return 0; 222170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord} 222270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 222370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord/** 222405b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_issue - Initiate a command to the host 222505b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to start 222605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 222705b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 222805b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it sanity checks our local 222905b308e1df6d9d673daedb517969241f41278b52Brett Russ * caches of the request producer/consumer indices then enables 223005b308e1df6d9d673daedb517969241f41278b52Brett Russ * DMA and bumps the request producer index. 223105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 223205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 223305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 223405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 22359a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 223631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 2237f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord static int limit_warnings = 10; 2238c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct ata_port *ap = qc->ap; 2239c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 2240c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp = ap->private_data; 2241bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 in_index; 224242ed893d8011264f9945c2f54055b47c298ac53eMark Lord unsigned int port_irqs; 2243f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord 2244d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */ 2245d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord 2246f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord switch (qc->tf.protocol) { 2247f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATA_PROT_DMA: 2248f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATA_PROT_NCQ: 2249f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord mv_start_edma(ap, port_mmio, pp, qc->tf.protocol); 2250f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2251f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 2252f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord 2253f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord /* Write the request in pointer to kick the EDMA to life */ 2254f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 2255cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + EDMA_REQ_Q_IN_PTR); 2256f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord return 0; 225731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2258f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATA_PROT_PIO: 2259c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord /* 2260c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * Errata SATA#16, SATA#24: warn if multiple DRQs expected. 2261c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * 2262c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * Someday, we might implement special polling workarounds 2263c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * for these, but it all seems rather unnecessary since we 2264c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * normally use only DMA for commands which transfer more 2265c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * than a single block of data. 2266c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * 2267c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * Much of the time, this could just work regardless. 2268c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * So for now, just log the incident, and allow the attempt. 2269c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord */ 2270c7843e8f565f624b0cff7cad1370fad4cb84dfbcMark Lord if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) { 2271c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord --limit_warnings; 2272c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME 2273c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord ": attempting PIO w/multiple DRQ: " 2274c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord "this may fail due to h/w errata\n"); 2275c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord } 2276f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord /* drop through */ 227742ed893d8011264f9945c2f54055b47c298ac53eMark Lord case ATA_PROT_NODATA: 2278f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATAPI_PROT_PIO: 227942ed893d8011264f9945c2f54055b47c298ac53eMark Lord case ATAPI_PROT_NODATA: 228042ed893d8011264f9945c2f54055b47c298ac53eMark Lord if (ap->flags & ATA_FLAG_PIO_POLLING) 228142ed893d8011264f9945c2f54055b47c298ac53eMark Lord qc->tf.flags |= ATA_TFLAG_POLLING; 228242ed893d8011264f9945c2f54055b47c298ac53eMark Lord break; 228331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 228442ed893d8011264f9945c2f54055b47c298ac53eMark Lord 228542ed893d8011264f9945c2f54055b47c298ac53eMark Lord if (qc->tf.flags & ATA_TFLAG_POLLING) 228642ed893d8011264f9945c2f54055b47c298ac53eMark Lord port_irqs = ERR_IRQ; /* mask device interrupt when polling */ 228742ed893d8011264f9945c2f54055b47c298ac53eMark Lord else 228842ed893d8011264f9945c2f54055b47c298ac53eMark Lord port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */ 228942ed893d8011264f9945c2f54055b47c298ac53eMark Lord 229042ed893d8011264f9945c2f54055b47c298ac53eMark Lord /* 229142ed893d8011264f9945c2f54055b47c298ac53eMark Lord * We're about to send a non-EDMA capable command to the 229242ed893d8011264f9945c2f54055b47c298ac53eMark Lord * port. Turn off EDMA so there won't be problems accessing 229342ed893d8011264f9945c2f54055b47c298ac53eMark Lord * shadow block, etc registers. 229442ed893d8011264f9945c2f54055b47c298ac53eMark Lord */ 229542ed893d8011264f9945c2f54055b47c298ac53eMark Lord mv_stop_edma(ap); 229642ed893d8011264f9945c2f54055b47c298ac53eMark Lord mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs); 229742ed893d8011264f9945c2f54055b47c298ac53eMark Lord mv_pmp_select(ap, qc->dev->link->pmp); 229870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 229970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (qc->tf.command == ATA_CMD_READ_LOG_EXT) { 230070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 230170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* 230270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Workaround for 88SX60x1 FEr SATA#25 (part 2). 230340f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * 230470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * After any NCQ error, the READ_LOG_EXT command 230570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * from libata-eh *must* use mv_qc_issue_fis(). 230670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Otherwise it might fail, due to chip errata. 230770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 230870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Rather than special-case it, we'll just *always* 230970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * use this method here for READ_LOG_EXT, making for 231070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * easier testing. 231170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 231270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (IS_GEN_II(hpriv)) 231370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return mv_qc_issue_fis(qc); 231470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } 231542ed893d8011264f9945c2f54055b47c298ac53eMark Lord return ata_sff_qc_issue(qc); 231631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 231731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 23188f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lordstatic struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) 23198f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 23208f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct mv_port_priv *pp = ap->private_data; 23218f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc; 23228f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 23238f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 23248f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord return NULL; 23258f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord qc = ata_qc_from_tag(ap, ap->link.active_tag); 232695db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord if (qc) { 232795db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord if (qc->tf.flags & ATA_TFLAG_POLLING) 232895db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord qc = NULL; 232995db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord else if (!(qc->flags & ATA_QCFLAG_ACTIVE)) 233095db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord qc = NULL; 233195db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord } 23328f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord return qc; 23338f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 23348f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 233529d187bb1e30682e228ce461c487d78d945c3e4fMark Lordstatic void mv_pmp_error_handler(struct ata_port *ap) 233629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord{ 233729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int pmp, pmp_map; 233829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord struct mv_port_priv *pp = ap->private_data; 233929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord 234029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { 234129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord /* 234229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * Perform NCQ error analysis on failed PMPs 234329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * before we freeze the port entirely. 234429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * 234529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * The failed PMPs are marked earlier by mv_pmp_eh_prep(). 234629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord */ 234729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pmp_map = pp->delayed_eh_pmp_map; 234829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; 234929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord for (pmp = 0; pmp_map != 0; pmp++) { 235029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int this_pmp = (1 << pmp); 235129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pmp_map & this_pmp) { 235229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord struct ata_link *link = &ap->pmp_link[pmp]; 235329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pmp_map &= ~this_pmp; 235429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord ata_eh_analyze_ncq_error(link); 235529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 235629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 235729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord ata_port_freeze(ap); 235829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 235929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord sata_pmp_error_handler(ap); 236029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord} 236129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord 23624c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic unsigned int mv_get_err_pmp_map(struct ata_port *ap) 23634c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 23644c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 23654c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 2366cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord return readl(port_mmio + SATA_TESTCTL) >> 16; 23674c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 23684c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 23694c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map) 23704c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 23714c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct ata_eh_info *ehi; 23724c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int pmp; 23734c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 23744c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 23754c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Initialize EH info for PMPs which saw device errors 23764c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 23774c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi = &ap->link.eh_info; 23784c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord for (pmp = 0; pmp_map != 0; pmp++) { 23794c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int this_pmp = (1 << pmp); 23804c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pmp_map & this_pmp) { 23814c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct ata_link *link = &ap->pmp_link[pmp]; 23824c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 23834c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pmp_map &= ~this_pmp; 23844c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi = &link->eh_info; 23854c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_ehi_clear_desc(ehi); 23864c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_ehi_push_desc(ehi, "dev err"); 23874c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi->err_mask |= AC_ERR_DEV; 23884c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi->action |= ATA_EH_RESET; 23894c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_link_abort(link); 23904c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 23914c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 23924c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 23934c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 239406aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lordstatic int mv_req_q_empty(struct ata_port *ap) 239506aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord{ 239606aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 239706aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord u32 in_ptr, out_ptr; 239806aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord 2399cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR) 240006aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2401cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR) 240206aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 240306aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord return (in_ptr == out_ptr); /* 1 == queue_is_empty */ 240406aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord} 240506aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord 24064c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_fbs_ncq_dev_err(struct ata_port *ap) 24074c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 24084c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp = ap->private_data; 24094c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord int failed_links; 24104c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int old_map, new_map; 24114c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24124c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 24134c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device error during FBS+NCQ operation: 24144c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 24154c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Set a port flag to prevent further I/O being enqueued. 24164c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Leave the EDMA running to drain outstanding commands from this port. 24174c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Perform the post-mortem/EH only when all responses are complete. 24184c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2). 24194c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 24204c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { 24214c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; 24224c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->delayed_eh_pmp_map = 0; 24234c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24244c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord old_map = pp->delayed_eh_pmp_map; 24254c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord new_map = old_map | mv_get_err_pmp_map(ap); 24264c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24274c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (old_map != new_map) { 24284c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->delayed_eh_pmp_map = new_map; 24294c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_pmp_eh_prep(ap, new_map & ~old_map); 24304c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 2431c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord failed_links = hweight16(new_map); 24324c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24334c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x " 24344c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "failed_links=%d nr_active_links=%d\n", 24354c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, pp->delayed_eh_pmp_map, 24364c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ap->qc_active, failed_links, 24374c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ap->nr_active_links); 24384c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 243906aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { 24404c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_process_crpb_entries(ap, pp); 24414c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_stop_edma(ap); 24424c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_eh_freeze(ap); 24434c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__); 24444c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 1; /* handled */ 24454c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24464c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__); 24474c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 1; /* handled */ 24484c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 24494c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24504c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap) 24514c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 24524c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 24534c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Possible future enhancement: 24544c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 24554c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * FBS+non-NCQ operation is not yet implemented. 24564c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * See related notes in mv_edma_cfg(). 24574c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 24584c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device error during FBS+non-NCQ operation: 24594c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 24604c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * We need to snapshot the shadow registers for each failed command. 24614c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3). 24624c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 24634c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 24644c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 24654c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24664c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause) 24674c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 24684c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp = ap->private_data; 24694c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24704c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 24714c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* EDMA was not active: not handled */ 24724c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) 24734c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* FBS was not active: not handled */ 24744c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24754c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(edma_err_cause & EDMA_ERR_DEV)) 24764c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* non DEV error: not handled */ 24774c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT; 24784c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS)) 24794c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* other problems: not handled */ 24804c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24814c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { 24824c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 24834c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * EDMA should NOT have self-disabled for this case. 24844c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * If it did, then something is wrong elsewhere, 24854c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * and we cannot handle it here. 24864c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 24874c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & EDMA_ERR_SELF_DIS) { 24884c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_WARNING, 24894c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "%s: err_cause=0x%x pp_flags=0x%x\n", 24904c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, edma_err_cause, pp->pp_flags); 24914c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 24924c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24934c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return mv_handle_fbs_ncq_dev_err(ap); 24944c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } else { 24954c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 24964c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * EDMA should have self-disabled for this case. 24974c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * If it did not, then something is wrong elsewhere, 24984c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * and we cannot handle it here. 24994c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 25004c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) { 25014c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_WARNING, 25024c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "%s: err_cause=0x%x pp_flags=0x%x\n", 25034c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, edma_err_cause, pp->pp_flags); 25044c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 25054c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 25064c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return mv_handle_fbs_non_ncq_dev_err(ap); 25074c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 25084c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 25094c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 25104c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 2511a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lordstatic void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled) 25128f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 25138f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_eh_info *ehi = &ap->link.eh_info; 2514a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord char *when = "idle"; 25158f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 25168f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_ehi_clear_desc(ehi); 2517c9abde12d6debe5b97f36fb43cf188c1b9cd477fBartlomiej Zolnierkiewicz if (ap->flags & ATA_FLAG_DISABLED) { 2518a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "disabled"; 2519a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } else if (edma_was_enabled) { 2520a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "EDMA enabled"; 25218f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } else { 25228f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 25238f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 2524a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "polling"; 25258f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } 2526a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when); 25278f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->err_mask |= AC_ERR_OTHER; 25288f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->action |= ATA_EH_RESET; 25298f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_port_freeze(ap); 25308f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 25318f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 253205b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 253305b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_err_intr - Handle error interrupts on the port 253405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 253505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 25368d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Most cases require a full reset of the chip's state machine, 25378d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * which also performs a COMRESET. 25388d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Also, if the port disabled DMA, update our cached copy to match. 253905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 254005b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 254105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 254205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 254337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lordstatic void mv_err_intr(struct ata_port *ap) 254431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 254531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 2546bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 edma_err_cause, eh_freeze_mask, serr = 0; 2547e40060772d85f3534d3d517197696e24bb01f45bMark Lord u32 fis_cause = 0; 2548bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 2549bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2550bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int action = 0, err_mask = 0; 25519af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_eh_info *ehi = &ap->link.eh_info; 255237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord struct ata_queued_cmd *qc; 255337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord int abort = 0; 255420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25558d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord /* 255637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Read and clear the SError and err_cause bits. 2557e40060772d85f3534d3d517197696e24bb01f45bMark Lord * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear 2558e40060772d85f3534d3d517197696e24bb01f45bMark Lord * the FIS_IRQ_CAUSE register before clearing edma_err_cause. 25598d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord */ 256037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord sata_scr_read(&ap->link, SCR_ERROR, &serr); 256137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 256237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord 2563cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE); 2564e40060772d85f3534d3d517197696e24bb01f45bMark Lord if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2565cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord fis_cause = readl(port_mmio + FIS_IRQ_CAUSE); 2566cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE); 2567e40060772d85f3534d3d517197696e24bb01f45bMark Lord } 2568cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE); 2569bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 25704c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & EDMA_ERR_DEV) { 25714c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 25724c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device errors during FIS-based switching operation 25734c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * require special handling. 25744c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 25754c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (mv_handle_dev_err(ap, edma_err_cause)) 25764c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return; 25774c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 25784c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 257937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord qc = mv_get_active_qc(ap); 258037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_clear_desc(ehi); 258137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x", 258237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord edma_err_cause, pp->pp_flags); 2583e40060772d85f3534d3d517197696e24bb01f45bMark Lord 2584c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2585e40060772d85f3534d3d517197696e24bb01f45bMark Lord ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause); 2586cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord if (fis_cause & FIS_IRQ_CAUSE_AN) { 2587c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord u32 ec = edma_err_cause & 2588c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT); 2589c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord sata_async_notification(ap); 2590c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord if (!ec) 2591c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord return; /* Just an AN; no need for the nukes */ 2592c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord ata_ehi_push_desc(ehi, "SDB notify"); 2593c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord } 2594c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord } 2595bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 2596352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * All generations share these EDMA error cause bits: 2597bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 259837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (edma_err_cause & EDMA_ERR_DEV) { 2599bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_DEV; 260037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord action |= ATA_EH_RESET; 260137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_push_desc(ehi, "dev error"); 260237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 2603bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 26046c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 2605bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR)) { 2606bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_ATA_BUS; 2607cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2608b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "parity error"); 2609bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2610bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 2611bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_hotplugged(ehi); 2612bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 2613b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo "dev disconnect" : "dev connect"); 2614cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2615bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2616bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2617352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 2618352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Gen-I has a different SELF_DIS bit, 2619352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * different FREEZE bits, and no SERR bit: 2620352fab701ca4753dd005b67ce5e512be944eb591Mark Lord */ 2621ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) { 2622bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE_5; 2623bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 2624bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2625b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 2626bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2627bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 2628bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE; 2629bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS) { 2630bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2631b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 2632bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2633bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SERR) { 26348d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord ata_ehi_push_desc(ehi, "SError=%08x", serr); 26358d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord err_mask |= AC_ERR_ATA_BUS; 2636cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2637bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2638afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 263920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2640bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!err_mask) { 2641bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_OTHER; 2642cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2643bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2644bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2645bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->serror |= serr; 2646bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->action |= action; 2647bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2648bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 2649bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 2650bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 2651bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 2652bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 265337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (err_mask == AC_ERR_DEV) { 265437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* 265537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Cannot do ata_port_freeze() here, 265637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * because it would kill PIO access, 265737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * which is needed for further diagnosis. 265837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord */ 265937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord mv_eh_freeze(ap); 266037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord abort = 1; 266137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } else if (edma_err_cause & eh_freeze_mask) { 266237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* 266337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Note to self: ata_port_freeze() calls ata_port_abort() 266437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord */ 2665bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 266637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } else { 266737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord abort = 1; 266837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 266937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord 267037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (abort) { 267137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (qc) 267237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_link_abort(qc->dev->link); 267337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord else 267437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_port_abort(ap); 267537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 2676bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2677bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2678fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_response(struct ata_port *ap, 2679fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response, unsigned int tag, int ncq_enabled) 2680fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord{ 2681fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag); 2682fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 2683fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (qc) { 2684fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 ata_status; 2685fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u16 edma_status = le16_to_cpu(response->flags); 2686fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 2687fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * edma_status from a response queue entry: 2688cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only). 2689fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * MSB is saved ATA status from command completion. 2690fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 2691fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (!ncq_enabled) { 2692fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; 2693fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (err_cause) { 2694fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 2695fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * Error will be seen/handled by mv_err_intr(). 2696fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * So do nothing at all here. 2697fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 2698fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord return; 2699fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2700fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2701fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; 270237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (!ac_err_mask(ata_status)) 270337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_qc_complete(qc); 270437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* else: leave it for mv_err_intr() */ 2705fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 2706fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n", 2707fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord __func__, tag); 2708fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2709fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord} 2710fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 2711fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) 2712bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2713bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 2714bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2715fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u32 in_index; 2716bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik bool work_done = false; 2717fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); 2718bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2719fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Get the hardware queue position index */ 2720cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR) 2721bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2722bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2723fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Process new responses from since the last time we looked */ 2724fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord while (in_index != pp->resp_idx) { 27256c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik unsigned int tag; 2726fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response = &pp->crpb[pp->resp_idx]; 2727bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2728fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2729bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2730fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (IS_GEN_I(hpriv)) { 2731fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 50xx: no NCQ, only one command active at a time */ 27329af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo tag = ap->link.active_tag; 2733fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 2734fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Gen II/IIE: get command tag from CRPB entry */ 2735fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord tag = le16_to_cpu(response->id) & 0x1f; 2736bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2737fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord mv_process_crpb_response(ap, response, tag, ncq_enabled); 2738bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik work_done = true; 2739bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2740bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2741352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Update the software queue position index in hardware */ 2742bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (work_done) 2743bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 2744fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), 2745cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + EDMA_RSP_Q_OUT_PTR); 274620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 274720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2748a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lordstatic void mv_port_intr(struct ata_port *ap, u32 port_cause) 2749a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord{ 2750a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord struct mv_port_priv *pp; 2751a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord int edma_was_enabled; 2752a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord 2753a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (!ap || (ap->flags & ATA_FLAG_DISABLED)) { 2754a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_unexpected_intr(ap, 0); 2755a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord return; 2756a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2757a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2758a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Grab a snapshot of the EDMA_EN flag setting, 2759a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * so that we have a consistent view for this port, 2760a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * even if something we call of our routines changes it. 2761a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2762a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord pp = ap->private_data; 2763a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); 2764a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2765a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Process completed CRPB response(s) before other events. 2766a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2767a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (edma_was_enabled && (port_cause & DONE_IRQ)) { 2768a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_process_crpb_entries(ap, pp); 27694c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 27704c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_handle_fbs_ncq_dev_err(ap); 2771a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2772a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2773a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Handle chip-reported errors, or continue on to handle PIO. 2774a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2775a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (unlikely(port_cause & ERR_IRQ)) { 2776a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_err_intr(ap); 2777a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } else if (!edma_was_enabled) { 2778a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord struct ata_queued_cmd *qc = mv_get_active_qc(ap); 2779a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (qc) 2780a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord ata_sff_host_intr(ap, qc); 2781a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord else 2782a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_unexpected_intr(ap, edma_was_enabled); 2783a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2784a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord} 2785a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord 278605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 278705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_host_intr - Handle all interrupts on the given host controller 2788cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * @host: host specific structure 27897368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * @main_irq_cause: Main interrupt cause register for the chip. 279005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 279105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 279205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 279305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 27947368f91926a2870a8c3f9546d86535ce71ae0757Mark Lordstatic int mv_host_intr(struct ata_host *host, u32 main_irq_cause) 279520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2796f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 2797eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord void __iomem *mmio = hpriv->base, *hc_mmio; 2798a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0, port; 279920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 28002b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* If asserted, clear the "all ports" IRQ coalescing bit */ 28012b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (main_irq_cause & ALL_PORTS_COAL_DONE) 2802cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); 28032b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 2804a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord for (port = 0; port < hpriv->n_ports; port++) { 2805cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_port *ap = host->ports[port]; 2806eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord unsigned int p, shift, hardport, port_cause; 2807eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord 2808a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2809a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord /* 2810eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * Each hc within the host has its own hc_irq_cause register, 2811eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * where the interrupting ports bits get ack'd. 2812a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord */ 2813eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (hardport == 0) { /* first port on this hc ? */ 2814eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND; 2815eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord u32 port_mask, ack_irqs; 2816eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord /* 2817eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * Skip this entire hc if nothing pending for any ports 2818eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord */ 2819eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (!hc_cause) { 2820eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord port += MV_PORTS_PER_HC - 1; 2821eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord continue; 2822eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord } 2823eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord /* 2824eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * We don't need/want to read the hc_irq_cause register, 2825eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * because doing so hurts performance, and 2826eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * main_irq_cause already gives us everything we need. 2827eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * 2828eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * But we do have to *write* to the hc_irq_cause to ack 2829eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * the ports that we are handling this time through. 2830eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * 2831eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * This requires that we create a bitmap for those 2832eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * ports which interrupted us, and use that bitmap 2833eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * to ack (only) those ports via hc_irq_cause. 2834eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord */ 2835eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord ack_irqs = 0; 28362b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (hc_cause & PORTS_0_3_COAL_DONE) 28372b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord ack_irqs = HC_COAL_IRQ; 2838eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord for (p = 0; p < MV_PORTS_PER_HC; ++p) { 2839eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if ((port + p) >= hpriv->n_ports) 2840eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord break; 2841eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2); 2842eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (hc_cause & port_mask) 2843eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord ack_irqs |= (DMA_IRQ | DEV_IRQ) << p; 2844eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord } 2845a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord hc_mmio = mv_hc_base_from_port(mmio, port); 2846cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE); 2847a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = 1; 2848a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord } 28498f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord /* 2850a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Handle interrupts signalled for this port: 28518f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord */ 2852a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ); 2853a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (port_cause) 2854a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_port_intr(ap, port_cause); 285520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 2856a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return handled; 285720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 285820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2859a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lordstatic int mv_pci_error(struct ata_host *host, void __iomem *mmio) 2860bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 286102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 2862bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_port *ap; 2863bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 2864bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_eh_info *ehi; 2865bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int i, err_mask, printed = 0; 2866bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 err_cause; 2867bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2868cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord err_cause = readl(mmio + hpriv->irq_cause_offset); 2869bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2870bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", 2871bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_cause); 2872bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2873bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik DPRINTK("All regs @ PCI error\n"); 2874bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 2875bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2876cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, mmio + hpriv->irq_cause_offset); 2877bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2878bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik for (i = 0; i < host->n_ports; i++) { 2879bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ap = host->ports[i]; 2880936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo if (!ata_link_offline(&ap->link)) { 28819af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo ehi = &ap->link.eh_info; 2882bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 2883bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!printed++) 2884bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, 2885bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik "PCI err cause 0x%08x", err_cause); 2886bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_HOST_BUS; 2887cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo ehi->action = ATA_EH_RESET; 28889af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 2889bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 2890bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 2891bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 2892bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 2893bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2894bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 2895bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2896bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2897a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return 1; /* handled */ 2898bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2899bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 290005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2901c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * mv_interrupt - Main interrupt event handler 290205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @irq: unused 290305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @dev_instance: private data; in this case the host structure 290405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 290505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read the read only register to determine if any host 290605b308e1df6d9d673daedb517969241f41278b52Brett Russ * controllers have pending interrupts. If so, call lower level 290705b308e1df6d9d673daedb517969241f41278b52Brett Russ * routine to handle. Also check for PCI errors which are only 290805b308e1df6d9d673daedb517969241f41278b52Brett Russ * reported here. 290905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 29108b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * LOCKING: 2911cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine holds the host lock while processing pending 291205b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts. 291305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 29147d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t mv_interrupt(int irq, void *dev_instance) 291520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2916cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = dev_instance; 2917f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 2918a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0; 29196d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI; 292096e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord u32 main_irq_cause, pending_irqs; 292120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2922646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord spin_lock(&host->lock); 29236d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 29246d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord /* for MSI: block new interrupts while in here */ 29256d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord if (using_msi) 29262b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_write_main_irq_mask(0, hpriv); 29276d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 29287368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_cause = readl(hpriv->main_irq_cause_addr); 292996e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord pending_irqs = main_irq_cause & hpriv->main_irq_mask; 2930352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 2931352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Deal with cases where we either have nothing pending, or have read 2932352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * a bogus register value which can indicate HW removal or PCI fault. 293320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2934a44253d24a97ec3efe601267274a5fb64d8696c1Mark Lord if (pending_irqs && main_irq_cause != 0xffffffffU) { 29351f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv))) 2936a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = mv_pci_error(host, hpriv->base); 2937a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord else 2938a44253d24a97ec3efe601267274a5fb64d8696c1Mark Lord handled = mv_host_intr(host, pending_irqs); 2939bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 29406d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 29416d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord /* for MSI: unmask; interrupt cause bits will retrigger now */ 29426d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord if (using_msi) 29432b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv); 29446d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 29459d51af7bd2f1d730cb6eeeb9ff837e3441ad4e07Mark Lord spin_unlock(&host->lock); 29469d51af7bd2f1d730cb6eeeb9ff837e3441ad4e07Mark Lord 294720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return IRQ_RETVAL(handled); 294820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 294920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2950c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic unsigned int mv5_scr_offset(unsigned int sc_reg_in) 2951c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2952c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs; 2953c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2954c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik switch (sc_reg_in) { 2955c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_STATUS: 2956c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_ERROR: 2957c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_CONTROL: 2958c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = sc_reg_in * sizeof(u32); 2959c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 2960c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik default: 2961c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = 0xffffffffU; 2962c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 2963c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2964c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return ofs; 2965c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2966c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 296782ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 2968c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 296982ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo struct mv_host_priv *hpriv = link->ap->host->private_data; 2970f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 297182ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 2972c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 2973c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2974da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 2975da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(addr + ofs); 2976da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 2977da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 2978da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 2979c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2980c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 298182ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 2982c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 298382ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo struct mv_host_priv *hpriv = link->ap->host->private_data; 2984f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 298582ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 2986c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 2987c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2988da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 29890d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo writelfl(val, addr + ofs); 2990da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 2991da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 2992da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 2993c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2994c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 29957bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 2996522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 29977bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara struct pci_dev *pdev = to_pci_dev(host->dev); 2998522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik int early_5080; 2999522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 300044c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 3001522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3002522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik if (!early_5080) { 3003522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 3004522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= (1 << 0); 3005522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 3006522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik } 3007522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 30087bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara mv_reset_pci_bus(host, mmio); 3009522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 3010522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3011522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 3012522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 3013cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x0fcfffff, mmio + FLASH_CTL); 3014522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 3015522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 301647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 3017ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 3018ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 3019c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 3020c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 3021c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3022c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 3023c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3024c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 3025c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 3026ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3027ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 302847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 3029ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 3030522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp; 3031522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3032cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0, mmio + GPIO_PORT_CTL); 3033522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3034522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 3035522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3036522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 3037522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= ~(1 << 0); 3038522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 3039ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3040ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 30412a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 30422a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 3043bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 3044c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, port); 3045c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 3046c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 3047c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 3048c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3049c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik if (fix_apm_sq) { 3050cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(phy_mmio + MV5_LTMODE); 3051c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= (1 << 19); 3052cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(tmp, phy_mmio + MV5_LTMODE); 3053c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3054cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(phy_mmio + MV5_PHY_CTL); 3055c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~0x3; 3056c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x1; 3057cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(tmp, phy_mmio + MV5_PHY_CTL); 3058c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 3059c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3060c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 3061c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~mask; 3062c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].pre; 3063c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].amps; 3064c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_MODE); 3065bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 3066bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3067c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3068c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 3069c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, port_mmio + (reg)) 3070c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 3071c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 3072c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 3073c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 3074c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3075e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 3076c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3077c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x028); /* command */ 3078cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x11f, port_mmio + EDMA_CFG); 3079c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x004); /* timer */ 3080c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x008); /* irq err cause */ 3081c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); /* irq err mask */ 3082c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); /* rq bah */ 3083c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); /* rq inp */ 3084c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); /* rq outp */ 3085c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x01c); /* respq bah */ 3086c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x024); /* respq outp */ 3087c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x020); /* respq inp */ 3088c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x02c); /* test control */ 3089cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 3090c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3091c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 3092c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3093c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, hc_mmio + (reg)) 3094c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3095c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc) 309647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik{ 3097c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 3098c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 3099c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3100c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); 3101c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); 3102c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); 3103c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); 3104c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3105c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(hc_mmio + 0x20); 3106c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= 0x1c1c1c1c; 3107c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x03030303; 3108c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, hc_mmio + 0x20); 3109c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3110c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 3111c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3112c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3113c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 3114c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 3115c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc, port; 3116c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3117c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (hc = 0; hc < n_hc; hc++) { 3118c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (port = 0; port < MV_PORTS_PER_HC; port++) 3119c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_hc_port(hpriv, mmio, 3120c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (hc * MV_PORTS_PER_HC) + port); 3121c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3122c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_one_hc(hpriv, mmio, hc); 3123c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 3124c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3125c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return 0; 312647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik} 312747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 3128101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 3129101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#define ZERO(reg) writel(0, mmio + (reg)) 31307bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 3131101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 313202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 3133101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 3134101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3135cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(mmio + MV_PCI_MODE); 3136101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0xff00ffff; 3137cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(tmp, mmio + MV_PCI_MODE); 3138101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3139101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_DISC_TIMER); 3140101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_MSI_TRIGGER); 3141cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); 3142101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_SERR_MASK); 3143cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ZERO(hpriv->irq_cause_offset); 3144cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ZERO(hpriv->irq_mask_offset); 3145101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_LOW_ADDRESS); 3146101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_HIGH_ADDRESS); 3147101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_ATTRIBUTE); 3148101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_COMMAND); 3149101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 3150101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 3151101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3152101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 3153101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 3154101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 3155101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3156101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik mv5_reset_flash(hpriv, mmio); 3157101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3158cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(mmio + GPIO_PORT_CTL); 3159101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0x3; 3160101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp |= (1 << 5) | (1 << 6); 3161cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(tmp, mmio + GPIO_PORT_CTL); 3162101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 3163101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3164101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik/** 3165101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * mv6_reset_hc - Perform the 6xxx global soft reset 3166101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * @mmio: base address of the HBA 3167101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 3168101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * This routine only applies to 6xxx parts. 3169101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 3170101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * LOCKING: 3171101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * Inherited from caller. 3172101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 3173c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3174c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 3175101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 3176cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord void __iomem *reg = mmio + PCI_MAIN_CMD_STS; 3177101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik int i, rc = 0; 3178101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 t; 3179101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3180101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* Following procedure defined in PCI "main command and status 3181101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * register" table. 3182101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 3183101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 3184101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | STOP_PCI_MASTER, reg); 3185101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3186101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik for (i = 0; i < 1000; i++) { 3187101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 3188101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 31892dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik if (PCI_MASTER_EMPTY & t) 3190101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik break; 3191101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3192101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(PCI_MASTER_EMPTY & t)) { 3193101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 3194101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 3195101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 3196101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3197101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3198101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* set reset */ 3199101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 3200101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 3201101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | GLOB_SFT_RST, reg); 3202101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 3203101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 3204101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 3205101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3206101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(GLOB_SFT_RST & t)) { 3207101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 3208101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 3209101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 3210101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3211101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3212101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 3213101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 3214101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 3215101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 3216101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 3217101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 3218101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while ((GLOB_SFT_RST & t) && (i-- > 0)); 3219101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3220101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (GLOB_SFT_RST & t) { 3221101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 3222101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 3223101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3224101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikdone: 3225101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik return rc; 3226101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 3227101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 322847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 3229ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 3230ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 3231ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *port_mmio; 3232ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik u32 tmp; 3233ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3234cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(mmio + RESET_CFG); 3235ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik if ((tmp & (1 << 0)) == 0) { 323647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->signal[idx].amps = 0x7 << 8; 3237ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = 0x1 << 5; 3238ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik return; 3239ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik } 3240ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3241ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik port_mmio = mv_port_base(mmio, idx); 3242ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(port_mmio + PHY_MODE2); 3243ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3244ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3245ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3246ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3247ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 324847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 3249ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 3250cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x00000060, mmio + GPIO_PORT_CTL); 3251ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3252ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3253c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 32542a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 3255bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 3256c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 3257c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3258bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 325947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik int fix_phy_mode2 = 326047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 3261bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik int fix_phy_mode4 = 326247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 32638c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord u32 m2, m3; 326447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 326547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (fix_phy_mode2) { 326647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 326747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 326847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 |= (1 << 31); 326947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 327047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 327147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 327247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 327347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 327447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~((1 << 16) | (1 << 31)); 327547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 327647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 327747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 327847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 327947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 32808c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord /* 32818c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord * Gen-II/IIe PHY_MODE3 errata RM#2: 32828c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord * Achieves better receiver noise performance than the h/w default: 32838c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord */ 32848c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord m3 = readl(port_mmio + PHY_MODE3); 32858c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord m3 = (m3 & 0x1f) | (0x5555601 << 5); 3286bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 32870388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord /* Guideline 88F5182 (GL# SATA-S11) */ 32880388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord if (IS_SOC(hpriv)) 32890388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord m3 &= ~0x1c; 32900388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord 3291bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (fix_phy_mode4) { 3292ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord u32 m4 = readl(port_mmio + PHY_MODE4); 3293ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord /* 3294ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * Enforce reserved-bit restrictions on GenIIe devices only. 3295ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * For earlier chipsets, force only the internal config field 3296ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * (workaround for errata FEr SATA#10 part 1). 3297ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord */ 32988c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord if (IS_GEN_IIE(hpriv)) 3299ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES; 3300ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord else 3301ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE; 33028c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord writel(m4, port_mmio + PHY_MODE4); 3303bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3304b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord /* 3305b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * Workaround for 60x1-B2 errata SATA#13: 3306b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3, 3307b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * so we must always rewrite PHY_MODE3 after PHY_MODE4. 3308ba68460b8e019dfd9c73ab69f5ed163a8b24e296Mark Lord * Or ensure we use writelfl() when writing PHY_MODE4. 3309b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord */ 3310b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord writel(m3, port_mmio + PHY_MODE3); 3311bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3312bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik /* Revert values of pre-emphasis and signal amps to the saved ones */ 3313bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 3314bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3315bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 &= ~MV_M2_PREAMP_MASK; 33162a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].amps; 33172a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].pre; 331847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 3319bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3320e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* according to mvSata 3.6.1, some IIE values are fixed */ 3321e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (IS_GEN_IIE(hpriv)) { 3322e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 &= ~0xC30FF01F; 3323e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 |= 0x0000900F; 3324e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 3325e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 3326bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 3327bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 3328bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3329f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* TODO: use the generic LED interface to configure the SATA Presence */ 3330f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* & Acitivy LEDs on the board */ 3331f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 3332f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3333f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3334f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 3335f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3336f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3337f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 3338f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3339f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3340f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio; 3341f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara u32 tmp; 3342f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3343f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara port_mmio = mv_port_base(mmio, idx); 3344f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(port_mmio + PHY_MODE2); 3345f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3346f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3347f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3348f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3349f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3350f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 3351f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, port_mmio + (reg)) 3352f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 3353f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int port) 3354f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3355f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio = mv_port_base(mmio, port); 3356f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3357e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 3358f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3359f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x028); /* command */ 3360cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x101f, port_mmio + EDMA_CFG); 3361f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x004); /* timer */ 3362f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x008); /* irq err cause */ 3363f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); /* irq err mask */ 3364f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); /* rq bah */ 3365f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); /* rq inp */ 3366f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x018); /* rq outp */ 3367f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x01c); /* respq bah */ 3368f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x024); /* respq outp */ 3369f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x020); /* respq inp */ 3370f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x02c); /* test control */ 3371cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 3372f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3373f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3374f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 3375f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3376f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, hc_mmio + (reg)) 3377f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 3378f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3379f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3380f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *hc_mmio = mv_hc_base(mmio, 0); 3381f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3382f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); 3383f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); 3384f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); 3385f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3386f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3387f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3388f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 3389f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3390f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 3391f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc) 3392f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3393f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int port; 3394f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3395f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara for (port = 0; port < hpriv->n_ports; port++) 3396f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_hc_port(hpriv, mmio, port); 3397f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3398f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_one_hc(hpriv, mmio); 3399f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3400f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 3401f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3402f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3403f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 3404f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3405f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3406f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 3407f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3408f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3409f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 3410f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3411f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 3412f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3413f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 341429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayrstatic void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, 341529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr void __iomem *mmio, unsigned int port) 341629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr{ 341729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr void __iomem *port_mmio = mv_port_base(mmio, port); 341829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr u32 reg; 341929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 342029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg = readl(port_mmio + PHY_MODE3); 342129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */ 342229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg |= (0x1 << 27); 342329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */ 342429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg |= (0x1 << 29); 342529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr writel(reg, port_mmio + PHY_MODE3); 342629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 342729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg = readl(port_mmio + PHY_MODE4); 342829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */ 342929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg |= (0x1 << 16); 343029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr writel(reg, port_mmio + PHY_MODE4); 343129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 343229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg = readl(port_mmio + PHY_MODE9_GEN2); 343329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */ 343429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg |= 0x8; 343529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */ 343629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr writel(reg, port_mmio + PHY_MODE9_GEN2); 343729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 343829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg = readl(port_mmio + PHY_MODE9_GEN1); 343929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */ 344029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg |= 0x8; 344129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */ 344229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr writel(reg, port_mmio + PHY_MODE9_GEN1); 344329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr} 344429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 344529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr/** 344629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr * soc_is_65 - check if the soc is 65 nano device 344729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr * 344829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr * Detect the type of the SoC, this is done by reading the PHYCFG_OFS 344929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr * register, this register should contain non-zero value and it exists only 345029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr * in the 65 nano devices, when reading it from older devices we get 0. 345129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr */ 345229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayrstatic bool soc_is_65n(struct mv_host_priv *hpriv) 345329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr{ 345429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr void __iomem *port0_mmio = mv_port_base(hpriv->base, 0); 345529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 345629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr if (readl(port0_mmio + PHYCFG_OFS)) 345729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr return true; 345829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr return false; 345929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr} 346029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 34618e7decdb8b132ee970a2636931b7653dec6af472Mark Lordstatic void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) 3462b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord{ 3463cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 ifcfg = readl(port_mmio + SATA_IFCFG); 3464b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 34658e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */ 3466b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (want_gen2i) 34678e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg |= (1 << 7); /* enable gen2i speed */ 3468cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(ifcfg, port_mmio + SATA_IFCFG); 3469b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord} 3470b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 3471e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 3472c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no) 3473c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 3474c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port_no); 3475c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 34768e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* 34778e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * The datasheet warns against setting EDMA_RESET when EDMA is active 34788e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * (but doesn't say what the problem might be). So we first try 34798e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * to disable the EDMA engine before doing the EDMA_RESET operation. 34808e7decdb8b132ee970a2636931b7653dec6af472Mark Lord */ 34810d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord mv_stop_edma_engine(port_mmio); 3482cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD); 3483c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3484b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (!IS_GEN_I(hpriv)) { 34858e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* Enable 3.0gb/s link speed: this survives EDMA_RESET */ 34868e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(port_mmio, 1); 3487c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 3488b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord /* 34898e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * Strobing EDMA_RESET here causes a hard reset of the SATA transport, 3490b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * link, and physical layers. It resets all SATA interface registers 3491cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord * (except for SATA_IFCFG), and issues a COMRESET to the dev. 3492c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik */ 3493cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD); 3494b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord udelay(25); /* allow reset propagation */ 3495cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, port_mmio + EDMA_CMD); 3496c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3497c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->ops->phy_errata(hpriv, mmio, port_no); 3498c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3499ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) 3500c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mdelay(1); 3501c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3502c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3503e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp) 350420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 3505e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (sata_pmp_supported(ap)) { 3506e49856d82a887ce365637176f9f99ab68076eae8Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 3507cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 reg = readl(port_mmio + SATA_IFCTL); 3508e49856d82a887ce365637176f9f99ab68076eae8Mark Lord int old = reg & 0xf; 350922374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 3510e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (old != pmp) { 3511e49856d82a887ce365637176f9f99ab68076eae8Mark Lord reg = (reg & ~0xf) | pmp; 3512cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(reg, port_mmio + SATA_IFCTL); 3513e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 351422374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik } 351520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 351620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3517e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 3518e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 351922374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik{ 3520e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 3521e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return sata_std_hardreset(link, class, deadline); 3522e49856d82a887ce365637176f9f99ab68076eae8Mark Lord} 3523bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3524e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 3525e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 3526e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 3527e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 3528e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return ata_sff_softreset(link, class, deadline); 352922374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik} 353022374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 3531cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 3532bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned long deadline) 353331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 3534cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo struct ata_port *ap = link->ap; 3535bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 3536b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 3537f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 35380d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord int rc, attempts = 0, extra = 0; 35390d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord u32 sstatus; 35400d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord bool online; 354131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3542e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, ap->port_no); 3543b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 3544d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= 3545d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 3546bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 35470d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Workaround for errata FEr SATA#10 (part 2) */ 35480d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord do { 354917c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord const unsigned long *timing = 355017c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord sata_ehc_deb_timing(&link->eh_context); 3551bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 355217c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord rc = sata_link_hardreset(link, timing, deadline + extra, 355317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord &online, NULL); 35549dcffd99d0b1c0c1b8b2c0f85d240e791eca1055Mark Lord rc = online ? -EAGAIN : rc; 355517c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord if (rc) 35560d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord return rc; 35570d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord sata_scr_read(link, SCR_STATUS, &sstatus); 35580d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 35590d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Force 1.5gb/s link speed and try again */ 35608e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(mv_ap_base(ap), 0); 35610d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (time_after(jiffies + HZ, deadline)) 35620d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord extra = HZ; /* only extend it once, max */ 35630d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } 35640d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); 356508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_save_cached_regs(ap); 356666e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord mv_edma_cfg(ap, 0, 0); 3567bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 356817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord return rc; 3569bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 3570bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3571bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap) 3572bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 35731cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord mv_stop_edma(ap); 3574c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_enable_port_irqs(ap, 0); 3575bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 3576bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3577bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap) 3578bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 3579f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 3580c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int port = ap->port_no; 3581c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int hardport = mv_hardport_from_port(port); 35821cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); 3583bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 3584c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 hc_irq_cause; 3585bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3586bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA errors on this port */ 3587cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 3588bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3589bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear pending irq events */ 3590cae6edc3b5a536119374a5439d9b253cb26f05e1Mark Lord hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 3591cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); 3592bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 359388e675e193159b9891c1c576de4348eaf490f5d0Mark Lord mv_enable_port_irqs(ap, ERR_IRQ); 359431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 359531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 359605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 359705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_init - Perform some early initialization on a single port. 359805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port: libata data structure storing shadow register addresses 359905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port_mmio: base address of the port 360005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 360105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Initialize shadow register mmio addresses, clear outstanding 360205b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts on the port, and unmask interrupts for the future 360305b308e1df6d9d673daedb517969241f41278b52Brett Russ * start of the port. 360405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 360505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 360605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 360705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 360831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 360920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 3610cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord void __iomem *serr, *shd_base = port_mmio + SHD_BLK; 361131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 36128b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik /* PIO related setup 361331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 361431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 36158b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->error_addr = 361631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 361731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 361831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 361931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 362031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 362131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 36228b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->status_addr = 362331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 362431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* special case: control/altstatus doesn't have ATA_REG_ address */ 3625cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST; 362631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 362731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* unused: */ 36288d9db2d2fbae9e05022825c32f86e00c8e342860Randy Dunlap port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; 362920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 363031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding port interrupt conditions */ 3631cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord serr = port_mmio + mv_scr_offset(SCR_ERROR); 3632cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(readl(serr), serr); 3633cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 363431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3635646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord /* unmask all non-transient EDMA error interrupts */ 3636cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK); 363720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 36388b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 3639cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(port_mmio + EDMA_CFG), 3640cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(port_mmio + EDMA_ERR_IRQ_CAUSE), 3641cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(port_mmio + EDMA_ERR_IRQ_MASK)); 364220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 364320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3644616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic unsigned int mv_in_pcix_mode(struct ata_host *host) 3645616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 3646616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 3647616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 3648616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 3649616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 36501f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (IS_SOC(hpriv) || !IS_PCIE(hpriv)) 3651616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not PCI-X capable */ 3652cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord reg = readl(mmio + MV_PCI_MODE); 3653616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if ((reg & MV_PCI_MODE_MASK) == 0) 3654616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* conventional PCI mode */ 3655616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* chip is in PCI-X mode */ 3656616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 3657616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 3658616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic int mv_pci_cut_through_okay(struct ata_host *host) 3659616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 3660616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 3661616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 3662616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 3663616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 3664616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (!mv_in_pcix_mode(host)) { 3665cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord reg = readl(mmio + MV_PCI_COMMAND); 3666cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord if (reg & MV_PCI_COMMAND_MRDTRIG) 3667616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not okay */ 3668616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord } 3669616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* okay */ 3670616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 3671616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 367265ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lordstatic void mv_60x1b2_errata_pci7(struct ata_host *host) 367365ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord{ 367465ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord struct mv_host_priv *hpriv = host->private_data; 367565ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord void __iomem *mmio = hpriv->base; 367665ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord 367765ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord /* workaround for 60x1-B2 errata PCI#7 */ 367865ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord if (mv_in_pcix_mode(host)) { 3679cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 reg = readl(mmio + MV_PCI_COMMAND); 3680cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND); 368165ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord } 368265ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord} 368365ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord 36844447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_chip_id(struct ata_host *host, unsigned int board_idx) 3685bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 36864447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 36874447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 3688bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 3689bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 36905796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik switch (board_idx) { 369147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case chip_5080: 369247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 3693ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 369447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 369544c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 369647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x1: 369747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 369847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 369947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 370047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 370147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 370247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 370347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 370447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying 50XXB2 workarounds to unknown rev\n"); 370547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 370647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 370747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 370847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 370947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 3710bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_504x: 3711bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_508x: 371247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 3713ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 3714bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 371544c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 371647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x0: 371747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 371847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 371947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 372047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 372147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 372247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 372347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 372447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 372547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 372647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 3727bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3728bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3729bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3730bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_604x: 3731bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_608x: 373247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv6xxx_ops; 3733ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_II; 373447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 373544c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 373647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x7: 373765ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord mv_60x1b2_errata_pci7(host); 373847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 373947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 374047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x9: 374147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3742bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3743bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 3744bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 374547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 374647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 3747bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3748bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3749bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3750bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3751e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_7042: 3752616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH; 3753306b30f74d37f289033c696285e07ce0158a5d7bMark Lord if (pdev->vendor == PCI_VENDOR_ID_TTI && 3754306b30f74d37f289033c696285e07ce0158a5d7bMark Lord (pdev->device == 0x2300 || pdev->device == 0x2310)) 3755306b30f74d37f289033c696285e07ce0158a5d7bMark Lord { 37564e5200334e03e5620aa19d538300c13db270a063Mark Lord /* 37574e5200334e03e5620aa19d538300c13db270a063Mark Lord * Highpoint RocketRAID PCIe 23xx series cards: 37584e5200334e03e5620aa19d538300c13db270a063Mark Lord * 37594e5200334e03e5620aa19d538300c13db270a063Mark Lord * Unconfigured drives are treated as "Legacy" 37604e5200334e03e5620aa19d538300c13db270a063Mark Lord * by the BIOS, and it overwrites sector 8 with 37614e5200334e03e5620aa19d538300c13db270a063Mark Lord * a "Lgcy" metadata block prior to Linux boot. 37624e5200334e03e5620aa19d538300c13db270a063Mark Lord * 37634e5200334e03e5620aa19d538300c13db270a063Mark Lord * Configured drives (RAID or JBOD) leave sector 8 37644e5200334e03e5620aa19d538300c13db270a063Mark Lord * alone, but instead overwrite a high numbered 37654e5200334e03e5620aa19d538300c13db270a063Mark Lord * sector for the RAID metadata. This sector can 37664e5200334e03e5620aa19d538300c13db270a063Mark Lord * be determined exactly, by truncating the physical 37674e5200334e03e5620aa19d538300c13db270a063Mark Lord * drive capacity to a nice even GB value. 37684e5200334e03e5620aa19d538300c13db270a063Mark Lord * 37694e5200334e03e5620aa19d538300c13db270a063Mark Lord * RAID metadata is at: (dev->n_sectors & ~0xfffff) 37704e5200334e03e5620aa19d538300c13db270a063Mark Lord * 37714e5200334e03e5620aa19d538300c13db270a063Mark Lord * Warn the user, lest they think we're just buggy. 37724e5200334e03e5620aa19d538300c13db270a063Mark Lord */ 37734e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 37744e5200334e03e5620aa19d538300c13db270a063Mark Lord " BIOS CORRUPTS DATA on all attached drives," 37754e5200334e03e5620aa19d538300c13db270a063Mark Lord " regardless of if/how they are configured." 37764e5200334e03e5620aa19d538300c13db270a063Mark Lord " BEWARE!\n"); 37774e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": For data safety, do not" 37784e5200334e03e5620aa19d538300c13db270a063Mark Lord " use sectors 8-9 on \"Legacy\" drives," 37794e5200334e03e5620aa19d538300c13db270a063Mark Lord " and avoid the final two gigabytes on" 37804e5200334e03e5620aa19d538300c13db270a063Mark Lord " all RocketRAID BIOS initialized drives.\n"); 3781306b30f74d37f289033c696285e07ce0158a5d7bMark Lord } 37828e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* drop through */ 3783e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_6042: 3784e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hpriv->ops = &mv6xxx_ops; 3785e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_GEN_IIE; 3786616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (board_idx == chip_6042 && mv_pci_cut_through_okay(host)) 3787616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_CUT_THROUGH; 3788e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 378944c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 37905cf73bfb061552aa18d816d2859409be9ace5306Mark Lord case 0x2: /* Rev.B0: the first/only public release */ 3791e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3792e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3793e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik default: 3794e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 3795e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik "Applying 60X1C0 workarounds to unknown rev\n"); 3796e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3797e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3798e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 3799e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3800f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara case chip_soc: 380129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr if (soc_is_65n(hpriv)) 380229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr hpriv->ops = &mv_soc_65n_ops; 380329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr else 380429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr hpriv->ops = &mv_soc_ops; 3805eb3a55a9f43f0f8e770c2abf70e65bdda2d5ff1eSaeed Bishara hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE | 3806eb3a55a9f43f0f8e770c2abf70e65bdda2d5ff1eSaeed Bishara MV_HP_ERRATA_60X1C0; 3807f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara break; 3808e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 3809bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 3810f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_ERR, host->dev, 38115796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik "BUG: invalid board index %u\n", board_idx); 3812bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 1; 3813bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3814bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3815bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik hpriv->hp_flags = hp_flags; 381602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord if (hp_flags & MV_HP_PCIE) { 3817cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->irq_cause_offset = PCIE_IRQ_CAUSE; 3818cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->irq_mask_offset = PCIE_IRQ_MASK; 381902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 382002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } else { 3821cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->irq_cause_offset = PCI_IRQ_CAUSE; 3822cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->irq_mask_offset = PCI_IRQ_MASK; 382302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 382402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } 3825bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3826bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 0; 3827bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 3828bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 382905b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 383047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik * mv_init_host - Perform some early initialization of the host. 38314447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to initialize 38324447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @board_idx: controller index 383305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 383405b308e1df6d9d673daedb517969241f41278b52Brett Russ * If possible, do an early global reset of the host. Then do 383505b308e1df6d9d673daedb517969241f41278b52Brett Russ * our port init and clear/unmask all/relevant host interrupts. 383605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 383705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 383805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 383905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 38404447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_init_host(struct ata_host *host, unsigned int board_idx) 384120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 384220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ int rc = 0, n_hc, port, hc; 38434447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 3844f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 384547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 38464447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_chip_id(host, board_idx); 3847bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (rc) 3848352fab701ca4753dd005b67ce5e512be944eb591Mark Lord goto done; 3849f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 38501f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (IS_SOC(hpriv)) { 3851cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE; 3852cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK; 38531f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord } else { 3854cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE; 3855cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK; 3856f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 3857352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 38585d0fb2e730e2085021cf5c8b6d14983e92aea75bThomas Reitmayr /* initialize shadow irq mask with register's value */ 38595d0fb2e730e2085021cf5c8b6d14983e92aea75bThomas Reitmayr hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr); 38605d0fb2e730e2085021cf5c8b6d14983e92aea75bThomas Reitmayr 3861352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* global interrupt mask: 0 == mask everything */ 3862c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_set_main_irq_mask(host, ~0, 0); 3863bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 38644447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_hc = mv_get_hc_count(host->ports[0]->flags); 3865bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 38664447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) 386729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr if (hpriv->ops->read_preamp) 386829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr hpriv->ops->read_preamp(hpriv, port, mmio); 386920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3870c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 387147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (rc) 387220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ goto done; 387320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3874522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik hpriv->ops->reset_flash(hpriv, mmio); 38757bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara hpriv->ops->reset_bus(host, mmio); 387647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->enable_leds(hpriv, mmio); 387720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 38784447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) { 3879cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo struct ata_port *ap = host->ports[port]; 38802a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 3881cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 3882cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo mv_port_init(&ap->ioaddr, port_mmio); 3883cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 38847bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 38851f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (!IS_SOC(hpriv)) { 3886f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int offset = port_mmio - mmio; 3887f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 3888f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 3889f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 38907bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 389120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 389220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 389320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hc; hc++) { 389431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 389531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 389631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 389731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ "(before clear)=0x%08x\n", hc, 3898cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(hc_mmio + HC_CFG), 3899cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(hc_mmio + HC_IRQ_CAUSE)); 390031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 390131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding hc interrupt conditions */ 3902cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, hc_mmio + HC_IRQ_CAUSE); 390320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 390420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 390544c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord if (!IS_SOC(hpriv)) { 390644c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord /* Clear any currently outstanding host interrupt conditions */ 3907cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, mmio + hpriv->irq_cause_offset); 390831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 390944c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord /* and unmask interrupt generation for host regs */ 3910cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset); 391144c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord } 391251de32d200b21333950abc52ea1e589bc4eecef7Mark Lord 39136be96ac15e4d913e1f48299db083ada5321803b2Mark Lord /* 39146be96ac15e4d913e1f48299db083ada5321803b2Mark Lord * enable only global host interrupts for now. 39156be96ac15e4d913e1f48299db083ada5321803b2Mark Lord * The per-port interrupts get done later as ports are set up. 39166be96ac15e4d913e1f48299db083ada5321803b2Mark Lord */ 39176be96ac15e4d913e1f48299db083ada5321803b2Mark Lord mv_set_main_irq_mask(host, 0, PCI_ERR); 39182b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_set_irq_coalescing(host, irq_coalescing_io_count, 39192b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord irq_coalescing_usecs); 3920f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharadone: 3921f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3922f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3923fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik 3924fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradleystatic int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 3925fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley{ 3926fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 3927fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRQB_Q_SZ, 0); 3928fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crqb_pool) 3929fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3930fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3931fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 3932fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRPB_Q_SZ, 0); 3933fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crpb_pool) 3934fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3935fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3936fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 3937fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_SG_TBL_SZ, 0); 3938fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->sg_tbl_pool) 3939fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3940fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3941fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return 0; 3942fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley} 3943fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 394415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhekstatic void mv_conf_mbus_windows(struct mv_host_priv *hpriv, 394515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_target_info *dram) 394615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek{ 394715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek int i; 394815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 394915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < 4; i++) { 395015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_CTRL(i)); 395115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_BASE(i)); 395215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 395315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 395415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < dram->num_cs; i++) { 395515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_window *cs = dram->cs + i; 395615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 395715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(((cs->size - 1) & 0xffff0000) | 395815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (cs->mbus_attr << 8) | 395915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (dram->mbus_dram_target_id << 4) | 1, 396015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek hpriv->base + WINDOW_CTRL(i)); 396115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(cs->base, hpriv->base + WINDOW_BASE(i)); 396215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 396315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek} 396415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 3965f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/** 3966f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_probe - handle a positive probe of an soc Marvell 3967f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * host 3968f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device found 3969f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 3970f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * LOCKING: 3971f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Inherited from caller. 3972f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3973f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev) 3974f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3975f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara static int printed_version; 3976f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct mv_sata_platform_data *mv_platform_data; 3977f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct ata_port_info *ppi[] = 3978f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { &mv_port_info[chip_soc], NULL }; 3979f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host; 3980f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv; 3981f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct resource *res; 3982f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports, rc; 398320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3984f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!printed_version++) 3985f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 3986bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3987f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 3988f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Simple resource validation .. 3989f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3990f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (unlikely(pdev->num_resources != 2)) { 3991f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_err(&pdev->dev, "invalid number of resources\n"); 3992f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 3993f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 3994f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3995f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 3996f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Get the register base first 3997f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3998f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3999f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (res == NULL) 4000f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 4001f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4002f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* allocate host */ 4003f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_platform_data = pdev->dev.platform_data; 4004f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara n_ports = mv_platform_data->n_ports; 4005f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4006f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 4007f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 4008f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4009f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!host || !hpriv) 4010f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -ENOMEM; 4011f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->private_data = hpriv; 4012f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 4013f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4014f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->iomap = NULL; 4015f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara hpriv->base = devm_ioremap(&pdev->dev, res->start, 4016041b5eac254107cd3ba60034c38a411531cc64eeJulia Lawall resource_size(res)); 4017cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->base -= SATAHC0_REG_BASE; 4018f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 401915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek /* 402015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek * (Re-)program MBUS remapping windows if we are asked to. 402115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek */ 402215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek if (mv_platform_data->dram != NULL) 402315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek mv_conf_mbus_windows(hpriv, mv_platform_data->dram); 402415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 4025fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley rc = mv_create_dma_pools(hpriv, &pdev->dev); 4026fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (rc) 4027fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return rc; 4028fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 4029f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* initialize adapter */ 4030f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = mv_init_host(host, chip_soc); 4031f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc) 4032f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 4033f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4034f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, 4035f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, 4036f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->n_ports); 4037f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4038f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, 4039f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara IRQF_SHARED, &mv6_sht); 4040f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 4041f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4042f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* 4043f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 4044f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_remove - unplug a platform interface 4045f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device 4046f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 4047f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * A platform bus SATA device has been unplugged. Perform the needed 4048f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * cleanup. Also called on module unload for any active devices. 4049f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 4050f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev) 4051f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 4052f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct device *dev = &pdev->dev; 4053f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host = dev_get_drvdata(dev); 4054f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4055f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_host_detach(host); 4056f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 405720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 405820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4059f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic struct platform_driver mv_platform_driver = { 4060f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_platform_probe, 4061f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .remove = __devexit_p(mv_platform_remove), 4062f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .driver = { 4063f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .name = DRV_NAME, 4064f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .owner = THIS_MODULE, 4065f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 4066f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 4067f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4068f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 40697bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 4070f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 4071f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent); 4072f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 40737bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 40747bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic struct pci_driver mv_pci_driver = { 40757bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .name = DRV_NAME, 40767bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .id_table = mv_pci_tbl, 4077f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_pci_init_one, 40787bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .remove = ata_pci_remove_one, 40797bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara}; 40807bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 40817bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* move to PCI layer or libata core? */ 40827bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int pci_go_64(struct pci_dev *pdev) 40837bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara{ 40847bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc; 40857bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 40866a35528a8346f6e6fd32ed7e51f04d1fa4ca2c01Yang Hongyang if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 40876a35528a8346f6e6fd32ed7e51f04d1fa4ca2c01Yang Hongyang rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 40887bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 4089284901a90a9e0b812ca3f5f852cbbfb60d10249dYang Hongyang rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 40907bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 40917bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 40927bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "64-bit DMA enable failed\n"); 40937bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 40947bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 40957bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 40967bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } else { 4097284901a90a9e0b812ca3f5f852cbbfb60d10249dYang Hongyang rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 40987bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 40997bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 41007bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit DMA enable failed\n"); 41017bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 41027bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 4103284901a90a9e0b812ca3f5f852cbbfb60d10249dYang Hongyang rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 41047bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 41057bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 41067bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit consistent DMA enable failed\n"); 41077bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 41087bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 41097bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 41107bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 41117bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 41127bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara} 41137bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 411405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 411505b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_print_info - Dump key info to kernel log for perusal. 41164447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to print info about 411705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 411805b308e1df6d9d673daedb517969241f41278b52Brett Russ * FIXME: complete this. 411905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 412005b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 412105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 412205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 41234447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic void mv_print_info(struct ata_host *host) 412431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 41254447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 41264447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 412744c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok u8 scc; 4128c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik const char *scc_s, *gen; 412931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 413031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Use this to determine the HW stepping of the chip so we know 413131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * what errata to workaround 413231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 413331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 413431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (scc == 0) 413531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "SCSI"; 413631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else if (scc == 0x01) 413731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "RAID"; 413831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else 4139c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik scc_s = "?"; 4140c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik 4141c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik if (IS_GEN_I(hpriv)) 4142c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "I"; 4143c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_II(hpriv)) 4144c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "II"; 4145c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_IIE(hpriv)) 4146c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "IIE"; 4147c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else 4148c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "?"; 414931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 4150a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, 4151c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 4152c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 415331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 415431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 415531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 415605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 4157f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_pci_init_one - handle a positive probe of a PCI Marvell host 415805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pdev: PCI device found 415905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ent: PCI device ID entry for the matched host 416005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 416105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 416205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 416305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 4164f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 4165f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent) 416620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 41672dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik static int printed_version; 416820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int board_idx = (unsigned int)ent->driver_data; 41694447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 41704447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct ata_host *host; 41714447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv; 41724447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo int n_ports, rc; 417320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4174a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik if (!printed_version++) 4175a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 417620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 41774447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* allocate host */ 41784447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 41794447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 41804447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 41814447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 41824447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (!host || !hpriv) 41834447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return -ENOMEM; 41844447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->private_data = hpriv; 4185f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 41864447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 41874447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* acquire resources */ 418824dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo rc = pcim_enable_device(pdev); 418924dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 419020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return rc; 419120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 41920d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 41930d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc == -EBUSY) 419424dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pcim_pin_device(pdev); 41950d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc) 419624dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 41974447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->iomap = pcim_iomap_table(pdev); 4198f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base = host->iomap[MV_PRIMARY_BAR]; 419920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4200d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik rc = pci_go_64(pdev); 4201d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik if (rc) 4202d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik return rc; 4203d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik 4204da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord rc = mv_create_dma_pools(hpriv, &pdev->dev); 4205da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (rc) 4206da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return rc; 4207da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 420820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* initialize adapter */ 42094447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_init_host(host, board_idx); 421024dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 421124dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 421220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 42136d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord /* Enable message-switched interrupts, if requested */ 42146d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord if (msi && pci_enable_msi(pdev) == 0) 42156d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord hpriv->hp_flags |= MV_HP_FLAG_MSI; 421620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 421731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 42184447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo mv_print_info(host); 421920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 42204447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo pci_set_master(pdev); 4221ea8b4db97aa41a66c05daa4055a1974692ccd52dJeff Garzik pci_try_set_mwi(pdev); 42224447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 4223c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 422420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 42257bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 422620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4227f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev); 4228f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev); 4229f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 423020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic int __init mv_init(void) 423120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 42327bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc = -ENODEV; 42337bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 42347bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_register_driver(&mv_pci_driver); 4235f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 4236f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 4237f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#endif 4238f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = platform_driver_register(&mv_platform_driver); 4239f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4240f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#ifdef CONFIG_PCI 4241f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 4242f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara pci_unregister_driver(&mv_pci_driver); 42437bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 42447bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 424520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 424620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 424720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic void __exit mv_exit(void) 424820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 42497bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 425020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ pci_unregister_driver(&mv_pci_driver); 42517bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 4252f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara platform_driver_unregister(&mv_platform_driver); 425320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 425420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 425520f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_AUTHOR("Brett Russ"); 425620f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 425720f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_LICENSE("GPL"); 425820f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DEVICE_TABLE(pci, mv_pci_tbl); 425920f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_VERSION(DRV_VERSION); 426017c5aab5b34e351531466e35b154ca86db7d46a9Mark LordMODULE_ALIAS("platform:" DRV_NAME); 426120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 426220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_init(mv_init); 426320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_exit(mv_exit); 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