sata_mv.c revision 17c5aab5b34e351531466e35b154ca86db7d46a9
120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * sata_mv.c - Marvell SATA support 320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 4e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * Copyright 2008: Marvell Corporation, all rights reserved. 58b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * Copyright 2005: EMC Corporation, all rights reserved. 6e2b1be56c5656902744c2b52e8304126a40bb609Jeff Garzik * Copyright 2005 Red Hat, Inc. All rights reserved. 720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is free software; you can redistribute it and/or modify 1120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * it under the terms of the GNU General Public License as published by 1220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * the Free Software Foundation; version 2 of the License. 1320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is distributed in the hope that it will be useful, 1520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * but WITHOUT ANY WARRANTY; without even the implied warranty of 1620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * GNU General Public License for more details. 1820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * You should have received a copy of the GNU General Public License 2020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * along with this program; if not, write to the Free Software 2120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 2220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 254a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik/* 264a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik sata_mv TODO list: 274a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 284a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 1) Needs a full errata audit for all chipsets. I implemented most 294a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik of the errata workarounds found in the Marvell vendor driver, but 304a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik I distinctly remember a couple workarounds (one related to PCI-X) 314a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik are still needed. 324a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 331fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 2) Improve/fix IRQ and error handling sequences. 341fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 351fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 3) ATAPI support (Marvell claims the 60xx/70xx chips can do it). 361fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 371fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 4) Think about TCQ support here, and for libata in general 381fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord with controllers that suppport it via host-queuing hardware 391fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord (a software-only implementation could be a nightmare). 404a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 414a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 5) Investigate problems with PCI Message Signalled Interrupts (MSI). 424a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 434a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 6) Add port multiplier support (intermediate) 444a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 454a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 8) Develop a low-power-consumption strategy, and implement it. 464a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 474a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 9) [Experiment, low priority] See if ATAPI can be supported using 484a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik "unknown FIS" or "vendor-specific FIS" support, or something creative 494a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik like that. 504a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 514a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 10) [Experiment, low priority] Investigate interrupt coalescing. 524a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik Quite often, especially with PCI Message Signalled Interrupts (MSI), 534a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik the overhead reduced by interrupt mitigation is quite often not 544a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik worth the latency cost. 554a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 564a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 11) [Experiment, Marvell value added] Is it possible to use target 574a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik mode to cross-connect two Linux boxes with Marvell cards? If so, 584a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik creating LibATA target mode support would be very interesting. 594a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 604a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik Target mode, for those without docs, is the ability to directly 614a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik connect two SATA controllers. 624a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 634a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik*/ 644a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 6520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/kernel.h> 6620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/module.h> 6720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/pci.h> 6820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/init.h> 6920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/blkdev.h> 7020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/delay.h> 7120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/interrupt.h> 728d8b60046d6a2328ca4b9031b4948084f775f607Andrew Morton#include <linux/dmapool.h> 7320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/dma-mapping.h> 74a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik#include <linux/device.h> 75f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/platform_device.h> 76f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/ata_platform.h> 7720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <scsi/scsi_host.h> 78193515d51ccb363165d6b09e9ba5c21089e34badJeff Garzik#include <scsi/scsi_cmnd.h> 796c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik#include <scsi/scsi_device.h> 8020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/libata.h> 8120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#define DRV_NAME "sata_mv" 831fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord#define DRV_VERSION "1.20" 8420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russenum { 8620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* BAR's are enumerated in terms of pci_resource_start() terms */ 8720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 8820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IO_BAR = 2, /* offset 0x18: IO space */ 8920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 9020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 9120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 9220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 9320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 9420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_BASE = 0, 9520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ 96615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08), 97615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88), 98615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c), 99615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc), 100615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0), 101615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 10220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC0_REG_BASE = 0x20000, 103522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_FLASH_CTL = 0x1046c, 104bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_GPIO_PORT_CTL = 0x104f0, 105bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_RESET_CFG = 0x180d8, 10620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 10720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 10820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 10920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 11020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 11120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 11231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH = 32, 11331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 11431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 11531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* CRQB needs alignment on a 1KB boundary. Size == 1KB 11631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * CRPB needs alignment on a 256B boundary. Size == 256B 11731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 11831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 11931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 12031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 121da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord MV_MAX_SG_CT = 256, 12231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 12331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 12420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORTS_PER_HC = 4, 12520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */ 12620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_HC_SHIFT = 2, 12731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */ 12820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_MASK = 3, 12920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 13020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Host Flags */ 13120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 13220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ 1337bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara /* SoC integrated controllers, no PCI interface */ 134e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord MV_FLAG_SOC = (1 << 28), 1357bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 136c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 137bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI | 138bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ATA_FLAG_PIO_POLLING, 13947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE, 14020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 14131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_FLAG_READ = (1 << 0), 14231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_TAG_SHIFT = 1, 143c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 144e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 145c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 14631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_ADDR_SHIFT = 8, 14731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_CS = (0x2 << 11), 14831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_LAST = (1 << 15), 14931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRPB_FLAG_STATUS_SHIFT = 8, 151c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 152c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 15331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EPRD_FLAG_END_OF_TBL = (1 << 31), 15531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* PCI interface registers */ 15720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 15831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ PCI_COMMAND_OFS = 0xc00, 15931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 16020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MAIN_CMD_STS_OFS = 0xd30, 16120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ STOP_PCI_MASTER = (1 << 2), 16220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MASTER_EMPTY = (1 << 3), 16320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GLOB_SFT_RST = (1 << 4), 16420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 165522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MODE = 0xd00, 166522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 167522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_DISC_TIMER = 0xd04, 168522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MSI_TRIGGER = 0xc38, 169522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_SERR_MASK = 0xc28, 170522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_XBAR_TMOUT = 0x1d04, 171522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 172522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 173522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_ATTRIBUTE = 0x1d48, 174522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_COMMAND = 0x1d50, 175522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 17602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_CAUSE_OFS = 0x1d58, 17702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_MASK_OFS = 0x1d5c, 17820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 17920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 18002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_CAUSE_OFS = 0x1900, 18102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_MASK_OFS = 0x1910, 182646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 18302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 18420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, 18520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_IRQ_MASK_OFS = 0x1d64, 186f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_SOC_MAIN_IRQ_CAUSE_OFS = 0x20020, 187f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_SOC_MAIN_IRQ_MASK_OFS = 0x20024, 18820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORT0_ERR = (1 << 0), /* shift by port # */ 18920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORT0_DONE = (1 << 1), /* shift by port # */ 19020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 19120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 19220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_ERR = (1 << 18), 19320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */ 19420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */ 195fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_0_3_COAL_DONE = (1 << 8), 196fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_4_7_COAL_DONE = (1 << 17), 19720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */ 19820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GPIO_INT = (1 << 22), 19920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SELF_INT = (1 << 23), 20020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TWSI_INT = (1 << 24), 20120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 202fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 203e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 2048b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | 20520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT | 20620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD), 207fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 208fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5), 209f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC), 21020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATAHC registers */ 21220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_CFG_OFS = 0, 21320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_IRQ_CAUSE_OFS = 0x14, 21531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRPB_DMA_DONE = (1 << 0), /* shift by port # */ 21620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */ 21720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ DEV_IRQ = (1 << 8), /* shift by port # */ 21820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Shadow block registers */ 22031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_BLK_OFS = 0x100, 22131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ 22220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 22320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATA registers */ 22420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ 22520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_ACTIVE_OFS = 0x350, 2260c58912e192fc3a4835d772aafa40b72552b819fMark Lord SATA_FIS_IRQ_CAUSE_OFS = 0x364, 22717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 228e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord LTMODE_OFS = 0x30c, 22917c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 23017c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 23147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik PHY_MODE3 = 0x310, 232bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE4 = 0x314, 233bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE2 = 0x330, 234e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFCTL_OFS = 0x344, 235e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFSTAT_OFS = 0x34c, 236e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord VENDOR_UNIQUE_FIS_OFS = 0x35c, 23717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 238e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord FIS_CFG_OFS = 0x360, 23917c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord FIS_CFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 24017c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 241c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_MODE = 0x74, 242c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_LT_MODE = 0x30, 243c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_CTL = 0x0C, 244e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_INTERFACE_CFG = 0x050, 245bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 246bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_M2_PREAMP_MASK = 0x7e0, 24720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 24820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Port registers */ 24920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_CFG_OFS = 0, 2500c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 2510c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 2520c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 2530c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 2540c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 255e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 256e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 25720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_CAUSE_OFS = 0x8, 25920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_MASK_OFS = 0xc, 2606c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 2616c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 2626c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV = (1 << 2), /* device error */ 2636c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 2646c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 2656c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 266c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 267c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 2686c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 269c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 2706c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 2716c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 2726c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 2736c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 274646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2756c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 276646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 277646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 278646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 279646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 280646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2816c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 282646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2836c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 284646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 285646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 286646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 287646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 288646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 289646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2906c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 291646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2926c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 293c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_OVERRUN_5 = (1 << 5), 294c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_UNDERRUN_5 = (1 << 6), 295646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 296646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 297646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 | 298646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 | 299646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX, 300646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 301bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 302bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 303bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 304bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 305bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SERR | 306bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS | 3076c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 308bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 309bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 310bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY | 311bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_CTRL_RX_2 | 312bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_RX | 313bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_TX | 314bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_TRANS_PROTO, 315e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 316bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 317bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 318bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 319bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 320bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_OVERRUN_5 | 321bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_UNDERRUN_5 | 322bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS_5 | 3236c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 324bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 325bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 326bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY, 32720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 32831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_BASE_HI_OFS = 0x10, 32931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ 33031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 33131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_OUT_PTR_OFS = 0x18, 33231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_PTR_SHIFT = 5, 33331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 33431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_BASE_HI_OFS = 0x1c, 33531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_IN_PTR_OFS = 0x20, 33631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ 33731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_PTR_SHIFT = 3, 33831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3390ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_CMD_OFS = 0x28, /* EDMA command register */ 3400ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_EN = (1 << 0), /* enable EDMA */ 3410ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 3420ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik ATA_RST = (1 << 2), /* reset trans/link/phy */ 34320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 344c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik EDMA_IORDY_TMOUT = 0x34, 345bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik EDMA_ARB_CFG = 0x38, 346bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 34731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Host private flags (hp_flags) */ 34831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_HP_FLAG_MSI = (1 << 0), 34947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB0 = (1 << 1), 35047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB2 = (1 << 2), 35147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1B2 = (1 << 3), 35247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1C0 = (1 << 4), 353e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik MV_HP_ERRATA_XX42A0 = (1 << 5), 3540ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 3550ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 3560ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 35702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 35820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 35931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Port private flags (pp_flags) */ 3600ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 361721091685f853ba4e6c49f26f989db0b1a811250Mark Lord MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 36220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 36320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 364ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 365ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 366e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 3677bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC)) 368bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 369095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzikenum { 370baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik /* DMA boundary 0xffff is required by the s/g splitting 371baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik * we need on /length/ in mv_fill-sg(). 372baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik */ 373baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik MV_DMA_BOUNDARY = 0xffffU, 374095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3750ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* mask of register bits containing lower 32 bits 3760ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik * of EDMA request queue DMA address 3770ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik */ 378095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 379095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3800ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* ditto, for response queue */ 381095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 382095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik}; 383095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 384522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikenum chip_type { 385522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_504x, 386522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_508x, 387522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_5080, 388522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_604x, 389522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_608x, 390e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_6042, 391e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_7042, 392f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara chip_soc, 393522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik}; 394522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 39531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ReQuest Block: 32B */ 39631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crqb { 397e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr; 398e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr_hi; 399e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ctrl_flags; 400e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ata_cmd[11]; 40131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 40220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 403e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstruct mv_crqb_iie { 404e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 405e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 406e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags; 407e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 len; 408e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 ata_cmd[4]; 409e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 410e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 41131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ResPonse Block: 8B */ 41231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crpb { 413e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 id; 414e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 flags; 415e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 tmstmp; 41620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 41720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 41831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 41931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_sg { 420e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 421e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags_size; 422e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 423e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 reserved; 42431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 42520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 42631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_port_priv { 42731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crqb *crqb; 42831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crqb_dma; 42931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crpb *crpb; 43031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crpb_dma; 431eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 432eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 433bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 434bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int req_idx; 435bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int resp_idx; 436bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 43731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 pp_flags; 43831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 43931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 440bca1c4eb9411533d613123618c0d127fae532595Jeff Garzikstruct mv_port_signal { 441bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 amps; 442bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 pre; 443bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik}; 444bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 44502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lordstruct mv_host_priv { 44602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 hp_flags; 44702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_port_signal signal[8]; 44802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord const struct mv_hw_ops *ops; 449f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports; 450f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *base; 451f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *main_cause_reg_addr; 452f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *main_mask_reg_addr; 45302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_cause_ofs; 45402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_mask_ofs; 45502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 unmask_all_irqs; 456da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord /* 457da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * These consistent DMA memory pools give us guaranteed 458da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * alignment for hardware-accessed data structures, 459da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * and less memory waste in accomplishing the alignment. 460da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord */ 461da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crqb_pool; 462da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crpb_pool; 463da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *sg_tbl_pool; 46402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord}; 46502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 46647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstruct mv_hw_ops { 4672a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 4682a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 46947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 47047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 47147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 472c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 473c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 474522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 4757bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 47647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 47747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 478da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 479da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 480da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 481da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 48231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap); 48331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap); 48431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc); 485e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc); 4869a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 487a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 488a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo unsigned long deadline); 489bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap); 490bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap); 491f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *dev); 49220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4932a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 4942a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 49547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 49647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 49747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 498c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 499c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 500522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 5017bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 50247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 5032a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5042a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 50547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 50647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 50747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 508c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 509c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 510522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 511f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 512f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 513f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 514f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 515f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 516f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc); 517f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 518f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 519f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 5207bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 521e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 522c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no); 523e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap); 524b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio); 525e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq); 52647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 527eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 528eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * because we have to allow room for worst case splitting of 529eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * PRDs for 64K boundaries in mv_fill_sg(). 530eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 531c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv5_sht = { 53268d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BASE_SHT(DRV_NAME), 533baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 534c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .dma_boundary = MV_DMA_BOUNDARY, 535c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik}; 536c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 537c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv6_sht = { 53868d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_NCQ_SHT(DRV_NAME), 539138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .can_queue = MV_MAX_Q_DEPTH - 1, 540baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 54120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .dma_boundary = MV_DMA_BOUNDARY, 54220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 54320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 544029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv5_ops = { 545029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &ata_sff_port_ops, 546c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 547c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_prep = mv_qc_prep, 548c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_issue = mv_qc_issue, 549c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 550bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .freeze = mv_eh_freeze, 551bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .thaw = mv_eh_thaw, 552a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .hardreset = mv_hardreset, 553a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .error_handler = ata_std_error_handler, /* avoid SFF EH */ 554029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .post_internal_cmd = ATA_OP_NULL, 555bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 556c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_read = mv5_scr_read, 557c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_write = mv5_scr_write, 558c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 559c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_start = mv_port_start, 560c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_stop = mv_port_stop, 561c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik}; 562c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 563029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv6_ops = { 564029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv5_ops, 565138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .qc_defer = ata_std_qc_defer, 566029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .dev_config = mv6_dev_config, 56720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_read = mv_scr_read, 56820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_write = mv_scr_write, 56920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 57020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 571029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv_iie_ops = { 572029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv6_ops, 573029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .dev_config = ATA_OP_NULL, 574e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .qc_prep = mv_qc_prep_iie, 575e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 576e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 57798ac62defe529d04a192688f40d801a2d8fbcf98Arjan van de Venstatic const struct ata_port_info mv_port_info[] = { 57820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_504x */ 579cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik .flags = MV_COMMON_FLAGS, 58031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 581bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 582c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 58320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 58420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_508x */ 585c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 58631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 587bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 588c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 58920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 59047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik { /* chip_5080 */ 591c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 59247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 593bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 594c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 59547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik }, 59620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_604x */ 597138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 598138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 59931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 600bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 601c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 60220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 60320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_608x */ 604c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 605138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ | MV_FLAG_DUAL_HC, 60631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 607bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 608c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 60920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 610e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_6042 */ 611138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 612138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 613e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 614bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 615e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 616e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 617e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_7042 */ 618138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 619138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 620e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 621bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 622e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 623e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 624f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { /* chip_soc */ 62517c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .flags = MV_COMMON_FLAGS | MV_FLAG_SOC, 62617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .pio_mask = 0x1f, /* pio0-4 */ 62717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .udma_mask = ATA_UDMA6, 62817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .port_ops = &mv_iie_ops, 629f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 63020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 63120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 6323b7d697dfb7d03edb87e50b743a7ecff029618e9Jeff Garzikstatic const struct pci_device_id mv_pci_tbl[] = { 6332d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 6342d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 6352d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 6362d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 637cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox /* RocketRAID 1740/174x have different identifiers */ 638cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox { PCI_VDEVICE(TTI, 0x1740), chip_508x }, 639cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox { PCI_VDEVICE(TTI, 0x1742), chip_508x }, 6402d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 6412d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 6422d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 6432d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 6442d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 6452d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 6462d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 6472d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 6482d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 649d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger /* Adaptec 1430SA */ 650d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 651d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger 65202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Marvell 7042 support */ 6536a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 6546a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom 65502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Highpoint RocketRAID PCIe series */ 65602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 65702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 65802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 6592d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { } /* terminate list */ 66020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 66120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 66247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv5xxx_ops = { 66347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv5_phy_errata, 66447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv5_enable_leds, 66547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv5_read_preamp, 66647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv5_reset_hc, 667522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv5_reset_flash, 668522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv5_reset_bus, 66947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 67047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 67147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv6xxx_ops = { 67247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv6_phy_errata, 67347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv6_enable_leds, 67447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv6_read_preamp, 67547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv6_reset_hc, 676522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv6_reset_flash, 677522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv_reset_pci_bus, 67847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 67947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 680f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic const struct mv_hw_ops mv_soc_ops = { 681f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .phy_errata = mv6_phy_errata, 682f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .enable_leds = mv_soc_enable_leds, 683f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .read_preamp = mv_soc_read_preamp, 684f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_hc = mv_soc_reset_hc, 685f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_flash = mv_soc_reset_flash, 686f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_bus = mv_soc_reset_bus, 687f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 688f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 68920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 69020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Functions 69120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 69220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 69320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void writelfl(unsigned long data, void __iomem *addr) 69420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 69520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writel(data, addr); 69620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ (void) readl(addr); /* flush to avoid PCI posted write */ 69720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 69820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 69920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 70020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 70120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 70220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 70320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 704c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hc_from_port(unsigned int port) 705c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 706c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port >> MV_PORT_HC_SHIFT; 707c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 708c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 709c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hardport_from_port(unsigned int port) 710c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 711c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port & MV_PORT_MASK; 712c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 713c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 714c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline void __iomem *mv_hc_base_from_port(void __iomem *base, 715c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 716c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 717c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base(base, mv_hc_from_port(port)); 718c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 719c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 72020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 72120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 722c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base_from_port(base, port) + 7238b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik MV_SATAHC_ARBTR_REG_SZ + 724c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 72520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 72620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 727e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 728e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord{ 729e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 730e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 731e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 732e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord return hc_mmio + ofs; 733e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord} 734e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 735f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic inline void __iomem *mv_host_base(struct ata_host *host) 736f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 737f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 738f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return hpriv->base; 739f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 740f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 74120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_ap_base(struct ata_port *ap) 74220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 743f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return mv_port_base(mv_host_base(ap->host), ap->port_no); 74420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 74520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 746cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic inline int mv_get_hc_count(unsigned long port_flags) 74731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 748cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 74931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 75031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 751c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic void mv_set_edma_ptrs(void __iomem *port_mmio, 752c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_host_priv *hpriv, 753c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp) 754c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik{ 755bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 index; 756bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 757c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 758c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize request queue 759c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 760bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik index = (pp->req_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_REQ_Q_PTR_SHIFT; 761bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 762c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crqb_dma & 0x3ff); 763c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); 764bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 765c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 766c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 767c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) 768bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & 0xffffffff) | index, 769c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 770c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik else 771bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 772c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 773c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 774c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize response queue 775c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 776bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik index = (pp->resp_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_RSP_Q_PTR_SHIFT; 777bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 778c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crpb_dma & 0xff); 779c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); 780c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 781c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) 782bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & 0xffffffff) | index, 783c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 784c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik else 785bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 786c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 787bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 788c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 789c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik} 790c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 79105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 79205b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_start_dma - Enable eDMA engine 79305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @base: port base address 79405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pp: port private data 79505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 796beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * Verify the local cache of the eDMA state is accurate with a 797beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * WARN_ON. 79805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 79905b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 80005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 80105b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 8020c58912e192fc3a4835d772aafa40b72552b819fMark Lordstatic void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio, 803721091685f853ba4e6c49f26f989db0b1a811250Mark Lord struct mv_port_priv *pp, u8 protocol) 80420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 805721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int want_ncq = (protocol == ATA_PROT_NCQ); 806721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 807721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 808721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 809721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq != using_ncq) 810b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 811721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } 812c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 8130c58912e192fc3a4835d772aafa40b72552b819fMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 8140c58912e192fc3a4835d772aafa40b72552b819fMark Lord int hard_port = mv_hardport_from_port(ap->port_no); 8150c58912e192fc3a4835d772aafa40b72552b819fMark Lord void __iomem *hc_mmio = mv_hc_base_from_port( 8160fca0d6f2ce3336022a22bc7fc2e009e599e63a4Saeed Bishara mv_host_base(ap->host), hard_port); 8170c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 hc_irq_cause, ipending; 8180c58912e192fc3a4835d772aafa40b72552b819fMark Lord 819bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA event indicators, if any */ 820f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 821bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 8220c58912e192fc3a4835d772aafa40b72552b819fMark Lord /* clear EDMA interrupt indicator, if any */ 8230c58912e192fc3a4835d772aafa40b72552b819fMark Lord hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 8240c58912e192fc3a4835d772aafa40b72552b819fMark Lord ipending = (DEV_IRQ << hard_port) | 8250c58912e192fc3a4835d772aafa40b72552b819fMark Lord (CRPB_DMA_DONE << hard_port); 8260c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (hc_irq_cause & ipending) { 8270c58912e192fc3a4835d772aafa40b72552b819fMark Lord writelfl(hc_irq_cause & ~ipending, 8280c58912e192fc3a4835d772aafa40b72552b819fMark Lord hc_mmio + HC_IRQ_CAUSE_OFS); 8290c58912e192fc3a4835d772aafa40b72552b819fMark Lord } 8300c58912e192fc3a4835d772aafa40b72552b819fMark Lord 831e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_edma_cfg(ap, want_ncq); 8320c58912e192fc3a4835d772aafa40b72552b819fMark Lord 8330c58912e192fc3a4835d772aafa40b72552b819fMark Lord /* clear FIS IRQ Cause */ 8340c58912e192fc3a4835d772aafa40b72552b819fMark Lord writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 8350c58912e192fc3a4835d772aafa40b72552b819fMark Lord 836f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord mv_set_edma_ptrs(port_mmio, hpriv, pp); 837bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 838f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS); 839afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 840afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 841f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord WARN_ON(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS))); 84220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 84320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 84405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 845e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * mv_stop_edma_engine - Disable eDMA engine 846b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * @port_mmio: io base address 84705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 84805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 84905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 85005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 851b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio) 85220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 853b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord int i; 85431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 855b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Disable eDMA. The disable bit auto clears. */ 856b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); 8578b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 858b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Wait for the chip to confirm eDMA is off. */ 859b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord for (i = 10000; i > 0; i--) { 860b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord u32 reg = readl(port_mmio + EDMA_CMD_OFS); 8614537deb5e90b717a725b3d74b58b4bb1d28443d0Jeff Garzik if (!(reg & EDMA_EN)) 862b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 863b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord udelay(10); 86431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 865b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 86620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 86720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 868e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap) 8690ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik{ 870b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord void __iomem *port_mmio = mv_ap_base(ap); 871b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 8720ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 873b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 874b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 875b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 876b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (mv_stop_edma_engine(port_mmio)) { 877b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); 878b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 879b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord } 880b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 8810ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik} 8820ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 8838a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#ifdef ATA_DEBUG 88431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_mem(void __iomem *start, unsigned bytes) 88520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 88631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 88731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 88831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%p: ", start + b); 88931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 8902dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", readl(start + b)); 89131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 89231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 89331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 89431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 89531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 8968a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#endif 8978a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik 89831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 89931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 90031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 90131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 90231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 dw; 90331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 90431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%02x: ", b); 90531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 9062dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik (void) pci_read_config_dword(pdev, b, &dw); 9072dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", dw); 90831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 90931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 91031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 91131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 91231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 91331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 91431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_all_regs(void __iomem *mmio_base, int port, 91531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct pci_dev *pdev) 91631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 91731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 9188b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik void __iomem *hc_base = mv_hc_base(mmio_base, 91931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port >> MV_PORT_HC_SHIFT); 92031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_base; 92131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int start_port, num_ports, p, start_hc, num_hcs, hc; 92231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 92331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (0 > port) { 92431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = start_port = 0; 92531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = 8; /* shld be benign for 4 port devs */ 92631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_hcs = 2; 92731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } else { 92831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = port >> MV_PORT_HC_SHIFT; 92931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_port = port; 93031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = num_hcs = 1; 93131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 9328b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik DPRINTK("All registers for port(s) %u-%u:\n", start_port, 93331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports > 1 ? num_ports - 1 : start_port); 93431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 93531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (NULL != pdev) { 93631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI config space regs:\n"); 93731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 93831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 93931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI regs:\n"); 94031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xc00, 0x3c); 94131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xd00, 0x34); 94231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xf00, 0x4); 94331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0x1d00, 0x6c); 94431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 945d220c37e0a3c9a47ae00e87e044d963b3ea040bcDan Aloni hc_base = mv_hc_base(mmio_base, hc); 94631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("HC regs (HC %i):\n", hc); 94731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(hc_base, 0x1c); 94831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 94931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (p = start_port; p < start_port + num_ports; p++) { 95031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port_base = mv_port_base(mmio_base, p); 9512dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("EDMA regs (port %i):\n", p); 95231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base, 0x54); 9532dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("SATA regs (port %i):\n", p); 95431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base+0x300, 0x60); 95531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 95631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 95720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 95820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 95920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic unsigned int mv_scr_offset(unsigned int sc_reg_in) 96020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 96120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs; 96220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 96320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ switch (sc_reg_in) { 96420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_STATUS: 96520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_CONTROL: 96620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ERROR: 96720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); 96820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 96920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ACTIVE: 97020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_ACTIVE_OFS; /* active is not with the others */ 97120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 97220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ default: 97320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = 0xffffffffU; 97420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 97520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 97620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return ofs; 97720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 97820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 979da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 98020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 98120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 98220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 983da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 984da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(mv_ap_base(ap) + ofs); 985da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 986da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 987da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 98820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 98920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 990da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 99120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 99220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 99320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 994da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 99520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writelfl(val, mv_ap_base(ap) + ofs); 996da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 997da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 998da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 99920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 100020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1001f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *adev) 1002f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord{ 1003f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord /* 1004f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord * We don't have hob_nsect when doing NCQ commands on Gen-II. 1005f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord * See mv_qc_prep() for more info. 1006f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord */ 1007f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord if (adev->flags & ATA_DFLAG_NCQ) 1008f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord if (adev->max_sectors > ATA_MAX_SECTORS) 1009f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord adev->max_sectors = ATA_MAX_SECTORS; 1010f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1011f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 1012e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq) 1013e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 10140c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 cfg; 1015e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_port_priv *pp = ap->private_data; 1016e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1017e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1018e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1019e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* set up non-NCQ EDMA configuration */ 10200c58912e192fc3a4835d772aafa40b72552b819fMark Lord cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 1021e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 10220c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (IS_GEN_I(hpriv)) 1023e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 8); /* enab config burst size mask */ 1024e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 10250c58912e192fc3a4835d772aafa40b72552b819fMark Lord else if (IS_GEN_II(hpriv)) 1026e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1027e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1028e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik else if (IS_GEN_IIE(hpriv)) { 1029e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 1030e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 22); /* enab 4-entry host queue cache */ 1031e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 18); /* enab early completion */ 1032e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */ 1033e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 1034e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1035721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq) { 1036721091685f853ba4e6c49f26f989db0b1a811250Mark Lord cfg |= EDMA_CFG_NCQ; 1037721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 1038721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } else 1039721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN; 1040721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1041e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik writelfl(cfg, port_mmio + EDMA_CFG_OFS); 1042e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1043e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1044da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordstatic void mv_port_free_dma_mem(struct ata_port *ap) 1045da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord{ 1046da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1047da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_port_priv *pp = ap->private_data; 1048eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord int tag; 1049da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1050da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crqb) { 1051da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1052da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = NULL; 1053da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1054da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crpb) { 1055da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1056da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = NULL; 1057da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1058eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1059eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1060eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we have one unique sg_tbl per NCQ tag. 1061eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1062eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1063eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (pp->sg_tbl[tag]) { 1064eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) 1065eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_pool_free(hpriv->sg_tbl_pool, 1066eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag], 1067eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag]); 1068eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = NULL; 1069eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1070da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1071da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord} 1072da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 107305b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 107405b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_start - Port specific init/start routine. 107505b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 107605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 107705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Allocate and point to DMA memory, init port private memory, 107805b308e1df6d9d673daedb517969241f41278b52Brett Russ * zero indices. 107905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 108005b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 108105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 108205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 108331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap) 108431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1085cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct device *dev = ap->host->dev; 1086cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 108731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp; 108831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 10890ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik unsigned long flags; 1090dde2020754aeb14e17052d61784dcb37f252aac2James Bottomley int tag; 109131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 109224dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 10936037d6bbdff65eb5a84fe35e140f4da4f7cc103aJeff Garzik if (!pp) 109424dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return -ENOMEM; 1095da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord ap->private_data = pp; 109631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1097da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1098da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crqb) 1099da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 1100da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crqb, 0, MV_CRQB_Q_SZ); 110131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1102da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1103da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crpb) 1104da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord goto out_port_free_dma_mem; 1105da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crpb, 0, MV_CRPB_Q_SZ); 110631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1107eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1108eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1109eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we need one unique sg_tbl per NCQ tag. 1110eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1111eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1112eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) { 1113eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1114eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1115eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (!pp->sg_tbl[tag]) 1116eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord goto out_port_free_dma_mem; 1117eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } else { 1118eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = pp->sg_tbl[0]; 1119eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1120eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1121eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 112231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 11230ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik spin_lock_irqsave(&ap->host->lock, flags); 11240ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 1125e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_edma_cfg(ap, 0); 1126c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik mv_set_edma_ptrs(port_mmio, hpriv, pp); 112731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 11280ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik spin_unlock_irqrestore(&ap->host->lock, flags); 11290ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 113031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Don't turn on EDMA here...do it before DMA commands only. Else 113131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * we'll be unable to send non-data, PIO, etc due to restricted access 113231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * to shadow regs. 113331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 113431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 1135da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1136da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordout_port_free_dma_mem: 1137da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 1138da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 113931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 114031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 114105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 114205b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_stop - Port specific cleanup/stop routine. 114305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 114405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 114505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Stop DMA, cleanup port memory. 114605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 114705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 1148cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine uses the host lock to protect the DMA stop. 114905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 115031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap) 115131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1152e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma(ap); 1153da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 115431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 115531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 115605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 115705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 115805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command whose SG list to source from 115905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 116005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Populate the SG list and mark the last entry. 116105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 116205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 116305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 116405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 11656c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzikstatic void mv_fill_sg(struct ata_queued_cmd *qc) 116631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 116731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = qc->ap->private_data; 1168972c26bdd6b58e7534473c4f7928584578cf43f4Jeff Garzik struct scatterlist *sg; 11693be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik struct mv_sg *mv_sg, *last_sg = NULL; 1170ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo unsigned int si; 117131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1172eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord mv_sg = pp->sg_tbl[qc->tag]; 1173ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 1174d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik dma_addr_t addr = sg_dma_address(sg); 1175d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik u32 sg_len = sg_dma_len(sg); 117622374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 11774007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson while (sg_len) { 11784007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 offset = addr & 0xffff; 11794007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 len = sg_len; 118022374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 11814007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson if ((offset + sg_len > 0x10000)) 11824007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson len = 0x10000 - offset; 11834007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 11844007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 11854007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 11866c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik mv_sg->flags_size = cpu_to_le32(len & 0xffff); 11874007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 11884007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson sg_len -= len; 11894007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson addr += len; 11904007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 11913be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg = mv_sg; 11924007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg++; 11934007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson } 119431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 11953be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik 11963be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik if (likely(last_sg)) 11973be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 119831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 119931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 12005796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzikstatic void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 120131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1202559eedad7f7764dacca33980127b4615011230e4Mark Lord u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 120331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ (last ? CRQB_CMD_LAST : 0); 1204559eedad7f7764dacca33980127b4615011230e4Mark Lord *cmdw = cpu_to_le16(tmp); 120531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 120631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 120705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 120805b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_prep - Host specific command preparation. 120905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to prepare 121005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 121105b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 121205b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it handles prep of the CRQB 121305b308e1df6d9d673daedb517969241f41278b52Brett Russ * (command request block), does some sanity checking, and calls 121405b308e1df6d9d673daedb517969241f41278b52Brett Russ * the SG load routine. 121505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 121605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 121705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 121805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 121931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc) 122031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 122131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_port *ap = qc->ap; 122231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = ap->private_data; 1223e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 *cw; 122431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_taskfile *tf; 122531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u16 flags = 0; 1226a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 122731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1228138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1229138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 123031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 123120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 123231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Fill in command request block 123331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1234e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 123531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= CRQB_FLAG_READ; 1236beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 123731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= qc->tag << CRQB_TAG_SHIFT; 123831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1239bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1240bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = pp->req_idx & MV_MAX_Q_DEPTH_MASK; 1241a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1242a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr = 1243eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1244a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr_hi = 1245eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1246a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 124731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1248a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord cw = &pp->crqb[in_index].ata_cmd[0]; 124931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ tf = &qc->tf; 125031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 125131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Sadly, the CRQB cannot accomodate all registers--there are 125231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * only 11 bytes...so we must pick and choose required 125331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * registers based on the command. So, we drop feature and 125431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * hob_feature for [RW] DMA commands, but they are needed for 125531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * NCQ. NCQ will drop hob_nsect. 125620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 125731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ switch (tf->command) { 125831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ: 125931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ_EXT: 126031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE: 126131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE_EXT: 1262c15d85c8f3f73b5f20aae7928e25b6996f16b328Jens Axboe case ATA_CMD_WRITE_FUA_EXT: 126331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 126431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 126531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_READ: 126631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_WRITE: 12678b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 126831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 126931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 127031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ default: 127131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* The only other commands EDMA supports in non-queued and 127231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 127331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * of which are defined/used by Linux. If we get here, this 127431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * driver needs work. 127531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * 127631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * FIXME: modify libata to give qc_prep a return value and 127731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * return error here. 127831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 127931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ BUG_ON(tf->command); 128031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 128131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 128231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 128331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 128431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 128531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 128631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 128731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 128831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 128931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 129031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 129131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1292e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 1293e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1294e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik mv_fill_sg(qc); 1295e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1296e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1297e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik/** 1298e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * mv_qc_prep_iie - Host specific command preparation. 1299e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * @qc: queued command to prepare 1300e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1301e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * This routine simply redirects to the general purpose routine 1302e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * if command is not DMA. Else, it handles prep of the CRQB 1303e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * (command request block), does some sanity checking, and calls 1304e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * the SG load routine. 1305e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1306e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * LOCKING: 1307e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * Inherited from caller. 1308e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik */ 1309e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc) 1310e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 1311e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_port *ap = qc->ap; 1312e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_port_priv *pp = ap->private_data; 1313e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_crqb_iie *crqb; 1314e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_taskfile *tf; 1315a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 1316e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik u32 flags = 0; 1317e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1318138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1319138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 1320e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1321e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1322e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* Fill in Gen IIE command request block */ 1323e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 1324e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= CRQB_FLAG_READ; 1325e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1326beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 1327e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= qc->tag << CRQB_TAG_SHIFT; 13288c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord flags |= qc->tag << CRQB_HOSTQ_SHIFT; 1329e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1330bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1331bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = pp->req_idx & MV_MAX_Q_DEPTH_MASK; 1332a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1333a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 1334eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1335eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1336e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->flags = cpu_to_le32(flags); 1337e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1338e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik tf = &qc->tf; 1339e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[0] = cpu_to_le32( 1340e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->command << 16) | 1341e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->feature << 24) 1342e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1343e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[1] = cpu_to_le32( 1344e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbal << 0) | 1345e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbam << 8) | 1346e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbah << 16) | 1347e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->device << 24) 1348e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1349e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[2] = cpu_to_le32( 1350e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbal << 0) | 1351e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbam << 8) | 1352e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbah << 16) | 1353e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_feature << 24) 1354e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1355e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[3] = cpu_to_le32( 1356e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->nsect << 0) | 1357e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_nsect << 8) 1358e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1359e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1360e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 136131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 136231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_fill_sg(qc); 136331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 136431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 136505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 136605b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_issue - Initiate a command to the host 136705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to start 136805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 136905b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 137005b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it sanity checks our local 137105b308e1df6d9d673daedb517969241f41278b52Brett Russ * caches of the request producer/consumer indices then enables 137205b308e1df6d9d673daedb517969241f41278b52Brett Russ * DMA and bumps the request producer index. 137305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 137405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 137505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 137605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 13779a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 137831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1379c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct ata_port *ap = qc->ap; 1380c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 1381c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1382bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 in_index; 138331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1384138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1385138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) { 138617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord /* 138717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord * We're about to send a non-EDMA capable command to the 138831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * port. Turn off EDMA so there won't be problems accessing 138931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * shadow block, etc registers. 139031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1391b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 13929363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo return ata_sff_qc_issue(qc); 139331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 139431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1395721091685f853ba4e6c49f26f989db0b1a811250Mark Lord mv_start_dma(ap, port_mmio, pp, qc->tf.protocol); 1396bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1397bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->req_idx++; 139831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1399bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = (pp->req_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_REQ_Q_PTR_SHIFT; 140031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 140131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* and write the request in pointer to kick the EDMA to life */ 1402bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 1403bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 140431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 140531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 140631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 140731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 140805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 140905b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_err_intr - Handle error interrupts on the port 141005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 14119b358e305c1d783c8a4ebf00344e95deb9e38f3dMark Lord * @reset_allowed: bool: 0 == don't trigger from reset here 141205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 141305b308e1df6d9d673daedb517969241f41278b52Brett Russ * In most cases, just clear the interrupt and move on. However, 1414e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * some cases require an eDMA reset, which also performs a COMRESET. 1415e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * The SERR case requires a clear of pending errors in the SATA 1416e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * SERROR register. Finally, if the port disabled DMA, 1417e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * update our cached copy to match. 141805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 141905b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 142005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 142105b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 1422bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc) 142331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 142431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 1425bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 edma_err_cause, eh_freeze_mask, serr = 0; 1426bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1427bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 1428bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int edma_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); 1429bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int action = 0, err_mask = 0; 14309af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_eh_info *ehi = &ap->link.eh_info; 143120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1432bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 143320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1434bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!edma_enabled) { 1435bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* just a guess: do we need to do this? should we 1436bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * expand this, and do it in all cases? 1437bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1438936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_read(&ap->link, SCR_ERROR, &serr); 1439936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 144020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 1441bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1442bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 1443bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1444bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, "edma_err 0x%08x", edma_err_cause); 1445bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1446bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 1447bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * all generations share these EDMA error cause bits 1448bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1449bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1450bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_DEV) 1451bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_DEV; 1452bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 14536c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 1454bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR)) { 1455bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_ATA_BUS; 1456cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1457b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "parity error"); 1458bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1459bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 1460bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_hotplugged(ehi); 1461bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 1462b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo "dev disconnect" : "dev connect"); 1463cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1464bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1465bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1466ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) { 1467bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE_5; 1468bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1469bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 14705ab063e397d9f6fcadb37a07465efcc87f9e9345Harvey Harrison pp = ap->private_data; 1471bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1472b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 1473bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1474bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 1475bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE; 1476bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1477bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS) { 14785ab063e397d9f6fcadb37a07465efcc87f9e9345Harvey Harrison pp = ap->private_data; 1479bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1480b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 1481bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1482bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1483bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SERR) { 1484936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_read(&ap->link, SCR_ERROR, &serr); 1485936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 1486bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_ATA_BUS; 1487cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1488bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1489afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 149020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 149120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Clear EDMA now that SERR cleanup done */ 14923606a380692cf958355a40fc1aa336800c17baf1Mark Lord writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 149320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1494bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!err_mask) { 1495bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_OTHER; 1496cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1497bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1498bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1499bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->serror |= serr; 1500bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->action |= action; 1501bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1502bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 1503bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 1504bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1505bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 1506bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1507bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & eh_freeze_mask) 1508bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 1509bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1510bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_abort(ap); 1511bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1512bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1513bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_intr_pio(struct ata_port *ap) 1514bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 1515bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 1516bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u8 ata_status; 1517bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1518bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* ignore spurious intr if drive still BUSY */ 1519bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_status = readb(ap->ioaddr.status_addr); 1520bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (unlikely(ata_status & ATA_BUSY)) 1521bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1522bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1523bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get active ATA command */ 15249af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 1525bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (unlikely(!qc)) /* no active tag */ 1526bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1527bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc->tf.flags & ATA_TFLAG_POLLING) /* polling; we don't own qc */ 1528bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1529bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1530bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* and finally, complete the ATA command */ 1531bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= ac_err_mask(ata_status); 1532bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_qc_complete(qc); 1533bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1534bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1535bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_intr_edma(struct ata_port *ap) 1536bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 1537bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 1538bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 1539bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1540bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 1541bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 out_index, in_index; 1542bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik bool work_done = false; 1543bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1544bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get h/w response queue pointer */ 1545bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) 1546bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 1547bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1548bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik while (1) { 1549bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u16 status; 15506c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik unsigned int tag; 1551bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1552bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get s/w response queue last-read pointer, and compare */ 1553bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik out_index = pp->resp_idx & MV_MAX_Q_DEPTH_MASK; 1554bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (in_index == out_index) 1555bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik break; 1556bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1557bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 50xx: get active ATA command */ 15580ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik if (IS_GEN_I(hpriv)) 15599af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo tag = ap->link.active_tag; 1560bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 15616c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik /* Gen II/IIE: get active ATA command via tag, to enable 15626c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik * support for queueing. this works transparently for 15636c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik * queued and non-queued modes. 1564bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 15658c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord else 15668c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord tag = le16_to_cpu(pp->crpb[out_index].id) & 0x1f; 1567bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 15686c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik qc = ata_qc_from_tag(ap, tag); 1569bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1570cb92441973ebd71d556fc7cdd9e597582327dd71Mark Lord /* For non-NCQ mode, the lower 8 bits of status 1571cb92441973ebd71d556fc7cdd9e597582327dd71Mark Lord * are from EDMA_ERR_IRQ_CAUSE_OFS, 1572cb92441973ebd71d556fc7cdd9e597582327dd71Mark Lord * which should be zero if all went well. 1573bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1574bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik status = le16_to_cpu(pp->crpb[out_index].flags); 1575cb92441973ebd71d556fc7cdd9e597582327dd71Mark Lord if ((status & 0xff) && !(pp->pp_flags & MV_PP_FLAG_NCQ_EN)) { 1576bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_err_intr(ap, qc); 1577bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1578bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1579bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1580bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* and finally, complete the ATA command */ 1581bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) { 1582bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= 1583bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ac_err_mask(status >> CRPB_FLAG_STATUS_SHIFT); 1584bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_qc_complete(qc); 1585bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1586bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 15870ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* advance software response queue pointer, to 1588bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * indicate (after the loop completes) to hardware 1589bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * that we have consumed a response queue entry. 1590bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1591bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik work_done = true; 1592bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->resp_idx++; 1593bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1594bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1595bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (work_done) 1596bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 1597bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik (out_index << EDMA_RSP_Q_PTR_SHIFT), 1598bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 159920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 160020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 160105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 160205b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_host_intr - Handle all interrupts on the given host controller 1603cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * @host: host specific structure 160405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @relevant: port error bits relevant to this host controller 160505b308e1df6d9d673daedb517969241f41278b52Brett Russ * @hc: which host controller we're to look at 160605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 160705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read then write clear the HC interrupt status then walk each 160805b308e1df6d9d673daedb517969241f41278b52Brett Russ * port connected to the HC and see if it needs servicing. Port 160905b308e1df6d9d673daedb517969241f41278b52Brett Russ * success ints are reported in the HC interrupt status reg, the 161005b308e1df6d9d673daedb517969241f41278b52Brett Russ * port error ints are reported in the higher level main 161105b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupt status register and thus are passed in via the 161205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 'relevant' argument. 161305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 161405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 161505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 161605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 1617cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc) 161820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1619f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 1620f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 162120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 162220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ u32 hc_irq_cause; 1623f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int port, port0, last_port; 162420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1625351772658a4d1acc0221a6e30676bb0594e74812Jeff Garzik if (hc == 0) 162620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ port0 = 0; 1627351772658a4d1acc0221a6e30676bb0594e74812Jeff Garzik else 162820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ port0 = MV_PORTS_PER_HC; 162920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1630f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) 1631f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara last_port = port0 + MV_PORTS_PER_HC; 1632f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara else 1633f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara last_port = port0 + hpriv->n_ports; 163420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* we'll need the HC success int register in most cases */ 163520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 1636bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!hc_irq_cause) 1637bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1638bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1639bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 164020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 164120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n", 16422dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik hc, relevant, hc_irq_cause); 164320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 16448f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu for (port = port0; port < last_port; port++) { 1645cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_port *ap = host->ports[port]; 16468f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu struct mv_port_priv *pp; 1647bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik int have_err_bits, hard_port, shift; 164855d8ca4f8094246da6e71889a4e04bfafaa78b10Jeff Garzik 1649bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if ((!ap) || (ap->flags & ATA_FLAG_DISABLED)) 1650a2c91a8819e315e9fd1aef3ff57badb6c1be3f80Jeff Garzik continue; 1651a2c91a8819e315e9fd1aef3ff57badb6c1be3f80Jeff Garzik 16528f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu pp = ap->private_data; 16538f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu 165431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ shift = port << 1; /* (port * 2) */ 1655e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord if (port >= MV_PORTS_PER_HC) 165620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ shift++; /* skip bit 8 in the HC Main IRQ reg */ 1657e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 1658bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik have_err_bits = ((PORT0_ERR << shift) & relevant); 1659bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1660bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (unlikely(have_err_bits)) { 1661bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 16628b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 16639af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 1664bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 1665bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik continue; 1666bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1667bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_err_intr(ap, qc); 1668bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik continue; 1669bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1670bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1671bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hard_port = mv_hardport_from_port(port); /* range 0..3 */ 1672bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1673bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 1674bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) 1675bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_intr_edma(ap); 1676bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 1677bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if ((DEV_IRQ << hard_port) & hc_irq_cause) 1678bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_intr_pio(ap); 167920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 168020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 168120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ VPRINTK("EXIT\n"); 168220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 168320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1684bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_pci_error(struct ata_host *host, void __iomem *mmio) 1685bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 168602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 1687bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_port *ap; 1688bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 1689bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_eh_info *ehi; 1690bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int i, err_mask, printed = 0; 1691bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 err_cause; 1692bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 169302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord err_cause = readl(mmio + hpriv->irq_cause_ofs); 1694bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1695bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", 1696bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_cause); 1697bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1698bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik DPRINTK("All regs @ PCI error\n"); 1699bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 1700bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 170102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord writelfl(0, mmio + hpriv->irq_cause_ofs); 1702bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1703bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik for (i = 0; i < host->n_ports; i++) { 1704bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ap = host->ports[i]; 1705936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo if (!ata_link_offline(&ap->link)) { 17069af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo ehi = &ap->link.eh_info; 1707bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 1708bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!printed++) 1709bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, 1710bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik "PCI err cause 0x%08x", err_cause); 1711bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_HOST_BUS; 1712cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo ehi->action = ATA_EH_RESET; 17139af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 1714bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 1715bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 1716bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1717bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 1718bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1719bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 1720bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1721bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1722bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1723bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 172405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1725c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * mv_interrupt - Main interrupt event handler 172605b308e1df6d9d673daedb517969241f41278b52Brett Russ * @irq: unused 172705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @dev_instance: private data; in this case the host structure 172805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 172905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read the read only register to determine if any host 173005b308e1df6d9d673daedb517969241f41278b52Brett Russ * controllers have pending interrupts. If so, call lower level 173105b308e1df6d9d673daedb517969241f41278b52Brett Russ * routine to handle. Also check for PCI errors which are only 173205b308e1df6d9d673daedb517969241f41278b52Brett Russ * reported here. 173305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 17348b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * LOCKING: 1735cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine holds the host lock while processing pending 173605b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts. 173705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 17387d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t mv_interrupt(int irq, void *dev_instance) 173920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1740cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = dev_instance; 1741f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 174220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int hc, handled = 0, n_hcs; 1743f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 1744646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord u32 irq_stat, irq_mask; 174520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1746e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* Note to self: &host->lock == &ap->host->lock == ap->lock */ 1747646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord spin_lock(&host->lock); 1748f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 1749f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara irq_stat = readl(hpriv->main_cause_reg_addr); 1750f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara irq_mask = readl(hpriv->main_mask_reg_addr); 175120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 175220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* check the cases where we either have nothing pending or have read 175320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * a bogus register value which can indicate HW removal or PCI fault 175420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 1755646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord if (!(irq_stat & irq_mask) || (0xffffffffU == irq_stat)) 1756646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord goto out_unlock; 175720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1758cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik n_hcs = mv_get_hc_count(host->ports[0]->flags); 175920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 17607bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (unlikely((irq_stat & PCI_ERR) && HAS_PCI(host))) { 1761bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_pci_error(host, mmio); 1762bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik handled = 1; 1763bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik goto out_unlock; /* skip all other HC irq handling */ 1764bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1765bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 176620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hcs; hc++) { 176720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT)); 176820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ if (relevant) { 1769cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik mv_host_intr(host, relevant, hc); 1770bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik handled = 1; 177120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 177220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 1773615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 1774bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikout_unlock: 1775cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik spin_unlock(&host->lock); 177620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 177720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return IRQ_RETVAL(handled); 177820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 177920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1780c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic unsigned int mv5_scr_offset(unsigned int sc_reg_in) 1781c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1782c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs; 1783c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1784c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik switch (sc_reg_in) { 1785c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_STATUS: 1786c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_ERROR: 1787c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_CONTROL: 1788c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = sc_reg_in * sizeof(u32); 1789c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 1790c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik default: 1791c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = 0xffffffffU; 1792c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 1793c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 1794c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return ofs; 1795c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1796c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1797da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 1798c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1799f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 1800f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 18010d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 1802c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 1803c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1804da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 1805da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(addr + ofs); 1806da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1807da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1808da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 1809c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1810c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1811da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 1812c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1813f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 1814f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 18150d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 1816c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 1817c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1818da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 18190d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo writelfl(val, addr + ofs); 1820da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1821da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1822da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 1823c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1824c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 18257bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 1826522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 18277bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara struct pci_dev *pdev = to_pci_dev(host->dev); 1828522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik int early_5080; 1829522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 183044c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 1831522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1832522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik if (!early_5080) { 1833522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 1834522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= (1 << 0); 1835522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 1836522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik } 1837522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 18387bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara mv_reset_pci_bus(host, mmio); 1839522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 1840522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1841522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 1842522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 1843522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(0x0fcfffff, mmio + MV_FLASH_CTL); 1844522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 1845522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 184647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 1847ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 1848ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 1849c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 1850c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 1851c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1852c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 1853c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1854c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 1855c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 1856ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 1857ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 185847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 1859ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 1860522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp; 1861522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1862522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(0, mmio + MV_GPIO_PORT_CTL); 1863522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1864522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 1865522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1866522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 1867522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= ~(1 << 0); 1868522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 1869ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 1870ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 18712a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 18722a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 1873bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 1874c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, port); 1875c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 1876c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 1877c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 1878c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1879c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik if (fix_apm_sq) { 1880c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_LT_MODE); 1881c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= (1 << 19); 1882c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_LT_MODE); 1883c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1884c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_CTL); 1885c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~0x3; 1886c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x1; 1887c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_CTL); 1888c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 1889c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1890c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 1891c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~mask; 1892c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].pre; 1893c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].amps; 1894c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_MODE); 1895bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 1896bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 1897c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1898c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 1899c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, port_mmio + (reg)) 1900c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 1901c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 1902c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1903c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 1904c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1905b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* 1906b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * The datasheet warns against setting ATA_RST when EDMA is active 1907b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * (but doesn't say what the problem might be). So we first try 1908b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * to disable the EDMA engine before doing the ATA_RST operation. 1909b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord */ 1910e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 1911c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1912c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x028); /* command */ 1913c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(0x11f, port_mmio + EDMA_CFG_OFS); 1914c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x004); /* timer */ 1915c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x008); /* irq err cause */ 1916c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); /* irq err mask */ 1917c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); /* rq bah */ 1918c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); /* rq inp */ 1919c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); /* rq outp */ 1920c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x01c); /* respq bah */ 1921c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x024); /* respq outp */ 1922c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x020); /* respq inp */ 1923c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x02c); /* test control */ 1924c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 1925c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1926c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 1927c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1928c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, hc_mmio + (reg)) 1929c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 1930c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc) 193147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik{ 1932c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 1933c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 1934c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1935c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); 1936c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); 1937c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); 1938c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); 1939c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1940c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(hc_mmio + 0x20); 1941c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= 0x1c1c1c1c; 1942c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x03030303; 1943c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, hc_mmio + 0x20); 1944c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1945c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 1946c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1947c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 1948c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 1949c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1950c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc, port; 1951c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1952c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (hc = 0; hc < n_hc; hc++) { 1953c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (port = 0; port < MV_PORTS_PER_HC; port++) 1954c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_hc_port(hpriv, mmio, 1955c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (hc * MV_PORTS_PER_HC) + port); 1956c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1957c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_one_hc(hpriv, mmio, hc); 1958c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 1959c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1960c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return 0; 196147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik} 196247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 1963101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 1964101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#define ZERO(reg) writel(0, mmio + (reg)) 19657bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 1966101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 196702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 1968101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 1969101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 1970101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp = readl(mmio + MV_PCI_MODE); 1971101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0xff00ffff; 1972101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(tmp, mmio + MV_PCI_MODE); 1973101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 1974101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_DISC_TIMER); 1975101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_MSI_TRIGGER); 1976101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); 1977101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(HC_MAIN_IRQ_MASK_OFS); 1978101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_SERR_MASK); 197902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_cause_ofs); 198002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_mask_ofs); 1981101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_LOW_ADDRESS); 1982101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_HIGH_ADDRESS); 1983101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_ATTRIBUTE); 1984101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_COMMAND); 1985101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 1986101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 1987101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 1988101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 1989101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 1990101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 1991101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 1992101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik mv5_reset_flash(hpriv, mmio); 1993101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 1994101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp = readl(mmio + MV_GPIO_PORT_CTL); 1995101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0x3; 1996101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp |= (1 << 5) | (1 << 6); 1997101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(tmp, mmio + MV_GPIO_PORT_CTL); 1998101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 1999101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2000101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik/** 2001101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * mv6_reset_hc - Perform the 6xxx global soft reset 2002101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * @mmio: base address of the HBA 2003101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2004101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * This routine only applies to 6xxx parts. 2005101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2006101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * LOCKING: 2007101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * Inherited from caller. 2008101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2009c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2010c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 2011101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 2012101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; 2013101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik int i, rc = 0; 2014101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 t; 2015101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2016101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* Following procedure defined in PCI "main command and status 2017101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * register" table. 2018101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2019101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2020101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | STOP_PCI_MASTER, reg); 2021101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2022101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik for (i = 0; i < 1000; i++) { 2023101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2024101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 20252dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik if (PCI_MASTER_EMPTY & t) 2026101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik break; 2027101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2028101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(PCI_MASTER_EMPTY & t)) { 2029101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 2030101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2031101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2032101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2033101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2034101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* set reset */ 2035101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2036101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2037101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | GLOB_SFT_RST, reg); 2038101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2039101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2040101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 2041101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2042101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(GLOB_SFT_RST & t)) { 2043101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 2044101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2045101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2046101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2047101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2048101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 2049101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2050101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2051101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 2052101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2053101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2054101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while ((GLOB_SFT_RST & t) && (i-- > 0)); 2055101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2056101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (GLOB_SFT_RST & t) { 2057101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 2058101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2059101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2060101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikdone: 2061101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik return rc; 2062101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2063101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 206447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 2065ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 2066ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 2067ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *port_mmio; 2068ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik u32 tmp; 2069ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2070ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(mmio + MV_RESET_CFG); 2071ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik if ((tmp & (1 << 0)) == 0) { 207247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->signal[idx].amps = 0x7 << 8; 2073ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = 0x1 << 5; 2074ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik return; 2075ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik } 2076ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2077ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik port_mmio = mv_port_base(mmio, idx); 2078ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(port_mmio + PHY_MODE2); 2079ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2080ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2081ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2082ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2083ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 208447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 2085ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 208647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(0x00000060, mmio + MV_GPIO_PORT_CTL); 2087ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2088ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2089c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 20902a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 2091bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 2092c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2093c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2094bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 209547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik int fix_phy_mode2 = 209647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 2097bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik int fix_phy_mode4 = 209847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 209947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik u32 m2, tmp; 210047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 210147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (fix_phy_mode2) { 210247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 210347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 210447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 |= (1 << 31); 210547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 210647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 210747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 210847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 210947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 211047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~((1 << 16) | (1 << 31)); 211147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 211247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 211347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 211447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 211547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 211647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik /* who knows what this magic does */ 211747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp = readl(port_mmio + PHY_MODE3); 211847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp &= ~0x7F800000; 211947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp |= 0x2A800000; 212047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(tmp, port_mmio + PHY_MODE3); 2121bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2122bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (fix_phy_mode4) { 212347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik u32 m4; 2124bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2125bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m4 = readl(port_mmio + PHY_MODE4); 212647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 212747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (hp_flags & MV_HP_ERRATA_60X1B2) 2128e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord tmp = readl(port_mmio + PHY_MODE3); 2129bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2130e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* workaround for errata FEr SATA#10 (part 1) */ 2131bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m4 = (m4 & ~(1 << 1)) | (1 << 0); 2132bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2133bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m4, port_mmio + PHY_MODE4); 213447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 213547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (hp_flags & MV_HP_ERRATA_60X1B2) 2136e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord writel(tmp, port_mmio + PHY_MODE3); 2137bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2138bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2139bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik /* Revert values of pre-emphasis and signal amps to the saved ones */ 2140bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 2141bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2142bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 &= ~MV_M2_PREAMP_MASK; 21432a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].amps; 21442a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].pre; 214547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 2146bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2147e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* according to mvSata 3.6.1, some IIE values are fixed */ 2148e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (IS_GEN_IIE(hpriv)) { 2149e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 &= ~0xC30FF01F; 2150e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 |= 0x0000900F; 2151e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 2152e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2153bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 2154bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2155bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2156f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* TODO: use the generic LED interface to configure the SATA Presence */ 2157f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* & Acitivy LEDs on the board */ 2158f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 2159f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2160f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2161f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2162f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2163f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2164f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 2165f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2166f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2167f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio; 2168f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara u32 tmp; 2169f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2170f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara port_mmio = mv_port_base(mmio, idx); 2171f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(port_mmio + PHY_MODE2); 2172f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2173f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2174f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2175f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2176f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2177f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2178f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, port_mmio + (reg)) 2179f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 2180f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int port) 2181f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2182f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio = mv_port_base(mmio, port); 2183f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2184b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* 2185b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * The datasheet warns against setting ATA_RST when EDMA is active 2186b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * (but doesn't say what the problem might be). So we first try 2187b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * to disable the EDMA engine before doing the ATA_RST operation. 2188b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord */ 2189e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 2190f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2191f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x028); /* command */ 2192f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0x101f, port_mmio + EDMA_CFG_OFS); 2193f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x004); /* timer */ 2194f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x008); /* irq err cause */ 2195f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); /* irq err mask */ 2196f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); /* rq bah */ 2197f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); /* rq inp */ 2198f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x018); /* rq outp */ 2199f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x01c); /* respq bah */ 2200f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x024); /* respq outp */ 2201f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x020); /* respq inp */ 2202f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x02c); /* test control */ 2203f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 2204f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2205f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2206f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2207f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2208f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, hc_mmio + (reg)) 2209f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 2210f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2211f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2212f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *hc_mmio = mv_hc_base(mmio, 0); 2213f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2214f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); 2215f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); 2216f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); 2217f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2218f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2219f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2220f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2221f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2222f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 2223f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc) 2224f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2225f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int port; 2226f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2227f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara for (port = 0; port < hpriv->n_ports; port++) 2228f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_hc_port(hpriv, mmio, port); 2229f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2230f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_one_hc(hpriv, mmio); 2231f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2232f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 2233f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2234f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2235f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 2236f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2237f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2238f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2239f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2240f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2241f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 2242f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2243f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2244f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2245f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2246b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lordstatic void mv_setup_ifctl(void __iomem *port_mmio, int want_gen2i) 2247b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord{ 2248b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord u32 ifctl = readl(port_mmio + SATA_INTERFACE_CFG); 2249b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 2250b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord ifctl = (ifctl & 0xf7f) | 0x9b1000; /* from chip spec */ 2251b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (want_gen2i) 2252b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord ifctl |= (1 << 7); /* enable gen2i speed */ 2253b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord writelfl(ifctl, port_mmio + SATA_INTERFACE_CFG); 2254b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord} 2255b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 2256b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord/* 2257b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * Caller must ensure that EDMA is not active, 2258b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * by first doing mv_stop_edma() where needed. 2259b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord */ 2260e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 2261c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no) 2262c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2263c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port_no); 2264c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 22650d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord mv_stop_edma_engine(port_mmio); 2266c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); 2267c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2268b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (!IS_GEN_I(hpriv)) { 2269b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord /* Enable 3.0gb/s link speed */ 2270b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord mv_setup_ifctl(port_mmio, 1); 2271c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2272b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord /* 2273b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * Strobing ATA_RST here causes a hard reset of the SATA transport, 2274b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * link, and physical layers. It resets all SATA interface registers 2275b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev. 2276c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik */ 2277b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); 2278b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord udelay(25); /* allow reset propagation */ 2279c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writelfl(0, port_mmio + EDMA_CMD_OFS); 2280c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2281c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->ops->phy_errata(hpriv, mmio, port_no); 2282c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2283ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) 2284c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mdelay(1); 2285c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2286c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2287cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 2288bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned long deadline) 228931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 2290cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo struct ata_port *ap = link->ap; 2291bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2292b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 2293f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 22940d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord int rc, attempts = 0, extra = 0; 22950d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord u32 sstatus; 22960d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord bool online; 229731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2298e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, ap->port_no); 2299b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2300bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 23010d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Workaround for errata FEr SATA#10 (part 2) */ 23020d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord do { 230317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord const unsigned long *timing = 230417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord sata_ehc_deb_timing(&link->eh_context); 2305bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 230617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord rc = sata_link_hardreset(link, timing, deadline + extra, 230717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord &online, NULL); 230817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord if (rc) 23090d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord return rc; 23100d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord sata_scr_read(link, SCR_STATUS, &sstatus); 23110d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 23120d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Force 1.5gb/s link speed and try again */ 23130d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord mv_setup_ifctl(mv_ap_base(ap), 0); 23140d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (time_after(jiffies + HZ, deadline)) 23150d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord extra = HZ; /* only extend it once, max */ 23160d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } 23170d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); 2318bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 231917c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord return rc; 2320bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2321bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2322bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap) 2323bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2324f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 2325bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int hc = (ap->port_no > 3) ? 1 : 0; 2326bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 tmp, mask; 2327bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int shift; 2328bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2329bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* FIXME: handle coalescing completion events properly */ 2330bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2331bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik shift = ap->port_no * 2; 2332bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (hc > 0) 2333bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik shift++; 2334bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2335bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mask = 0x3 << shift; 2336bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2337bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* disable assertion of portN err, done events */ 2338f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(hpriv->main_mask_reg_addr); 2339f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(tmp & ~mask, hpriv->main_mask_reg_addr); 2340bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2341bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2342bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap) 2343bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2344f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 2345f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 2346bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int hc = (ap->port_no > 3) ? 1 : 0; 2347bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 2348bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 2349bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 tmp, mask, hc_irq_cause; 2350bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int shift, hc_port_no = ap->port_no; 2351bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2352bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* FIXME: handle coalescing completion events properly */ 2353bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2354bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik shift = ap->port_no * 2; 2355bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (hc > 0) { 2356bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik shift++; 2357bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_port_no -= 4; 2358bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2359bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2360bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mask = 0x3 << shift; 2361bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2362bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA errors on this port */ 2363bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2364bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2365bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear pending irq events */ 2366bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 2367bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_irq_cause &= ~(1 << hc_port_no); /* clear CRPB-done */ 2368bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_irq_cause &= ~(1 << (hc_port_no + 8)); /* clear Device int */ 2369bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writel(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 2370bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2371bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* enable assertion of portN err, done events */ 2372f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(hpriv->main_mask_reg_addr); 2373f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(tmp | mask, hpriv->main_mask_reg_addr); 237431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 237531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 237605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 237705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_init - Perform some early initialization on a single port. 237805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port: libata data structure storing shadow register addresses 237905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port_mmio: base address of the port 238005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 238105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Initialize shadow register mmio addresses, clear outstanding 238205b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts on the port, and unmask interrupts for the future 238305b308e1df6d9d673daedb517969241f41278b52Brett Russ * start of the port. 238405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 238505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 238605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 238705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 238831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 238920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 23900d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *shd_base = port_mmio + SHD_BLK_OFS; 239131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ unsigned serr_ofs; 239231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 23938b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik /* PIO related setup 239431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 239531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 23968b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->error_addr = 239731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 239831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 239931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 240031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 240131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 240231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 24038b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->status_addr = 240431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 240531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* special case: control/altstatus doesn't have ATA_REG_ address */ 240631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; 240731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 240831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* unused: */ 24098d9db2d2fbae9e05022825c32f86e00c8e342860Randy Dunlap port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; 241020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 241131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding port interrupt conditions */ 241231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ serr_ofs = mv_scr_offset(SCR_ERROR); 241331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); 241431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 241531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2416646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord /* unmask all non-transient EDMA error interrupts */ 2417646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS); 241820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 24198b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 242031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_CFG_OFS), 242131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), 242231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); 242320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 242420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 24254447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_chip_id(struct ata_host *host, unsigned int board_idx) 2426bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 24274447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 24284447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 2429bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 2430bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 24315796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik switch (board_idx) { 243247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case chip_5080: 243347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 2434ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 243547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 243644c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 243747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x1: 243847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 243947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 244047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 244147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 244247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 244347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 244447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 244547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying 50XXB2 workarounds to unknown rev\n"); 244647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 244747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 244847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 244947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 245047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 2451bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_504x: 2452bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_508x: 245347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 2454ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 2455bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 245644c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 245747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x0: 245847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 245947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 246047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 246147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 246247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 246347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 246447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 246547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 246647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 246747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 2468bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2469bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2470bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2471bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_604x: 2472bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_608x: 247347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv6xxx_ops; 2474ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_II; 247547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 247644c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 247747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x7: 247847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 247947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 248047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x9: 248147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2482bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2483bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 2484bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 248547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 248647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 2487bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2488bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2489bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2490bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2491e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_7042: 249202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hp_flags |= MV_HP_PCIE; 2493306b30f74d37f289033c696285e07ce0158a5d7bMark Lord if (pdev->vendor == PCI_VENDOR_ID_TTI && 2494306b30f74d37f289033c696285e07ce0158a5d7bMark Lord (pdev->device == 0x2300 || pdev->device == 0x2310)) 2495306b30f74d37f289033c696285e07ce0158a5d7bMark Lord { 24964e5200334e03e5620aa19d538300c13db270a063Mark Lord /* 24974e5200334e03e5620aa19d538300c13db270a063Mark Lord * Highpoint RocketRAID PCIe 23xx series cards: 24984e5200334e03e5620aa19d538300c13db270a063Mark Lord * 24994e5200334e03e5620aa19d538300c13db270a063Mark Lord * Unconfigured drives are treated as "Legacy" 25004e5200334e03e5620aa19d538300c13db270a063Mark Lord * by the BIOS, and it overwrites sector 8 with 25014e5200334e03e5620aa19d538300c13db270a063Mark Lord * a "Lgcy" metadata block prior to Linux boot. 25024e5200334e03e5620aa19d538300c13db270a063Mark Lord * 25034e5200334e03e5620aa19d538300c13db270a063Mark Lord * Configured drives (RAID or JBOD) leave sector 8 25044e5200334e03e5620aa19d538300c13db270a063Mark Lord * alone, but instead overwrite a high numbered 25054e5200334e03e5620aa19d538300c13db270a063Mark Lord * sector for the RAID metadata. This sector can 25064e5200334e03e5620aa19d538300c13db270a063Mark Lord * be determined exactly, by truncating the physical 25074e5200334e03e5620aa19d538300c13db270a063Mark Lord * drive capacity to a nice even GB value. 25084e5200334e03e5620aa19d538300c13db270a063Mark Lord * 25094e5200334e03e5620aa19d538300c13db270a063Mark Lord * RAID metadata is at: (dev->n_sectors & ~0xfffff) 25104e5200334e03e5620aa19d538300c13db270a063Mark Lord * 25114e5200334e03e5620aa19d538300c13db270a063Mark Lord * Warn the user, lest they think we're just buggy. 25124e5200334e03e5620aa19d538300c13db270a063Mark Lord */ 25134e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 25144e5200334e03e5620aa19d538300c13db270a063Mark Lord " BIOS CORRUPTS DATA on all attached drives," 25154e5200334e03e5620aa19d538300c13db270a063Mark Lord " regardless of if/how they are configured." 25164e5200334e03e5620aa19d538300c13db270a063Mark Lord " BEWARE!\n"); 25174e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": For data safety, do not" 25184e5200334e03e5620aa19d538300c13db270a063Mark Lord " use sectors 8-9 on \"Legacy\" drives," 25194e5200334e03e5620aa19d538300c13db270a063Mark Lord " and avoid the final two gigabytes on" 25204e5200334e03e5620aa19d538300c13db270a063Mark Lord " all RocketRAID BIOS initialized drives.\n"); 2521306b30f74d37f289033c696285e07ce0158a5d7bMark Lord } 2522e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_6042: 2523e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hpriv->ops = &mv6xxx_ops; 2524e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_GEN_IIE; 2525e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 252644c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 2527e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case 0x0: 2528e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_XX42A0; 2529e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2530e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case 0x1: 2531e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2532e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2533e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik default: 2534e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 2535e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik "Applying 60X1C0 workarounds to unknown rev\n"); 2536e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2537e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2538e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 2539e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2540f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara case chip_soc: 2541f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->ops = &mv_soc_ops; 2542f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hp_flags |= MV_HP_ERRATA_60X1C0; 2543f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara break; 2544e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2545bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 2546f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_ERR, host->dev, 25475796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik "BUG: invalid board index %u\n", board_idx); 2548bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 1; 2549bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2550bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2551bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik hpriv->hp_flags = hp_flags; 255202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord if (hp_flags & MV_HP_PCIE) { 255302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS; 255402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS; 255502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 255602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } else { 255702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS; 255802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS; 255902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 256002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } 2561bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2562bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 0; 2563bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2564bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 256505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 256647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik * mv_init_host - Perform some early initialization of the host. 25674447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to initialize 25684447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @board_idx: controller index 256905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 257005b308e1df6d9d673daedb517969241f41278b52Brett Russ * If possible, do an early global reset of the host. Then do 257105b308e1df6d9d673daedb517969241f41278b52Brett Russ * our port init and clear/unmask all/relevant host interrupts. 257205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 257305b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 257405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 257505b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 25764447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_init_host(struct ata_host *host, unsigned int board_idx) 257720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 257820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ int rc = 0, n_hc, port, hc; 25794447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 2580f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 258147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 25824447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_chip_id(host, board_idx); 2583bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (rc) 2584f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara goto done; 2585f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2586f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2587f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_cause_reg_addr = hpriv->base + 2588f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_MAIN_IRQ_CAUSE_OFS; 2589f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr = hpriv->base + HC_MAIN_IRQ_MASK_OFS; 2590f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } else { 2591f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_cause_reg_addr = hpriv->base + 2592f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_SOC_MAIN_IRQ_CAUSE_OFS; 2593f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr = hpriv->base + 2594f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_SOC_MAIN_IRQ_MASK_OFS; 2595f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2596f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* global interrupt mask */ 2597f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0, hpriv->main_mask_reg_addr); 2598bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 25994447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_hc = mv_get_hc_count(host->ports[0]->flags); 2600bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 26014447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) 260247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->read_preamp(hpriv, port, mmio); 260320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2604c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 260547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (rc) 260620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ goto done; 260720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2608522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik hpriv->ops->reset_flash(hpriv, mmio); 26097bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara hpriv->ops->reset_bus(host, mmio); 261047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->enable_leds(hpriv, mmio); 261120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 26124447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) { 2613cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo struct ata_port *ap = host->ports[port]; 26142a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2615cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 2616cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo mv_port_init(&ap->ioaddr, port_mmio); 2617cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 26187bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 2619f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2620f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int offset = port_mmio - mmio; 2621f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 2622f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 2623f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 26247bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 262520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 262620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 262720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hc; hc++) { 262831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 262931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 263031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 263131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ "(before clear)=0x%08x\n", hc, 263231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_CFG_OFS), 263331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_IRQ_CAUSE_OFS)); 263431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 263531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding hc interrupt conditions */ 263631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); 263720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 263820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2639f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2640f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* Clear any currently outstanding host interrupt conditions */ 2641f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(0, mmio + hpriv->irq_cause_ofs); 264231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2643f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* and unmask interrupt generation for host regs */ 2644f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs); 2645f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (IS_GEN_I(hpriv)) 2646f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS_5, 2647f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr); 2648f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara else 2649f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS, 2650f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr); 2651f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2652f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x " 2653f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "PCI int cause/mask=0x%08x/0x%08x\n", 2654f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_cause_reg_addr), 2655f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_mask_reg_addr), 2656f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(mmio + hpriv->irq_cause_ofs), 2657f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(mmio + hpriv->irq_mask_ofs)); 2658f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } else { 2659f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS_SOC, 2660f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr); 2661f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n", 2662f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_cause_reg_addr), 2663f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_mask_reg_addr)); 2664f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2665f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharadone: 2666f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 2667f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2668fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik 2669fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradleystatic int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 2670fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley{ 2671fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 2672fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRQB_Q_SZ, 0); 2673fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crqb_pool) 2674fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2675fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2676fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 2677fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRPB_Q_SZ, 0); 2678fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crpb_pool) 2679fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2680fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2681fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 2682fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_SG_TBL_SZ, 0); 2683fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->sg_tbl_pool) 2684fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2685fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2686fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return 0; 2687fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley} 2688fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2689f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/** 2690f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_probe - handle a positive probe of an soc Marvell 2691f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * host 2692f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device found 2693f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2694f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * LOCKING: 2695f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Inherited from caller. 2696f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2697f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev) 2698f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2699f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara static int printed_version; 2700f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct mv_sata_platform_data *mv_platform_data; 2701f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct ata_port_info *ppi[] = 2702f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { &mv_port_info[chip_soc], NULL }; 2703f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host; 2704f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv; 2705f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct resource *res; 2706f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports, rc; 270720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2708f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!printed_version++) 2709f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 2710bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2711f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 2712f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Simple resource validation .. 2713f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2714f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (unlikely(pdev->num_resources != 2)) { 2715f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_err(&pdev->dev, "invalid number of resources\n"); 2716f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 2717f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2718f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2719f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 2720f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Get the register base first 2721f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2722f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2723f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (res == NULL) 2724f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 2725f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2726f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* allocate host */ 2727f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_platform_data = pdev->dev.platform_data; 2728f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara n_ports = mv_platform_data->n_ports; 2729f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2730f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 2731f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 2732f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2733f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!host || !hpriv) 2734f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -ENOMEM; 2735f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->private_data = hpriv; 2736f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 2737f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2738f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->iomap = NULL; 2739f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara hpriv->base = devm_ioremap(&pdev->dev, res->start, 2740f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara res->end - res->start + 1); 2741f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base -= MV_SATAHC0_REG_BASE; 2742f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2743fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley rc = mv_create_dma_pools(hpriv, &pdev->dev); 2744fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (rc) 2745fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return rc; 2746fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2747f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* initialize adapter */ 2748f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = mv_init_host(host, chip_soc); 2749f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc) 2750f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 2751f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2752f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, 2753f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, 2754f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->n_ports); 2755f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2756f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, 2757f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara IRQF_SHARED, &mv6_sht); 2758f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2759f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2760f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* 2761f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2762f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_remove - unplug a platform interface 2763f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device 2764f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2765f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * A platform bus SATA device has been unplugged. Perform the needed 2766f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * cleanup. Also called on module unload for any active devices. 2767f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2768f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev) 2769f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2770f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct device *dev = &pdev->dev; 2771f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host = dev_get_drvdata(dev); 2772f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2773f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_host_detach(host); 2774f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 277520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 277620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2777f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic struct platform_driver mv_platform_driver = { 2778f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_platform_probe, 2779f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .remove = __devexit_p(mv_platform_remove), 2780f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .driver = { 2781f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .name = DRV_NAME, 2782f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .owner = THIS_MODULE, 2783f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 2784f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 2785f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2786f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 27877bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 2788f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 2789f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent); 2790f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 27917bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 27927bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic struct pci_driver mv_pci_driver = { 27937bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .name = DRV_NAME, 27947bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .id_table = mv_pci_tbl, 2795f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_pci_init_one, 27967bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .remove = ata_pci_remove_one, 27977bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara}; 27987bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 27997bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* 28007bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara * module options 28017bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara */ 28027bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int msi; /* Use PCI msi; either zero (off, default) or non-zero */ 28037bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 28047bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 28057bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* move to PCI layer or libata core? */ 28067bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int pci_go_64(struct pci_dev *pdev) 28077bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara{ 28087bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc; 28097bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 28107bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 28117bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 28127bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 28137bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 28147bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 28157bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 28167bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "64-bit DMA enable failed\n"); 28177bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 28187bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 28197bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 28207bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } else { 28217bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 28227bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 28237bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 28247bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit DMA enable failed\n"); 28257bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 28267bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 28277bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 28287bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 28297bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 28307bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit consistent DMA enable failed\n"); 28317bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 28327bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 28337bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 28347bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 28357bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 28367bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara} 28377bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 283805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 283905b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_print_info - Dump key info to kernel log for perusal. 28404447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to print info about 284105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 284205b308e1df6d9d673daedb517969241f41278b52Brett Russ * FIXME: complete this. 284305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 284405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 284505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 284605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 28474447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic void mv_print_info(struct ata_host *host) 284831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 28494447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 28504447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 285144c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok u8 scc; 2852c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik const char *scc_s, *gen; 285331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 285431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Use this to determine the HW stepping of the chip so we know 285531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * what errata to workaround 285631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 285731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 285831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (scc == 0) 285931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "SCSI"; 286031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else if (scc == 0x01) 286131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "RAID"; 286231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else 2863c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik scc_s = "?"; 2864c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik 2865c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik if (IS_GEN_I(hpriv)) 2866c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "I"; 2867c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_II(hpriv)) 2868c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "II"; 2869c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_IIE(hpriv)) 2870c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "IIE"; 2871c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else 2872c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "?"; 287331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2874a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, 2875c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 2876c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 287731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 287831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 287931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 288005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2881f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_pci_init_one - handle a positive probe of a PCI Marvell host 288205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pdev: PCI device found 288305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ent: PCI device ID entry for the matched host 288405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 288505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 288605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 288705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 2888f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 2889f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent) 289020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 28912dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik static int printed_version; 289220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int board_idx = (unsigned int)ent->driver_data; 28934447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 28944447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct ata_host *host; 28954447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv; 28964447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo int n_ports, rc; 289720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2898a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik if (!printed_version++) 2899a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 290020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 29014447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* allocate host */ 29024447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 29034447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 29044447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 29054447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 29064447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (!host || !hpriv) 29074447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return -ENOMEM; 29084447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->private_data = hpriv; 2909f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 29104447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 29114447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* acquire resources */ 291224dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo rc = pcim_enable_device(pdev); 291324dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 291420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return rc; 291520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 29160d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 29170d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc == -EBUSY) 291824dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pcim_pin_device(pdev); 29190d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc) 292024dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 29214447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->iomap = pcim_iomap_table(pdev); 2922f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base = host->iomap[MV_PRIMARY_BAR]; 292320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2924d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik rc = pci_go_64(pdev); 2925d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik if (rc) 2926d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik return rc; 2927d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik 2928da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord rc = mv_create_dma_pools(hpriv, &pdev->dev); 2929da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (rc) 2930da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return rc; 2931da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 293220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* initialize adapter */ 29334447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_init_host(host, board_idx); 293424dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 293524dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 293620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 293731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Enable interrupts */ 29386a59dcf8678cbc4106a8a6e158d7408a87691358Tejun Heo if (msi && pci_enable_msi(pdev)) 293931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_intx(pdev, 1); 294020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 294131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 29424447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo mv_print_info(host); 294320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 29444447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo pci_set_master(pdev); 2945ea8b4db97aa41a66c05daa4055a1974692ccd52dJeff Garzik pci_try_set_mwi(pdev); 29464447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 2947c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 294820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 29497bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 295020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2951f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev); 2952f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev); 2953f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 295420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic int __init mv_init(void) 295520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 29567bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc = -ENODEV; 29577bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 29587bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_register_driver(&mv_pci_driver); 2959f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 2960f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 2961f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#endif 2962f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = platform_driver_register(&mv_platform_driver); 2963f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2964f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#ifdef CONFIG_PCI 2965f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 2966f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara pci_unregister_driver(&mv_pci_driver); 29677bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 29687bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 296920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 297020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 297120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic void __exit mv_exit(void) 297220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 29737bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 297420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ pci_unregister_driver(&mv_pci_driver); 29757bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 2976f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara platform_driver_unregister(&mv_platform_driver); 297720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 297820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 297920f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_AUTHOR("Brett Russ"); 298020f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 298120f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_LICENSE("GPL"); 298220f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DEVICE_TABLE(pci, mv_pci_tbl); 298320f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_VERSION(DRV_VERSION); 298417c5aab5b34e351531466e35b154ca86db7d46a9Mark LordMODULE_ALIAS("platform:" DRV_NAME); 298520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 29867bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 2987ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzikmodule_param(msi, int, 0444); 2988ddef9bb367b19383df627e388cb4c01c86ddba6cJeff GarzikMODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 29897bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 2990ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzik 299120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_init(mv_init); 299220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_exit(mv_exit); 2993