sata_mv.c revision 2009177329ae565d9e9efd31b399d2f4ed4f0c44
120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * sata_mv.c - Marvell SATA support 320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * Copyright 2008-2009: Marvell Corporation, all rights reserved. 58b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * Copyright 2005: EMC Corporation, all rights reserved. 6e2b1be56c5656902744c2b52e8304126a40bb609Jeff Garzik * Copyright 2005 Red Hat, Inc. All rights reserved. 720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 840f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * Originally written by Brett Russ. 940f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>. 1040f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * 1120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 1220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is free software; you can redistribute it and/or modify 1420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * it under the terms of the GNU General Public License as published by 1520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * the Free Software Foundation; version 2 of the License. 1620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is distributed in the hope that it will be useful, 1820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * but WITHOUT ANY WARRANTY; without even the implied warranty of 1920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 2020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * GNU General Public License for more details. 2120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * You should have received a copy of the GNU General Public License 2320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * along with this program; if not, write to the Free Software 2420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 2520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 284a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik/* 2985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * sata_mv TODO list: 3085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Develop a low-power-consumption strategy, and implement it. 3285afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 332b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds. 3485afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3585afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> [Experiment, Marvell value added] Is it possible to use target 3685afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * mode to cross-connect two Linux boxes with Marvell cards? If so, 3785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * creating LibATA target mode support would be very interesting. 3885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * Target mode, for those without docs, is the ability to directly 4085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * connect two SATA ports. 4185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord */ 424a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 4365ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord/* 4465ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * 80x1-B2 errata PCI#11: 4565ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * 4665ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * Users of the 6041/6081 Rev.B2 chips (current is C0) 4765ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * should be careful to insert those cards only onto PCI-X bus #0, 4865ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * and only in device slots 0..7, not higher. The chips may not 4965ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * work correctly otherwise (note: this is a pretty rare condition). 5065ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord */ 5165ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord 5220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/kernel.h> 5320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/module.h> 5420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/pci.h> 5520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/init.h> 5620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/blkdev.h> 5720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/delay.h> 5820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/interrupt.h> 598d8b60046d6a2328ca4b9031b4948084f775f607Andrew Morton#include <linux/dmapool.h> 6020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/dma-mapping.h> 61a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik#include <linux/device.h> 62f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/platform_device.h> 63f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/ata_platform.h> 6415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#include <linux/mbus.h> 65c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord#include <linux/bitops.h> 6620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <scsi/scsi_host.h> 67193515d51ccb363165d6b09e9ba5c21089e34badJeff Garzik#include <scsi/scsi_cmnd.h> 686c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik#include <scsi/scsi_device.h> 6920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/libata.h> 7020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#define DRV_NAME "sata_mv" 722b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord#define DRV_VERSION "1.27" 7320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord/* 7540f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * module options 7640f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord */ 7740f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord 7840f21b1124a9552bc093469280eb8239dc5f73d7Mark Lordstatic int msi; 7940f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord#ifdef CONFIG_PCI 8040f21b1124a9552bc093469280eb8239dc5f73d7Mark Lordmodule_param(msi, int, S_IRUGO); 8140f21b1124a9552bc093469280eb8239dc5f73d7Mark LordMODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 8240f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord#endif 8340f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord 842b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic int irq_coalescing_io_count; 852b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordmodule_param(irq_coalescing_io_count, int, S_IRUGO); 862b748a0a344847fe6b924407bbe153e1878c9f09Mark LordMODULE_PARM_DESC(irq_coalescing_io_count, 872b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord "IRQ coalescing I/O count threshold (0..255)"); 882b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 892b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic int irq_coalescing_usecs; 902b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordmodule_param(irq_coalescing_usecs, int, S_IRUGO); 912b748a0a344847fe6b924407bbe153e1878c9f09Mark LordMODULE_PARM_DESC(irq_coalescing_usecs, 922b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord "IRQ coalescing time threshold in usecs"); 932b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 9420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russenum { 9520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* BAR's are enumerated in terms of pci_resource_start() terms */ 9620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 9720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IO_BAR = 2, /* offset 0x18: IO space */ 9820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 9920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 10020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 10120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 10220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1032b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */ 1042b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */ 1052b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */ 1062b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord MAX_COAL_IO_COUNT = 255, /* completed I/O count */ 1072b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 10820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_BASE = 0, 109615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 1102b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 1112b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Per-chip ("all ports") interrupt coalescing feature. 1122b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * This is only for GEN_II / GEN_IIE hardware. 1132b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * 1142b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Coalescing defers the interrupt until either the IO_THRESHOLD 1152b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. 1162b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 1172b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord MV_COAL_REG_BASE = 0x18000, 1182b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord MV_IRQ_COAL_CAUSE = (MV_COAL_REG_BASE + 0x08), 1192b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */ 1202b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 1212b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord MV_IRQ_COAL_IO_THRESHOLD = (MV_COAL_REG_BASE + 0xcc), 1222b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord MV_IRQ_COAL_TIME_THRESHOLD = (MV_COAL_REG_BASE + 0xd0), 1232b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 1242b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 1252b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Registers for the (unused here) transaction coalescing feature: 1262b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 1272b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord MV_TRAN_COAL_CAUSE_LO = (MV_COAL_REG_BASE + 0x88), 1282b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord MV_TRAN_COAL_CAUSE_HI = (MV_COAL_REG_BASE + 0x8c), 1292b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 13020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC0_REG_BASE = 0x20000, 1318e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_FLASH_CTL_OFS = 0x1046c, 1328e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_GPIO_PORT_CTL_OFS = 0x104f0, 1338e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_RESET_CFG_OFS = 0x180d8, 13420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 13520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 13620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 13720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 13820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 13920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 14031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH = 32, 14131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 14231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* CRQB needs alignment on a 1KB boundary. Size == 1KB 14431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * CRPB needs alignment on a 256B boundary. Size == 256B 14531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 14631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 14731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 14831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 149da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord MV_MAX_SG_CT = 256, 15031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 15131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 152352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ 15320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_HC_SHIFT = 2, 154352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ 155352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ 156352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ 15720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 15820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Host Flags */ 15920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 1607bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 161c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 16291b1a84c10869e2e46a576e5367de3166bff8eccMark Lord ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING, 163ad3aef51e17b9c6a90a9014805f1645e8e441c17Mark Lord 16491b1a84c10869e2e46a576e5367de3166bff8eccMark Lord MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI, 16520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 16640f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ | 16740f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA, 16891b1a84c10869e2e46a576e5367de3166bff8eccMark Lord 16991b1a84c10869e2e46a576e5367de3166bff8eccMark Lord MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN, 170ad3aef51e17b9c6a90a9014805f1645e8e441c17Mark Lord 17131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_FLAG_READ = (1 << 0), 17231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_TAG_SHIFT = 1, 173c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 174e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 175c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 17631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_ADDR_SHIFT = 8, 17731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_CS = (0x2 << 11), 17831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_LAST = (1 << 15), 17931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 18031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRPB_FLAG_STATUS_SHIFT = 8, 181c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 182c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 18331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 18431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EPRD_FLAG_END_OF_TBL = (1 << 31), 18531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 18620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* PCI interface registers */ 18720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 18831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ PCI_COMMAND_OFS = 0xc00, 18965ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */ 1908e7decdb8b132ee970a2636931b7653dec6af472Mark Lord PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */ 19131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 19220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MAIN_CMD_STS_OFS = 0xd30, 19320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ STOP_PCI_MASTER = (1 << 2), 19420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MASTER_EMPTY = (1 << 3), 19520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GLOB_SFT_RST = (1 << 4), 19620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1978e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_MODE_OFS = 0xd00, 1988e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_MODE_MASK = 0x30, 1998e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 200522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 201522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_DISC_TIMER = 0xd04, 202522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MSI_TRIGGER = 0xc38, 203522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_SERR_MASK = 0xc28, 2048e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_XBAR_TMOUT_OFS = 0x1d04, 205522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 206522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 207522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_ATTRIBUTE = 0x1d48, 208522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_COMMAND = 0x1d50, 209522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 21002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_CAUSE_OFS = 0x1d58, 21102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_MASK_OFS = 0x1d5c, 21220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 21320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_CAUSE_OFS = 0x1900, 21502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_MASK_OFS = 0x1910, 216646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 21702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 2187368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */ 2197368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, 2207368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64, 2217368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020, 2227368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024, 22340f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord ERR_IRQ = (1 << 0), /* shift by (2 * port #) */ 22440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord DONE_IRQ = (1 << 1), /* shift by (2 * port #) */ 22520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 22620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 2272b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */ 2282b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */ 22920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_ERR = (1 << 18), 23040f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */ 23140f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */ 23240f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */ 23340f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */ 23440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */ 23520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GPIO_INT = (1 << 22), 23620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SELF_INT = (1 << 23), 23720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TWSI_INT = (1 << 24), 23820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 239fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 240e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 24120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 24220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATAHC registers */ 24320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_CFG_OFS = 0, 24420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 24520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_IRQ_CAUSE_OFS = 0x14, 246352fab701ca4753dd005b67ce5e512be944eb591Mark Lord DMA_IRQ = (1 << 0), /* shift by port # */ 247352fab701ca4753dd005b67ce5e512be944eb591Mark Lord HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ 24820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ DEV_IRQ = (1 << 8), /* shift by port # */ 24920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2502b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 2512b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Per-HC (Host-Controller) interrupt coalescing feature. 2522b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * This is present on all chip generations. 2532b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * 2542b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Coalescing defers the interrupt until either the IO_THRESHOLD 2552b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. 2562b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 2572b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord HC_IRQ_COAL_IO_THRESHOLD_OFS = 0x000c, 2582b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord HC_IRQ_COAL_TIME_THRESHOLD_OFS = 0x0010, 2592b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 260000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord SOC_LED_CTRL_OFS = 0x2c, 261000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */ 262000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */ 263000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord /* with dev activity LED */ 264000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 26520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Shadow block registers */ 26631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_BLK_OFS = 0x100, 26731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ 26820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 26920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATA registers */ 27020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ 27120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_ACTIVE_OFS = 0x350, 2720c58912e192fc3a4835d772aafa40b72552b819fMark Lord SATA_FIS_IRQ_CAUSE_OFS = 0x364, 273c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord SATA_FIS_IRQ_AN = (1 << 9), /* async notification */ 27417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 275e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord LTMODE_OFS = 0x30c, 27617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 27717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 27847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik PHY_MODE3 = 0x310, 279bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE4 = 0x314, 280ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */ 281ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */ 282ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */ 283ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */ 284ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord 285bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE2 = 0x330, 286e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFCTL_OFS = 0x344, 2878e7decdb8b132ee970a2636931b7653dec6af472Mark Lord SATA_TESTCTL_OFS = 0x348, 288e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFSTAT_OFS = 0x34c, 289e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord VENDOR_UNIQUE_FIS_OFS = 0x35c, 29017c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 2918e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_OFS = 0x360, 2928e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */ 2938e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 29417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 295c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_MODE = 0x74, 2968e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV5_LTMODE_OFS = 0x30, 2978e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV5_PHY_CTL_OFS = 0x0C, 2988e7decdb8b132ee970a2636931b7653dec6af472Mark Lord SATA_INTERFACE_CFG_OFS = 0x050, 299bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 300bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_M2_PREAMP_MASK = 0x7e0, 30120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Port registers */ 30320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_CFG_OFS = 0, 3040c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 3050c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 3060c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 3070c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 3080c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 309e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 310e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 31120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 31220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_CAUSE_OFS = 0x8, 31320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_MASK_OFS = 0xc, 3146c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 3156c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 3166c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV = (1 << 2), /* device error */ 3176c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 3186c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 3196c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 320c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 321c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 3226c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 323c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 3246c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 3256c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 3266c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 3276c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 328646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3296c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 330646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 331646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 332646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 333646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 334646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3356c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 336646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3376c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 338646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 339646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 340646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 341646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 342646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 343646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3446c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 345646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3466c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 347c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_OVERRUN_5 = (1 << 5), 348c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_UNDERRUN_5 = (1 << 6), 349646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 350646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 351646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 | 352646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 | 35385afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord EDMA_ERR_LNK_CTRL_TX, 354646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 355bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 356bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 357bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 358bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 359bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SERR | 360bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS | 3616c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 362bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 363bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 364bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY | 365bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_CTRL_RX_2 | 366bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_RX | 367bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_TX | 368bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_TRANS_PROTO, 369e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 370bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 371bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 372bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 373bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 374bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_OVERRUN_5 | 375bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_UNDERRUN_5 | 376bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS_5 | 3776c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 378bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 379bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 380bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY, 38120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 38231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_BASE_HI_OFS = 0x10, 38331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ 38431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 38531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_OUT_PTR_OFS = 0x18, 38631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_PTR_SHIFT = 5, 38731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 38831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_BASE_HI_OFS = 0x1c, 38931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_IN_PTR_OFS = 0x20, 39031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ 39131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_PTR_SHIFT = 3, 39231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3930ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_CMD_OFS = 0x28, /* EDMA command register */ 3940ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_EN = (1 << 0), /* enable EDMA */ 3950ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 3968e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */ 3978e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 3988e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_OFS = 0x30, /* EDMA engine status */ 3998e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */ 4008e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */ 40120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4028e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_IORDY_TMOUT_OFS = 0x34, 4038e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_ARB_CFG_OFS = 0x38, 4048e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 4058e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */ 406c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord EDMA_UNKNOWN_RSVD_OFS = 0x6C, /* GenIIe unknown/reserved */ 407da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 408da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord BMDMA_CMD_OFS = 0x224, /* bmdma command register */ 409da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord BMDMA_STATUS_OFS = 0x228, /* bmdma status register */ 410da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord BMDMA_PRD_LOW_OFS = 0x22c, /* bmdma PRD addr 31:0 */ 411da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord BMDMA_PRD_HIGH_OFS = 0x230, /* bmdma PRD addr 63:32 */ 412da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 41331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Host private flags (hp_flags) */ 41431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_HP_FLAG_MSI = (1 << 0), 41547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB0 = (1 << 1), 41647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB2 = (1 << 2), 41747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1B2 = (1 << 3), 41847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1C0 = (1 << 4), 4190ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 4200ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 4210ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 42202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 423616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ 4241f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */ 425000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */ 42620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 42731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Port private flags (pp_flags) */ 4280ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 429721091685f853ba4e6c49f26f989db0b1a811250Mark Lord MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 43000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */ 43129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */ 432d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */ 43320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 43420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 435ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 436ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 437e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 4388e7decdb8b132ee970a2636931b7653dec6af472Mark Lord#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) 4391f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC) 440bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 44115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 44215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_BASE(i) (0x20034 + ((i) << 4)) 44315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 444095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzikenum { 445baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik /* DMA boundary 0xffff is required by the s/g splitting 446baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik * we need on /length/ in mv_fill-sg(). 447baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik */ 448baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik MV_DMA_BOUNDARY = 0xffffU, 449095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 4500ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* mask of register bits containing lower 32 bits 4510ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik * of EDMA request queue DMA address 4520ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik */ 453095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 454095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 4550ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* ditto, for response queue */ 456095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 457095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik}; 458095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 459522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikenum chip_type { 460522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_504x, 461522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_508x, 462522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_5080, 463522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_604x, 464522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_608x, 465e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_6042, 466e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_7042, 467f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara chip_soc, 468522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik}; 469522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 47031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ReQuest Block: 32B */ 47131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crqb { 472e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr; 473e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr_hi; 474e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ctrl_flags; 475e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ata_cmd[11]; 47631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 47720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 478e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstruct mv_crqb_iie { 479e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 480e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 481e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags; 482e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 len; 483e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 ata_cmd[4]; 484e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 485e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 48631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ResPonse Block: 8B */ 48731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crpb { 488e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 id; 489e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 flags; 490e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 tmstmp; 49120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 49220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 49331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 49431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_sg { 495e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 496e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags_size; 497e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 498e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 reserved; 49931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 50020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 50108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord/* 50208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * We keep a local cache of a few frequently accessed port 50308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * registers here, to avoid having to read them (very slow) 50408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * when switching between EDMA and non-EDMA modes. 50508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord */ 50608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstruct mv_cached_regs { 50708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 fiscfg; 50808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 ltmode; 50908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 haltcond; 510c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord u32 unknown_rsvd; 51108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord}; 51208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 51331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_port_priv { 51431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crqb *crqb; 51531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crqb_dma; 51631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crpb *crpb; 51731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crpb_dma; 518eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 519eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 520bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 521bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int req_idx; 522bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int resp_idx; 523bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 52431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 pp_flags; 52508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord struct mv_cached_regs cached; 52629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int delayed_eh_pmp_map; 52731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 52831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 529bca1c4eb9411533d613123618c0d127fae532595Jeff Garzikstruct mv_port_signal { 530bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 amps; 531bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 pre; 532bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik}; 533bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 53402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lordstruct mv_host_priv { 53502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 hp_flags; 53696e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord u32 main_irq_mask; 53702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_port_signal signal[8]; 53802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord const struct mv_hw_ops *ops; 539f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports; 540f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *base; 5417368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_cause_addr; 5427368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_mask_addr; 54302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_cause_ofs; 54402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_mask_ofs; 54502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 unmask_all_irqs; 546da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord /* 547da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * These consistent DMA memory pools give us guaranteed 548da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * alignment for hardware-accessed data structures, 549da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * and less memory waste in accomplishing the alignment. 550da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord */ 551da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crqb_pool; 552da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crpb_pool; 553da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *sg_tbl_pool; 55402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord}; 55502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 55647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstruct mv_hw_ops { 5572a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 5582a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 55947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 56047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 56147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 562c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 563c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 564522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 5657bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 56647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 56747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 56882ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 56982ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 57082ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 57182ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 57231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap); 57331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap); 5743e4a139107e497a741c26f8a377a10f214d63ec1Mark Lordstatic int mv_qc_defer(struct ata_queued_cmd *qc); 57531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc); 576e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc); 5779a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 578a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 579a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo unsigned long deadline); 580bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap); 581bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap); 582f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *dev); 58320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 5842a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5852a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 58647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 58747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 58847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 589c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 590c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 591522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 5927bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 59347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 5942a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5952a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 59647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 59747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 59847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 599c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 600c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 601522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 602f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 603f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 604f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 605f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 606f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 607f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc); 608f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 609f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 610f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 6117bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 612e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 613c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no); 614e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap); 615b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio); 61600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma); 61747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 618e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp); 619e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 620e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 621e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 622e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 62329d187bb1e30682e228ce461c487d78d945c3e4fMark Lordstatic void mv_pmp_error_handler(struct ata_port *ap); 6244c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic void mv_process_crpb_entries(struct ata_port *ap, 6254c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp); 62647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 627da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_sff_irq_clear(struct ata_port *ap); 628da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic int mv_check_atapi_dma(struct ata_queued_cmd *qc); 629da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_setup(struct ata_queued_cmd *qc); 630da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_start(struct ata_queued_cmd *qc); 631da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_stop(struct ata_queued_cmd *qc); 632da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic u8 mv_bmdma_status(struct ata_port *ap); 633d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lordstatic u8 mv_sff_check_status(struct ata_port *ap); 634da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 635eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 636eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * because we have to allow room for worst case splitting of 637eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * PRDs for 64K boundaries in mv_fill_sg(). 638eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 639c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv5_sht = { 64068d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BASE_SHT(DRV_NAME), 641baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 642c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .dma_boundary = MV_DMA_BOUNDARY, 643c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik}; 644c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 645c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv6_sht = { 64668d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_NCQ_SHT(DRV_NAME), 647138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .can_queue = MV_MAX_Q_DEPTH - 1, 648baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 64920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .dma_boundary = MV_DMA_BOUNDARY, 65020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 65120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 652029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv5_ops = { 653029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &ata_sff_port_ops, 654c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 655c96f1732e25362d10ee7bcac1df8412a2e6b7d23Alan Cox .lost_interrupt = ATA_OP_NULL, 656c96f1732e25362d10ee7bcac1df8412a2e6b7d23Alan Cox 6573e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord .qc_defer = mv_qc_defer, 658c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_prep = mv_qc_prep, 659c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_issue = mv_qc_issue, 660c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 661bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .freeze = mv_eh_freeze, 662bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .thaw = mv_eh_thaw, 663a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .hardreset = mv_hardreset, 664a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .error_handler = ata_std_error_handler, /* avoid SFF EH */ 665029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .post_internal_cmd = ATA_OP_NULL, 666bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 667c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_read = mv5_scr_read, 668c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_write = mv5_scr_write, 669c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 670c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_start = mv_port_start, 671c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_stop = mv_port_stop, 672c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik}; 673c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 674029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv6_ops = { 675029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv5_ops, 676f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord .dev_config = mv6_dev_config, 67720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_read = mv_scr_read, 67820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_write = mv_scr_write, 67920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 680e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_hardreset = mv_pmp_hardreset, 681e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_softreset = mv_softreset, 682e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .softreset = mv_softreset, 68329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord .error_handler = mv_pmp_error_handler, 684da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 68540f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord .sff_check_status = mv_sff_check_status, 686da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .sff_irq_clear = mv_sff_irq_clear, 687da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .check_atapi_dma = mv_check_atapi_dma, 688da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_setup = mv_bmdma_setup, 689da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_start = mv_bmdma_start, 690da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_stop = mv_bmdma_stop, 691da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_status = mv_bmdma_status, 69220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 69320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 694029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv_iie_ops = { 695029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv6_ops, 696029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .dev_config = ATA_OP_NULL, 697e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .qc_prep = mv_qc_prep_iie, 698e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 699e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 70098ac62defe529d04a192688f40d801a2d8fbcf98Arjan van de Venstatic const struct ata_port_info mv_port_info[] = { 70120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_504x */ 70291b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_I_FLAGS, 703c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 704bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 705c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 70620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 70720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_508x */ 70891b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 709c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 710bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 711c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 71220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 71347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik { /* chip_5080 */ 71491b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 715c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 716bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 717c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 71847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik }, 71920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_604x */ 72091b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_II_FLAGS, 721c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 722bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 723c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 72420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 72520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_608x */ 72691b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC, 727c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 728bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 729c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 73020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 731e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_6042 */ 73291b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_IIE_FLAGS, 733c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 734bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 735e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 736e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 737e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_7042 */ 73891b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_IIE_FLAGS, 739c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 740bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 741e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 742e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 743f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { /* chip_soc */ 74491b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_IIE_FLAGS, 745c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 74617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .udma_mask = ATA_UDMA6, 74717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .port_ops = &mv_iie_ops, 748f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 74920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 75020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7513b7d697dfb7d03edb87e50b743a7ecff029618e9Jeff Garzikstatic const struct pci_device_id mv_pci_tbl[] = { 7522d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 7532d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 7542d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 7552d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 75646c5784c8fa736c2bb42fe681189b86e99abdc2eMark Lord /* RocketRAID 1720/174x have different identifiers */ 75746c5784c8fa736c2bb42fe681189b86e99abdc2eMark Lord { PCI_VDEVICE(TTI, 0x1720), chip_6042 }, 7584462254ac6be9150aae87d54d388fc348d6fceadMark Lord { PCI_VDEVICE(TTI, 0x1740), chip_6042 }, 7594462254ac6be9150aae87d54d388fc348d6fceadMark Lord { PCI_VDEVICE(TTI, 0x1742), chip_6042 }, 7602d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 7612d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 7622d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 7632d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 7642d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 7652d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 7662d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 7672d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 7682d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 769d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger /* Adaptec 1430SA */ 770d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 771d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger 77202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Marvell 7042 support */ 7736a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 7746a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom 77502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Highpoint RocketRAID PCIe series */ 77602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 77702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 77802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 7792d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { } /* terminate list */ 78020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 78120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 78247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv5xxx_ops = { 78347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv5_phy_errata, 78447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv5_enable_leds, 78547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv5_read_preamp, 78647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv5_reset_hc, 787522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv5_reset_flash, 788522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv5_reset_bus, 78947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 79047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 79147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv6xxx_ops = { 79247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv6_phy_errata, 79347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv6_enable_leds, 79447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv6_read_preamp, 79547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv6_reset_hc, 796522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv6_reset_flash, 797522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv_reset_pci_bus, 79847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 79947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 800f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic const struct mv_hw_ops mv_soc_ops = { 801f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .phy_errata = mv6_phy_errata, 802f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .enable_leds = mv_soc_enable_leds, 803f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .read_preamp = mv_soc_read_preamp, 804f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_hc = mv_soc_reset_hc, 805f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_flash = mv_soc_reset_flash, 806f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_bus = mv_soc_reset_bus, 807f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 808f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 80920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 81020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Functions 81120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 81220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 81320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void writelfl(unsigned long data, void __iomem *addr) 81420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 81520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writel(data, addr); 81620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ (void) readl(addr); /* flush to avoid PCI posted write */ 81720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 81820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 819c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hc_from_port(unsigned int port) 820c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 821c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port >> MV_PORT_HC_SHIFT; 822c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 823c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 824c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hardport_from_port(unsigned int port) 825c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 826c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port & MV_PORT_MASK; 827c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 828c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 8291cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord/* 8301cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Consolidate some rather tricky bit shift calculations. 8311cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * This is hot-path stuff, so not a function. 8321cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Simple code, with two return values, so macro rather than inline. 8331cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 8341cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * port is the sole input, in range 0..7. 8357368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * shift is one output, for use with main_irq_cause / main_irq_mask registers. 8367368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * hardport is the other output, in range 0..3. 8371cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 8381cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Note that port and hardport may be the same variable in some cases. 8391cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord */ 8401cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ 8411cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord{ \ 8421cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift = mv_hc_from_port(port) * HC_SHIFT; \ 8431cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord hardport = mv_hardport_from_port(port); \ 8441cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift += hardport * 2; \ 8451cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord} 8461cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord 847352fab701ca4753dd005b67ce5e512be944eb591Mark Lordstatic inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 848352fab701ca4753dd005b67ce5e512be944eb591Mark Lord{ 849352fab701ca4753dd005b67ce5e512be944eb591Mark Lord return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 850352fab701ca4753dd005b67ce5e512be944eb591Mark Lord} 851352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 852c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline void __iomem *mv_hc_base_from_port(void __iomem *base, 853c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 854c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 855c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base(base, mv_hc_from_port(port)); 856c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 857c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 85820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 85920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 860c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base_from_port(base, port) + 8618b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik MV_SATAHC_ARBTR_REG_SZ + 862c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 86320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 86420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 865e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 866e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord{ 867e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 868e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 869e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 870e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord return hc_mmio + ofs; 871e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord} 872e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 873f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic inline void __iomem *mv_host_base(struct ata_host *host) 874f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 875f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 876f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return hpriv->base; 877f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 878f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 87920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_ap_base(struct ata_port *ap) 88020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 881f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return mv_port_base(mv_host_base(ap->host), ap->port_no); 88220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 88320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 884cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic inline int mv_get_hc_count(unsigned long port_flags) 88531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 886cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 88731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 88831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 88908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord/** 89008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * mv_save_cached_regs - (re-)initialize cached port registers 89108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @ap: the port whose registers we are caching 89208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * 89308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * Initialize the local cache of port registers, 89408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * so that reading them over and over again can 89508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * be avoided on the hotter paths of this driver. 89608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * This saves a few microseconds each time we switch 89708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * to/from EDMA mode to perform (eg.) a drive cache flush. 89808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord */ 89908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstatic void mv_save_cached_regs(struct ata_port *ap) 90008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord{ 90108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 90208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord struct mv_port_priv *pp = ap->private_data; 90308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 90408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord pp->cached.fiscfg = readl(port_mmio + FISCFG_OFS); 90508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord pp->cached.ltmode = readl(port_mmio + LTMODE_OFS); 90608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND_OFS); 907c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD_OFS); 90808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord} 90908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 91008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord/** 91108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * mv_write_cached_reg - write to a cached port register 91208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @addr: hardware address of the register 91308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @old: pointer to cached value of the register 91408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @new: new value for the register 91508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * 91608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * Write a new value to a cached register, 91708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * but only if the value is different from before. 91808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord */ 91908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstatic inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new) 92008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord{ 92108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord if (new != *old) { 92208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord *old = new; 92308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord writel(new, addr); 92408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord } 92508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord} 92608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 927c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic void mv_set_edma_ptrs(void __iomem *port_mmio, 928c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_host_priv *hpriv, 929c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp) 930c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik{ 931bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 index; 932bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 933c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 934c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize request queue 935c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 936fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 937fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 938bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 939c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crqb_dma & 0x3ff); 940c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); 941bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 942c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 9435cf73bfb061552aa18d816d2859409be9ace5306Mark Lord writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 944c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 945c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 946c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize response queue 947c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 948fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 949fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; 950bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 951c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crpb_dma & 0xff); 952c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); 9535cf73bfb061552aa18d816d2859409be9ace5306Mark Lord writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 954bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 955c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 956c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik} 957c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 9582b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv) 9592b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord{ 9602b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 9612b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * When writing to the main_irq_mask in hardware, 9622b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * we must ensure exclusivity between the interrupt coalescing bits 9632b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * and the corresponding individual port DONE_IRQ bits. 9642b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * 9652b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Note that this register is really an "IRQ enable" register, 9662b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * not an "IRQ mask" register as Marvell's naming might suggest. 9672b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 9682b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE)) 9692b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mask &= ~DONE_IRQ_0_3; 9702b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE)) 9712b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mask &= ~DONE_IRQ_4_7; 9722b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord writelfl(mask, hpriv->main_irq_mask_addr); 9732b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord} 9742b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 975c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lordstatic void mv_set_main_irq_mask(struct ata_host *host, 976c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 disable_bits, u32 enable_bits) 977c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord{ 978c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord struct mv_host_priv *hpriv = host->private_data; 979c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 old_mask, new_mask; 980c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 98196e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord old_mask = hpriv->main_irq_mask; 982c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord new_mask = (old_mask & ~disable_bits) | enable_bits; 98396e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord if (new_mask != old_mask) { 98496e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord hpriv->main_irq_mask = new_mask; 9852b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_write_main_irq_mask(new_mask, hpriv); 98696e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord } 987c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord} 988c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 989c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lordstatic void mv_enable_port_irqs(struct ata_port *ap, 990c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int port_bits) 991c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord{ 992c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int shift, hardport, port = ap->port_no; 993c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 disable_bits, enable_bits; 994c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 995c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 996c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 997c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord disable_bits = (DONE_IRQ | ERR_IRQ) << shift; 998c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord enable_bits = port_bits << shift; 999c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); 1000c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord} 1001c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 100200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_clear_and_enable_port_irqs(struct ata_port *ap, 100300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord void __iomem *port_mmio, 100400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord unsigned int port_irqs) 100500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord{ 100600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 100700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord int hardport = mv_hardport_from_port(ap->port_no); 100800b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port( 100900b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_host_base(ap->host), ap->port_no); 101000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord u32 hc_irq_cause; 101100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 101200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord /* clear EDMA event indicators, if any */ 101300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 101400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 101500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord /* clear pending irq events */ 101600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 101700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 101800b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 101900b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord /* clear FIS IRQ Cause */ 102000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord if (IS_GEN_IIE(hpriv)) 102100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 102200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 102300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_enable_port_irqs(ap, port_irqs); 102400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord} 102500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 10262b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic void mv_set_irq_coalescing(struct ata_host *host, 10272b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord unsigned int count, unsigned int usecs) 10282b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord{ 10292b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord struct mv_host_priv *hpriv = host->private_data; 10302b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord void __iomem *mmio = hpriv->base, *hc_mmio; 10312b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord u32 coal_enable = 0; 10322b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord unsigned long flags; 10336abf4678261218938ccdac90767d34ce9937634fMark Lord unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC; 10342b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 10352b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord ALL_PORTS_COAL_DONE; 10362b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 10372b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* Disable IRQ coalescing if either threshold is zero */ 10382b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (!usecs || !count) { 10392b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord clks = count = 0; 10402b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } else { 10412b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* Respect maximum limits of the hardware */ 10422b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord clks = usecs * COAL_CLOCKS_PER_USEC; 10432b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (clks > MAX_COAL_TIME_THRESHOLD) 10442b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord clks = MAX_COAL_TIME_THRESHOLD; 10452b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (count > MAX_COAL_IO_COUNT) 10462b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord count = MAX_COAL_IO_COUNT; 10472b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } 10482b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 10492b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord spin_lock_irqsave(&host->lock, flags); 10506abf4678261218938ccdac90767d34ce9937634fMark Lord mv_set_main_irq_mask(host, coal_disable, 0); 10512b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 10526abf4678261218938ccdac90767d34ce9937634fMark Lord if (is_dual_hc && !IS_GEN_I(hpriv)) { 10532b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 10546abf4678261218938ccdac90767d34ce9937634fMark Lord * GEN_II/GEN_IIE with dual host controllers: 10556abf4678261218938ccdac90767d34ce9937634fMark Lord * one set of global thresholds for the entire chip. 10562b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 10572b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord writel(clks, mmio + MV_IRQ_COAL_TIME_THRESHOLD); 10582b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord writel(count, mmio + MV_IRQ_COAL_IO_THRESHOLD); 10592b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* clear leftover coal IRQ bit */ 10606abf4678261218938ccdac90767d34ce9937634fMark Lord writel(~ALL_PORTS_COAL_IRQ, mmio + MV_IRQ_COAL_CAUSE); 10616abf4678261218938ccdac90767d34ce9937634fMark Lord if (count) 10626abf4678261218938ccdac90767d34ce9937634fMark Lord coal_enable = ALL_PORTS_COAL_DONE; 10636abf4678261218938ccdac90767d34ce9937634fMark Lord clks = count = 0; /* force clearing of regular regs below */ 10642b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } 10656abf4678261218938ccdac90767d34ce9937634fMark Lord 10662b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 10672b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * All chips: independent thresholds for each HC on the chip. 10682b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 10692b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord hc_mmio = mv_hc_base_from_port(mmio, 0); 10702b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD_OFS); 10712b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD_OFS); 10726abf4678261218938ccdac90767d34ce9937634fMark Lord writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE_OFS); 10736abf4678261218938ccdac90767d34ce9937634fMark Lord if (count) 10746abf4678261218938ccdac90767d34ce9937634fMark Lord coal_enable |= PORTS_0_3_COAL_DONE; 10756abf4678261218938ccdac90767d34ce9937634fMark Lord if (is_dual_hc) { 10762b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC); 10772b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD_OFS); 10782b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD_OFS); 10796abf4678261218938ccdac90767d34ce9937634fMark Lord writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE_OFS); 10806abf4678261218938ccdac90767d34ce9937634fMark Lord if (count) 10816abf4678261218938ccdac90767d34ce9937634fMark Lord coal_enable |= PORTS_4_7_COAL_DONE; 10822b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } 10832b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 10846abf4678261218938ccdac90767d34ce9937634fMark Lord mv_set_main_irq_mask(host, 0, coal_enable); 10852b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord spin_unlock_irqrestore(&host->lock, flags); 10862b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord} 10872b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 108805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 108900b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord * mv_start_edma - Enable eDMA engine 109005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @base: port base address 109105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pp: port private data 109205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 1093beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * Verify the local cache of the eDMA state is accurate with a 1094beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * WARN_ON. 109505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 109605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 109705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 109805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 109900b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio, 1100721091685f853ba4e6c49f26f989db0b1a811250Mark Lord struct mv_port_priv *pp, u8 protocol) 110120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1102721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int want_ncq = (protocol == ATA_PROT_NCQ); 1103721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1104721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 1105721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 1106721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq != using_ncq) 1107b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 1108721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } 1109c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 11100c58912e192fc3a4835d772aafa40b72552b819fMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 11110c58912e192fc3a4835d772aafa40b72552b819fMark Lord 111200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_edma_cfg(ap, want_ncq, 1); 11130c58912e192fc3a4835d772aafa40b72552b819fMark Lord 1114f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord mv_set_edma_ptrs(port_mmio, hpriv, pp); 111500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ); 1116bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1117f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS); 1118afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 1119afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 112020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 112120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 11229b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lordstatic void mv_wait_for_edma_empty_idle(struct ata_port *ap) 11239b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord{ 11249b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 11259b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE); 11269b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const int per_loop = 5, timeout = (15 * 1000 / per_loop); 11279b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord int i; 11289b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 11299b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord /* 11309b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord * Wait for the EDMA engine to finish transactions in progress. 1131c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * No idea what a good "timeout" value might be, but measurements 1132c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * indicate that it often requires hundreds of microseconds 1133c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * with two drives in-use. So we use the 15msec value above 1134c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * as a rough guess at what even more drives might require. 11359b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord */ 11369b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord for (i = 0; i < timeout; ++i) { 11379b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS); 11389b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord if ((edma_stat & empty_idle) == empty_idle) 11399b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord break; 11409b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord udelay(per_loop); 11419b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord } 11429b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */ 11439b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord} 11449b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 114505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1146e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * mv_stop_edma_engine - Disable eDMA engine 1147b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * @port_mmio: io base address 114805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 114905b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 115005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 115105b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 1152b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio) 115320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1154b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord int i; 115531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1156b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Disable eDMA. The disable bit auto clears. */ 1157b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); 11588b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 1159b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Wait for the chip to confirm eDMA is off. */ 1160b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord for (i = 10000; i > 0; i--) { 1161b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord u32 reg = readl(port_mmio + EDMA_CMD_OFS); 11624537deb5e90b717a725b3d74b58b4bb1d28443d0Jeff Garzik if (!(reg & EDMA_EN)) 1163b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 1164b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord udelay(10); 116531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 1166b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 116720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 116820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1169e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap) 11700ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik{ 1171b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord void __iomem *port_mmio = mv_ap_base(ap); 1172b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 117366e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord int err = 0; 11740ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 1175b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 1176b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 1177b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 11789b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord mv_wait_for_edma_empty_idle(ap); 1179b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (mv_stop_edma_engine(port_mmio)) { 1180b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); 118166e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord err = -EIO; 1182b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord } 118366e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord mv_edma_cfg(ap, 0, 0); 118466e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord return err; 11850ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik} 11860ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 11878a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#ifdef ATA_DEBUG 118831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_mem(void __iomem *start, unsigned bytes) 118920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 119031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 119131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 119231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%p: ", start + b); 119331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 11942dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", readl(start + b)); 119531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 119631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 119731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 119831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 119931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 12008a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#endif 12018a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik 120231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 120331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 120431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 120531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 120631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 dw; 120731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 120831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%02x: ", b); 120931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 12102dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik (void) pci_read_config_dword(pdev, b, &dw); 12112dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", dw); 121231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 121331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 121431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 121531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 121631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 121731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 121831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_all_regs(void __iomem *mmio_base, int port, 121931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct pci_dev *pdev) 122031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 122131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 12228b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik void __iomem *hc_base = mv_hc_base(mmio_base, 122331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port >> MV_PORT_HC_SHIFT); 122431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_base; 122531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int start_port, num_ports, p, start_hc, num_hcs, hc; 122631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 122731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (0 > port) { 122831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = start_port = 0; 122931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = 8; /* shld be benign for 4 port devs */ 123031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_hcs = 2; 123131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } else { 123231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = port >> MV_PORT_HC_SHIFT; 123331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_port = port; 123431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = num_hcs = 1; 123531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 12368b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik DPRINTK("All registers for port(s) %u-%u:\n", start_port, 123731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports > 1 ? num_ports - 1 : start_port); 123831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 123931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (NULL != pdev) { 124031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI config space regs:\n"); 124131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 124231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 124331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI regs:\n"); 124431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xc00, 0x3c); 124531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xd00, 0x34); 124631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xf00, 0x4); 124731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0x1d00, 0x6c); 124831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 1249d220c37e0a3c9a47ae00e87e044d963b3ea040bcDan Aloni hc_base = mv_hc_base(mmio_base, hc); 125031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("HC regs (HC %i):\n", hc); 125131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(hc_base, 0x1c); 125231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 125331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (p = start_port; p < start_port + num_ports; p++) { 125431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port_base = mv_port_base(mmio_base, p); 12552dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("EDMA regs (port %i):\n", p); 125631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base, 0x54); 12572dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("SATA regs (port %i):\n", p); 125831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base+0x300, 0x60); 125931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 126031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 126120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 126220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 126320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic unsigned int mv_scr_offset(unsigned int sc_reg_in) 126420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 126520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs; 126620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 126720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ switch (sc_reg_in) { 126820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_STATUS: 126920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_CONTROL: 127020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ERROR: 127120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); 127220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 127320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ACTIVE: 127420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_ACTIVE_OFS; /* active is not with the others */ 127520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 127620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ default: 127720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = 0xffffffffU; 127820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 127920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 128020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return ofs; 128120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 128220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 128382ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 128420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 128520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 128620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1287da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 128882ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo *val = readl(mv_ap_base(link->ap) + ofs); 1289da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1290da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1291da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 129220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 129320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 129482ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 129520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 129620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 129720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1298da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 12992009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord void __iomem *addr = mv_ap_base(link->ap) + ofs; 13002009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord if (sc_reg_in == SCR_CONTROL) { 13012009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord /* 13022009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * Workaround for 88SX60x1 FEr SATA#26: 13032009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * 13042009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * COMRESETs have to take care not to accidently 13052009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * put the drive to sleep when writing SCR_CONTROL. 13062009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * Setting bits 12..15 prevents this problem. 13072009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * 13082009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * So if we see an outbound COMMRESET, set those bits. 13092009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * Ditto for the followup write that clears the reset. 13102009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * 13112009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * The proprietary driver does this for 13122009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * all chip versions, and so do we. 13132009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord */ 13142009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1) 13152009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord val |= 0xf000; 13162009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord } 13172009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord writelfl(val, addr); 1318da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1319da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1320da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 132120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 132220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1323f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *adev) 1324f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord{ 1325f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord /* 1326e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Deal with Gen-II ("mv6") hardware quirks/restrictions: 1327e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * 1328e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Gen-II does not support NCQ over a port multiplier 1329e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * (no FIS-based switching). 1330f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord */ 1331e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (adev->flags & ATA_DFLAG_NCQ) { 1332352fab701ca4753dd005b67ce5e512be944eb591Mark Lord if (sata_pmp_attached(adev->link->ap)) { 1333e49856d82a887ce365637176f9f99ab68076eae8Mark Lord adev->flags &= ~ATA_DFLAG_NCQ; 1334352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ata_dev_printk(adev, KERN_INFO, 1335352fab701ca4753dd005b67ce5e512be944eb591Mark Lord "NCQ disabled for command-based switching\n"); 1336352fab701ca4753dd005b67ce5e512be944eb591Mark Lord } 1337e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 1338f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1339f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 13403e4a139107e497a741c26f8a377a10f214d63ec1Mark Lordstatic int mv_qc_defer(struct ata_queued_cmd *qc) 13413e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord{ 13423e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct ata_link *link = qc->dev->link; 13433e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct ata_port *ap = link->ap; 13443e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct mv_port_priv *pp = ap->private_data; 13453e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 13463e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord /* 134729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * Don't allow new commands if we're in a delayed EH state 134829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * for NCQ and/or FIS-based switching. 134929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord */ 135029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 135129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord return ATA_DEFER_PORT; 135229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord /* 13533e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * If the port is completely idle, then allow the new qc. 13543e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord */ 13553e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (ap->nr_active_links == 0) 13563e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return 0; 13573e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 13584bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo /* 13594bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * The port is operating in host queuing mode (EDMA) with NCQ 13604bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * enabled, allow multiple NCQ commands. EDMA also allows 13614bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * queueing multiple DMA commands but libata core currently 13624bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * doesn't allow it. 13634bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo */ 13644bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) && 13654bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol)) 13664bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo return 0; 13674bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo 13683e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return ATA_DEFER_PORT; 13693e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord} 13703e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 137108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstatic void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs) 1372e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 137308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord struct mv_port_priv *pp = ap->private_data; 137408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord void __iomem *port_mmio; 137500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 137608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg; 137708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 ltmode, *old_ltmode = &pp->cached.ltmode; 137808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 haltcond, *old_haltcond = &pp->cached.haltcond; 137900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 138008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord ltmode = *old_ltmode & ~LTMODE_BIT8; 138108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord haltcond = *old_haltcond | EDMA_ERR_DEV; 138200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 138300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (want_fbs) { 138408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC; 138508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord ltmode = *old_ltmode | LTMODE_BIT8; 13864c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (want_ncq) 138708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord haltcond &= ~EDMA_ERR_DEV; 13884c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord else 138908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord fiscfg |= FISCFG_WAIT_DEV_ERR; 139008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord } else { 139108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR); 1392e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 139300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 139408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord port_mmio = mv_ap_base(ap); 139508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_write_cached_reg(port_mmio + FISCFG_OFS, old_fiscfg, fiscfg); 139608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_write_cached_reg(port_mmio + LTMODE_OFS, old_ltmode, ltmode); 139708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_write_cached_reg(port_mmio + EDMA_HALTCOND_OFS, old_haltcond, haltcond); 1398f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1399f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 1400dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lordstatic void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq) 1401dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord{ 1402dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1403dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord u32 old, new; 1404dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord 1405dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord /* workaround for 88SX60x1 FEr SATA#25 (part 1) */ 1406dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS); 1407dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord if (want_ncq) 1408dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord new = old | (1 << 22); 1409dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord else 1410dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord new = old & ~(1 << 22); 1411dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord if (new != old) 1412dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS); 1413dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord} 1414dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord 1415c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord/** 141640f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma 141740f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * @ap: Port being initialized 1418c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * 1419c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * There are two DMA modes on these chips: basic DMA, and EDMA. 1420c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * 1421c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * Bit-0 of the "EDMA RESERVED" register enables/disables use 1422c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * of basic DMA on the GEN_IIE versions of the chips. 1423c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * 1424c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * This bit survives EDMA resets, and must be set for basic DMA 1425c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * to function, and should be cleared when EDMA is active. 1426c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord */ 1427c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lordstatic void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma) 1428c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord{ 1429c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord struct mv_port_priv *pp = ap->private_data; 1430c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord u32 new, *old = &pp->cached.unknown_rsvd; 1431c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord 1432c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord if (enable_bmdma) 1433c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord new = *old | 1; 1434c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord else 1435c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord new = *old & ~1; 1436c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD_OFS, old, new); 1437c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord} 1438c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord 1439000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord/* 1440000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * SOC chips have an issue whereby the HDD LEDs don't always blink 1441000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * during I/O when NCQ is enabled. Enabling a special "LED blink" mode 1442000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * of the SOC takes care of it, generating a steady blink rate when 1443000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * any drive on the chip is active. 1444000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * 1445000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * Unfortunately, the blink mode is a global hardware setting for the SOC, 1446000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * so we must use it whenever at least one port on the SOC has NCQ enabled. 1447000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * 1448000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * We turn "LED blink" off when NCQ is not in use anywhere, because the normal 1449000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * LED operation works then, and provides better (more accurate) feedback. 1450000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * 1451000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * Note that this code assumes that an SOC never has more than one HC onboard. 1452000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord */ 1453000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lordstatic void mv_soc_led_blink_enable(struct ata_port *ap) 1454000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord{ 1455000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct ata_host *host = ap->host; 1456000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct mv_host_priv *hpriv = host->private_data; 1457000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord void __iomem *hc_mmio; 1458000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord u32 led_ctrl; 1459000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1460000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN) 1461000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord return; 1462000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN; 1463000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); 1464000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord led_ctrl = readl(hc_mmio + SOC_LED_CTRL_OFS); 1465000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL_OFS); 1466000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord} 1467000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1468000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lordstatic void mv_soc_led_blink_disable(struct ata_port *ap) 1469000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord{ 1470000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct ata_host *host = ap->host; 1471000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct mv_host_priv *hpriv = host->private_data; 1472000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord void __iomem *hc_mmio; 1473000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord u32 led_ctrl; 1474000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord unsigned int port; 1475000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1476000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)) 1477000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord return; 1478000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1479000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord /* disable led-blink only if no ports are using NCQ */ 1480000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord for (port = 0; port < hpriv->n_ports; port++) { 1481000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct ata_port *this_ap = host->ports[port]; 1482000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct mv_port_priv *pp = this_ap->private_data; 1483000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1484000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 1485000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord return; 1486000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord } 1487000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1488000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN; 1489000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); 1490000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord led_ctrl = readl(hc_mmio + SOC_LED_CTRL_OFS); 1491000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL_OFS); 1492000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord} 1493000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 149400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma) 1495e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 14960c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 cfg; 1497e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_port_priv *pp = ap->private_data; 1498e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1499e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1500e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1501e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* set up non-NCQ EDMA configuration */ 15020c58912e192fc3a4835d772aafa40b72552b819fMark Lord cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 1503d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= 1504d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 1505e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 15060c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (IS_GEN_I(hpriv)) 1507e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 8); /* enab config burst size mask */ 1508e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1509dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord else if (IS_GEN_II(hpriv)) { 1510e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1511dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord mv_60x1_errata_sata25(ap, want_ncq); 1512e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1513dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord } else if (IS_GEN_IIE(hpriv)) { 151400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord int want_fbs = sata_pmp_attached(ap); 151500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord /* 151600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * Possible future enhancement: 151700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * 151800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * The chip can use FBS with non-NCQ, if we allow it, 151900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * But first we need to have the error handling in place 152000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * for this mode (datasheet section 7.3.15.4.2.3). 152100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * So disallow non-NCQ FBS for now. 152200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord */ 152300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord want_fbs &= want_ncq; 152400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 152508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_config_fbs(ap, want_ncq, want_fbs); 152600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 152700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (want_fbs) { 152800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord pp->pp_flags |= MV_PP_FLAG_FBS_EN; 152900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ 153000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord } 153100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 1532e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 153300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord if (want_edma) { 153400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord cfg |= (1 << 22); /* enab 4-entry host queue cache */ 153500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord if (!IS_SOC(hpriv)) 153600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord cfg |= (1 << 18); /* enab early completion */ 153700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord } 1538616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (hpriv->hp_flags & MV_HP_CUT_THROUGH) 1539616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ 1540c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord mv_bmdma_enable_iie(ap, !want_edma); 1541000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1542000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (IS_SOC(hpriv)) { 1543000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (want_ncq) 1544000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord mv_soc_led_blink_enable(ap); 1545000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord else 1546000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord mv_soc_led_blink_disable(ap); 1547000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord } 1548e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 1549e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1550721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq) { 1551721091685f853ba4e6c49f26f989db0b1a811250Mark Lord cfg |= EDMA_CFG_NCQ; 1552721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 155300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord } 1554721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1555e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik writelfl(cfg, port_mmio + EDMA_CFG_OFS); 1556e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1557e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1558da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordstatic void mv_port_free_dma_mem(struct ata_port *ap) 1559da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord{ 1560da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1561da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_port_priv *pp = ap->private_data; 1562eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord int tag; 1563da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1564da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crqb) { 1565da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1566da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = NULL; 1567da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1568da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crpb) { 1569da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1570da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = NULL; 1571da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1572eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1573eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1574eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we have one unique sg_tbl per NCQ tag. 1575eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1576eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1577eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (pp->sg_tbl[tag]) { 1578eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) 1579eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_pool_free(hpriv->sg_tbl_pool, 1580eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag], 1581eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag]); 1582eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = NULL; 1583eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1584da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1585da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord} 1586da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 158705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 158805b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_start - Port specific init/start routine. 158905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 159005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 159105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Allocate and point to DMA memory, init port private memory, 159205b308e1df6d9d673daedb517969241f41278b52Brett Russ * zero indices. 159305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 159405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 159505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 159605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 159731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap) 159831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1599cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct device *dev = ap->host->dev; 1600cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 160131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp; 1602933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord unsigned long flags; 1603dde2020754aeb14e17052d61784dcb37f252aac2James Bottomley int tag; 160431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 160524dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 16066037d6bbdff65eb5a84fe35e140f4da4f7cc103aJeff Garzik if (!pp) 160724dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return -ENOMEM; 1608da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord ap->private_data = pp; 160931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1610da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1611da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crqb) 1612da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 1613da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crqb, 0, MV_CRQB_Q_SZ); 161431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1615da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1616da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crpb) 1617da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord goto out_port_free_dma_mem; 1618da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crpb, 0, MV_CRPB_Q_SZ); 161931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 16203bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */ 16213bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) 16223bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord ap->flags |= ATA_FLAG_AN; 1623eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1624eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1625eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we need one unique sg_tbl per NCQ tag. 1626eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1627eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1628eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) { 1629eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1630eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1631eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (!pp->sg_tbl[tag]) 1632eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord goto out_port_free_dma_mem; 1633eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } else { 1634eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = pp->sg_tbl[0]; 1635eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1636eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1637eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1638933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord 1639933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_lock_irqsave(ap->lock, flags); 164008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_save_cached_regs(ap); 164166e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord mv_edma_cfg(ap, 0, 0); 1642933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_unlock_irqrestore(ap->lock, flags); 1643933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord 164431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 1645da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1646da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordout_port_free_dma_mem: 1647da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 1648da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 164931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 165031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 165105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 165205b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_stop - Port specific cleanup/stop routine. 165305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 165405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 165505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Stop DMA, cleanup port memory. 165605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 165705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 1658cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine uses the host lock to protect the DMA stop. 165905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 166031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap) 166131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1662933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord unsigned long flags; 1663933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord 1664933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_lock_irqsave(ap->lock, flags); 1665e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma(ap); 166688e675e193159b9891c1c576de4348eaf490f5d0Mark Lord mv_enable_port_irqs(ap, 0); 1667933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_unlock_irqrestore(ap->lock, flags); 1668da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 166931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 167031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 167105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 167205b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 167305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command whose SG list to source from 167405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 167505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Populate the SG list and mark the last entry. 167605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 167705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 167805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 167905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 16806c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzikstatic void mv_fill_sg(struct ata_queued_cmd *qc) 168131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 168231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = qc->ap->private_data; 1683972c26bdd6b58e7534473c4f7928584578cf43f4Jeff Garzik struct scatterlist *sg; 16843be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik struct mv_sg *mv_sg, *last_sg = NULL; 1685ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo unsigned int si; 168631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1687eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord mv_sg = pp->sg_tbl[qc->tag]; 1688ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 1689d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik dma_addr_t addr = sg_dma_address(sg); 1690d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik u32 sg_len = sg_dma_len(sg); 169122374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 16924007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson while (sg_len) { 16934007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 offset = addr & 0xffff; 16944007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 len = sg_len; 169522374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 169632cd11a61007511ddb38783deec8bb1aa6735789Mark Lord if (offset + len > 0x10000) 16974007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson len = 0x10000 - offset; 16984007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 16994007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 17004007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 17016c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik mv_sg->flags_size = cpu_to_le32(len & 0xffff); 170232cd11a61007511ddb38783deec8bb1aa6735789Mark Lord mv_sg->reserved = 0; 17034007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 17044007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson sg_len -= len; 17054007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson addr += len; 17064007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 17073be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg = mv_sg; 17084007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg++; 17094007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson } 171031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 17113be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik 17123be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik if (likely(last_sg)) 17133be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 171432cd11a61007511ddb38783deec8bb1aa6735789Mark Lord mb(); /* ensure data structure is visible to the chipset */ 171531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 171631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 17175796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzikstatic void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 171831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1719559eedad7f7764dacca33980127b4615011230e4Mark Lord u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 172031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ (last ? CRQB_CMD_LAST : 0); 1721559eedad7f7764dacca33980127b4615011230e4Mark Lord *cmdw = cpu_to_le16(tmp); 172231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 172331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 172405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1725da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_sff_irq_clear - Clear hardware interrupt after DMA. 1726da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @ap: Port associated with this ATA transaction. 1727da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1728da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * We need this only for ATAPI bmdma transactions, 1729da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * as otherwise we experience spurious interrupts 1730da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * after libata-sff handles the bmdma interrupts. 1731da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1732da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_sff_irq_clear(struct ata_port *ap) 1733da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1734da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ); 1735da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1736da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1737da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1738da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA. 1739da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to check for chipset/DMA compatibility. 1740da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1741da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * The bmdma engines cannot handle speculative data sizes 1742da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * (bytecount under/over flow). So only allow DMA for 1743da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * data transfer commands with known data sizes. 1744da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1745da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1746da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1747da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1748da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic int mv_check_atapi_dma(struct ata_queued_cmd *qc) 1749da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1750da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct scsi_cmnd *scmd = qc->scsicmd; 1751da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1752da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord if (scmd) { 1753da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord switch (scmd->cmnd[0]) { 1754da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case READ_6: 1755da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case READ_10: 1756da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case READ_12: 1757da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case WRITE_6: 1758da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case WRITE_10: 1759da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case WRITE_12: 1760da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case GPCMD_READ_CD: 1761da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case GPCMD_SEND_DVD_STRUCTURE: 1762da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case GPCMD_SEND_CUE_SHEET: 1763da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord return 0; /* DMA is safe */ 1764da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord } 1765da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord } 1766da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord return -EOPNOTSUPP; /* use PIO instead */ 1767da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1768da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1769da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1770da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_setup - Set up BMDMA transaction 1771da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to prepare DMA for. 1772da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1773da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1774da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1775da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1776da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_setup(struct ata_queued_cmd *qc) 1777da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1778da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct ata_port *ap = qc->ap; 1779da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1780da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct mv_port_priv *pp = ap->private_data; 1781da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1782da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord mv_fill_sg(qc); 1783da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1784da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* clear all DMA cmd bits */ 1785da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord writel(0, port_mmio + BMDMA_CMD_OFS); 1786da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1787da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* load PRD table addr. */ 1788da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16, 1789da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord port_mmio + BMDMA_PRD_HIGH_OFS); 1790da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord writelfl(pp->sg_tbl_dma[qc->tag], 1791da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord port_mmio + BMDMA_PRD_LOW_OFS); 1792da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1793da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* issue r/w command */ 1794da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord ap->ops->sff_exec_command(ap, &qc->tf); 1795da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1796da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1797da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1798da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_start - Start a BMDMA transaction 1799da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to start DMA on. 1800da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1801da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1802da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1803da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1804da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_start(struct ata_queued_cmd *qc) 1805da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1806da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct ata_port *ap = qc->ap; 1807da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1808da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 1809da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START; 1810da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1811da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* start host DMA transaction */ 1812da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord writelfl(cmd, port_mmio + BMDMA_CMD_OFS); 1813da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1814da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1815da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1816da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_stop - Stop BMDMA transfer 1817da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to stop DMA on. 1818da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1819da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Clears the ATA_DMA_START flag in the bmdma control register 1820da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1821da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1822da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1823da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1824da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_stop(struct ata_queued_cmd *qc) 1825da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1826da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct ata_port *ap = qc->ap; 1827da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1828da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord u32 cmd; 1829da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1830da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* clear start/stop bit */ 1831da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord cmd = readl(port_mmio + BMDMA_CMD_OFS); 1832da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord cmd &= ~ATA_DMA_START; 1833da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord writelfl(cmd, port_mmio + BMDMA_CMD_OFS); 1834da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1835da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 1836da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord ata_sff_dma_pause(ap); 1837da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1838da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1839da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1840da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_status - Read BMDMA status 1841da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @ap: port for which to retrieve DMA status. 1842da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1843da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Read and return equivalent of the sff BMDMA status register. 1844da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1845da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1846da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1847da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1848da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic u8 mv_bmdma_status(struct ata_port *ap) 1849da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1850da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1851da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord u32 reg, status; 1852da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1853da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* 1854da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Other bits are valid only if ATA_DMA_ACTIVE==0, 1855da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * and the ATA_DMA_INTR bit doesn't exist. 1856da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1857da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord reg = readl(port_mmio + BMDMA_STATUS_OFS); 1858da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord if (reg & ATA_DMA_ACTIVE) 1859da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord status = ATA_DMA_ACTIVE; 1860da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord else 1861da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR; 1862da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord return status; 1863da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1864da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1865da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 186605b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_prep - Host specific command preparation. 186705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to prepare 186805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 186905b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 187005b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it handles prep of the CRQB 187105b308e1df6d9d673daedb517969241f41278b52Brett Russ * (command request block), does some sanity checking, and calls 187205b308e1df6d9d673daedb517969241f41278b52Brett Russ * the SG load routine. 187305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 187405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 187505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 187605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 187731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc) 187831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 187931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_port *ap = qc->ap; 188031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = ap->private_data; 1881e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 *cw; 188231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_taskfile *tf; 188331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u16 flags = 0; 1884a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 188531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1886138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1887138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 188831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 188920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 189031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Fill in command request block 189131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1892e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 189331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= CRQB_FLAG_READ; 1894beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 189531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= qc->tag << CRQB_TAG_SHIFT; 1896e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 189731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1898bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1899fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 1900a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1901a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr = 1902eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1903a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr_hi = 1904eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1905a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 190631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1907a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord cw = &pp->crqb[in_index].ata_cmd[0]; 190831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ tf = &qc->tf; 190931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 191031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Sadly, the CRQB cannot accomodate all registers--there are 191131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * only 11 bytes...so we must pick and choose required 191231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * registers based on the command. So, we drop feature and 191331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * hob_feature for [RW] DMA commands, but they are needed for 1914cd12e1f7a2c28917c89d65c0d4a52d3919b4c125Mark Lord * NCQ. NCQ will drop hob_nsect, which is not needed there 1915cd12e1f7a2c28917c89d65c0d4a52d3919b4c125Mark Lord * (nsect is used only for the tag; feat/hob_feat hold true nsect). 191620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 191731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ switch (tf->command) { 191831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ: 191931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ_EXT: 192031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE: 192131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE_EXT: 1922c15d85c8f3f73b5f20aae7928e25b6996f16b328Jens Axboe case ATA_CMD_WRITE_FUA_EXT: 192331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 192431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 192531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_READ: 192631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_WRITE: 19278b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 192831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 192931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 193031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ default: 193131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* The only other commands EDMA supports in non-queued and 193231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 193331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * of which are defined/used by Linux. If we get here, this 193431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * driver needs work. 193531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * 193631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * FIXME: modify libata to give qc_prep a return value and 193731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * return error here. 193831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 193931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ BUG_ON(tf->command); 194031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 194131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 194231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 194331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 194431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 194531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 194631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 194731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 194831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 194931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 195031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 195131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1952e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 1953e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1954e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik mv_fill_sg(qc); 1955e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1956e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1957e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik/** 1958e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * mv_qc_prep_iie - Host specific command preparation. 1959e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * @qc: queued command to prepare 1960e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1961e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * This routine simply redirects to the general purpose routine 1962e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * if command is not DMA. Else, it handles prep of the CRQB 1963e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * (command request block), does some sanity checking, and calls 1964e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * the SG load routine. 1965e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1966e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * LOCKING: 1967e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * Inherited from caller. 1968e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik */ 1969e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc) 1970e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 1971e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_port *ap = qc->ap; 1972e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_port_priv *pp = ap->private_data; 1973e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_crqb_iie *crqb; 1974e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_taskfile *tf; 1975a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 1976e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik u32 flags = 0; 1977e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1978138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1979138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 1980e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1981e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1982e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* Fill in Gen IIE command request block */ 1983e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 1984e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= CRQB_FLAG_READ; 1985e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1986beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 1987e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= qc->tag << CRQB_TAG_SHIFT; 19888c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord flags |= qc->tag << CRQB_HOSTQ_SHIFT; 1989e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 1990e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1991bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1992fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 1993a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1994a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 1995eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1996eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1997e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->flags = cpu_to_le32(flags); 1998e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1999e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik tf = &qc->tf; 2000e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[0] = cpu_to_le32( 2001e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->command << 16) | 2002e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->feature << 24) 2003e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2004e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[1] = cpu_to_le32( 2005e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbal << 0) | 2006e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbam << 8) | 2007e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbah << 16) | 2008e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->device << 24) 2009e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2010e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[2] = cpu_to_le32( 2011e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbal << 0) | 2012e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbam << 8) | 2013e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbah << 16) | 2014e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_feature << 24) 2015e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2016e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[3] = cpu_to_le32( 2017e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->nsect << 0) | 2018e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_nsect << 8) 2019e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2020e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2021e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 202231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 202331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_fill_sg(qc); 202431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 202531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 202605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2027d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * mv_sff_check_status - fetch device status, if valid 2028d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * @ap: ATA port to fetch status from 2029d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * 2030d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * When using command issue via mv_qc_issue_fis(), 2031d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * the initial ATA_BUSY state does not show up in the 2032d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * ATA status (shadow) register. This can confuse libata! 2033d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * 2034d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * So we have a hook here to fake ATA_BUSY for that situation, 2035d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * until the first time a BUSY, DRQ, or ERR bit is seen. 2036d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * 2037d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * The rest of the time, it simply returns the ATA status register. 2038d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord */ 2039d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lordstatic u8 mv_sff_check_status(struct ata_port *ap) 2040d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord{ 2041d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord u8 stat = ioread8(ap->ioaddr.status_addr); 2042d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord struct mv_port_priv *pp = ap->private_data; 2043d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord 2044d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) { 2045d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) 2046d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; 2047d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord else 2048d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord stat = ATA_BUSY; 2049d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord } 2050d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord return stat; 2051d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord} 2052d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord 2053d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord/** 205470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register 205570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * @fis: fis to be sent 205670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * @nwords: number of 32-bit words in the fis 205770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 205870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lordstatic unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords) 205970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord{ 206070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 206170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord u32 ifctl, old_ifctl, ifstat; 206270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord int i, timeout = 200, final_word = nwords - 1; 206370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 206470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Initiate FIS transmission mode */ 206570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord old_ifctl = readl(port_mmio + SATA_IFCTL_OFS); 206670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ifctl = 0x100 | (old_ifctl & 0xf); 206770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord writelfl(ifctl, port_mmio + SATA_IFCTL_OFS); 206870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 206970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Send all words of the FIS except for the final word */ 207070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord for (i = 0; i < final_word; ++i) 207170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS_OFS); 207270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 207370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Flag end-of-transmission, and then send the final word */ 207470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL_OFS); 207570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS_OFS); 207670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 207770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* 207870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Wait for FIS transmission to complete. 207970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * This typically takes just a single iteration. 208070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 208170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord do { 208270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ifstat = readl(port_mmio + SATA_IFSTAT_OFS); 208370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } while (!(ifstat & 0x1000) && --timeout); 208470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 208570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Restore original port configuration */ 208670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord writelfl(old_ifctl, port_mmio + SATA_IFCTL_OFS); 208770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 208870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* See if it worked */ 208970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if ((ifstat & 0x3000) != 0x1000) { 209070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ata_port_printk(ap, KERN_WARNING, 209170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord "%s transmission error, ifstat=%08x\n", 209270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord __func__, ifstat); 209370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return AC_ERR_OTHER; 209470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } 209570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return 0; 209670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord} 209770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 209870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord/** 209970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * mv_qc_issue_fis - Issue a command directly as a FIS 210070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * @qc: queued command to start 210170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 210270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Note that the ATA shadow registers are not updated 210370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * after command issue, so the device will appear "READY" 210470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * if polled, even while it is BUSY processing the command. 210570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 210670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * So we use a status hook to fake ATA_BUSY until the drive changes state. 210770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 210870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Note: we don't get updated shadow regs on *completion* 210970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * of non-data commands. So avoid sending them via this function, 211070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * as they will appear to have completed immediately. 211170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 211270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * GEN_IIE has special registers that we could get the result tf from, 211370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * but earlier chipsets do not. For now, we ignore those registers. 211470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 211570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lordstatic unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc) 211670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord{ 211770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct ata_port *ap = qc->ap; 211870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct mv_port_priv *pp = ap->private_data; 211970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct ata_link *link = qc->dev->link; 212070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord u32 fis[5]; 212170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord int err = 0; 212270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 212370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis); 212470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord err = mv_send_fis(ap, fis, sizeof(fis) / sizeof(fis[0])); 212570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (err) 212670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return err; 212770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 212870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord switch (qc->tf.protocol) { 212970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord case ATAPI_PROT_PIO: 213070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; 213170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* fall through */ 213270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord case ATAPI_PROT_NODATA: 213370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST_FIRST; 213470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord break; 213570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord case ATA_PROT_PIO: 213670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; 213770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (qc->tf.flags & ATA_TFLAG_WRITE) 213870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST_FIRST; 213970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord else 214070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST; 214170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord break; 214270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord default: 214370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST_LAST; 214470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord break; 214570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } 214670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 214770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (qc->tf.flags & ATA_TFLAG_POLLING) 214870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ata_pio_queue_task(ap, qc, 0); 214970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return 0; 215070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord} 215170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 215270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord/** 215305b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_issue - Initiate a command to the host 215405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to start 215505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 215605b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 215705b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it sanity checks our local 215805b308e1df6d9d673daedb517969241f41278b52Brett Russ * caches of the request producer/consumer indices then enables 215905b308e1df6d9d673daedb517969241f41278b52Brett Russ * DMA and bumps the request producer index. 216005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 216105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 216205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 216305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 21649a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 216531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 2166f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord static int limit_warnings = 10; 2167c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct ata_port *ap = qc->ap; 2168c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 2169c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp = ap->private_data; 2170bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 in_index; 217142ed893d8011264f9945c2f54055b47c298ac53eMark Lord unsigned int port_irqs; 2172f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord 2173d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */ 2174d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord 2175f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord switch (qc->tf.protocol) { 2176f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATA_PROT_DMA: 2177f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATA_PROT_NCQ: 2178f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord mv_start_edma(ap, port_mmio, pp, qc->tf.protocol); 2179f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2180f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 2181f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord 2182f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord /* Write the request in pointer to kick the EDMA to life */ 2183f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 2184f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 2185f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord return 0; 218631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2187f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATA_PROT_PIO: 2188c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord /* 2189c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * Errata SATA#16, SATA#24: warn if multiple DRQs expected. 2190c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * 2191c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * Someday, we might implement special polling workarounds 2192c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * for these, but it all seems rather unnecessary since we 2193c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * normally use only DMA for commands which transfer more 2194c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * than a single block of data. 2195c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * 2196c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * Much of the time, this could just work regardless. 2197c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * So for now, just log the incident, and allow the attempt. 2198c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord */ 2199c7843e8f565f624b0cff7cad1370fad4cb84dfbcMark Lord if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) { 2200c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord --limit_warnings; 2201c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME 2202c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord ": attempting PIO w/multiple DRQ: " 2203c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord "this may fail due to h/w errata\n"); 2204c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord } 2205f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord /* drop through */ 220642ed893d8011264f9945c2f54055b47c298ac53eMark Lord case ATA_PROT_NODATA: 2207f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATAPI_PROT_PIO: 220842ed893d8011264f9945c2f54055b47c298ac53eMark Lord case ATAPI_PROT_NODATA: 220942ed893d8011264f9945c2f54055b47c298ac53eMark Lord if (ap->flags & ATA_FLAG_PIO_POLLING) 221042ed893d8011264f9945c2f54055b47c298ac53eMark Lord qc->tf.flags |= ATA_TFLAG_POLLING; 221142ed893d8011264f9945c2f54055b47c298ac53eMark Lord break; 221231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 221342ed893d8011264f9945c2f54055b47c298ac53eMark Lord 221442ed893d8011264f9945c2f54055b47c298ac53eMark Lord if (qc->tf.flags & ATA_TFLAG_POLLING) 221542ed893d8011264f9945c2f54055b47c298ac53eMark Lord port_irqs = ERR_IRQ; /* mask device interrupt when polling */ 221642ed893d8011264f9945c2f54055b47c298ac53eMark Lord else 221742ed893d8011264f9945c2f54055b47c298ac53eMark Lord port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */ 221842ed893d8011264f9945c2f54055b47c298ac53eMark Lord 221942ed893d8011264f9945c2f54055b47c298ac53eMark Lord /* 222042ed893d8011264f9945c2f54055b47c298ac53eMark Lord * We're about to send a non-EDMA capable command to the 222142ed893d8011264f9945c2f54055b47c298ac53eMark Lord * port. Turn off EDMA so there won't be problems accessing 222242ed893d8011264f9945c2f54055b47c298ac53eMark Lord * shadow block, etc registers. 222342ed893d8011264f9945c2f54055b47c298ac53eMark Lord */ 222442ed893d8011264f9945c2f54055b47c298ac53eMark Lord mv_stop_edma(ap); 222542ed893d8011264f9945c2f54055b47c298ac53eMark Lord mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs); 222642ed893d8011264f9945c2f54055b47c298ac53eMark Lord mv_pmp_select(ap, qc->dev->link->pmp); 222770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 222870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (qc->tf.command == ATA_CMD_READ_LOG_EXT) { 222970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 223070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* 223170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Workaround for 88SX60x1 FEr SATA#25 (part 2). 223240f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * 223370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * After any NCQ error, the READ_LOG_EXT command 223470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * from libata-eh *must* use mv_qc_issue_fis(). 223570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Otherwise it might fail, due to chip errata. 223670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 223770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Rather than special-case it, we'll just *always* 223870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * use this method here for READ_LOG_EXT, making for 223970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * easier testing. 224070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 224170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (IS_GEN_II(hpriv)) 224270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return mv_qc_issue_fis(qc); 224370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } 224442ed893d8011264f9945c2f54055b47c298ac53eMark Lord return ata_sff_qc_issue(qc); 224531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 224631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 22478f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lordstatic struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) 22488f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 22498f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct mv_port_priv *pp = ap->private_data; 22508f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc; 22518f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 22528f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 22538f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord return NULL; 22548f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord qc = ata_qc_from_tag(ap, ap->link.active_tag); 225595db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord if (qc) { 225695db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord if (qc->tf.flags & ATA_TFLAG_POLLING) 225795db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord qc = NULL; 225895db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord else if (!(qc->flags & ATA_QCFLAG_ACTIVE)) 225995db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord qc = NULL; 226095db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord } 22618f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord return qc; 22628f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 22638f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 226429d187bb1e30682e228ce461c487d78d945c3e4fMark Lordstatic void mv_pmp_error_handler(struct ata_port *ap) 226529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord{ 226629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int pmp, pmp_map; 226729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord struct mv_port_priv *pp = ap->private_data; 226829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord 226929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { 227029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord /* 227129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * Perform NCQ error analysis on failed PMPs 227229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * before we freeze the port entirely. 227329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * 227429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * The failed PMPs are marked earlier by mv_pmp_eh_prep(). 227529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord */ 227629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pmp_map = pp->delayed_eh_pmp_map; 227729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; 227829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord for (pmp = 0; pmp_map != 0; pmp++) { 227929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int this_pmp = (1 << pmp); 228029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pmp_map & this_pmp) { 228129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord struct ata_link *link = &ap->pmp_link[pmp]; 228229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pmp_map &= ~this_pmp; 228329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord ata_eh_analyze_ncq_error(link); 228429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 228529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 228629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord ata_port_freeze(ap); 228729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 228829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord sata_pmp_error_handler(ap); 228929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord} 229029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord 22914c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic unsigned int mv_get_err_pmp_map(struct ata_port *ap) 22924c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 22934c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 22944c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 22954c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return readl(port_mmio + SATA_TESTCTL_OFS) >> 16; 22964c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 22974c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 22984c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map) 22994c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 23004c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct ata_eh_info *ehi; 23014c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int pmp; 23024c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 23034c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 23044c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Initialize EH info for PMPs which saw device errors 23054c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 23064c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi = &ap->link.eh_info; 23074c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord for (pmp = 0; pmp_map != 0; pmp++) { 23084c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int this_pmp = (1 << pmp); 23094c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pmp_map & this_pmp) { 23104c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct ata_link *link = &ap->pmp_link[pmp]; 23114c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 23124c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pmp_map &= ~this_pmp; 23134c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi = &link->eh_info; 23144c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_ehi_clear_desc(ehi); 23154c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_ehi_push_desc(ehi, "dev err"); 23164c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi->err_mask |= AC_ERR_DEV; 23174c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi->action |= ATA_EH_RESET; 23184c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_link_abort(link); 23194c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 23204c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 23214c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 23224c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 232306aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lordstatic int mv_req_q_empty(struct ata_port *ap) 232406aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord{ 232506aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 232606aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord u32 in_ptr, out_ptr; 232706aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord 232806aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS) 232906aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 233006aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) 233106aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 233206aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord return (in_ptr == out_ptr); /* 1 == queue_is_empty */ 233306aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord} 233406aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord 23354c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_fbs_ncq_dev_err(struct ata_port *ap) 23364c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 23374c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp = ap->private_data; 23384c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord int failed_links; 23394c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int old_map, new_map; 23404c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 23414c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 23424c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device error during FBS+NCQ operation: 23434c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 23444c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Set a port flag to prevent further I/O being enqueued. 23454c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Leave the EDMA running to drain outstanding commands from this port. 23464c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Perform the post-mortem/EH only when all responses are complete. 23474c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2). 23484c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 23494c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { 23504c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; 23514c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->delayed_eh_pmp_map = 0; 23524c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 23534c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord old_map = pp->delayed_eh_pmp_map; 23544c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord new_map = old_map | mv_get_err_pmp_map(ap); 23554c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 23564c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (old_map != new_map) { 23574c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->delayed_eh_pmp_map = new_map; 23584c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_pmp_eh_prep(ap, new_map & ~old_map); 23594c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 2360c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord failed_links = hweight16(new_map); 23614c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 23624c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x " 23634c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "failed_links=%d nr_active_links=%d\n", 23644c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, pp->delayed_eh_pmp_map, 23654c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ap->qc_active, failed_links, 23664c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ap->nr_active_links); 23674c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 236806aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { 23694c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_process_crpb_entries(ap, pp); 23704c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_stop_edma(ap); 23714c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_eh_freeze(ap); 23724c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__); 23734c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 1; /* handled */ 23744c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 23754c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__); 23764c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 1; /* handled */ 23774c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 23784c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 23794c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap) 23804c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 23814c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 23824c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Possible future enhancement: 23834c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 23844c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * FBS+non-NCQ operation is not yet implemented. 23854c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * See related notes in mv_edma_cfg(). 23864c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 23874c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device error during FBS+non-NCQ operation: 23884c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 23894c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * We need to snapshot the shadow registers for each failed command. 23904c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3). 23914c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 23924c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 23934c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 23944c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 23954c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause) 23964c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 23974c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp = ap->private_data; 23984c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 23994c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 24004c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* EDMA was not active: not handled */ 24014c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) 24024c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* FBS was not active: not handled */ 24034c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24044c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(edma_err_cause & EDMA_ERR_DEV)) 24054c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* non DEV error: not handled */ 24064c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT; 24074c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS)) 24084c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* other problems: not handled */ 24094c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24104c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { 24114c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 24124c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * EDMA should NOT have self-disabled for this case. 24134c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * If it did, then something is wrong elsewhere, 24144c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * and we cannot handle it here. 24154c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 24164c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & EDMA_ERR_SELF_DIS) { 24174c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_WARNING, 24184c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "%s: err_cause=0x%x pp_flags=0x%x\n", 24194c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, edma_err_cause, pp->pp_flags); 24204c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 24214c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24224c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return mv_handle_fbs_ncq_dev_err(ap); 24234c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } else { 24244c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 24254c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * EDMA should have self-disabled for this case. 24264c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * If it did not, then something is wrong elsewhere, 24274c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * and we cannot handle it here. 24284c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 24294c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) { 24304c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_WARNING, 24314c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "%s: err_cause=0x%x pp_flags=0x%x\n", 24324c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, edma_err_cause, pp->pp_flags); 24334c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 24344c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24354c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return mv_handle_fbs_non_ncq_dev_err(ap); 24364c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24374c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 24384c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 24394c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 2440a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lordstatic void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled) 24418f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 24428f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_eh_info *ehi = &ap->link.eh_info; 2443a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord char *when = "idle"; 24448f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 24458f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_ehi_clear_desc(ehi); 2446a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (!ap || (ap->flags & ATA_FLAG_DISABLED)) { 2447a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "disabled"; 2448a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } else if (edma_was_enabled) { 2449a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "EDMA enabled"; 24508f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } else { 24518f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 24528f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 2453a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "polling"; 24548f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } 2455a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when); 24568f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->err_mask |= AC_ERR_OTHER; 24578f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->action |= ATA_EH_RESET; 24588f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_port_freeze(ap); 24598f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 24608f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 246105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 246205b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_err_intr - Handle error interrupts on the port 246305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 246405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 24658d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Most cases require a full reset of the chip's state machine, 24668d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * which also performs a COMRESET. 24678d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Also, if the port disabled DMA, update our cached copy to match. 246805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 246905b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 247005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 247105b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 247237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lordstatic void mv_err_intr(struct ata_port *ap) 247331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 247431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 2475bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 edma_err_cause, eh_freeze_mask, serr = 0; 2476e40060772d85f3534d3d517197696e24bb01f45bMark Lord u32 fis_cause = 0; 2477bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 2478bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2479bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int action = 0, err_mask = 0; 24809af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_eh_info *ehi = &ap->link.eh_info; 248137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord struct ata_queued_cmd *qc; 248237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord int abort = 0; 248320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 24848d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord /* 248537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Read and clear the SError and err_cause bits. 2486e40060772d85f3534d3d517197696e24bb01f45bMark Lord * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear 2487e40060772d85f3534d3d517197696e24bb01f45bMark Lord * the FIS_IRQ_CAUSE register before clearing edma_err_cause. 24888d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord */ 248937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord sata_scr_read(&ap->link, SCR_ERROR, &serr); 249037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 249137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord 2492bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2493e40060772d85f3534d3d517197696e24bb01f45bMark Lord if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2494e40060772d85f3534d3d517197696e24bb01f45bMark Lord fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 2495e40060772d85f3534d3d517197696e24bb01f45bMark Lord writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 2496e40060772d85f3534d3d517197696e24bb01f45bMark Lord } 24978d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2498bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 24994c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & EDMA_ERR_DEV) { 25004c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 25014c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device errors during FIS-based switching operation 25024c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * require special handling. 25034c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 25044c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (mv_handle_dev_err(ap, edma_err_cause)) 25054c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return; 25064c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 25074c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 250837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord qc = mv_get_active_qc(ap); 250937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_clear_desc(ehi); 251037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x", 251137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord edma_err_cause, pp->pp_flags); 2512e40060772d85f3534d3d517197696e24bb01f45bMark Lord 2513c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2514e40060772d85f3534d3d517197696e24bb01f45bMark Lord ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause); 2515c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord if (fis_cause & SATA_FIS_IRQ_AN) { 2516c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord u32 ec = edma_err_cause & 2517c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT); 2518c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord sata_async_notification(ap); 2519c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord if (!ec) 2520c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord return; /* Just an AN; no need for the nukes */ 2521c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord ata_ehi_push_desc(ehi, "SDB notify"); 2522c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord } 2523c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord } 2524bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 2525352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * All generations share these EDMA error cause bits: 2526bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 252737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (edma_err_cause & EDMA_ERR_DEV) { 2528bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_DEV; 252937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord action |= ATA_EH_RESET; 253037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_push_desc(ehi, "dev error"); 253137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 2532bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 25336c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 2534bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR)) { 2535bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_ATA_BUS; 2536cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2537b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "parity error"); 2538bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2539bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 2540bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_hotplugged(ehi); 2541bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 2542b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo "dev disconnect" : "dev connect"); 2543cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2544bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2545bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2546352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 2547352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Gen-I has a different SELF_DIS bit, 2548352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * different FREEZE bits, and no SERR bit: 2549352fab701ca4753dd005b67ce5e512be944eb591Mark Lord */ 2550ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) { 2551bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE_5; 2552bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 2553bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2554b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 2555bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2556bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 2557bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE; 2558bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS) { 2559bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2560b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 2561bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2562bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SERR) { 25638d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord ata_ehi_push_desc(ehi, "SError=%08x", serr); 25648d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord err_mask |= AC_ERR_ATA_BUS; 2565cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2566bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2567afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 256820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2569bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!err_mask) { 2570bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_OTHER; 2571cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2572bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2573bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2574bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->serror |= serr; 2575bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->action |= action; 2576bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2577bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 2578bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 2579bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 2580bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 2581bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 258237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (err_mask == AC_ERR_DEV) { 258337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* 258437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Cannot do ata_port_freeze() here, 258537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * because it would kill PIO access, 258637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * which is needed for further diagnosis. 258737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord */ 258837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord mv_eh_freeze(ap); 258937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord abort = 1; 259037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } else if (edma_err_cause & eh_freeze_mask) { 259137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* 259237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Note to self: ata_port_freeze() calls ata_port_abort() 259337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord */ 2594bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 259537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } else { 259637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord abort = 1; 259737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 259837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord 259937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (abort) { 260037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (qc) 260137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_link_abort(qc->dev->link); 260237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord else 260337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_port_abort(ap); 260437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 2605bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2606bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2607fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_response(struct ata_port *ap, 2608fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response, unsigned int tag, int ncq_enabled) 2609fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord{ 2610fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag); 2611fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 2612fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (qc) { 2613fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 ata_status; 2614fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u16 edma_status = le16_to_cpu(response->flags); 2615fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 2616fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * edma_status from a response queue entry: 2617fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only). 2618fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * MSB is saved ATA status from command completion. 2619fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 2620fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (!ncq_enabled) { 2621fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; 2622fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (err_cause) { 2623fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 2624fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * Error will be seen/handled by mv_err_intr(). 2625fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * So do nothing at all here. 2626fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 2627fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord return; 2628fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2629fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2630fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; 263137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (!ac_err_mask(ata_status)) 263237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_qc_complete(qc); 263337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* else: leave it for mv_err_intr() */ 2634fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 2635fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n", 2636fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord __func__, tag); 2637fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2638fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord} 2639fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 2640fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) 2641bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2642bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 2643bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2644fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u32 in_index; 2645bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik bool work_done = false; 2646fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); 2647bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2648fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Get the hardware queue position index */ 2649bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) 2650bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2651bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2652fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Process new responses from since the last time we looked */ 2653fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord while (in_index != pp->resp_idx) { 26546c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik unsigned int tag; 2655fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response = &pp->crpb[pp->resp_idx]; 2656bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2657fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2658bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2659fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (IS_GEN_I(hpriv)) { 2660fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 50xx: no NCQ, only one command active at a time */ 26619af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo tag = ap->link.active_tag; 2662fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 2663fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Gen II/IIE: get command tag from CRPB entry */ 2664fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord tag = le16_to_cpu(response->id) & 0x1f; 2665bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2666fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord mv_process_crpb_response(ap, response, tag, ncq_enabled); 2667bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik work_done = true; 2668bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2669bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2670352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Update the software queue position index in hardware */ 2671bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (work_done) 2672bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 2673fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), 2674bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 267520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 267620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2677a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lordstatic void mv_port_intr(struct ata_port *ap, u32 port_cause) 2678a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord{ 2679a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord struct mv_port_priv *pp; 2680a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord int edma_was_enabled; 2681a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord 2682a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (!ap || (ap->flags & ATA_FLAG_DISABLED)) { 2683a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_unexpected_intr(ap, 0); 2684a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord return; 2685a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2686a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2687a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Grab a snapshot of the EDMA_EN flag setting, 2688a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * so that we have a consistent view for this port, 2689a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * even if something we call of our routines changes it. 2690a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2691a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord pp = ap->private_data; 2692a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); 2693a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2694a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Process completed CRPB response(s) before other events. 2695a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2696a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (edma_was_enabled && (port_cause & DONE_IRQ)) { 2697a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_process_crpb_entries(ap, pp); 26984c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 26994c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_handle_fbs_ncq_dev_err(ap); 2700a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2701a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2702a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Handle chip-reported errors, or continue on to handle PIO. 2703a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2704a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (unlikely(port_cause & ERR_IRQ)) { 2705a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_err_intr(ap); 2706a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } else if (!edma_was_enabled) { 2707a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord struct ata_queued_cmd *qc = mv_get_active_qc(ap); 2708a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (qc) 2709a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord ata_sff_host_intr(ap, qc); 2710a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord else 2711a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_unexpected_intr(ap, edma_was_enabled); 2712a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2713a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord} 2714a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord 271505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 271605b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_host_intr - Handle all interrupts on the given host controller 2717cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * @host: host specific structure 27187368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * @main_irq_cause: Main interrupt cause register for the chip. 271905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 272005b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 272105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 272205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 27237368f91926a2870a8c3f9546d86535ce71ae0757Mark Lordstatic int mv_host_intr(struct ata_host *host, u32 main_irq_cause) 272420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2725f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 2726eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord void __iomem *mmio = hpriv->base, *hc_mmio; 2727a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0, port; 272820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 27292b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* If asserted, clear the "all ports" IRQ coalescing bit */ 27302b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (main_irq_cause & ALL_PORTS_COAL_DONE) 27312b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord writel(~ALL_PORTS_COAL_IRQ, mmio + MV_IRQ_COAL_CAUSE); 27322b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 2733a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord for (port = 0; port < hpriv->n_ports; port++) { 2734cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_port *ap = host->ports[port]; 2735eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord unsigned int p, shift, hardport, port_cause; 2736eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord 2737a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2738a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord /* 2739eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * Each hc within the host has its own hc_irq_cause register, 2740eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * where the interrupting ports bits get ack'd. 2741a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord */ 2742eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (hardport == 0) { /* first port on this hc ? */ 2743eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND; 2744eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord u32 port_mask, ack_irqs; 2745eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord /* 2746eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * Skip this entire hc if nothing pending for any ports 2747eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord */ 2748eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (!hc_cause) { 2749eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord port += MV_PORTS_PER_HC - 1; 2750eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord continue; 2751eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord } 2752eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord /* 2753eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * We don't need/want to read the hc_irq_cause register, 2754eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * because doing so hurts performance, and 2755eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * main_irq_cause already gives us everything we need. 2756eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * 2757eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * But we do have to *write* to the hc_irq_cause to ack 2758eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * the ports that we are handling this time through. 2759eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * 2760eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * This requires that we create a bitmap for those 2761eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * ports which interrupted us, and use that bitmap 2762eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * to ack (only) those ports via hc_irq_cause. 2763eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord */ 2764eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord ack_irqs = 0; 27652b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (hc_cause & PORTS_0_3_COAL_DONE) 27662b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord ack_irqs = HC_COAL_IRQ; 2767eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord for (p = 0; p < MV_PORTS_PER_HC; ++p) { 2768eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if ((port + p) >= hpriv->n_ports) 2769eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord break; 2770eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2); 2771eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (hc_cause & port_mask) 2772eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord ack_irqs |= (DMA_IRQ | DEV_IRQ) << p; 2773eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord } 2774a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord hc_mmio = mv_hc_base_from_port(mmio, port); 2775eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS); 2776a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = 1; 2777a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord } 27788f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord /* 2779a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Handle interrupts signalled for this port: 27808f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord */ 2781a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ); 2782a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (port_cause) 2783a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_port_intr(ap, port_cause); 278420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 2785a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return handled; 278620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 278720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2788a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lordstatic int mv_pci_error(struct ata_host *host, void __iomem *mmio) 2789bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 279002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 2791bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_port *ap; 2792bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 2793bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_eh_info *ehi; 2794bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int i, err_mask, printed = 0; 2795bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 err_cause; 2796bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 279702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord err_cause = readl(mmio + hpriv->irq_cause_ofs); 2798bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2799bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", 2800bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_cause); 2801bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2802bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik DPRINTK("All regs @ PCI error\n"); 2803bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 2804bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 280502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord writelfl(0, mmio + hpriv->irq_cause_ofs); 2806bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2807bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik for (i = 0; i < host->n_ports; i++) { 2808bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ap = host->ports[i]; 2809936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo if (!ata_link_offline(&ap->link)) { 28109af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo ehi = &ap->link.eh_info; 2811bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 2812bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!printed++) 2813bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, 2814bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik "PCI err cause 0x%08x", err_cause); 2815bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_HOST_BUS; 2816cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo ehi->action = ATA_EH_RESET; 28179af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 2818bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 2819bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 2820bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 2821bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 2822bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2823bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 2824bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2825bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2826a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return 1; /* handled */ 2827bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2828bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 282905b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2830c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * mv_interrupt - Main interrupt event handler 283105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @irq: unused 283205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @dev_instance: private data; in this case the host structure 283305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 283405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read the read only register to determine if any host 283505b308e1df6d9d673daedb517969241f41278b52Brett Russ * controllers have pending interrupts. If so, call lower level 283605b308e1df6d9d673daedb517969241f41278b52Brett Russ * routine to handle. Also check for PCI errors which are only 283705b308e1df6d9d673daedb517969241f41278b52Brett Russ * reported here. 283805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 28398b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * LOCKING: 2840cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine holds the host lock while processing pending 284105b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts. 284205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 28437d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t mv_interrupt(int irq, void *dev_instance) 284420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2845cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = dev_instance; 2846f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 2847a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0; 28486d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI; 284996e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord u32 main_irq_cause, pending_irqs; 285020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2851646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord spin_lock(&host->lock); 28526d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 28536d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord /* for MSI: block new interrupts while in here */ 28546d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord if (using_msi) 28552b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_write_main_irq_mask(0, hpriv); 28566d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 28577368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_cause = readl(hpriv->main_irq_cause_addr); 285896e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord pending_irqs = main_irq_cause & hpriv->main_irq_mask; 2859352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 2860352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Deal with cases where we either have nothing pending, or have read 2861352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * a bogus register value which can indicate HW removal or PCI fault. 286220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2863a44253d24a97ec3efe601267274a5fb64d8696c1Mark Lord if (pending_irqs && main_irq_cause != 0xffffffffU) { 28641f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv))) 2865a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = mv_pci_error(host, hpriv->base); 2866a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord else 2867a44253d24a97ec3efe601267274a5fb64d8696c1Mark Lord handled = mv_host_intr(host, pending_irqs); 2868bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 28696d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 28706d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord /* for MSI: unmask; interrupt cause bits will retrigger now */ 28716d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord if (using_msi) 28722b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv); 28736d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 28749d51af7bd2f1d730cb6eeeb9ff837e3441ad4e07Mark Lord spin_unlock(&host->lock); 28759d51af7bd2f1d730cb6eeeb9ff837e3441ad4e07Mark Lord 287620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return IRQ_RETVAL(handled); 287720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 287820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2879c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic unsigned int mv5_scr_offset(unsigned int sc_reg_in) 2880c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2881c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs; 2882c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2883c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik switch (sc_reg_in) { 2884c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_STATUS: 2885c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_ERROR: 2886c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_CONTROL: 2887c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = sc_reg_in * sizeof(u32); 2888c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 2889c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik default: 2890c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = 0xffffffffU; 2891c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 2892c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2893c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return ofs; 2894c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2895c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 289682ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 2897c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 289882ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo struct mv_host_priv *hpriv = link->ap->host->private_data; 2899f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 290082ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 2901c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 2902c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2903da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 2904da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(addr + ofs); 2905da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 2906da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 2907da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 2908c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2909c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 291082ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 2911c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 291282ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo struct mv_host_priv *hpriv = link->ap->host->private_data; 2913f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 291482ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 2915c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 2916c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2917da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 29180d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo writelfl(val, addr + ofs); 2919da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 2920da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 2921da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 2922c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2923c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 29247bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 2925522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 29267bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara struct pci_dev *pdev = to_pci_dev(host->dev); 2927522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik int early_5080; 2928522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 292944c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 2930522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2931522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik if (!early_5080) { 2932522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 2933522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= (1 << 0); 2934522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 2935522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik } 2936522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 29377bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara mv_reset_pci_bus(host, mmio); 2938522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 2939522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2940522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 2941522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 29428e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS); 2943522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 2944522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 294547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 2946ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 2947ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 2948c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 2949c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 2950c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2951c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 2952c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2953c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 2954c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 2955ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2956ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 295747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 2958ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 2959522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp; 2960522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 29618e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0, mmio + MV_GPIO_PORT_CTL_OFS); 2962522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2963522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 2964522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2965522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 2966522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= ~(1 << 0); 2967522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 2968ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2969ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 29702a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 29712a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 2972bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 2973c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, port); 2974c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 2975c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 2976c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 2977c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2978c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik if (fix_apm_sq) { 29798e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(phy_mmio + MV5_LTMODE_OFS); 2980c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= (1 << 19); 29818e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, phy_mmio + MV5_LTMODE_OFS); 2982c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 29838e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(phy_mmio + MV5_PHY_CTL_OFS); 2984c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~0x3; 2985c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x1; 29868e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, phy_mmio + MV5_PHY_CTL_OFS); 2987c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2988c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2989c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 2990c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~mask; 2991c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].pre; 2992c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].amps; 2993c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_MODE); 2994bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2995bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2996c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2997c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 2998c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, port_mmio + (reg)) 2999c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 3000c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 3001c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 3002c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 3003c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3004e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 3005c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3006c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x028); /* command */ 3007c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(0x11f, port_mmio + EDMA_CFG_OFS); 3008c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x004); /* timer */ 3009c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x008); /* irq err cause */ 3010c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); /* irq err mask */ 3011c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); /* rq bah */ 3012c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); /* rq inp */ 3013c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); /* rq outp */ 3014c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x01c); /* respq bah */ 3015c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x024); /* respq outp */ 3016c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x020); /* respq inp */ 3017c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x02c); /* test control */ 30188e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS); 3019c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3020c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 3021c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3022c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, hc_mmio + (reg)) 3023c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3024c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc) 302547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik{ 3026c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 3027c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 3028c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3029c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); 3030c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); 3031c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); 3032c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); 3033c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3034c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(hc_mmio + 0x20); 3035c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= 0x1c1c1c1c; 3036c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x03030303; 3037c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, hc_mmio + 0x20); 3038c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3039c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 3040c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3041c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3042c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 3043c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 3044c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc, port; 3045c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3046c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (hc = 0; hc < n_hc; hc++) { 3047c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (port = 0; port < MV_PORTS_PER_HC; port++) 3048c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_hc_port(hpriv, mmio, 3049c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (hc * MV_PORTS_PER_HC) + port); 3050c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3051c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_one_hc(hpriv, mmio, hc); 3052c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 3053c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3054c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return 0; 305547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik} 305647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 3057101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 3058101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#define ZERO(reg) writel(0, mmio + (reg)) 30597bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 3060101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 306102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 3062101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 3063101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 30648e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(mmio + MV_PCI_MODE_OFS); 3065101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0xff00ffff; 30668e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, mmio + MV_PCI_MODE_OFS); 3067101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3068101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_DISC_TIMER); 3069101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_MSI_TRIGGER); 30708e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS); 3071101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_SERR_MASK); 307202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_cause_ofs); 307302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_mask_ofs); 3074101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_LOW_ADDRESS); 3075101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_HIGH_ADDRESS); 3076101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_ATTRIBUTE); 3077101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_COMMAND); 3078101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 3079101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 3080101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3081101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 3082101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 3083101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 3084101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3085101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik mv5_reset_flash(hpriv, mmio); 3086101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 30878e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS); 3088101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0x3; 3089101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp |= (1 << 5) | (1 << 6); 30908e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS); 3091101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 3092101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3093101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik/** 3094101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * mv6_reset_hc - Perform the 6xxx global soft reset 3095101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * @mmio: base address of the HBA 3096101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 3097101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * This routine only applies to 6xxx parts. 3098101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 3099101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * LOCKING: 3100101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * Inherited from caller. 3101101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 3102c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3103c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 3104101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 3105101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; 3106101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik int i, rc = 0; 3107101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 t; 3108101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3109101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* Following procedure defined in PCI "main command and status 3110101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * register" table. 3111101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 3112101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 3113101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | STOP_PCI_MASTER, reg); 3114101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3115101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik for (i = 0; i < 1000; i++) { 3116101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 3117101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 31182dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik if (PCI_MASTER_EMPTY & t) 3119101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik break; 3120101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3121101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(PCI_MASTER_EMPTY & t)) { 3122101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 3123101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 3124101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 3125101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3126101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3127101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* set reset */ 3128101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 3129101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 3130101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | GLOB_SFT_RST, reg); 3131101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 3132101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 3133101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 3134101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3135101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(GLOB_SFT_RST & t)) { 3136101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 3137101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 3138101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 3139101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3140101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3141101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 3142101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 3143101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 3144101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 3145101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 3146101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 3147101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while ((GLOB_SFT_RST & t) && (i-- > 0)); 3148101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3149101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (GLOB_SFT_RST & t) { 3150101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 3151101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 3152101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3153101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikdone: 3154101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik return rc; 3155101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 3156101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 315747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 3158ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 3159ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 3160ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *port_mmio; 3161ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik u32 tmp; 3162ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 31638e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(mmio + MV_RESET_CFG_OFS); 3164ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik if ((tmp & (1 << 0)) == 0) { 316547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->signal[idx].amps = 0x7 << 8; 3166ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = 0x1 << 5; 3167ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik return; 3168ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik } 3169ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3170ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik port_mmio = mv_port_base(mmio, idx); 3171ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(port_mmio + PHY_MODE2); 3172ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3173ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3174ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3175ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3176ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 317747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 3178ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 31798e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS); 3180ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3181ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3182c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 31832a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 3184bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 3185c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 3186c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3187bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 318847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik int fix_phy_mode2 = 318947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 3190bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik int fix_phy_mode4 = 319147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 31928c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord u32 m2, m3; 319347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 319447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (fix_phy_mode2) { 319547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 319647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 319747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 |= (1 << 31); 319847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 319947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 320047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 320147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 320247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 320347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~((1 << 16) | (1 << 31)); 320447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 320547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 320647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 320747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 320847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 32098c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord /* 32108c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord * Gen-II/IIe PHY_MODE3 errata RM#2: 32118c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord * Achieves better receiver noise performance than the h/w default: 32128c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord */ 32138c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord m3 = readl(port_mmio + PHY_MODE3); 32148c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord m3 = (m3 & 0x1f) | (0x5555601 << 5); 3215bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 32160388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord /* Guideline 88F5182 (GL# SATA-S11) */ 32170388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord if (IS_SOC(hpriv)) 32180388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord m3 &= ~0x1c; 32190388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord 3220bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (fix_phy_mode4) { 3221ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord u32 m4 = readl(port_mmio + PHY_MODE4); 3222ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord /* 3223ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * Enforce reserved-bit restrictions on GenIIe devices only. 3224ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * For earlier chipsets, force only the internal config field 3225ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * (workaround for errata FEr SATA#10 part 1). 3226ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord */ 32278c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord if (IS_GEN_IIE(hpriv)) 3228ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES; 3229ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord else 3230ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE; 32318c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord writel(m4, port_mmio + PHY_MODE4); 3232bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3233b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord /* 3234b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * Workaround for 60x1-B2 errata SATA#13: 3235b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3, 3236b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * so we must always rewrite PHY_MODE3 after PHY_MODE4. 3237b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord */ 3238b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord writel(m3, port_mmio + PHY_MODE3); 3239bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3240bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik /* Revert values of pre-emphasis and signal amps to the saved ones */ 3241bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 3242bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3243bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 &= ~MV_M2_PREAMP_MASK; 32442a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].amps; 32452a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].pre; 324647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 3247bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3248e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* according to mvSata 3.6.1, some IIE values are fixed */ 3249e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (IS_GEN_IIE(hpriv)) { 3250e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 &= ~0xC30FF01F; 3251e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 |= 0x0000900F; 3252e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 3253e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 3254bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 3255bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 3256bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3257f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* TODO: use the generic LED interface to configure the SATA Presence */ 3258f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* & Acitivy LEDs on the board */ 3259f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 3260f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3261f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3262f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 3263f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3264f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3265f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 3266f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3267f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3268f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio; 3269f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara u32 tmp; 3270f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3271f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara port_mmio = mv_port_base(mmio, idx); 3272f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(port_mmio + PHY_MODE2); 3273f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3274f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3275f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3276f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3277f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3278f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 3279f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, port_mmio + (reg)) 3280f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 3281f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int port) 3282f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3283f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio = mv_port_base(mmio, port); 3284f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3285e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 3286f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3287f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x028); /* command */ 3288f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0x101f, port_mmio + EDMA_CFG_OFS); 3289f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x004); /* timer */ 3290f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x008); /* irq err cause */ 3291f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); /* irq err mask */ 3292f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); /* rq bah */ 3293f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); /* rq inp */ 3294f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x018); /* rq outp */ 3295f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x01c); /* respq bah */ 3296f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x024); /* respq outp */ 3297f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x020); /* respq inp */ 3298f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x02c); /* test control */ 32998e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS); 3300f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3301f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3302f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 3303f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3304f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, hc_mmio + (reg)) 3305f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 3306f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3307f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3308f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *hc_mmio = mv_hc_base(mmio, 0); 3309f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3310f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); 3311f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); 3312f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); 3313f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3314f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3315f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3316f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 3317f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3318f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 3319f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc) 3320f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3321f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int port; 3322f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3323f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara for (port = 0; port < hpriv->n_ports; port++) 3324f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_hc_port(hpriv, mmio, port); 3325f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3326f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_one_hc(hpriv, mmio); 3327f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3328f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 3329f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3330f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3331f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 3332f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3333f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3334f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 3335f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3336f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3337f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 3338f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3339f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 3340f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3341f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 33428e7decdb8b132ee970a2636931b7653dec6af472Mark Lordstatic void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) 3343b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord{ 33448e7decdb8b132ee970a2636931b7653dec6af472Mark Lord u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS); 3345b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 33468e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */ 3347b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (want_gen2i) 33488e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg |= (1 << 7); /* enable gen2i speed */ 33498e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS); 3350b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord} 3351b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 3352e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 3353c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no) 3354c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 3355c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port_no); 3356c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 33578e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* 33588e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * The datasheet warns against setting EDMA_RESET when EDMA is active 33598e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * (but doesn't say what the problem might be). So we first try 33608e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * to disable the EDMA engine before doing the EDMA_RESET operation. 33618e7decdb8b132ee970a2636931b7653dec6af472Mark Lord */ 33620d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord mv_stop_edma_engine(port_mmio); 33638e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS); 3364c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3365b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (!IS_GEN_I(hpriv)) { 33668e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* Enable 3.0gb/s link speed: this survives EDMA_RESET */ 33678e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(port_mmio, 1); 3368c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 3369b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord /* 33708e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * Strobing EDMA_RESET here causes a hard reset of the SATA transport, 3371b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * link, and physical layers. It resets all SATA interface registers 3372b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev. 3373c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik */ 33748e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS); 3375b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord udelay(25); /* allow reset propagation */ 3376c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writelfl(0, port_mmio + EDMA_CMD_OFS); 3377c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3378c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->ops->phy_errata(hpriv, mmio, port_no); 3379c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3380ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) 3381c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mdelay(1); 3382c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3383c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3384e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp) 338520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 3386e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (sata_pmp_supported(ap)) { 3387e49856d82a887ce365637176f9f99ab68076eae8Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 3388e49856d82a887ce365637176f9f99ab68076eae8Mark Lord u32 reg = readl(port_mmio + SATA_IFCTL_OFS); 3389e49856d82a887ce365637176f9f99ab68076eae8Mark Lord int old = reg & 0xf; 339022374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 3391e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (old != pmp) { 3392e49856d82a887ce365637176f9f99ab68076eae8Mark Lord reg = (reg & ~0xf) | pmp; 3393e49856d82a887ce365637176f9f99ab68076eae8Mark Lord writelfl(reg, port_mmio + SATA_IFCTL_OFS); 3394e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 339522374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik } 339620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 339720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3398e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 3399e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 340022374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik{ 3401e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 3402e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return sata_std_hardreset(link, class, deadline); 3403e49856d82a887ce365637176f9f99ab68076eae8Mark Lord} 3404bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3405e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 3406e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 3407e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 3408e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 3409e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return ata_sff_softreset(link, class, deadline); 341022374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik} 341122374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 3412cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 3413bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned long deadline) 341431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 3415cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo struct ata_port *ap = link->ap; 3416bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 3417b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 3418f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 34190d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord int rc, attempts = 0, extra = 0; 34200d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord u32 sstatus; 34210d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord bool online; 342231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3423e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, ap->port_no); 3424b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 3425d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= 3426d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 3427bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 34280d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Workaround for errata FEr SATA#10 (part 2) */ 34290d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord do { 343017c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord const unsigned long *timing = 343117c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord sata_ehc_deb_timing(&link->eh_context); 3432bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 343317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord rc = sata_link_hardreset(link, timing, deadline + extra, 343417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord &online, NULL); 34359dcffd99d0b1c0c1b8b2c0f85d240e791eca1055Mark Lord rc = online ? -EAGAIN : rc; 343617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord if (rc) 34370d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord return rc; 34380d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord sata_scr_read(link, SCR_STATUS, &sstatus); 34390d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 34400d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Force 1.5gb/s link speed and try again */ 34418e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(mv_ap_base(ap), 0); 34420d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (time_after(jiffies + HZ, deadline)) 34430d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord extra = HZ; /* only extend it once, max */ 34440d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } 34450d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); 344608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_save_cached_regs(ap); 344766e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord mv_edma_cfg(ap, 0, 0); 3448bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 344917c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord return rc; 3450bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 3451bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3452bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap) 3453bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 34541cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord mv_stop_edma(ap); 3455c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_enable_port_irqs(ap, 0); 3456bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 3457bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3458bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap) 3459bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 3460f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 3461c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int port = ap->port_no; 3462c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int hardport = mv_hardport_from_port(port); 34631cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); 3464bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 3465c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 hc_irq_cause; 3466bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3467bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA errors on this port */ 3468bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 3469bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3470bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear pending irq events */ 3471cae6edc3b5a536119374a5439d9b253cb26f05e1Mark Lord hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 34721cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 3473bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 347488e675e193159b9891c1c576de4348eaf490f5d0Mark Lord mv_enable_port_irqs(ap, ERR_IRQ); 347531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 347631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 347705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 347805b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_init - Perform some early initialization on a single port. 347905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port: libata data structure storing shadow register addresses 348005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port_mmio: base address of the port 348105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 348205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Initialize shadow register mmio addresses, clear outstanding 348305b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts on the port, and unmask interrupts for the future 348405b308e1df6d9d673daedb517969241f41278b52Brett Russ * start of the port. 348505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 348605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 348705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 348805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 348931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 349020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 34910d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *shd_base = port_mmio + SHD_BLK_OFS; 349231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ unsigned serr_ofs; 349331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 34948b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik /* PIO related setup 349531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 349631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 34978b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->error_addr = 349831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 349931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 350031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 350131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 350231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 350331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 35048b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->status_addr = 350531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 350631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* special case: control/altstatus doesn't have ATA_REG_ address */ 350731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; 350831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 350931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* unused: */ 35108d9db2d2fbae9e05022825c32f86e00c8e342860Randy Dunlap port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; 351120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 351231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding port interrupt conditions */ 351331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ serr_ofs = mv_scr_offset(SCR_ERROR); 351431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); 351531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 351631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3517646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord /* unmask all non-transient EDMA error interrupts */ 3518646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS); 351920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 35208b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 352131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_CFG_OFS), 352231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), 352331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); 352420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 352520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3526616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic unsigned int mv_in_pcix_mode(struct ata_host *host) 3527616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 3528616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 3529616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 3530616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 3531616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 35321f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (IS_SOC(hpriv) || !IS_PCIE(hpriv)) 3533616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not PCI-X capable */ 3534616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord reg = readl(mmio + MV_PCI_MODE_OFS); 3535616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if ((reg & MV_PCI_MODE_MASK) == 0) 3536616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* conventional PCI mode */ 3537616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* chip is in PCI-X mode */ 3538616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 3539616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 3540616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic int mv_pci_cut_through_okay(struct ata_host *host) 3541616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 3542616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 3543616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 3544616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 3545616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 3546616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (!mv_in_pcix_mode(host)) { 3547616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord reg = readl(mmio + PCI_COMMAND_OFS); 3548616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (reg & PCI_COMMAND_MRDTRIG) 3549616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not okay */ 3550616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord } 3551616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* okay */ 3552616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 3553616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 355465ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lordstatic void mv_60x1b2_errata_pci7(struct ata_host *host) 355565ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord{ 355665ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord struct mv_host_priv *hpriv = host->private_data; 355765ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord void __iomem *mmio = hpriv->base; 355865ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord 355965ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord /* workaround for 60x1-B2 errata PCI#7 */ 356065ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord if (mv_in_pcix_mode(host)) { 356165ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord u32 reg = readl(mmio + PCI_COMMAND_OFS); 356265ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord writelfl(reg & ~PCI_COMMAND_MWRCOM, mmio + PCI_COMMAND_OFS); 356365ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord } 356465ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord} 356565ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord 35664447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_chip_id(struct ata_host *host, unsigned int board_idx) 3567bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 35684447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 35694447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 3570bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 3571bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 35725796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik switch (board_idx) { 357347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case chip_5080: 357447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 3575ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 357647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 357744c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 357847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x1: 357947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 358047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 358147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 358247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 358347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 358447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 358547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 358647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying 50XXB2 workarounds to unknown rev\n"); 358747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 358847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 358947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 359047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 359147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 3592bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_504x: 3593bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_508x: 359447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 3595ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 3596bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 359744c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 359847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x0: 359947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 360047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 360147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 360247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 360347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 360447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 360547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 360647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 360747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 360847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 3609bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3610bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3611bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3612bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_604x: 3613bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_608x: 361447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv6xxx_ops; 3615ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_II; 361647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 361744c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 361847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x7: 361965ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord mv_60x1b2_errata_pci7(host); 362047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 362147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 362247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x9: 362347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3624bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3625bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 3626bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 362747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 362847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 3629bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3630bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3631bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3632bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3633e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_7042: 3634616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH; 3635306b30f74d37f289033c696285e07ce0158a5d7bMark Lord if (pdev->vendor == PCI_VENDOR_ID_TTI && 3636306b30f74d37f289033c696285e07ce0158a5d7bMark Lord (pdev->device == 0x2300 || pdev->device == 0x2310)) 3637306b30f74d37f289033c696285e07ce0158a5d7bMark Lord { 36384e5200334e03e5620aa19d538300c13db270a063Mark Lord /* 36394e5200334e03e5620aa19d538300c13db270a063Mark Lord * Highpoint RocketRAID PCIe 23xx series cards: 36404e5200334e03e5620aa19d538300c13db270a063Mark Lord * 36414e5200334e03e5620aa19d538300c13db270a063Mark Lord * Unconfigured drives are treated as "Legacy" 36424e5200334e03e5620aa19d538300c13db270a063Mark Lord * by the BIOS, and it overwrites sector 8 with 36434e5200334e03e5620aa19d538300c13db270a063Mark Lord * a "Lgcy" metadata block prior to Linux boot. 36444e5200334e03e5620aa19d538300c13db270a063Mark Lord * 36454e5200334e03e5620aa19d538300c13db270a063Mark Lord * Configured drives (RAID or JBOD) leave sector 8 36464e5200334e03e5620aa19d538300c13db270a063Mark Lord * alone, but instead overwrite a high numbered 36474e5200334e03e5620aa19d538300c13db270a063Mark Lord * sector for the RAID metadata. This sector can 36484e5200334e03e5620aa19d538300c13db270a063Mark Lord * be determined exactly, by truncating the physical 36494e5200334e03e5620aa19d538300c13db270a063Mark Lord * drive capacity to a nice even GB value. 36504e5200334e03e5620aa19d538300c13db270a063Mark Lord * 36514e5200334e03e5620aa19d538300c13db270a063Mark Lord * RAID metadata is at: (dev->n_sectors & ~0xfffff) 36524e5200334e03e5620aa19d538300c13db270a063Mark Lord * 36534e5200334e03e5620aa19d538300c13db270a063Mark Lord * Warn the user, lest they think we're just buggy. 36544e5200334e03e5620aa19d538300c13db270a063Mark Lord */ 36554e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 36564e5200334e03e5620aa19d538300c13db270a063Mark Lord " BIOS CORRUPTS DATA on all attached drives," 36574e5200334e03e5620aa19d538300c13db270a063Mark Lord " regardless of if/how they are configured." 36584e5200334e03e5620aa19d538300c13db270a063Mark Lord " BEWARE!\n"); 36594e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": For data safety, do not" 36604e5200334e03e5620aa19d538300c13db270a063Mark Lord " use sectors 8-9 on \"Legacy\" drives," 36614e5200334e03e5620aa19d538300c13db270a063Mark Lord " and avoid the final two gigabytes on" 36624e5200334e03e5620aa19d538300c13db270a063Mark Lord " all RocketRAID BIOS initialized drives.\n"); 3663306b30f74d37f289033c696285e07ce0158a5d7bMark Lord } 36648e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* drop through */ 3665e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_6042: 3666e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hpriv->ops = &mv6xxx_ops; 3667e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_GEN_IIE; 3668616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (board_idx == chip_6042 && mv_pci_cut_through_okay(host)) 3669616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_CUT_THROUGH; 3670e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 367144c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 36725cf73bfb061552aa18d816d2859409be9ace5306Mark Lord case 0x2: /* Rev.B0: the first/only public release */ 3673e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3674e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3675e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik default: 3676e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 3677e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik "Applying 60X1C0 workarounds to unknown rev\n"); 3678e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3679e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3680e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 3681e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3682f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara case chip_soc: 3683f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->ops = &mv_soc_ops; 3684eb3a55a9f43f0f8e770c2abf70e65bdda2d5ff1eSaeed Bishara hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE | 3685eb3a55a9f43f0f8e770c2abf70e65bdda2d5ff1eSaeed Bishara MV_HP_ERRATA_60X1C0; 3686f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara break; 3687e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 3688bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 3689f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_ERR, host->dev, 36905796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik "BUG: invalid board index %u\n", board_idx); 3691bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 1; 3692bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3693bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3694bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik hpriv->hp_flags = hp_flags; 369502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord if (hp_flags & MV_HP_PCIE) { 369602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS; 369702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS; 369802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 369902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } else { 370002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS; 370102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS; 370202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 370302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } 3704bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3705bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 0; 3706bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 3707bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 370805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 370947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik * mv_init_host - Perform some early initialization of the host. 37104447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to initialize 37114447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @board_idx: controller index 371205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 371305b308e1df6d9d673daedb517969241f41278b52Brett Russ * If possible, do an early global reset of the host. Then do 371405b308e1df6d9d673daedb517969241f41278b52Brett Russ * our port init and clear/unmask all/relevant host interrupts. 371505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 371605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 371705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 371805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 37194447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_init_host(struct ata_host *host, unsigned int board_idx) 372020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 372120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ int rc = 0, n_hc, port, hc; 37224447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 3723f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 372447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 37254447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_chip_id(host, board_idx); 3726bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (rc) 3727352fab701ca4753dd005b67ce5e512be944eb591Mark Lord goto done; 3728f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 37291f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (IS_SOC(hpriv)) { 37307368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS; 37317368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS; 37321f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord } else { 37331f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS; 37341f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS; 3735f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 3736352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 37375d0fb2e730e2085021cf5c8b6d14983e92aea75bThomas Reitmayr /* initialize shadow irq mask with register's value */ 37385d0fb2e730e2085021cf5c8b6d14983e92aea75bThomas Reitmayr hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr); 37395d0fb2e730e2085021cf5c8b6d14983e92aea75bThomas Reitmayr 3740352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* global interrupt mask: 0 == mask everything */ 3741c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_set_main_irq_mask(host, ~0, 0); 3742bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 37434447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_hc = mv_get_hc_count(host->ports[0]->flags); 3744bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 37454447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) 374647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->read_preamp(hpriv, port, mmio); 374720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3748c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 374947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (rc) 375020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ goto done; 375120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3752522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik hpriv->ops->reset_flash(hpriv, mmio); 37537bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara hpriv->ops->reset_bus(host, mmio); 375447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->enable_leds(hpriv, mmio); 375520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 37564447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) { 3757cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo struct ata_port *ap = host->ports[port]; 37582a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 3759cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 3760cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo mv_port_init(&ap->ioaddr, port_mmio); 3761cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 37627bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 37631f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (!IS_SOC(hpriv)) { 3764f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int offset = port_mmio - mmio; 3765f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 3766f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 3767f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 37687bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 376920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 377020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 377120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hc; hc++) { 377231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 377331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 377431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 377531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ "(before clear)=0x%08x\n", hc, 377631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_CFG_OFS), 377731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_IRQ_CAUSE_OFS)); 377831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 377931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding hc interrupt conditions */ 378031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); 378120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 378220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 378344c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord if (!IS_SOC(hpriv)) { 378444c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord /* Clear any currently outstanding host interrupt conditions */ 378544c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord writelfl(0, mmio + hpriv->irq_cause_ofs); 378631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 378744c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord /* and unmask interrupt generation for host regs */ 378844c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs); 378944c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord } 379051de32d200b21333950abc52ea1e589bc4eecef7Mark Lord 37916be96ac15e4d913e1f48299db083ada5321803b2Mark Lord /* 37926be96ac15e4d913e1f48299db083ada5321803b2Mark Lord * enable only global host interrupts for now. 37936be96ac15e4d913e1f48299db083ada5321803b2Mark Lord * The per-port interrupts get done later as ports are set up. 37946be96ac15e4d913e1f48299db083ada5321803b2Mark Lord */ 37956be96ac15e4d913e1f48299db083ada5321803b2Mark Lord mv_set_main_irq_mask(host, 0, PCI_ERR); 37962b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_set_irq_coalescing(host, irq_coalescing_io_count, 37972b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord irq_coalescing_usecs); 3798f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharadone: 3799f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3800f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3801fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik 3802fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradleystatic int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 3803fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley{ 3804fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 3805fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRQB_Q_SZ, 0); 3806fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crqb_pool) 3807fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3808fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3809fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 3810fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRPB_Q_SZ, 0); 3811fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crpb_pool) 3812fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3813fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3814fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 3815fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_SG_TBL_SZ, 0); 3816fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->sg_tbl_pool) 3817fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3818fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3819fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return 0; 3820fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley} 3821fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 382215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhekstatic void mv_conf_mbus_windows(struct mv_host_priv *hpriv, 382315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_target_info *dram) 382415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek{ 382515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek int i; 382615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 382715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < 4; i++) { 382815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_CTRL(i)); 382915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_BASE(i)); 383015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 383115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 383215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < dram->num_cs; i++) { 383315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_window *cs = dram->cs + i; 383415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 383515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(((cs->size - 1) & 0xffff0000) | 383615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (cs->mbus_attr << 8) | 383715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (dram->mbus_dram_target_id << 4) | 1, 383815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek hpriv->base + WINDOW_CTRL(i)); 383915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(cs->base, hpriv->base + WINDOW_BASE(i)); 384015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 384115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek} 384215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 3843f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/** 3844f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_probe - handle a positive probe of an soc Marvell 3845f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * host 3846f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device found 3847f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 3848f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * LOCKING: 3849f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Inherited from caller. 3850f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3851f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev) 3852f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3853f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara static int printed_version; 3854f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct mv_sata_platform_data *mv_platform_data; 3855f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct ata_port_info *ppi[] = 3856f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { &mv_port_info[chip_soc], NULL }; 3857f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host; 3858f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv; 3859f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct resource *res; 3860f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports, rc; 386120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3862f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!printed_version++) 3863f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 3864bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3865f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 3866f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Simple resource validation .. 3867f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3868f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (unlikely(pdev->num_resources != 2)) { 3869f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_err(&pdev->dev, "invalid number of resources\n"); 3870f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 3871f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 3872f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3873f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 3874f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Get the register base first 3875f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3876f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3877f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (res == NULL) 3878f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 3879f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3880f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* allocate host */ 3881f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_platform_data = pdev->dev.platform_data; 3882f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara n_ports = mv_platform_data->n_ports; 3883f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3884f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 3885f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 3886f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3887f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!host || !hpriv) 3888f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -ENOMEM; 3889f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->private_data = hpriv; 3890f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 3891f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3892f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->iomap = NULL; 3893f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara hpriv->base = devm_ioremap(&pdev->dev, res->start, 3894f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara res->end - res->start + 1); 3895f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base -= MV_SATAHC0_REG_BASE; 3896f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 389715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek /* 389815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek * (Re-)program MBUS remapping windows if we are asked to. 389915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek */ 390015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek if (mv_platform_data->dram != NULL) 390115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek mv_conf_mbus_windows(hpriv, mv_platform_data->dram); 390215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 3903fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley rc = mv_create_dma_pools(hpriv, &pdev->dev); 3904fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (rc) 3905fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return rc; 3906fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3907f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* initialize adapter */ 3908f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = mv_init_host(host, chip_soc); 3909f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc) 3910f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3911f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3912f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, 3913f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, 3914f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->n_ports); 3915f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3916f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, 3917f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara IRQF_SHARED, &mv6_sht); 3918f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3919f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3920f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* 3921f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 3922f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_remove - unplug a platform interface 3923f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device 3924f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 3925f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * A platform bus SATA device has been unplugged. Perform the needed 3926f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * cleanup. Also called on module unload for any active devices. 3927f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3928f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev) 3929f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3930f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct device *dev = &pdev->dev; 3931f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host = dev_get_drvdata(dev); 3932f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3933f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_host_detach(host); 3934f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 393520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 393620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3937f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic struct platform_driver mv_platform_driver = { 3938f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_platform_probe, 3939f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .remove = __devexit_p(mv_platform_remove), 3940f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .driver = { 3941f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .name = DRV_NAME, 3942f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .owner = THIS_MODULE, 3943f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 3944f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 3945f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3946f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 39477bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 3948f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 3949f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent); 3950f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 39517bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 39527bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic struct pci_driver mv_pci_driver = { 39537bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .name = DRV_NAME, 39547bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .id_table = mv_pci_tbl, 3955f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_pci_init_one, 39567bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .remove = ata_pci_remove_one, 39577bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara}; 39587bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 39597bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* move to PCI layer or libata core? */ 39607bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int pci_go_64(struct pci_dev *pdev) 39617bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara{ 39627bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc; 39637bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 39647bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 39657bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 39667bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 39677bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 39687bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 39697bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 39707bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "64-bit DMA enable failed\n"); 39717bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 39727bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 39737bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 39747bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } else { 39757bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 39767bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 39777bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 39787bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit DMA enable failed\n"); 39797bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 39807bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 39817bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 39827bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 39837bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 39847bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit consistent DMA enable failed\n"); 39857bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 39867bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 39877bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 39887bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 39897bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 39907bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara} 39917bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 399205b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 399305b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_print_info - Dump key info to kernel log for perusal. 39944447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to print info about 399505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 399605b308e1df6d9d673daedb517969241f41278b52Brett Russ * FIXME: complete this. 399705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 399805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 399905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 400005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 40014447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic void mv_print_info(struct ata_host *host) 400231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 40034447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 40044447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 400544c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok u8 scc; 4006c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik const char *scc_s, *gen; 400731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 400831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Use this to determine the HW stepping of the chip so we know 400931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * what errata to workaround 401031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 401131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 401231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (scc == 0) 401331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "SCSI"; 401431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else if (scc == 0x01) 401531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "RAID"; 401631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else 4017c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik scc_s = "?"; 4018c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik 4019c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik if (IS_GEN_I(hpriv)) 4020c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "I"; 4021c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_II(hpriv)) 4022c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "II"; 4023c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_IIE(hpriv)) 4024c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "IIE"; 4025c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else 4026c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "?"; 402731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 4028a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, 4029c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 4030c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 403131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 403231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 403331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 403405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 4035f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_pci_init_one - handle a positive probe of a PCI Marvell host 403605b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pdev: PCI device found 403705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ent: PCI device ID entry for the matched host 403805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 403905b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 404005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 404105b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 4042f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 4043f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent) 404420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 40452dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik static int printed_version; 404620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int board_idx = (unsigned int)ent->driver_data; 40474447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 40484447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct ata_host *host; 40494447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv; 40504447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo int n_ports, rc; 405120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4052a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik if (!printed_version++) 4053a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 405420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 40554447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* allocate host */ 40564447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 40574447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 40584447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 40594447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 40604447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (!host || !hpriv) 40614447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return -ENOMEM; 40624447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->private_data = hpriv; 4063f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 40644447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 40654447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* acquire resources */ 406624dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo rc = pcim_enable_device(pdev); 406724dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 406820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return rc; 406920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 40700d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 40710d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc == -EBUSY) 407224dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pcim_pin_device(pdev); 40730d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc) 407424dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 40754447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->iomap = pcim_iomap_table(pdev); 4076f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base = host->iomap[MV_PRIMARY_BAR]; 407720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4078d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik rc = pci_go_64(pdev); 4079d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik if (rc) 4080d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik return rc; 4081d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik 4082da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord rc = mv_create_dma_pools(hpriv, &pdev->dev); 4083da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (rc) 4084da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return rc; 4085da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 408620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* initialize adapter */ 40874447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_init_host(host, board_idx); 408824dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 408924dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 409020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 40916d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord /* Enable message-switched interrupts, if requested */ 40926d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord if (msi && pci_enable_msi(pdev) == 0) 40936d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord hpriv->hp_flags |= MV_HP_FLAG_MSI; 409420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 409531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 40964447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo mv_print_info(host); 409720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 40984447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo pci_set_master(pdev); 4099ea8b4db97aa41a66c05daa4055a1974692ccd52dJeff Garzik pci_try_set_mwi(pdev); 41004447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 4101c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 410220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 41037bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 410420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4105f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev); 4106f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev); 4107f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 410820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic int __init mv_init(void) 410920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 41107bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc = -ENODEV; 41117bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 41127bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_register_driver(&mv_pci_driver); 4113f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 4114f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 4115f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#endif 4116f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = platform_driver_register(&mv_platform_driver); 4117f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4118f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#ifdef CONFIG_PCI 4119f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 4120f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara pci_unregister_driver(&mv_pci_driver); 41217bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 41227bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 412320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 412420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 412520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic void __exit mv_exit(void) 412620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 41277bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 412820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ pci_unregister_driver(&mv_pci_driver); 41297bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 4130f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara platform_driver_unregister(&mv_platform_driver); 413120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 413220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 413320f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_AUTHOR("Brett Russ"); 413420f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 413520f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_LICENSE("GPL"); 413620f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DEVICE_TABLE(pci, mv_pci_tbl); 413720f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_VERSION(DRV_VERSION); 413817c5aab5b34e351531466e35b154ca86db7d46a9Mark LordMODULE_ALIAS("platform:" DRV_NAME); 413920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 414020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_init(mv_init); 414120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_exit(mv_exit); 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