sata_mv.c revision 299b3f8df90a3f7416d8df121d8a42b1a2aeced4
120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * sata_mv.c - Marvell SATA support 320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * Copyright 2008-2009: Marvell Corporation, all rights reserved. 58b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * Copyright 2005: EMC Corporation, all rights reserved. 6e2b1be56c5656902744c2b52e8304126a40bb609Jeff Garzik * Copyright 2005 Red Hat, Inc. All rights reserved. 720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 840f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * Originally written by Brett Russ. 940f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>. 1040f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * 1120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 1220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is free software; you can redistribute it and/or modify 1420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * it under the terms of the GNU General Public License as published by 1520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * the Free Software Foundation; version 2 of the License. 1620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is distributed in the hope that it will be useful, 1820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * but WITHOUT ANY WARRANTY; without even the implied warranty of 1920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 2020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * GNU General Public License for more details. 2120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * You should have received a copy of the GNU General Public License 2320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * along with this program; if not, write to the Free Software 2420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 2520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 284a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik/* 2985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * sata_mv TODO list: 3085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Develop a low-power-consumption strategy, and implement it. 3285afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 332b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds. 3485afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3585afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> [Experiment, Marvell value added] Is it possible to use target 3685afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * mode to cross-connect two Linux boxes with Marvell cards? If so, 3785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * creating LibATA target mode support would be very interesting. 3885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * Target mode, for those without docs, is the ability to directly 4085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * connect two SATA ports. 4185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord */ 424a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 4365ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord/* 4465ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * 80x1-B2 errata PCI#11: 4565ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * 4665ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * Users of the 6041/6081 Rev.B2 chips (current is C0) 4765ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * should be careful to insert those cards only onto PCI-X bus #0, 4865ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * and only in device slots 0..7, not higher. The chips may not 4965ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * work correctly otherwise (note: this is a pretty rare condition). 5065ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord */ 5165ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord 5220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/kernel.h> 5320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/module.h> 5420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/pci.h> 5520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/init.h> 5620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/blkdev.h> 5720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/delay.h> 5820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/interrupt.h> 598d8b60046d6a2328ca4b9031b4948084f775f607Andrew Morton#include <linux/dmapool.h> 6020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/dma-mapping.h> 61a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik#include <linux/device.h> 62f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/platform_device.h> 63f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/ata_platform.h> 6415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#include <linux/mbus.h> 65c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord#include <linux/bitops.h> 6620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <scsi/scsi_host.h> 67193515d51ccb363165d6b09e9ba5c21089e34badJeff Garzik#include <scsi/scsi_cmnd.h> 686c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik#include <scsi/scsi_device.h> 6920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/libata.h> 7020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#define DRV_NAME "sata_mv" 72cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord#define DRV_VERSION "1.28" 7320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord/* 7540f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * module options 7640f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord */ 7740f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord 7840f21b1124a9552bc093469280eb8239dc5f73d7Mark Lordstatic int msi; 7940f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord#ifdef CONFIG_PCI 8040f21b1124a9552bc093469280eb8239dc5f73d7Mark Lordmodule_param(msi, int, S_IRUGO); 8140f21b1124a9552bc093469280eb8239dc5f73d7Mark LordMODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 8240f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord#endif 8340f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord 842b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic int irq_coalescing_io_count; 852b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordmodule_param(irq_coalescing_io_count, int, S_IRUGO); 862b748a0a344847fe6b924407bbe153e1878c9f09Mark LordMODULE_PARM_DESC(irq_coalescing_io_count, 872b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord "IRQ coalescing I/O count threshold (0..255)"); 882b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 892b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic int irq_coalescing_usecs; 902b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordmodule_param(irq_coalescing_usecs, int, S_IRUGO); 912b748a0a344847fe6b924407bbe153e1878c9f09Mark LordMODULE_PARM_DESC(irq_coalescing_usecs, 922b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord "IRQ coalescing time threshold in usecs"); 932b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 9420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russenum { 9520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* BAR's are enumerated in terms of pci_resource_start() terms */ 9620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 9720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IO_BAR = 2, /* offset 0x18: IO space */ 9820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 9920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 10020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 10120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 10220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1032b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */ 1042b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */ 1052b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */ 1062b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord MAX_COAL_IO_COUNT = 255, /* completed I/O count */ 1072b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 10820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_BASE = 0, 109615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 1102b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 1112b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Per-chip ("all ports") interrupt coalescing feature. 1122b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * This is only for GEN_II / GEN_IIE hardware. 1132b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * 1142b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Coalescing defers the interrupt until either the IO_THRESHOLD 1152b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. 1162b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 117cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord COAL_REG_BASE = 0x18000, 118cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08), 1192b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */ 1202b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 121cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc), 122cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0), 1232b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 1242b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 1252b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Registers for the (unused here) transaction coalescing feature: 1262b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 127cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88), 128cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c), 1292b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 130cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATAHC0_REG_BASE = 0x20000, 131cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord FLASH_CTL = 0x1046c, 132cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord GPIO_PORT_CTL = 0x104f0, 133cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord RESET_CFG = 0x180d8, 13420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 13520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 13620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 13720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 13820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 13920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 14031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH = 32, 14131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 14231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* CRQB needs alignment on a 1KB boundary. Size == 1KB 14431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * CRPB needs alignment on a 256B boundary. Size == 256B 14531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 14631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 14731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 14831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 149da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord MV_MAX_SG_CT = 256, 15031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 15131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 152352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ 15320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_HC_SHIFT = 2, 154352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ 155352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ 156352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ 15720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 15820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Host Flags */ 15920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 1607bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 161c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 16291b1a84c10869e2e46a576e5367de3166bff8eccMark Lord ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING, 163ad3aef51e17b9c6a90a9014805f1645e8e441c17Mark Lord 16491b1a84c10869e2e46a576e5367de3166bff8eccMark Lord MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI, 16520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 16640f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ | 16740f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA, 16891b1a84c10869e2e46a576e5367de3166bff8eccMark Lord 16991b1a84c10869e2e46a576e5367de3166bff8eccMark Lord MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN, 170ad3aef51e17b9c6a90a9014805f1645e8e441c17Mark Lord 17131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_FLAG_READ = (1 << 0), 17231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_TAG_SHIFT = 1, 173c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 174e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 175c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 17631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_ADDR_SHIFT = 8, 17731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_CS = (0x2 << 11), 17831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_LAST = (1 << 15), 17931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 18031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRPB_FLAG_STATUS_SHIFT = 8, 181c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 182c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 18331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 18431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EPRD_FLAG_END_OF_TBL = (1 << 31), 18531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 18620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* PCI interface registers */ 18720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 188cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_COMMAND = 0xc00, 189cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */ 190cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */ 19131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 192cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_MAIN_CMD_STS = 0xd30, 19320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ STOP_PCI_MASTER = (1 << 2), 19420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MASTER_EMPTY = (1 << 3), 19520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GLOB_SFT_RST = (1 << 4), 19620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 197cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_MODE = 0xd00, 1988e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_MODE_MASK = 0x30, 1998e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 200522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 201522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_DISC_TIMER = 0xd04, 202522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MSI_TRIGGER = 0xc38, 203522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_SERR_MASK = 0xc28, 204cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_XBAR_TMOUT = 0x1d04, 205522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 206522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 207522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_ATTRIBUTE = 0x1d48, 208522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_COMMAND = 0x1d50, 209522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 210cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_IRQ_CAUSE = 0x1d58, 211cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_IRQ_MASK = 0x1d5c, 21220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 21320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 214cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCIE_IRQ_CAUSE = 0x1900, 215cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCIE_IRQ_MASK = 0x1910, 216646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 21702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 2187368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */ 219cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_HC_MAIN_IRQ_CAUSE = 0x1d60, 220cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_HC_MAIN_IRQ_MASK = 0x1d64, 221cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SOC_HC_MAIN_IRQ_CAUSE = 0x20020, 222cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SOC_HC_MAIN_IRQ_MASK = 0x20024, 22340f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord ERR_IRQ = (1 << 0), /* shift by (2 * port #) */ 22440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord DONE_IRQ = (1 << 1), /* shift by (2 * port #) */ 22520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 22620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 2272b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */ 2282b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */ 22920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_ERR = (1 << 18), 23040f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */ 23140f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */ 23240f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */ 23340f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */ 23440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */ 23520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GPIO_INT = (1 << 22), 23620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SELF_INT = (1 << 23), 23720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TWSI_INT = (1 << 24), 23820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 239fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 240e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 24120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 24220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATAHC registers */ 243cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord HC_CFG = 0x00, 24420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 245cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord HC_IRQ_CAUSE = 0x14, 246352fab701ca4753dd005b67ce5e512be944eb591Mark Lord DMA_IRQ = (1 << 0), /* shift by port # */ 247352fab701ca4753dd005b67ce5e512be944eb591Mark Lord HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ 24820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ DEV_IRQ = (1 << 8), /* shift by port # */ 24920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2502b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 2512b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Per-HC (Host-Controller) interrupt coalescing feature. 2522b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * This is present on all chip generations. 2532b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * 2542b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Coalescing defers the interrupt until either the IO_THRESHOLD 2552b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. 2562b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 257cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord HC_IRQ_COAL_IO_THRESHOLD = 0x000c, 258cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord HC_IRQ_COAL_TIME_THRESHOLD = 0x0010, 2592b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 260cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SOC_LED_CTRL = 0x2c, 261000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */ 262000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */ 263000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord /* with dev activity LED */ 264000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 26520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Shadow block registers */ 266cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SHD_BLK = 0x100, 267cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */ 26820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 26920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATA registers */ 270cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_STATUS = 0x300, /* ctrl, err regs follow status */ 271cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_ACTIVE = 0x350, 272cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord FIS_IRQ_CAUSE = 0x364, 273cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */ 27417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 275cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord LTMODE = 0x30c, /* requires read-after-write */ 27617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 27717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 278cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PHY_MODE2 = 0x330, 27947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik PHY_MODE3 = 0x310, 280cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord 281cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PHY_MODE4 = 0x314, /* requires read-after-write */ 282ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */ 283ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */ 284ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */ 285ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */ 286ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord 287cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_IFCTL = 0x344, 288cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_TESTCTL = 0x348, 289cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_IFSTAT = 0x34c, 290cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord VENDOR_UNIQUE_FIS = 0x35c, 29117c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 292cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord FISCFG = 0x360, 2938e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */ 2948e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 29517c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 296c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_MODE = 0x74, 297cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV5_LTMODE = 0x30, 298cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV5_PHY_CTL = 0x0C, 299cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_IFCFG = 0x050, 300bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 301bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_M2_PREAMP_MASK = 0x7e0, 30220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Port registers */ 304cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_CFG = 0, 3050c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 3060c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 3070c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 3080c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 3090c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 310e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 311e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 31220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 313cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_ERR_IRQ_CAUSE = 0x8, 314cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_ERR_IRQ_MASK = 0xc, 3156c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 3166c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 3176c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV = (1 << 2), /* device error */ 3186c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 3196c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 3206c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 321c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 322c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 3236c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 324c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 3256c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 3266c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 3276c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 3286c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 329646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3306c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 331646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 332646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 333646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 334646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 335646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3366c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 337646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3386c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 339646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 340646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 341646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 342646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 343646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 344646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3456c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 346646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3476c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 348c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_OVERRUN_5 = (1 << 5), 349c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_UNDERRUN_5 = (1 << 6), 350646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 351646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 352646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 | 353646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 | 35485afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord EDMA_ERR_LNK_CTRL_TX, 355646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 356bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 357bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 358bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 359bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 360bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SERR | 361bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS | 3626c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 363bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 364bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 365bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY | 366bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_CTRL_RX_2 | 367bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_RX | 368bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_TX | 369bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_TRANS_PROTO, 370e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 371bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 372bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 373bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 374bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 375bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_OVERRUN_5 | 376bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_UNDERRUN_5 | 377bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS_5 | 3786c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 379bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 380bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 381bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY, 38220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 383cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_REQ_Q_BASE_HI = 0x10, 384cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */ 38531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 386cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_REQ_Q_OUT_PTR = 0x18, 38731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_PTR_SHIFT = 5, 38831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 389cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_RSP_Q_BASE_HI = 0x1c, 390cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_RSP_Q_IN_PTR = 0x20, 391cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */ 39231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_PTR_SHIFT = 3, 39331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 394cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_CMD = 0x28, /* EDMA command register */ 3950ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_EN = (1 << 0), /* enable EDMA */ 3960ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 3978e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */ 3988e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 399cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_STATUS = 0x30, /* EDMA engine status */ 4008e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */ 4018e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */ 40220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 403cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_IORDY_TMOUT = 0x34, 404cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_ARB_CFG = 0x38, 4058e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 406cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */ 407cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */ 408da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 409cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord BMDMA_CMD = 0x224, /* bmdma command register */ 410cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord BMDMA_STATUS = 0x228, /* bmdma status register */ 411cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */ 412cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */ 413da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 41431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Host private flags (hp_flags) */ 41531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_HP_FLAG_MSI = (1 << 0), 41647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB0 = (1 << 1), 41747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB2 = (1 << 2), 41847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1B2 = (1 << 3), 41947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1C0 = (1 << 4), 4200ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 4210ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 4220ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 42302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 424616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ 4251f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */ 426000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */ 42720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 42831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Port private flags (pp_flags) */ 4290ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 430721091685f853ba4e6c49f26f989db0b1a811250Mark Lord MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 43100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */ 43229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */ 433d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */ 43420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 43520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 436ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 437ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 438e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 4398e7decdb8b132ee970a2636931b7653dec6af472Mark Lord#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) 4401f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC) 441bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 44215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 44315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_BASE(i) (0x20034 + ((i) << 4)) 44415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 445095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzikenum { 446baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik /* DMA boundary 0xffff is required by the s/g splitting 447baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik * we need on /length/ in mv_fill-sg(). 448baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik */ 449baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik MV_DMA_BOUNDARY = 0xffffU, 450095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 4510ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* mask of register bits containing lower 32 bits 4520ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik * of EDMA request queue DMA address 4530ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik */ 454095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 455095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 4560ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* ditto, for response queue */ 457095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 458095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik}; 459095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 460522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikenum chip_type { 461522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_504x, 462522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_508x, 463522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_5080, 464522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_604x, 465522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_608x, 466e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_6042, 467e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_7042, 468f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara chip_soc, 469522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik}; 470522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 47131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ReQuest Block: 32B */ 47231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crqb { 473e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr; 474e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr_hi; 475e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ctrl_flags; 476e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ata_cmd[11]; 47731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 47820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 479e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstruct mv_crqb_iie { 480e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 481e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 482e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags; 483e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 len; 484e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 ata_cmd[4]; 485e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 486e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 48731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ResPonse Block: 8B */ 48831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crpb { 489e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 id; 490e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 flags; 491e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 tmstmp; 49220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 49320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 49431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 49531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_sg { 496e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 497e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags_size; 498e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 499e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 reserved; 50031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 50120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 50208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord/* 50308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * We keep a local cache of a few frequently accessed port 50408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * registers here, to avoid having to read them (very slow) 50508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * when switching between EDMA and non-EDMA modes. 50608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord */ 50708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstruct mv_cached_regs { 50808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 fiscfg; 50908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 ltmode; 51008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 haltcond; 511c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord u32 unknown_rsvd; 51208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord}; 51308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 51431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_port_priv { 51531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crqb *crqb; 51631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crqb_dma; 51731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crpb *crpb; 51831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crpb_dma; 519eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 520eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 521bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 522bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int req_idx; 523bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int resp_idx; 524bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 52531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 pp_flags; 52608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord struct mv_cached_regs cached; 52729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int delayed_eh_pmp_map; 52831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 52931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 530bca1c4eb9411533d613123618c0d127fae532595Jeff Garzikstruct mv_port_signal { 531bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 amps; 532bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 pre; 533bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik}; 534bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 53502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lordstruct mv_host_priv { 53602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 hp_flags; 53796e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord u32 main_irq_mask; 53802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_port_signal signal[8]; 53902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord const struct mv_hw_ops *ops; 540f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports; 541f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *base; 5427368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_cause_addr; 5437368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_mask_addr; 544cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 irq_cause_offset; 545cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 irq_mask_offset; 54602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 unmask_all_irqs; 547da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord /* 548da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * These consistent DMA memory pools give us guaranteed 549da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * alignment for hardware-accessed data structures, 550da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * and less memory waste in accomplishing the alignment. 551da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord */ 552da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crqb_pool; 553da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crpb_pool; 554da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *sg_tbl_pool; 55502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord}; 55602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 55747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstruct mv_hw_ops { 5582a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 5592a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 56047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 56147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 56247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 563c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 564c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 565522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 5667bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 56747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 56847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 56982ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 57082ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 57182ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 57282ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 57331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap); 57431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap); 5753e4a139107e497a741c26f8a377a10f214d63ec1Mark Lordstatic int mv_qc_defer(struct ata_queued_cmd *qc); 57631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc); 577e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc); 5789a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 579a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 580a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo unsigned long deadline); 581bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap); 582bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap); 583f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *dev); 58420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 5852a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5862a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 58747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 58847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 58947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 590c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 591c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 592522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 5937bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 59447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 5952a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5962a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 59747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 59847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 59947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 600c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 601c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 602522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 603f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 604f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 605f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 606f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 607f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 608f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc); 609f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 610f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 611f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 6127bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 613e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 614c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no); 615e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap); 616b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio); 61700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma); 61847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 619e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp); 620e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 621e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 622e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 623e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 62429d187bb1e30682e228ce461c487d78d945c3e4fMark Lordstatic void mv_pmp_error_handler(struct ata_port *ap); 6254c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic void mv_process_crpb_entries(struct ata_port *ap, 6264c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp); 62747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 628da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_sff_irq_clear(struct ata_port *ap); 629da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic int mv_check_atapi_dma(struct ata_queued_cmd *qc); 630da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_setup(struct ata_queued_cmd *qc); 631da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_start(struct ata_queued_cmd *qc); 632da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_stop(struct ata_queued_cmd *qc); 633da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic u8 mv_bmdma_status(struct ata_port *ap); 634d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lordstatic u8 mv_sff_check_status(struct ata_port *ap); 635da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 636eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 637eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * because we have to allow room for worst case splitting of 638eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * PRDs for 64K boundaries in mv_fill_sg(). 639eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 640c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv5_sht = { 64168d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BASE_SHT(DRV_NAME), 642baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 643c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .dma_boundary = MV_DMA_BOUNDARY, 644c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik}; 645c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 646c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv6_sht = { 64768d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_NCQ_SHT(DRV_NAME), 648138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .can_queue = MV_MAX_Q_DEPTH - 1, 649baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 65020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .dma_boundary = MV_DMA_BOUNDARY, 65120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 65220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 653029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv5_ops = { 654029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &ata_sff_port_ops, 655c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 656c96f1732e25362d10ee7bcac1df8412a2e6b7d23Alan Cox .lost_interrupt = ATA_OP_NULL, 657c96f1732e25362d10ee7bcac1df8412a2e6b7d23Alan Cox 6583e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord .qc_defer = mv_qc_defer, 659c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_prep = mv_qc_prep, 660c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_issue = mv_qc_issue, 661c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 662bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .freeze = mv_eh_freeze, 663bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .thaw = mv_eh_thaw, 664a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .hardreset = mv_hardreset, 665a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .error_handler = ata_std_error_handler, /* avoid SFF EH */ 666029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .post_internal_cmd = ATA_OP_NULL, 667bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 668c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_read = mv5_scr_read, 669c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_write = mv5_scr_write, 670c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 671c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_start = mv_port_start, 672c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_stop = mv_port_stop, 673c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik}; 674c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 675029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv6_ops = { 676029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv5_ops, 677f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord .dev_config = mv6_dev_config, 67820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_read = mv_scr_read, 67920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_write = mv_scr_write, 68020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 681e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_hardreset = mv_pmp_hardreset, 682e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_softreset = mv_softreset, 683e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .softreset = mv_softreset, 68429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord .error_handler = mv_pmp_error_handler, 685da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 68640f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord .sff_check_status = mv_sff_check_status, 687da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .sff_irq_clear = mv_sff_irq_clear, 688da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .check_atapi_dma = mv_check_atapi_dma, 689da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_setup = mv_bmdma_setup, 690da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_start = mv_bmdma_start, 691da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_stop = mv_bmdma_stop, 692da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_status = mv_bmdma_status, 69320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 69420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 695029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv_iie_ops = { 696029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv6_ops, 697029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .dev_config = ATA_OP_NULL, 698e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .qc_prep = mv_qc_prep_iie, 699e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 700e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 70198ac62defe529d04a192688f40d801a2d8fbcf98Arjan van de Venstatic const struct ata_port_info mv_port_info[] = { 70220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_504x */ 70391b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_I_FLAGS, 704c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 705bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 706c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 70720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 70820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_508x */ 70991b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 710c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 711bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 712c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 71320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 71447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik { /* chip_5080 */ 71591b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 716c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 717bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 718c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 71947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik }, 72020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_604x */ 72191b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_II_FLAGS, 722c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 723bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 724c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 72520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 72620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_608x */ 72791b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC, 728c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 729bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 730c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 73120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 732e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_6042 */ 73391b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_IIE_FLAGS, 734c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 735bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 736e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 737e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 738e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_7042 */ 73991b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_IIE_FLAGS, 740c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 741bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 742e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 743e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 744f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { /* chip_soc */ 74591b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_IIE_FLAGS, 746c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 74717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .udma_mask = ATA_UDMA6, 74817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .port_ops = &mv_iie_ops, 749f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 75020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 75120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7523b7d697dfb7d03edb87e50b743a7ecff029618e9Jeff Garzikstatic const struct pci_device_id mv_pci_tbl[] = { 7532d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 7542d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 7552d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 7562d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 75746c5784c8fa736c2bb42fe681189b86e99abdc2eMark Lord /* RocketRAID 1720/174x have different identifiers */ 75846c5784c8fa736c2bb42fe681189b86e99abdc2eMark Lord { PCI_VDEVICE(TTI, 0x1720), chip_6042 }, 7594462254ac6be9150aae87d54d388fc348d6fceadMark Lord { PCI_VDEVICE(TTI, 0x1740), chip_6042 }, 7604462254ac6be9150aae87d54d388fc348d6fceadMark Lord { PCI_VDEVICE(TTI, 0x1742), chip_6042 }, 7612d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 7622d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 7632d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 7642d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 7652d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 7662d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 7672d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 7682d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 7692d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 770d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger /* Adaptec 1430SA */ 771d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 772d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger 77302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Marvell 7042 support */ 7746a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 7756a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom 77602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Highpoint RocketRAID PCIe series */ 77702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 77802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 77902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 7802d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { } /* terminate list */ 78120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 78220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 78347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv5xxx_ops = { 78447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv5_phy_errata, 78547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv5_enable_leds, 78647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv5_read_preamp, 78747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv5_reset_hc, 788522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv5_reset_flash, 789522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv5_reset_bus, 79047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 79147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 79247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv6xxx_ops = { 79347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv6_phy_errata, 79447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv6_enable_leds, 79547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv6_read_preamp, 79647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv6_reset_hc, 797522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv6_reset_flash, 798522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv_reset_pci_bus, 79947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 80047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 801f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic const struct mv_hw_ops mv_soc_ops = { 802f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .phy_errata = mv6_phy_errata, 803f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .enable_leds = mv_soc_enable_leds, 804f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .read_preamp = mv_soc_read_preamp, 805f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_hc = mv_soc_reset_hc, 806f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_flash = mv_soc_reset_flash, 807f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_bus = mv_soc_reset_bus, 808f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 809f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 81020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 81120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Functions 81220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 81320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 81420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void writelfl(unsigned long data, void __iomem *addr) 81520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 81620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writel(data, addr); 81720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ (void) readl(addr); /* flush to avoid PCI posted write */ 81820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 81920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 820c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hc_from_port(unsigned int port) 821c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 822c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port >> MV_PORT_HC_SHIFT; 823c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 824c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 825c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hardport_from_port(unsigned int port) 826c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 827c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port & MV_PORT_MASK; 828c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 829c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 8301cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord/* 8311cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Consolidate some rather tricky bit shift calculations. 8321cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * This is hot-path stuff, so not a function. 8331cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Simple code, with two return values, so macro rather than inline. 8341cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 8351cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * port is the sole input, in range 0..7. 8367368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * shift is one output, for use with main_irq_cause / main_irq_mask registers. 8377368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * hardport is the other output, in range 0..3. 8381cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 8391cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Note that port and hardport may be the same variable in some cases. 8401cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord */ 8411cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ 8421cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord{ \ 8431cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift = mv_hc_from_port(port) * HC_SHIFT; \ 8441cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord hardport = mv_hardport_from_port(port); \ 8451cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift += hardport * 2; \ 8461cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord} 8471cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord 848352fab701ca4753dd005b67ce5e512be944eb591Mark Lordstatic inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 849352fab701ca4753dd005b67ce5e512be944eb591Mark Lord{ 850cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 851352fab701ca4753dd005b67ce5e512be944eb591Mark Lord} 852352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 853c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline void __iomem *mv_hc_base_from_port(void __iomem *base, 854c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 855c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 856c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base(base, mv_hc_from_port(port)); 857c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 858c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 85920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 86020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 861c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base_from_port(base, port) + 8628b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik MV_SATAHC_ARBTR_REG_SZ + 863c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 86420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 86520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 866e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 867e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord{ 868e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 869e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 870e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 871e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord return hc_mmio + ofs; 872e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord} 873e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 874f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic inline void __iomem *mv_host_base(struct ata_host *host) 875f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 876f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 877f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return hpriv->base; 878f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 879f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 88020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_ap_base(struct ata_port *ap) 88120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 882f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return mv_port_base(mv_host_base(ap->host), ap->port_no); 88320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 88420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 885cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic inline int mv_get_hc_count(unsigned long port_flags) 88631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 887cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 88831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 88931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 89008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord/** 89108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * mv_save_cached_regs - (re-)initialize cached port registers 89208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @ap: the port whose registers we are caching 89308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * 89408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * Initialize the local cache of port registers, 89508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * so that reading them over and over again can 89608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * be avoided on the hotter paths of this driver. 89708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * This saves a few microseconds each time we switch 89808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * to/from EDMA mode to perform (eg.) a drive cache flush. 89908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord */ 90008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstatic void mv_save_cached_regs(struct ata_port *ap) 90108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord{ 90208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 90308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord struct mv_port_priv *pp = ap->private_data; 90408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 905cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord pp->cached.fiscfg = readl(port_mmio + FISCFG); 906cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord pp->cached.ltmode = readl(port_mmio + LTMODE); 907cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND); 908cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD); 90908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord} 91008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 91108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord/** 91208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * mv_write_cached_reg - write to a cached port register 91308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @addr: hardware address of the register 91408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @old: pointer to cached value of the register 91508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @new: new value for the register 91608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * 91708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * Write a new value to a cached register, 91808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * but only if the value is different from before. 91908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord */ 92008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstatic inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new) 92108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord{ 92208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord if (new != *old) { 92312f3b6d7551306c00cf834540a33184de67c9187Mark Lord unsigned long laddr; 92408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord *old = new; 92512f3b6d7551306c00cf834540a33184de67c9187Mark Lord /* 92612f3b6d7551306c00cf834540a33184de67c9187Mark Lord * Workaround for 88SX60x1-B2 FEr SATA#13: 92712f3b6d7551306c00cf834540a33184de67c9187Mark Lord * Read-after-write is needed to prevent generating 64-bit 92812f3b6d7551306c00cf834540a33184de67c9187Mark Lord * write cycles on the PCI bus for SATA interface registers 92912f3b6d7551306c00cf834540a33184de67c9187Mark Lord * at offsets ending in 0x4 or 0xc. 93012f3b6d7551306c00cf834540a33184de67c9187Mark Lord * 93112f3b6d7551306c00cf834540a33184de67c9187Mark Lord * Looks like a lot of fuss, but it avoids an unnecessary 93212f3b6d7551306c00cf834540a33184de67c9187Mark Lord * +1 usec read-after-write delay for unaffected registers. 93312f3b6d7551306c00cf834540a33184de67c9187Mark Lord */ 93412f3b6d7551306c00cf834540a33184de67c9187Mark Lord laddr = (long)addr & 0xffff; 93512f3b6d7551306c00cf834540a33184de67c9187Mark Lord if (laddr >= 0x300 && laddr <= 0x33c) { 93612f3b6d7551306c00cf834540a33184de67c9187Mark Lord laddr &= 0x000f; 93712f3b6d7551306c00cf834540a33184de67c9187Mark Lord if (laddr == 0x4 || laddr == 0xc) { 93812f3b6d7551306c00cf834540a33184de67c9187Mark Lord writelfl(new, addr); /* read after write */ 93912f3b6d7551306c00cf834540a33184de67c9187Mark Lord return; 94012f3b6d7551306c00cf834540a33184de67c9187Mark Lord } 94112f3b6d7551306c00cf834540a33184de67c9187Mark Lord } 94212f3b6d7551306c00cf834540a33184de67c9187Mark Lord writel(new, addr); /* unaffected by the errata */ 94308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord } 94408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord} 94508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 946c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic void mv_set_edma_ptrs(void __iomem *port_mmio, 947c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_host_priv *hpriv, 948c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp) 949c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik{ 950bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 index; 951bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 952c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 953c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize request queue 954c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 955fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 956fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 957bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 958c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crqb_dma & 0x3ff); 959cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI); 960bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 961cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + EDMA_REQ_Q_IN_PTR); 962cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR); 963c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 964c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 965c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize response queue 966c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 967fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 968fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; 969bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 970c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crpb_dma & 0xff); 971cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI); 972cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR); 973bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 974cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + EDMA_RSP_Q_OUT_PTR); 975c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik} 976c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 9772b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv) 9782b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord{ 9792b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 9802b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * When writing to the main_irq_mask in hardware, 9812b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * we must ensure exclusivity between the interrupt coalescing bits 9822b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * and the corresponding individual port DONE_IRQ bits. 9832b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * 9842b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Note that this register is really an "IRQ enable" register, 9852b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * not an "IRQ mask" register as Marvell's naming might suggest. 9862b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 9872b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE)) 9882b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mask &= ~DONE_IRQ_0_3; 9892b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE)) 9902b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mask &= ~DONE_IRQ_4_7; 9912b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord writelfl(mask, hpriv->main_irq_mask_addr); 9922b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord} 9932b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 994c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lordstatic void mv_set_main_irq_mask(struct ata_host *host, 995c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 disable_bits, u32 enable_bits) 996c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord{ 997c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord struct mv_host_priv *hpriv = host->private_data; 998c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 old_mask, new_mask; 999c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 100096e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord old_mask = hpriv->main_irq_mask; 1001c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord new_mask = (old_mask & ~disable_bits) | enable_bits; 100296e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord if (new_mask != old_mask) { 100396e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord hpriv->main_irq_mask = new_mask; 10042b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_write_main_irq_mask(new_mask, hpriv); 100596e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord } 1006c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord} 1007c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 1008c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lordstatic void mv_enable_port_irqs(struct ata_port *ap, 1009c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int port_bits) 1010c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord{ 1011c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int shift, hardport, port = ap->port_no; 1012c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 disable_bits, enable_bits; 1013c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 1014c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 1015c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 1016c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord disable_bits = (DONE_IRQ | ERR_IRQ) << shift; 1017c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord enable_bits = port_bits << shift; 1018c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); 1019c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord} 1020c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 102100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_clear_and_enable_port_irqs(struct ata_port *ap, 102200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord void __iomem *port_mmio, 102300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord unsigned int port_irqs) 102400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord{ 102500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 102600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord int hardport = mv_hardport_from_port(ap->port_no); 102700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port( 102800b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_host_base(ap->host), ap->port_no); 102900b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord u32 hc_irq_cause; 103000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 103100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord /* clear EDMA event indicators, if any */ 1032cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 103300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 103400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord /* clear pending irq events */ 103500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 1036cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); 103700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 103800b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord /* clear FIS IRQ Cause */ 103900b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord if (IS_GEN_IIE(hpriv)) 1040cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, port_mmio + FIS_IRQ_CAUSE); 104100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 104200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_enable_port_irqs(ap, port_irqs); 104300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord} 104400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 10452b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic void mv_set_irq_coalescing(struct ata_host *host, 10462b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord unsigned int count, unsigned int usecs) 10472b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord{ 10482b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord struct mv_host_priv *hpriv = host->private_data; 10492b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord void __iomem *mmio = hpriv->base, *hc_mmio; 10502b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord u32 coal_enable = 0; 10512b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord unsigned long flags; 10526abf4678261218938ccdac90767d34ce9937634fMark Lord unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC; 10532b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 10542b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord ALL_PORTS_COAL_DONE; 10552b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 10562b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* Disable IRQ coalescing if either threshold is zero */ 10572b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (!usecs || !count) { 10582b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord clks = count = 0; 10592b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } else { 10602b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* Respect maximum limits of the hardware */ 10612b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord clks = usecs * COAL_CLOCKS_PER_USEC; 10622b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (clks > MAX_COAL_TIME_THRESHOLD) 10632b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord clks = MAX_COAL_TIME_THRESHOLD; 10642b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (count > MAX_COAL_IO_COUNT) 10652b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord count = MAX_COAL_IO_COUNT; 10662b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } 10672b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 10682b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord spin_lock_irqsave(&host->lock, flags); 10696abf4678261218938ccdac90767d34ce9937634fMark Lord mv_set_main_irq_mask(host, coal_disable, 0); 10702b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 10716abf4678261218938ccdac90767d34ce9937634fMark Lord if (is_dual_hc && !IS_GEN_I(hpriv)) { 10722b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 10736abf4678261218938ccdac90767d34ce9937634fMark Lord * GEN_II/GEN_IIE with dual host controllers: 10746abf4678261218938ccdac90767d34ce9937634fMark Lord * one set of global thresholds for the entire chip. 10752b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 1076cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD); 1077cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(count, mmio + IRQ_COAL_IO_THRESHOLD); 10782b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* clear leftover coal IRQ bit */ 1079cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); 10806abf4678261218938ccdac90767d34ce9937634fMark Lord if (count) 10816abf4678261218938ccdac90767d34ce9937634fMark Lord coal_enable = ALL_PORTS_COAL_DONE; 10826abf4678261218938ccdac90767d34ce9937634fMark Lord clks = count = 0; /* force clearing of regular regs below */ 10832b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } 10846abf4678261218938ccdac90767d34ce9937634fMark Lord 10852b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 10862b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * All chips: independent thresholds for each HC on the chip. 10872b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 10882b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord hc_mmio = mv_hc_base_from_port(mmio, 0); 1089cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); 1090cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); 1091cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); 10926abf4678261218938ccdac90767d34ce9937634fMark Lord if (count) 10936abf4678261218938ccdac90767d34ce9937634fMark Lord coal_enable |= PORTS_0_3_COAL_DONE; 10946abf4678261218938ccdac90767d34ce9937634fMark Lord if (is_dual_hc) { 10952b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC); 1096cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); 1097cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); 1098cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); 10996abf4678261218938ccdac90767d34ce9937634fMark Lord if (count) 11006abf4678261218938ccdac90767d34ce9937634fMark Lord coal_enable |= PORTS_4_7_COAL_DONE; 11012b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } 11022b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 11036abf4678261218938ccdac90767d34ce9937634fMark Lord mv_set_main_irq_mask(host, 0, coal_enable); 11042b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord spin_unlock_irqrestore(&host->lock, flags); 11052b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord} 11062b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 110705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 110800b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord * mv_start_edma - Enable eDMA engine 110905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @base: port base address 111005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pp: port private data 111105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 1112beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * Verify the local cache of the eDMA state is accurate with a 1113beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * WARN_ON. 111405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 111505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 111605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 111705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 111800b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio, 1119721091685f853ba4e6c49f26f989db0b1a811250Mark Lord struct mv_port_priv *pp, u8 protocol) 112020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1121721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int want_ncq = (protocol == ATA_PROT_NCQ); 1122721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1123721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 1124721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 1125721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq != using_ncq) 1126b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 1127721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } 1128c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 11290c58912e192fc3a4835d772aafa40b72552b819fMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 11300c58912e192fc3a4835d772aafa40b72552b819fMark Lord 113100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_edma_cfg(ap, want_ncq, 1); 11320c58912e192fc3a4835d772aafa40b72552b819fMark Lord 1133f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord mv_set_edma_ptrs(port_mmio, hpriv, pp); 113400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ); 1135bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1136cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(EDMA_EN, port_mmio + EDMA_CMD); 1137afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 1138afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 113920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 114020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 11419b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lordstatic void mv_wait_for_edma_empty_idle(struct ata_port *ap) 11429b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord{ 11439b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 11449b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE); 11459b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const int per_loop = 5, timeout = (15 * 1000 / per_loop); 11469b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord int i; 11479b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 11489b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord /* 11499b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord * Wait for the EDMA engine to finish transactions in progress. 1150c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * No idea what a good "timeout" value might be, but measurements 1151c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * indicate that it often requires hundreds of microseconds 1152c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * with two drives in-use. So we use the 15msec value above 1153c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * as a rough guess at what even more drives might require. 11549b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord */ 11559b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord for (i = 0; i < timeout; ++i) { 1156cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 edma_stat = readl(port_mmio + EDMA_STATUS); 11579b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord if ((edma_stat & empty_idle) == empty_idle) 11589b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord break; 11599b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord udelay(per_loop); 11609b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord } 11619b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */ 11629b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord} 11639b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 116405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1165e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * mv_stop_edma_engine - Disable eDMA engine 1166b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * @port_mmio: io base address 116705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 116805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 116905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 117005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 1171b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio) 117220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1173b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord int i; 117431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1175b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Disable eDMA. The disable bit auto clears. */ 1176cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(EDMA_DS, port_mmio + EDMA_CMD); 11778b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 1178b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Wait for the chip to confirm eDMA is off. */ 1179b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord for (i = 10000; i > 0; i--) { 1180cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 reg = readl(port_mmio + EDMA_CMD); 11814537deb5e90b717a725b3d74b58b4bb1d28443d0Jeff Garzik if (!(reg & EDMA_EN)) 1182b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 1183b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord udelay(10); 118431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 1185b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 118620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 118720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1188e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap) 11890ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik{ 1190b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord void __iomem *port_mmio = mv_ap_base(ap); 1191b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 119266e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord int err = 0; 11930ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 1194b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 1195b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 1196b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 11979b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord mv_wait_for_edma_empty_idle(ap); 1198b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (mv_stop_edma_engine(port_mmio)) { 1199b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); 120066e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord err = -EIO; 1201b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord } 120266e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord mv_edma_cfg(ap, 0, 0); 120366e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord return err; 12040ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik} 12050ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 12068a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#ifdef ATA_DEBUG 120731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_mem(void __iomem *start, unsigned bytes) 120820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 120931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 121031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 121131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%p: ", start + b); 121231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 12132dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", readl(start + b)); 121431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 121531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 121631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 121731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 121831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 12198a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#endif 12208a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik 122131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 122231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 122331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 122431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 122531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 dw; 122631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 122731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%02x: ", b); 122831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 12292dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik (void) pci_read_config_dword(pdev, b, &dw); 12302dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", dw); 123131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 123231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 123331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 123431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 123531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 123631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 123731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_all_regs(void __iomem *mmio_base, int port, 123831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct pci_dev *pdev) 123931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 124031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 12418b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik void __iomem *hc_base = mv_hc_base(mmio_base, 124231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port >> MV_PORT_HC_SHIFT); 124331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_base; 124431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int start_port, num_ports, p, start_hc, num_hcs, hc; 124531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 124631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (0 > port) { 124731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = start_port = 0; 124831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = 8; /* shld be benign for 4 port devs */ 124931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_hcs = 2; 125031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } else { 125131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = port >> MV_PORT_HC_SHIFT; 125231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_port = port; 125331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = num_hcs = 1; 125431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 12558b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik DPRINTK("All registers for port(s) %u-%u:\n", start_port, 125631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports > 1 ? num_ports - 1 : start_port); 125731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 125831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (NULL != pdev) { 125931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI config space regs:\n"); 126031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 126131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 126231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI regs:\n"); 126331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xc00, 0x3c); 126431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xd00, 0x34); 126531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xf00, 0x4); 126631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0x1d00, 0x6c); 126731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 1268d220c37e0a3c9a47ae00e87e044d963b3ea040bcDan Aloni hc_base = mv_hc_base(mmio_base, hc); 126931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("HC regs (HC %i):\n", hc); 127031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(hc_base, 0x1c); 127131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 127231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (p = start_port; p < start_port + num_ports; p++) { 127331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port_base = mv_port_base(mmio_base, p); 12742dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("EDMA regs (port %i):\n", p); 127531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base, 0x54); 12762dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("SATA regs (port %i):\n", p); 127731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base+0x300, 0x60); 127831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 127931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 128020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 128120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 128220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic unsigned int mv_scr_offset(unsigned int sc_reg_in) 128320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 128420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs; 128520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 128620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ switch (sc_reg_in) { 128720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_STATUS: 128820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_CONTROL: 128920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ERROR: 1290cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ofs = SATA_STATUS + (sc_reg_in * sizeof(u32)); 129120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 129220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ACTIVE: 1293cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ofs = SATA_ACTIVE; /* active is not with the others */ 129420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 129520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ default: 129620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = 0xffffffffU; 129720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 129820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 129920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return ofs; 130020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 130120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 130282ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 130320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 130420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 130520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1306da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 130782ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo *val = readl(mv_ap_base(link->ap) + ofs); 1308da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1309da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1310da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 131120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 131220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 131382ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 131420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 131520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 131620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1317da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 13182009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord void __iomem *addr = mv_ap_base(link->ap) + ofs; 13192009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord if (sc_reg_in == SCR_CONTROL) { 13202009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord /* 13212009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * Workaround for 88SX60x1 FEr SATA#26: 13222009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * 13232009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * COMRESETs have to take care not to accidently 13242009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * put the drive to sleep when writing SCR_CONTROL. 13252009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * Setting bits 12..15 prevents this problem. 13262009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * 13272009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * So if we see an outbound COMMRESET, set those bits. 13282009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * Ditto for the followup write that clears the reset. 13292009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * 13302009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * The proprietary driver does this for 13312009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * all chip versions, and so do we. 13322009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord */ 13332009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1) 13342009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord val |= 0xf000; 13352009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord } 13362009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord writelfl(val, addr); 1337da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1338da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1339da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 134020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 134120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1342f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *adev) 1343f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord{ 1344f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord /* 1345e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Deal with Gen-II ("mv6") hardware quirks/restrictions: 1346e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * 1347e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Gen-II does not support NCQ over a port multiplier 1348e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * (no FIS-based switching). 1349f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord */ 1350e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (adev->flags & ATA_DFLAG_NCQ) { 1351352fab701ca4753dd005b67ce5e512be944eb591Mark Lord if (sata_pmp_attached(adev->link->ap)) { 1352e49856d82a887ce365637176f9f99ab68076eae8Mark Lord adev->flags &= ~ATA_DFLAG_NCQ; 1353352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ata_dev_printk(adev, KERN_INFO, 1354352fab701ca4753dd005b67ce5e512be944eb591Mark Lord "NCQ disabled for command-based switching\n"); 1355352fab701ca4753dd005b67ce5e512be944eb591Mark Lord } 1356e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 1357f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1358f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 13593e4a139107e497a741c26f8a377a10f214d63ec1Mark Lordstatic int mv_qc_defer(struct ata_queued_cmd *qc) 13603e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord{ 13613e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct ata_link *link = qc->dev->link; 13623e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct ata_port *ap = link->ap; 13633e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct mv_port_priv *pp = ap->private_data; 13643e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 13653e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord /* 136629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * Don't allow new commands if we're in a delayed EH state 136729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * for NCQ and/or FIS-based switching. 136829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord */ 136929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 137029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord return ATA_DEFER_PORT; 137129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord /* 13723e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * If the port is completely idle, then allow the new qc. 13733e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord */ 13743e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (ap->nr_active_links == 0) 13753e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return 0; 13763e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 13774bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo /* 13784bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * The port is operating in host queuing mode (EDMA) with NCQ 13794bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * enabled, allow multiple NCQ commands. EDMA also allows 13804bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * queueing multiple DMA commands but libata core currently 13814bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * doesn't allow it. 13824bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo */ 13834bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) && 13844bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol)) 13854bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo return 0; 13864bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo 13873e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return ATA_DEFER_PORT; 13883e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord} 13893e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 139008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstatic void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs) 1391e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 139208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord struct mv_port_priv *pp = ap->private_data; 139308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord void __iomem *port_mmio; 139400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 139508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg; 139608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 ltmode, *old_ltmode = &pp->cached.ltmode; 139708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 haltcond, *old_haltcond = &pp->cached.haltcond; 139800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 139908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord ltmode = *old_ltmode & ~LTMODE_BIT8; 140008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord haltcond = *old_haltcond | EDMA_ERR_DEV; 140100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 140200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (want_fbs) { 140308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC; 140408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord ltmode = *old_ltmode | LTMODE_BIT8; 14054c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (want_ncq) 140608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord haltcond &= ~EDMA_ERR_DEV; 14074c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord else 140808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord fiscfg |= FISCFG_WAIT_DEV_ERR; 140908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord } else { 141008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR); 1411e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 141200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 141308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord port_mmio = mv_ap_base(ap); 1414cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg); 1415cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode); 1416cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond); 1417f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1418f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 1419dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lordstatic void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq) 1420dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord{ 1421dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1422dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord u32 old, new; 1423dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord 1424dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord /* workaround for 88SX60x1 FEr SATA#25 (part 1) */ 1425cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord old = readl(hpriv->base + GPIO_PORT_CTL); 1426dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord if (want_ncq) 1427dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord new = old | (1 << 22); 1428dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord else 1429dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord new = old & ~(1 << 22); 1430dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord if (new != old) 1431cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(new, hpriv->base + GPIO_PORT_CTL); 1432dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord} 1433dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord 1434c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord/** 143540f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma 143640f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * @ap: Port being initialized 1437c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * 1438c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * There are two DMA modes on these chips: basic DMA, and EDMA. 1439c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * 1440c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * Bit-0 of the "EDMA RESERVED" register enables/disables use 1441c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * of basic DMA on the GEN_IIE versions of the chips. 1442c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * 1443c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * This bit survives EDMA resets, and must be set for basic DMA 1444c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * to function, and should be cleared when EDMA is active. 1445c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord */ 1446c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lordstatic void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma) 1447c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord{ 1448c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord struct mv_port_priv *pp = ap->private_data; 1449c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord u32 new, *old = &pp->cached.unknown_rsvd; 1450c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord 1451c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord if (enable_bmdma) 1452c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord new = *old | 1; 1453c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord else 1454c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord new = *old & ~1; 1455cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new); 1456c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord} 1457c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord 1458000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord/* 1459000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * SOC chips have an issue whereby the HDD LEDs don't always blink 1460000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * during I/O when NCQ is enabled. Enabling a special "LED blink" mode 1461000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * of the SOC takes care of it, generating a steady blink rate when 1462000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * any drive on the chip is active. 1463000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * 1464000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * Unfortunately, the blink mode is a global hardware setting for the SOC, 1465000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * so we must use it whenever at least one port on the SOC has NCQ enabled. 1466000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * 1467000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * We turn "LED blink" off when NCQ is not in use anywhere, because the normal 1468000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * LED operation works then, and provides better (more accurate) feedback. 1469000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * 1470000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * Note that this code assumes that an SOC never has more than one HC onboard. 1471000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord */ 1472000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lordstatic void mv_soc_led_blink_enable(struct ata_port *ap) 1473000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord{ 1474000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct ata_host *host = ap->host; 1475000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct mv_host_priv *hpriv = host->private_data; 1476000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord void __iomem *hc_mmio; 1477000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord u32 led_ctrl; 1478000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1479000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN) 1480000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord return; 1481000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN; 1482000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); 1483cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord led_ctrl = readl(hc_mmio + SOC_LED_CTRL); 1484cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); 1485000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord} 1486000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1487000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lordstatic void mv_soc_led_blink_disable(struct ata_port *ap) 1488000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord{ 1489000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct ata_host *host = ap->host; 1490000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct mv_host_priv *hpriv = host->private_data; 1491000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord void __iomem *hc_mmio; 1492000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord u32 led_ctrl; 1493000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord unsigned int port; 1494000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1495000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)) 1496000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord return; 1497000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1498000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord /* disable led-blink only if no ports are using NCQ */ 1499000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord for (port = 0; port < hpriv->n_ports; port++) { 1500000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct ata_port *this_ap = host->ports[port]; 1501000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct mv_port_priv *pp = this_ap->private_data; 1502000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1503000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 1504000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord return; 1505000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord } 1506000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1507000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN; 1508000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); 1509cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord led_ctrl = readl(hc_mmio + SOC_LED_CTRL); 1510cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); 1511000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord} 1512000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 151300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma) 1514e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 15150c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 cfg; 1516e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_port_priv *pp = ap->private_data; 1517e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1518e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1519e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1520e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* set up non-NCQ EDMA configuration */ 15210c58912e192fc3a4835d772aafa40b72552b819fMark Lord cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 1522d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= 1523d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 1524e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 15250c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (IS_GEN_I(hpriv)) 1526e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 8); /* enab config burst size mask */ 1527e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1528dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord else if (IS_GEN_II(hpriv)) { 1529e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1530dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord mv_60x1_errata_sata25(ap, want_ncq); 1531e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1532dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord } else if (IS_GEN_IIE(hpriv)) { 153300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord int want_fbs = sata_pmp_attached(ap); 153400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord /* 153500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * Possible future enhancement: 153600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * 153700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * The chip can use FBS with non-NCQ, if we allow it, 153800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * But first we need to have the error handling in place 153900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * for this mode (datasheet section 7.3.15.4.2.3). 154000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * So disallow non-NCQ FBS for now. 154100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord */ 154200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord want_fbs &= want_ncq; 154300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 154408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_config_fbs(ap, want_ncq, want_fbs); 154500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 154600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (want_fbs) { 154700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord pp->pp_flags |= MV_PP_FLAG_FBS_EN; 154800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ 154900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord } 155000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 1551e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 155200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord if (want_edma) { 155300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord cfg |= (1 << 22); /* enab 4-entry host queue cache */ 155400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord if (!IS_SOC(hpriv)) 155500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord cfg |= (1 << 18); /* enab early completion */ 155600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord } 1557616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (hpriv->hp_flags & MV_HP_CUT_THROUGH) 1558616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ 1559c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord mv_bmdma_enable_iie(ap, !want_edma); 1560000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1561000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (IS_SOC(hpriv)) { 1562000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (want_ncq) 1563000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord mv_soc_led_blink_enable(ap); 1564000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord else 1565000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord mv_soc_led_blink_disable(ap); 1566000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord } 1567e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 1568e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1569721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq) { 1570721091685f853ba4e6c49f26f989db0b1a811250Mark Lord cfg |= EDMA_CFG_NCQ; 1571721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 157200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord } 1573721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1574cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(cfg, port_mmio + EDMA_CFG); 1575e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1576e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1577da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordstatic void mv_port_free_dma_mem(struct ata_port *ap) 1578da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord{ 1579da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1580da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_port_priv *pp = ap->private_data; 1581eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord int tag; 1582da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1583da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crqb) { 1584da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1585da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = NULL; 1586da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1587da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crpb) { 1588da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1589da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = NULL; 1590da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1591eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1592eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1593eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we have one unique sg_tbl per NCQ tag. 1594eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1595eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1596eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (pp->sg_tbl[tag]) { 1597eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) 1598eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_pool_free(hpriv->sg_tbl_pool, 1599eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag], 1600eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag]); 1601eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = NULL; 1602eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1603da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1604da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord} 1605da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 160605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 160705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_start - Port specific init/start routine. 160805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 160905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 161005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Allocate and point to DMA memory, init port private memory, 161105b308e1df6d9d673daedb517969241f41278b52Brett Russ * zero indices. 161205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 161305b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 161405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 161505b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 161631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap) 161731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1618cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct device *dev = ap->host->dev; 1619cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 162031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp; 1621933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord unsigned long flags; 1622dde2020754aeb14e17052d61784dcb37f252aac2James Bottomley int tag; 162331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 162424dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 16256037d6bbdff65eb5a84fe35e140f4da4f7cc103aJeff Garzik if (!pp) 162624dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return -ENOMEM; 1627da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord ap->private_data = pp; 162831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1629da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1630da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crqb) 1631da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 1632da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crqb, 0, MV_CRQB_Q_SZ); 163331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1634da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1635da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crpb) 1636da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord goto out_port_free_dma_mem; 1637da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crpb, 0, MV_CRPB_Q_SZ); 163831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 16393bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */ 16403bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) 16413bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord ap->flags |= ATA_FLAG_AN; 1642eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1643eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1644eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we need one unique sg_tbl per NCQ tag. 1645eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1646eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1647eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) { 1648eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1649eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1650eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (!pp->sg_tbl[tag]) 1651eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord goto out_port_free_dma_mem; 1652eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } else { 1653eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = pp->sg_tbl[0]; 1654eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1655eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1656eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1657933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord 1658933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_lock_irqsave(ap->lock, flags); 165908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_save_cached_regs(ap); 166066e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord mv_edma_cfg(ap, 0, 0); 1661933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_unlock_irqrestore(ap->lock, flags); 1662933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord 166331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 1664da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1665da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordout_port_free_dma_mem: 1666da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 1667da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 166831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 166931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 167005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 167105b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_stop - Port specific cleanup/stop routine. 167205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 167305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 167405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Stop DMA, cleanup port memory. 167505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 167605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 1677cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine uses the host lock to protect the DMA stop. 167805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 167931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap) 168031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1681933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord unsigned long flags; 1682933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord 1683933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_lock_irqsave(ap->lock, flags); 1684e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma(ap); 168588e675e193159b9891c1c576de4348eaf490f5d0Mark Lord mv_enable_port_irqs(ap, 0); 1686933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_unlock_irqrestore(ap->lock, flags); 1687da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 168831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 168931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 169005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 169105b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 169205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command whose SG list to source from 169305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 169405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Populate the SG list and mark the last entry. 169505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 169605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 169705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 169805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 16996c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzikstatic void mv_fill_sg(struct ata_queued_cmd *qc) 170031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 170131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = qc->ap->private_data; 1702972c26bdd6b58e7534473c4f7928584578cf43f4Jeff Garzik struct scatterlist *sg; 17033be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik struct mv_sg *mv_sg, *last_sg = NULL; 1704ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo unsigned int si; 170531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1706eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord mv_sg = pp->sg_tbl[qc->tag]; 1707ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 1708d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik dma_addr_t addr = sg_dma_address(sg); 1709d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik u32 sg_len = sg_dma_len(sg); 171022374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 17114007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson while (sg_len) { 17124007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 offset = addr & 0xffff; 17134007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 len = sg_len; 171422374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 171532cd11a61007511ddb38783deec8bb1aa6735789Mark Lord if (offset + len > 0x10000) 17164007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson len = 0x10000 - offset; 17174007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 17184007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 17194007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 17206c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik mv_sg->flags_size = cpu_to_le32(len & 0xffff); 172132cd11a61007511ddb38783deec8bb1aa6735789Mark Lord mv_sg->reserved = 0; 17224007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 17234007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson sg_len -= len; 17244007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson addr += len; 17254007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 17263be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg = mv_sg; 17274007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg++; 17284007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson } 172931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 17303be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik 17313be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik if (likely(last_sg)) 17323be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 173332cd11a61007511ddb38783deec8bb1aa6735789Mark Lord mb(); /* ensure data structure is visible to the chipset */ 173431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 173531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 17365796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzikstatic void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 173731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1738559eedad7f7764dacca33980127b4615011230e4Mark Lord u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 173931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ (last ? CRQB_CMD_LAST : 0); 1740559eedad7f7764dacca33980127b4615011230e4Mark Lord *cmdw = cpu_to_le16(tmp); 174131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 174231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 174305b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1744da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_sff_irq_clear - Clear hardware interrupt after DMA. 1745da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @ap: Port associated with this ATA transaction. 1746da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1747da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * We need this only for ATAPI bmdma transactions, 1748da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * as otherwise we experience spurious interrupts 1749da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * after libata-sff handles the bmdma interrupts. 1750da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1751da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_sff_irq_clear(struct ata_port *ap) 1752da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1753da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ); 1754da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1755da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1756da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1757da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA. 1758da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to check for chipset/DMA compatibility. 1759da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1760da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * The bmdma engines cannot handle speculative data sizes 1761da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * (bytecount under/over flow). So only allow DMA for 1762da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * data transfer commands with known data sizes. 1763da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1764da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1765da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1766da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1767da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic int mv_check_atapi_dma(struct ata_queued_cmd *qc) 1768da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1769da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct scsi_cmnd *scmd = qc->scsicmd; 1770da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1771da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord if (scmd) { 1772da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord switch (scmd->cmnd[0]) { 1773da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case READ_6: 1774da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case READ_10: 1775da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case READ_12: 1776da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case WRITE_6: 1777da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case WRITE_10: 1778da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case WRITE_12: 1779da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case GPCMD_READ_CD: 1780da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case GPCMD_SEND_DVD_STRUCTURE: 1781da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case GPCMD_SEND_CUE_SHEET: 1782da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord return 0; /* DMA is safe */ 1783da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord } 1784da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord } 1785da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord return -EOPNOTSUPP; /* use PIO instead */ 1786da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1787da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1788da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1789da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_setup - Set up BMDMA transaction 1790da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to prepare DMA for. 1791da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1792da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1793da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1794da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1795da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_setup(struct ata_queued_cmd *qc) 1796da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1797da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct ata_port *ap = qc->ap; 1798da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1799da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct mv_port_priv *pp = ap->private_data; 1800da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1801da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord mv_fill_sg(qc); 1802da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1803da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* clear all DMA cmd bits */ 1804cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0, port_mmio + BMDMA_CMD); 1805da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1806da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* load PRD table addr. */ 1807da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16, 1808cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + BMDMA_PRD_HIGH); 1809da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord writelfl(pp->sg_tbl_dma[qc->tag], 1810cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + BMDMA_PRD_LOW); 1811da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1812da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* issue r/w command */ 1813da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord ap->ops->sff_exec_command(ap, &qc->tf); 1814da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1815da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1816da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1817da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_start - Start a BMDMA transaction 1818da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to start DMA on. 1819da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1820da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1821da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1822da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1823da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_start(struct ata_queued_cmd *qc) 1824da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1825da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct ata_port *ap = qc->ap; 1826da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1827da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 1828da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START; 1829da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1830da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* start host DMA transaction */ 1831cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(cmd, port_mmio + BMDMA_CMD); 1832da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1833da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1834da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1835da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_stop - Stop BMDMA transfer 1836da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to stop DMA on. 1837da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1838da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Clears the ATA_DMA_START flag in the bmdma control register 1839da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1840da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1841da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1842da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1843da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_stop(struct ata_queued_cmd *qc) 1844da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1845da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct ata_port *ap = qc->ap; 1846da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1847da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord u32 cmd; 1848da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1849da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* clear start/stop bit */ 1850cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord cmd = readl(port_mmio + BMDMA_CMD); 1851da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord cmd &= ~ATA_DMA_START; 1852cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(cmd, port_mmio + BMDMA_CMD); 1853da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1854da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 1855da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord ata_sff_dma_pause(ap); 1856da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1857da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1858da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1859da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_status - Read BMDMA status 1860da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @ap: port for which to retrieve DMA status. 1861da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1862da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Read and return equivalent of the sff BMDMA status register. 1863da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1864da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1865da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1866da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1867da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic u8 mv_bmdma_status(struct ata_port *ap) 1868da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1869da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1870da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord u32 reg, status; 1871da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1872da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* 1873da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Other bits are valid only if ATA_DMA_ACTIVE==0, 1874da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * and the ATA_DMA_INTR bit doesn't exist. 1875da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1876cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord reg = readl(port_mmio + BMDMA_STATUS); 1877da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord if (reg & ATA_DMA_ACTIVE) 1878da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord status = ATA_DMA_ACTIVE; 1879da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord else 1880da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR; 1881da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord return status; 1882da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1883da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1884299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lordstatic void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc) 1885299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord{ 1886299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord struct ata_taskfile *tf = &qc->tf; 1887299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord /* 1888299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * Workaround for 88SX60x1 FEr SATA#24. 1889299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * 1890299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * Chip may corrupt WRITEs if multi_count >= 4kB. 1891299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * Note that READs are unaffected. 1892299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * 1893299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * It's not clear if this errata really means "4K bytes", 1894299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * or if it always happens for multi_count > 7 1895299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * regardless of device sector_size. 1896299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * 1897299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * So, for safety, any write with multi_count > 7 1898299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * gets converted here into a regular PIO write instead: 1899299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord */ 1900299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) { 1901299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord if (qc->dev->multi_count > 7) { 1902299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord switch (tf->command) { 1903299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_CMD_WRITE_MULTI: 1904299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord tf->command = ATA_CMD_PIO_WRITE; 1905299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord break; 1906299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_CMD_WRITE_MULTI_FUA_EXT: 1907299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord tf->flags &= ~ATA_TFLAG_FUA; /* ugh */ 1908299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord /* fall through */ 1909299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_CMD_WRITE_MULTI_EXT: 1910299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord tf->command = ATA_CMD_PIO_WRITE_EXT; 1911299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord break; 1912299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord } 1913299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord } 1914299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord } 1915299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord} 1916299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord 1917da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 191805b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_prep - Host specific command preparation. 191905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to prepare 192005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 192105b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 192205b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it handles prep of the CRQB 192305b308e1df6d9d673daedb517969241f41278b52Brett Russ * (command request block), does some sanity checking, and calls 192405b308e1df6d9d673daedb517969241f41278b52Brett Russ * the SG load routine. 192505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 192605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 192705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 192805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 192931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc) 193031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 193131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_port *ap = qc->ap; 193231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = ap->private_data; 1933e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 *cw; 19348d2b450d0f9233f221d545f26720eebbc468e857Mark Lord struct ata_taskfile *tf = &qc->tf; 193531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u16 flags = 0; 1936a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 193731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1938299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord switch (tf->protocol) { 1939299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_PROT_DMA: 1940299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_PROT_NCQ: 1941299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord break; /* continue below */ 1942299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_PROT_PIO: 1943299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord mv_rw_multi_errata_sata24(qc); 194431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 1945299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord default: 1946299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord return; 1947299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord } 194820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 194931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Fill in command request block 195031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 19518d2b450d0f9233f221d545f26720eebbc468e857Mark Lord if (!(tf->flags & ATA_TFLAG_WRITE)) 195231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= CRQB_FLAG_READ; 1953beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 195431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= qc->tag << CRQB_TAG_SHIFT; 1955e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 195631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1957bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1958fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 1959a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1960a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr = 1961eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1962a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr_hi = 1963eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1964a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 196531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1966a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord cw = &pp->crqb[in_index].ata_cmd[0]; 196731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 196831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Sadly, the CRQB cannot accomodate all registers--there are 196931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * only 11 bytes...so we must pick and choose required 197031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * registers based on the command. So, we drop feature and 197131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * hob_feature for [RW] DMA commands, but they are needed for 1972cd12e1f7a2c28917c89d65c0d4a52d3919b4c125Mark Lord * NCQ. NCQ will drop hob_nsect, which is not needed there 1973cd12e1f7a2c28917c89d65c0d4a52d3919b4c125Mark Lord * (nsect is used only for the tag; feat/hob_feat hold true nsect). 197420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 197531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ switch (tf->command) { 197631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ: 197731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ_EXT: 197831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE: 197931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE_EXT: 1980c15d85c8f3f73b5f20aae7928e25b6996f16b328Jens Axboe case ATA_CMD_WRITE_FUA_EXT: 198131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 198231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 198331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_READ: 198431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_WRITE: 19858b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 198631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 198731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 198831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ default: 198931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* The only other commands EDMA supports in non-queued and 199031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 199131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * of which are defined/used by Linux. If we get here, this 199231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * driver needs work. 199331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * 199431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * FIXME: modify libata to give qc_prep a return value and 199531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * return error here. 199631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 199731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ BUG_ON(tf->command); 199831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 199931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 200031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 200131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 200231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 200331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 200431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 200531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 200631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 200731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 200831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 200931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2010e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 2011e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 2012e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik mv_fill_sg(qc); 2013e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 2014e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2015e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik/** 2016e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * mv_qc_prep_iie - Host specific command preparation. 2017e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * @qc: queued command to prepare 2018e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 2019e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * This routine simply redirects to the general purpose routine 2020e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * if command is not DMA. Else, it handles prep of the CRQB 2021e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * (command request block), does some sanity checking, and calls 2022e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * the SG load routine. 2023e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 2024e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * LOCKING: 2025e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * Inherited from caller. 2026e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik */ 2027e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc) 2028e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 2029e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_port *ap = qc->ap; 2030e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_port_priv *pp = ap->private_data; 2031e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_crqb_iie *crqb; 20328d2b450d0f9233f221d545f26720eebbc468e857Mark Lord struct ata_taskfile *tf = &qc->tf; 2033a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 2034e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik u32 flags = 0; 2035e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 20368d2b450d0f9233f221d545f26720eebbc468e857Mark Lord if ((tf->protocol != ATA_PROT_DMA) && 20378d2b450d0f9233f221d545f26720eebbc468e857Mark Lord (tf->protocol != ATA_PROT_NCQ)) 2038e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 2039e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2040e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* Fill in Gen IIE command request block */ 20418d2b450d0f9233f221d545f26720eebbc468e857Mark Lord if (!(tf->flags & ATA_TFLAG_WRITE)) 2042e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= CRQB_FLAG_READ; 2043e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2044beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 2045e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= qc->tag << CRQB_TAG_SHIFT; 20468c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord flags |= qc->tag << CRQB_HOSTQ_SHIFT; 2047e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 2048e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2049bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 2050fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 2051a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 2052a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 2053eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 2054eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 2055e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->flags = cpu_to_le32(flags); 2056e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2057e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[0] = cpu_to_le32( 2058e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->command << 16) | 2059e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->feature << 24) 2060e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2061e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[1] = cpu_to_le32( 2062e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbal << 0) | 2063e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbam << 8) | 2064e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbah << 16) | 2065e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->device << 24) 2066e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2067e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[2] = cpu_to_le32( 2068e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbal << 0) | 2069e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbam << 8) | 2070e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbah << 16) | 2071e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_feature << 24) 2072e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2073e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[3] = cpu_to_le32( 2074e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->nsect << 0) | 2075e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_nsect << 8) 2076e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2077e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2078e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 207931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 208031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_fill_sg(qc); 208131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 208231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 208305b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2084d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * mv_sff_check_status - fetch device status, if valid 2085d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * @ap: ATA port to fetch status from 2086d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * 2087d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * When using command issue via mv_qc_issue_fis(), 2088d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * the initial ATA_BUSY state does not show up in the 2089d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * ATA status (shadow) register. This can confuse libata! 2090d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * 2091d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * So we have a hook here to fake ATA_BUSY for that situation, 2092d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * until the first time a BUSY, DRQ, or ERR bit is seen. 2093d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * 2094d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * The rest of the time, it simply returns the ATA status register. 2095d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord */ 2096d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lordstatic u8 mv_sff_check_status(struct ata_port *ap) 2097d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord{ 2098d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord u8 stat = ioread8(ap->ioaddr.status_addr); 2099d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord struct mv_port_priv *pp = ap->private_data; 2100d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord 2101d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) { 2102d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) 2103d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; 2104d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord else 2105d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord stat = ATA_BUSY; 2106d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord } 2107d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord return stat; 2108d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord} 2109d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord 2110d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord/** 211170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register 211270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * @fis: fis to be sent 211370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * @nwords: number of 32-bit words in the fis 211470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 211570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lordstatic unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords) 211670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord{ 211770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 211870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord u32 ifctl, old_ifctl, ifstat; 211970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord int i, timeout = 200, final_word = nwords - 1; 212070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 212170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Initiate FIS transmission mode */ 2122cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord old_ifctl = readl(port_mmio + SATA_IFCTL); 212370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ifctl = 0x100 | (old_ifctl & 0xf); 2124cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(ifctl, port_mmio + SATA_IFCTL); 212570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 212670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Send all words of the FIS except for the final word */ 212770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord for (i = 0; i < final_word; ++i) 2128cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS); 212970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 213070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Flag end-of-transmission, and then send the final word */ 2131cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL); 2132cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS); 213370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 213470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* 213570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Wait for FIS transmission to complete. 213670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * This typically takes just a single iteration. 213770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 213870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord do { 2139cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ifstat = readl(port_mmio + SATA_IFSTAT); 214070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } while (!(ifstat & 0x1000) && --timeout); 214170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 214270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Restore original port configuration */ 2143cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(old_ifctl, port_mmio + SATA_IFCTL); 214470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 214570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* See if it worked */ 214670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if ((ifstat & 0x3000) != 0x1000) { 214770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ata_port_printk(ap, KERN_WARNING, 214870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord "%s transmission error, ifstat=%08x\n", 214970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord __func__, ifstat); 215070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return AC_ERR_OTHER; 215170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } 215270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return 0; 215370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord} 215470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 215570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord/** 215670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * mv_qc_issue_fis - Issue a command directly as a FIS 215770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * @qc: queued command to start 215870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 215970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Note that the ATA shadow registers are not updated 216070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * after command issue, so the device will appear "READY" 216170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * if polled, even while it is BUSY processing the command. 216270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 216370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * So we use a status hook to fake ATA_BUSY until the drive changes state. 216470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 216570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Note: we don't get updated shadow regs on *completion* 216670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * of non-data commands. So avoid sending them via this function, 216770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * as they will appear to have completed immediately. 216870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 216970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * GEN_IIE has special registers that we could get the result tf from, 217070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * but earlier chipsets do not. For now, we ignore those registers. 217170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 217270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lordstatic unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc) 217370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord{ 217470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct ata_port *ap = qc->ap; 217570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct mv_port_priv *pp = ap->private_data; 217670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct ata_link *link = qc->dev->link; 217770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord u32 fis[5]; 217870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord int err = 0; 217970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 218070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis); 218170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord err = mv_send_fis(ap, fis, sizeof(fis) / sizeof(fis[0])); 218270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (err) 218370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return err; 218470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 218570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord switch (qc->tf.protocol) { 218670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord case ATAPI_PROT_PIO: 218770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; 218870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* fall through */ 218970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord case ATAPI_PROT_NODATA: 219070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST_FIRST; 219170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord break; 219270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord case ATA_PROT_PIO: 219370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; 219470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (qc->tf.flags & ATA_TFLAG_WRITE) 219570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST_FIRST; 219670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord else 219770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST; 219870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord break; 219970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord default: 220070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST_LAST; 220170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord break; 220270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } 220370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 220470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (qc->tf.flags & ATA_TFLAG_POLLING) 220570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ata_pio_queue_task(ap, qc, 0); 220670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return 0; 220770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord} 220870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 220970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord/** 221005b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_issue - Initiate a command to the host 221105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to start 221205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 221305b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 221405b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it sanity checks our local 221505b308e1df6d9d673daedb517969241f41278b52Brett Russ * caches of the request producer/consumer indices then enables 221605b308e1df6d9d673daedb517969241f41278b52Brett Russ * DMA and bumps the request producer index. 221705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 221805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 221905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 222005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 22219a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 222231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 2223f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord static int limit_warnings = 10; 2224c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct ata_port *ap = qc->ap; 2225c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 2226c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp = ap->private_data; 2227bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 in_index; 222842ed893d8011264f9945c2f54055b47c298ac53eMark Lord unsigned int port_irqs; 2229f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord 2230d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */ 2231d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord 2232f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord switch (qc->tf.protocol) { 2233f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATA_PROT_DMA: 2234f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATA_PROT_NCQ: 2235f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord mv_start_edma(ap, port_mmio, pp, qc->tf.protocol); 2236f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2237f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 2238f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord 2239f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord /* Write the request in pointer to kick the EDMA to life */ 2240f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 2241cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + EDMA_REQ_Q_IN_PTR); 2242f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord return 0; 224331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2244f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATA_PROT_PIO: 2245c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord /* 2246c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * Errata SATA#16, SATA#24: warn if multiple DRQs expected. 2247c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * 2248c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * Someday, we might implement special polling workarounds 2249c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * for these, but it all seems rather unnecessary since we 2250c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * normally use only DMA for commands which transfer more 2251c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * than a single block of data. 2252c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * 2253c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * Much of the time, this could just work regardless. 2254c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * So for now, just log the incident, and allow the attempt. 2255c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord */ 2256c7843e8f565f624b0cff7cad1370fad4cb84dfbcMark Lord if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) { 2257c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord --limit_warnings; 2258c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME 2259c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord ": attempting PIO w/multiple DRQ: " 2260c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord "this may fail due to h/w errata\n"); 2261c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord } 2262f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord /* drop through */ 226342ed893d8011264f9945c2f54055b47c298ac53eMark Lord case ATA_PROT_NODATA: 2264f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATAPI_PROT_PIO: 226542ed893d8011264f9945c2f54055b47c298ac53eMark Lord case ATAPI_PROT_NODATA: 226642ed893d8011264f9945c2f54055b47c298ac53eMark Lord if (ap->flags & ATA_FLAG_PIO_POLLING) 226742ed893d8011264f9945c2f54055b47c298ac53eMark Lord qc->tf.flags |= ATA_TFLAG_POLLING; 226842ed893d8011264f9945c2f54055b47c298ac53eMark Lord break; 226931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 227042ed893d8011264f9945c2f54055b47c298ac53eMark Lord 227142ed893d8011264f9945c2f54055b47c298ac53eMark Lord if (qc->tf.flags & ATA_TFLAG_POLLING) 227242ed893d8011264f9945c2f54055b47c298ac53eMark Lord port_irqs = ERR_IRQ; /* mask device interrupt when polling */ 227342ed893d8011264f9945c2f54055b47c298ac53eMark Lord else 227442ed893d8011264f9945c2f54055b47c298ac53eMark Lord port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */ 227542ed893d8011264f9945c2f54055b47c298ac53eMark Lord 227642ed893d8011264f9945c2f54055b47c298ac53eMark Lord /* 227742ed893d8011264f9945c2f54055b47c298ac53eMark Lord * We're about to send a non-EDMA capable command to the 227842ed893d8011264f9945c2f54055b47c298ac53eMark Lord * port. Turn off EDMA so there won't be problems accessing 227942ed893d8011264f9945c2f54055b47c298ac53eMark Lord * shadow block, etc registers. 228042ed893d8011264f9945c2f54055b47c298ac53eMark Lord */ 228142ed893d8011264f9945c2f54055b47c298ac53eMark Lord mv_stop_edma(ap); 228242ed893d8011264f9945c2f54055b47c298ac53eMark Lord mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs); 228342ed893d8011264f9945c2f54055b47c298ac53eMark Lord mv_pmp_select(ap, qc->dev->link->pmp); 228470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 228570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (qc->tf.command == ATA_CMD_READ_LOG_EXT) { 228670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 228770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* 228870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Workaround for 88SX60x1 FEr SATA#25 (part 2). 228940f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * 229070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * After any NCQ error, the READ_LOG_EXT command 229170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * from libata-eh *must* use mv_qc_issue_fis(). 229270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Otherwise it might fail, due to chip errata. 229370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 229470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Rather than special-case it, we'll just *always* 229570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * use this method here for READ_LOG_EXT, making for 229670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * easier testing. 229770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 229870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (IS_GEN_II(hpriv)) 229970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return mv_qc_issue_fis(qc); 230070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } 230142ed893d8011264f9945c2f54055b47c298ac53eMark Lord return ata_sff_qc_issue(qc); 230231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 230331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 23048f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lordstatic struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) 23058f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 23068f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct mv_port_priv *pp = ap->private_data; 23078f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc; 23088f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 23098f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 23108f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord return NULL; 23118f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord qc = ata_qc_from_tag(ap, ap->link.active_tag); 231295db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord if (qc) { 231395db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord if (qc->tf.flags & ATA_TFLAG_POLLING) 231495db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord qc = NULL; 231595db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord else if (!(qc->flags & ATA_QCFLAG_ACTIVE)) 231695db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord qc = NULL; 231795db505125fb7bc624b7c3b6747bbeaebbffc2e4Mark Lord } 23188f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord return qc; 23198f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 23208f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 232129d187bb1e30682e228ce461c487d78d945c3e4fMark Lordstatic void mv_pmp_error_handler(struct ata_port *ap) 232229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord{ 232329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int pmp, pmp_map; 232429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord struct mv_port_priv *pp = ap->private_data; 232529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord 232629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { 232729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord /* 232829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * Perform NCQ error analysis on failed PMPs 232929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * before we freeze the port entirely. 233029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * 233129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * The failed PMPs are marked earlier by mv_pmp_eh_prep(). 233229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord */ 233329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pmp_map = pp->delayed_eh_pmp_map; 233429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; 233529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord for (pmp = 0; pmp_map != 0; pmp++) { 233629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int this_pmp = (1 << pmp); 233729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pmp_map & this_pmp) { 233829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord struct ata_link *link = &ap->pmp_link[pmp]; 233929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pmp_map &= ~this_pmp; 234029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord ata_eh_analyze_ncq_error(link); 234129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 234229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 234329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord ata_port_freeze(ap); 234429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 234529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord sata_pmp_error_handler(ap); 234629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord} 234729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord 23484c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic unsigned int mv_get_err_pmp_map(struct ata_port *ap) 23494c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 23504c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 23514c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 2352cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord return readl(port_mmio + SATA_TESTCTL) >> 16; 23534c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 23544c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 23554c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map) 23564c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 23574c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct ata_eh_info *ehi; 23584c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int pmp; 23594c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 23604c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 23614c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Initialize EH info for PMPs which saw device errors 23624c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 23634c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi = &ap->link.eh_info; 23644c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord for (pmp = 0; pmp_map != 0; pmp++) { 23654c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int this_pmp = (1 << pmp); 23664c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pmp_map & this_pmp) { 23674c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct ata_link *link = &ap->pmp_link[pmp]; 23684c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 23694c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pmp_map &= ~this_pmp; 23704c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi = &link->eh_info; 23714c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_ehi_clear_desc(ehi); 23724c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_ehi_push_desc(ehi, "dev err"); 23734c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi->err_mask |= AC_ERR_DEV; 23744c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi->action |= ATA_EH_RESET; 23754c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_link_abort(link); 23764c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 23774c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 23784c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 23794c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 238006aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lordstatic int mv_req_q_empty(struct ata_port *ap) 238106aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord{ 238206aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 238306aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord u32 in_ptr, out_ptr; 238406aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord 2385cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR) 238606aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2387cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR) 238806aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 238906aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord return (in_ptr == out_ptr); /* 1 == queue_is_empty */ 239006aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord} 239106aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord 23924c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_fbs_ncq_dev_err(struct ata_port *ap) 23934c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 23944c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp = ap->private_data; 23954c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord int failed_links; 23964c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int old_map, new_map; 23974c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 23984c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 23994c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device error during FBS+NCQ operation: 24004c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 24014c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Set a port flag to prevent further I/O being enqueued. 24024c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Leave the EDMA running to drain outstanding commands from this port. 24034c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Perform the post-mortem/EH only when all responses are complete. 24044c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2). 24054c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 24064c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { 24074c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; 24084c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->delayed_eh_pmp_map = 0; 24094c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24104c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord old_map = pp->delayed_eh_pmp_map; 24114c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord new_map = old_map | mv_get_err_pmp_map(ap); 24124c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24134c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (old_map != new_map) { 24144c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->delayed_eh_pmp_map = new_map; 24154c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_pmp_eh_prep(ap, new_map & ~old_map); 24164c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 2417c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord failed_links = hweight16(new_map); 24184c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24194c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x " 24204c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "failed_links=%d nr_active_links=%d\n", 24214c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, pp->delayed_eh_pmp_map, 24224c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ap->qc_active, failed_links, 24234c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ap->nr_active_links); 24244c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 242506aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { 24264c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_process_crpb_entries(ap, pp); 24274c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_stop_edma(ap); 24284c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_eh_freeze(ap); 24294c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__); 24304c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 1; /* handled */ 24314c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24324c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__); 24334c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 1; /* handled */ 24344c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 24354c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24364c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap) 24374c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 24384c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 24394c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Possible future enhancement: 24404c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 24414c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * FBS+non-NCQ operation is not yet implemented. 24424c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * See related notes in mv_edma_cfg(). 24434c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 24444c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device error during FBS+non-NCQ operation: 24454c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 24464c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * We need to snapshot the shadow registers for each failed command. 24474c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3). 24484c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 24494c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 24504c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 24514c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24524c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause) 24534c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 24544c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp = ap->private_data; 24554c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24564c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 24574c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* EDMA was not active: not handled */ 24584c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) 24594c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* FBS was not active: not handled */ 24604c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24614c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(edma_err_cause & EDMA_ERR_DEV)) 24624c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* non DEV error: not handled */ 24634c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT; 24644c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS)) 24654c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* other problems: not handled */ 24664c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24674c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { 24684c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 24694c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * EDMA should NOT have self-disabled for this case. 24704c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * If it did, then something is wrong elsewhere, 24714c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * and we cannot handle it here. 24724c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 24734c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & EDMA_ERR_SELF_DIS) { 24744c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_WARNING, 24754c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "%s: err_cause=0x%x pp_flags=0x%x\n", 24764c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, edma_err_cause, pp->pp_flags); 24774c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 24784c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24794c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return mv_handle_fbs_ncq_dev_err(ap); 24804c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } else { 24814c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 24824c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * EDMA should have self-disabled for this case. 24834c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * If it did not, then something is wrong elsewhere, 24844c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * and we cannot handle it here. 24854c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 24864c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) { 24874c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_WARNING, 24884c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "%s: err_cause=0x%x pp_flags=0x%x\n", 24894c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, edma_err_cause, pp->pp_flags); 24904c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 24914c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24924c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return mv_handle_fbs_non_ncq_dev_err(ap); 24934c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24944c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 24954c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 24964c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 2497a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lordstatic void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled) 24988f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 24998f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_eh_info *ehi = &ap->link.eh_info; 2500a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord char *when = "idle"; 25018f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 25028f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_ehi_clear_desc(ehi); 2503a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (!ap || (ap->flags & ATA_FLAG_DISABLED)) { 2504a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "disabled"; 2505a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } else if (edma_was_enabled) { 2506a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "EDMA enabled"; 25078f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } else { 25088f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 25098f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 2510a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "polling"; 25118f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } 2512a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when); 25138f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->err_mask |= AC_ERR_OTHER; 25148f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->action |= ATA_EH_RESET; 25158f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_port_freeze(ap); 25168f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 25178f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 251805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 251905b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_err_intr - Handle error interrupts on the port 252005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 252105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 25228d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Most cases require a full reset of the chip's state machine, 25238d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * which also performs a COMRESET. 25248d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Also, if the port disabled DMA, update our cached copy to match. 252505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 252605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 252705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 252805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 252937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lordstatic void mv_err_intr(struct ata_port *ap) 253031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 253131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 2532bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 edma_err_cause, eh_freeze_mask, serr = 0; 2533e40060772d85f3534d3d517197696e24bb01f45bMark Lord u32 fis_cause = 0; 2534bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 2535bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2536bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int action = 0, err_mask = 0; 25379af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_eh_info *ehi = &ap->link.eh_info; 253837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord struct ata_queued_cmd *qc; 253937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord int abort = 0; 254020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25418d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord /* 254237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Read and clear the SError and err_cause bits. 2543e40060772d85f3534d3d517197696e24bb01f45bMark Lord * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear 2544e40060772d85f3534d3d517197696e24bb01f45bMark Lord * the FIS_IRQ_CAUSE register before clearing edma_err_cause. 25458d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord */ 254637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord sata_scr_read(&ap->link, SCR_ERROR, &serr); 254737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 254837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord 2549cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE); 2550e40060772d85f3534d3d517197696e24bb01f45bMark Lord if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2551cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord fis_cause = readl(port_mmio + FIS_IRQ_CAUSE); 2552cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE); 2553e40060772d85f3534d3d517197696e24bb01f45bMark Lord } 2554cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE); 2555bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 25564c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & EDMA_ERR_DEV) { 25574c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 25584c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device errors during FIS-based switching operation 25594c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * require special handling. 25604c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 25614c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (mv_handle_dev_err(ap, edma_err_cause)) 25624c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return; 25634c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 25644c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 256537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord qc = mv_get_active_qc(ap); 256637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_clear_desc(ehi); 256737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x", 256837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord edma_err_cause, pp->pp_flags); 2569e40060772d85f3534d3d517197696e24bb01f45bMark Lord 2570c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2571e40060772d85f3534d3d517197696e24bb01f45bMark Lord ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause); 2572cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord if (fis_cause & FIS_IRQ_CAUSE_AN) { 2573c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord u32 ec = edma_err_cause & 2574c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT); 2575c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord sata_async_notification(ap); 2576c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord if (!ec) 2577c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord return; /* Just an AN; no need for the nukes */ 2578c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord ata_ehi_push_desc(ehi, "SDB notify"); 2579c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord } 2580c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord } 2581bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 2582352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * All generations share these EDMA error cause bits: 2583bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 258437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (edma_err_cause & EDMA_ERR_DEV) { 2585bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_DEV; 258637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord action |= ATA_EH_RESET; 258737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_push_desc(ehi, "dev error"); 258837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 2589bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 25906c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 2591bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR)) { 2592bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_ATA_BUS; 2593cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2594b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "parity error"); 2595bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2596bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 2597bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_hotplugged(ehi); 2598bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 2599b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo "dev disconnect" : "dev connect"); 2600cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2601bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2602bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2603352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 2604352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Gen-I has a different SELF_DIS bit, 2605352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * different FREEZE bits, and no SERR bit: 2606352fab701ca4753dd005b67ce5e512be944eb591Mark Lord */ 2607ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) { 2608bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE_5; 2609bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 2610bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2611b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 2612bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2613bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 2614bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE; 2615bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS) { 2616bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2617b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 2618bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2619bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SERR) { 26208d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord ata_ehi_push_desc(ehi, "SError=%08x", serr); 26218d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord err_mask |= AC_ERR_ATA_BUS; 2622cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2623bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2624afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 262520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2626bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!err_mask) { 2627bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_OTHER; 2628cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2629bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2630bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2631bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->serror |= serr; 2632bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->action |= action; 2633bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2634bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 2635bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 2636bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 2637bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 2638bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 263937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (err_mask == AC_ERR_DEV) { 264037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* 264137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Cannot do ata_port_freeze() here, 264237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * because it would kill PIO access, 264337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * which is needed for further diagnosis. 264437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord */ 264537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord mv_eh_freeze(ap); 264637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord abort = 1; 264737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } else if (edma_err_cause & eh_freeze_mask) { 264837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* 264937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Note to self: ata_port_freeze() calls ata_port_abort() 265037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord */ 2651bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 265237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } else { 265337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord abort = 1; 265437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 265537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord 265637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (abort) { 265737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (qc) 265837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_link_abort(qc->dev->link); 265937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord else 266037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_port_abort(ap); 266137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 2662bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2663bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2664fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_response(struct ata_port *ap, 2665fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response, unsigned int tag, int ncq_enabled) 2666fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord{ 2667fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag); 2668fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 2669fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (qc) { 2670fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 ata_status; 2671fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u16 edma_status = le16_to_cpu(response->flags); 2672fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 2673fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * edma_status from a response queue entry: 2674cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only). 2675fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * MSB is saved ATA status from command completion. 2676fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 2677fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (!ncq_enabled) { 2678fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; 2679fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (err_cause) { 2680fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 2681fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * Error will be seen/handled by mv_err_intr(). 2682fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * So do nothing at all here. 2683fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 2684fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord return; 2685fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2686fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2687fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; 268837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (!ac_err_mask(ata_status)) 268937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_qc_complete(qc); 269037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* else: leave it for mv_err_intr() */ 2691fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 2692fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n", 2693fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord __func__, tag); 2694fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2695fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord} 2696fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 2697fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) 2698bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2699bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 2700bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2701fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u32 in_index; 2702bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik bool work_done = false; 2703fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); 2704bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2705fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Get the hardware queue position index */ 2706cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR) 2707bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2708bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2709fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Process new responses from since the last time we looked */ 2710fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord while (in_index != pp->resp_idx) { 27116c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik unsigned int tag; 2712fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response = &pp->crpb[pp->resp_idx]; 2713bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2714fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2715bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2716fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (IS_GEN_I(hpriv)) { 2717fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 50xx: no NCQ, only one command active at a time */ 27189af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo tag = ap->link.active_tag; 2719fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 2720fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Gen II/IIE: get command tag from CRPB entry */ 2721fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord tag = le16_to_cpu(response->id) & 0x1f; 2722bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2723fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord mv_process_crpb_response(ap, response, tag, ncq_enabled); 2724bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik work_done = true; 2725bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2726bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2727352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Update the software queue position index in hardware */ 2728bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (work_done) 2729bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 2730fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), 2731cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + EDMA_RSP_Q_OUT_PTR); 273220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 273320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2734a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lordstatic void mv_port_intr(struct ata_port *ap, u32 port_cause) 2735a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord{ 2736a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord struct mv_port_priv *pp; 2737a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord int edma_was_enabled; 2738a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord 2739a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (!ap || (ap->flags & ATA_FLAG_DISABLED)) { 2740a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_unexpected_intr(ap, 0); 2741a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord return; 2742a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2743a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2744a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Grab a snapshot of the EDMA_EN flag setting, 2745a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * so that we have a consistent view for this port, 2746a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * even if something we call of our routines changes it. 2747a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2748a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord pp = ap->private_data; 2749a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); 2750a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2751a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Process completed CRPB response(s) before other events. 2752a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2753a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (edma_was_enabled && (port_cause & DONE_IRQ)) { 2754a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_process_crpb_entries(ap, pp); 27554c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 27564c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_handle_fbs_ncq_dev_err(ap); 2757a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2758a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2759a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Handle chip-reported errors, or continue on to handle PIO. 2760a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2761a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (unlikely(port_cause & ERR_IRQ)) { 2762a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_err_intr(ap); 2763a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } else if (!edma_was_enabled) { 2764a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord struct ata_queued_cmd *qc = mv_get_active_qc(ap); 2765a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (qc) 2766a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord ata_sff_host_intr(ap, qc); 2767a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord else 2768a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_unexpected_intr(ap, edma_was_enabled); 2769a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2770a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord} 2771a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord 277205b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 277305b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_host_intr - Handle all interrupts on the given host controller 2774cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * @host: host specific structure 27757368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * @main_irq_cause: Main interrupt cause register for the chip. 277605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 277705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 277805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 277905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 27807368f91926a2870a8c3f9546d86535ce71ae0757Mark Lordstatic int mv_host_intr(struct ata_host *host, u32 main_irq_cause) 278120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2782f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 2783eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord void __iomem *mmio = hpriv->base, *hc_mmio; 2784a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0, port; 278520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 27862b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* If asserted, clear the "all ports" IRQ coalescing bit */ 27872b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (main_irq_cause & ALL_PORTS_COAL_DONE) 2788cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); 27892b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 2790a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord for (port = 0; port < hpriv->n_ports; port++) { 2791cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_port *ap = host->ports[port]; 2792eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord unsigned int p, shift, hardport, port_cause; 2793eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord 2794a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2795a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord /* 2796eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * Each hc within the host has its own hc_irq_cause register, 2797eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * where the interrupting ports bits get ack'd. 2798a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord */ 2799eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (hardport == 0) { /* first port on this hc ? */ 2800eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND; 2801eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord u32 port_mask, ack_irqs; 2802eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord /* 2803eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * Skip this entire hc if nothing pending for any ports 2804eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord */ 2805eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (!hc_cause) { 2806eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord port += MV_PORTS_PER_HC - 1; 2807eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord continue; 2808eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord } 2809eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord /* 2810eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * We don't need/want to read the hc_irq_cause register, 2811eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * because doing so hurts performance, and 2812eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * main_irq_cause already gives us everything we need. 2813eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * 2814eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * But we do have to *write* to the hc_irq_cause to ack 2815eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * the ports that we are handling this time through. 2816eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * 2817eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * This requires that we create a bitmap for those 2818eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * ports which interrupted us, and use that bitmap 2819eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * to ack (only) those ports via hc_irq_cause. 2820eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord */ 2821eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord ack_irqs = 0; 28222b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (hc_cause & PORTS_0_3_COAL_DONE) 28232b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord ack_irqs = HC_COAL_IRQ; 2824eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord for (p = 0; p < MV_PORTS_PER_HC; ++p) { 2825eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if ((port + p) >= hpriv->n_ports) 2826eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord break; 2827eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2); 2828eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (hc_cause & port_mask) 2829eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord ack_irqs |= (DMA_IRQ | DEV_IRQ) << p; 2830eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord } 2831a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord hc_mmio = mv_hc_base_from_port(mmio, port); 2832cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE); 2833a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = 1; 2834a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord } 28358f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord /* 2836a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Handle interrupts signalled for this port: 28378f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord */ 2838a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ); 2839a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (port_cause) 2840a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_port_intr(ap, port_cause); 284120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 2842a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return handled; 284320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 284420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2845a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lordstatic int mv_pci_error(struct ata_host *host, void __iomem *mmio) 2846bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 284702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 2848bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_port *ap; 2849bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 2850bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_eh_info *ehi; 2851bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int i, err_mask, printed = 0; 2852bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 err_cause; 2853bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2854cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord err_cause = readl(mmio + hpriv->irq_cause_offset); 2855bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2856bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", 2857bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_cause); 2858bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2859bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik DPRINTK("All regs @ PCI error\n"); 2860bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 2861bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2862cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, mmio + hpriv->irq_cause_offset); 2863bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2864bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik for (i = 0; i < host->n_ports; i++) { 2865bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ap = host->ports[i]; 2866936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo if (!ata_link_offline(&ap->link)) { 28679af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo ehi = &ap->link.eh_info; 2868bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 2869bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!printed++) 2870bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, 2871bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik "PCI err cause 0x%08x", err_cause); 2872bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_HOST_BUS; 2873cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo ehi->action = ATA_EH_RESET; 28749af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 2875bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 2876bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 2877bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 2878bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 2879bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2880bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 2881bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2882bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2883a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return 1; /* handled */ 2884bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2885bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 288605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2887c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * mv_interrupt - Main interrupt event handler 288805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @irq: unused 288905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @dev_instance: private data; in this case the host structure 289005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 289105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read the read only register to determine if any host 289205b308e1df6d9d673daedb517969241f41278b52Brett Russ * controllers have pending interrupts. If so, call lower level 289305b308e1df6d9d673daedb517969241f41278b52Brett Russ * routine to handle. Also check for PCI errors which are only 289405b308e1df6d9d673daedb517969241f41278b52Brett Russ * reported here. 289505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 28968b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * LOCKING: 2897cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine holds the host lock while processing pending 289805b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts. 289905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 29007d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t mv_interrupt(int irq, void *dev_instance) 290120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2902cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = dev_instance; 2903f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 2904a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0; 29056d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI; 290696e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord u32 main_irq_cause, pending_irqs; 290720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2908646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord spin_lock(&host->lock); 29096d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 29106d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord /* for MSI: block new interrupts while in here */ 29116d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord if (using_msi) 29122b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_write_main_irq_mask(0, hpriv); 29136d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 29147368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_cause = readl(hpriv->main_irq_cause_addr); 291596e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord pending_irqs = main_irq_cause & hpriv->main_irq_mask; 2916352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 2917352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Deal with cases where we either have nothing pending, or have read 2918352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * a bogus register value which can indicate HW removal or PCI fault. 291920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2920a44253d24a97ec3efe601267274a5fb64d8696c1Mark Lord if (pending_irqs && main_irq_cause != 0xffffffffU) { 29211f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv))) 2922a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = mv_pci_error(host, hpriv->base); 2923a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord else 2924a44253d24a97ec3efe601267274a5fb64d8696c1Mark Lord handled = mv_host_intr(host, pending_irqs); 2925bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 29266d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 29276d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord /* for MSI: unmask; interrupt cause bits will retrigger now */ 29286d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord if (using_msi) 29292b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv); 29306d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 29319d51af7bd2f1d730cb6eeeb9ff837e3441ad4e07Mark Lord spin_unlock(&host->lock); 29329d51af7bd2f1d730cb6eeeb9ff837e3441ad4e07Mark Lord 293320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return IRQ_RETVAL(handled); 293420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 293520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2936c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic unsigned int mv5_scr_offset(unsigned int sc_reg_in) 2937c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2938c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs; 2939c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2940c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik switch (sc_reg_in) { 2941c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_STATUS: 2942c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_ERROR: 2943c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_CONTROL: 2944c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = sc_reg_in * sizeof(u32); 2945c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 2946c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik default: 2947c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = 0xffffffffU; 2948c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 2949c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2950c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return ofs; 2951c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2952c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 295382ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 2954c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 295582ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo struct mv_host_priv *hpriv = link->ap->host->private_data; 2956f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 295782ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 2958c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 2959c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2960da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 2961da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(addr + ofs); 2962da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 2963da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 2964da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 2965c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2966c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 296782ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 2968c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 296982ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo struct mv_host_priv *hpriv = link->ap->host->private_data; 2970f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 297182ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 2972c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 2973c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2974da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 29750d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo writelfl(val, addr + ofs); 2976da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 2977da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 2978da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 2979c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2980c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 29817bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 2982522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 29837bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara struct pci_dev *pdev = to_pci_dev(host->dev); 2984522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik int early_5080; 2985522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 298644c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 2987522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2988522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik if (!early_5080) { 2989522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 2990522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= (1 << 0); 2991522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 2992522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik } 2993522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 29947bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara mv_reset_pci_bus(host, mmio); 2995522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 2996522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2997522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 2998522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 2999cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x0fcfffff, mmio + FLASH_CTL); 3000522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 3001522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 300247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 3003ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 3004ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 3005c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 3006c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 3007c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3008c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 3009c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3010c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 3011c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 3012ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3013ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 301447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 3015ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 3016522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp; 3017522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3018cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0, mmio + GPIO_PORT_CTL); 3019522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3020522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 3021522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3022522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 3023522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= ~(1 << 0); 3024522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 3025ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3026ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 30272a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 30282a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 3029bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 3030c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, port); 3031c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 3032c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 3033c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 3034c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3035c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik if (fix_apm_sq) { 3036cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(phy_mmio + MV5_LTMODE); 3037c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= (1 << 19); 3038cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(tmp, phy_mmio + MV5_LTMODE); 3039c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3040cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(phy_mmio + MV5_PHY_CTL); 3041c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~0x3; 3042c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x1; 3043cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(tmp, phy_mmio + MV5_PHY_CTL); 3044c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 3045c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3046c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 3047c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~mask; 3048c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].pre; 3049c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].amps; 3050c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_MODE); 3051bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 3052bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3053c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3054c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 3055c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, port_mmio + (reg)) 3056c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 3057c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 3058c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 3059c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 3060c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3061e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 3062c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3063c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x028); /* command */ 3064cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x11f, port_mmio + EDMA_CFG); 3065c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x004); /* timer */ 3066c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x008); /* irq err cause */ 3067c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); /* irq err mask */ 3068c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); /* rq bah */ 3069c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); /* rq inp */ 3070c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); /* rq outp */ 3071c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x01c); /* respq bah */ 3072c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x024); /* respq outp */ 3073c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x020); /* respq inp */ 3074c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x02c); /* test control */ 3075cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 3076c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3077c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 3078c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3079c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, hc_mmio + (reg)) 3080c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3081c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc) 308247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik{ 3083c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 3084c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 3085c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3086c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); 3087c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); 3088c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); 3089c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); 3090c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3091c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(hc_mmio + 0x20); 3092c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= 0x1c1c1c1c; 3093c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x03030303; 3094c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, hc_mmio + 0x20); 3095c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3096c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 3097c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3098c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3099c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 3100c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 3101c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc, port; 3102c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3103c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (hc = 0; hc < n_hc; hc++) { 3104c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (port = 0; port < MV_PORTS_PER_HC; port++) 3105c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_hc_port(hpriv, mmio, 3106c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (hc * MV_PORTS_PER_HC) + port); 3107c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3108c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_one_hc(hpriv, mmio, hc); 3109c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 3110c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3111c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return 0; 311247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik} 311347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 3114101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 3115101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#define ZERO(reg) writel(0, mmio + (reg)) 31167bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 3117101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 311802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 3119101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 3120101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3121cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(mmio + MV_PCI_MODE); 3122101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0xff00ffff; 3123cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(tmp, mmio + MV_PCI_MODE); 3124101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3125101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_DISC_TIMER); 3126101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_MSI_TRIGGER); 3127cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); 3128101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_SERR_MASK); 3129cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ZERO(hpriv->irq_cause_offset); 3130cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ZERO(hpriv->irq_mask_offset); 3131101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_LOW_ADDRESS); 3132101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_HIGH_ADDRESS); 3133101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_ATTRIBUTE); 3134101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_COMMAND); 3135101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 3136101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 3137101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3138101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 3139101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 3140101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 3141101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3142101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik mv5_reset_flash(hpriv, mmio); 3143101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3144cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(mmio + GPIO_PORT_CTL); 3145101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0x3; 3146101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp |= (1 << 5) | (1 << 6); 3147cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(tmp, mmio + GPIO_PORT_CTL); 3148101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 3149101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3150101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik/** 3151101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * mv6_reset_hc - Perform the 6xxx global soft reset 3152101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * @mmio: base address of the HBA 3153101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 3154101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * This routine only applies to 6xxx parts. 3155101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 3156101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * LOCKING: 3157101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * Inherited from caller. 3158101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 3159c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3160c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 3161101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 3162cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord void __iomem *reg = mmio + PCI_MAIN_CMD_STS; 3163101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik int i, rc = 0; 3164101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 t; 3165101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3166101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* Following procedure defined in PCI "main command and status 3167101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * register" table. 3168101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 3169101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 3170101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | STOP_PCI_MASTER, reg); 3171101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3172101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik for (i = 0; i < 1000; i++) { 3173101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 3174101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 31752dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik if (PCI_MASTER_EMPTY & t) 3176101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik break; 3177101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3178101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(PCI_MASTER_EMPTY & t)) { 3179101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 3180101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 3181101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 3182101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3183101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3184101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* set reset */ 3185101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 3186101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 3187101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | GLOB_SFT_RST, reg); 3188101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 3189101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 3190101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 3191101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3192101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(GLOB_SFT_RST & t)) { 3193101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 3194101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 3195101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 3196101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3197101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3198101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 3199101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 3200101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 3201101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 3202101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 3203101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 3204101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while ((GLOB_SFT_RST & t) && (i-- > 0)); 3205101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3206101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (GLOB_SFT_RST & t) { 3207101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 3208101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 3209101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3210101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikdone: 3211101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik return rc; 3212101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 3213101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 321447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 3215ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 3216ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 3217ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *port_mmio; 3218ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik u32 tmp; 3219ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3220cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(mmio + RESET_CFG); 3221ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik if ((tmp & (1 << 0)) == 0) { 322247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->signal[idx].amps = 0x7 << 8; 3223ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = 0x1 << 5; 3224ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik return; 3225ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik } 3226ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3227ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik port_mmio = mv_port_base(mmio, idx); 3228ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(port_mmio + PHY_MODE2); 3229ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3230ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3231ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3232ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3233ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 323447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 3235ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 3236cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x00000060, mmio + GPIO_PORT_CTL); 3237ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3238ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3239c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 32402a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 3241bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 3242c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 3243c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3244bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 324547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik int fix_phy_mode2 = 324647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 3247bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik int fix_phy_mode4 = 324847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 32498c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord u32 m2, m3; 325047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 325147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (fix_phy_mode2) { 325247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 325347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 325447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 |= (1 << 31); 325547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 325647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 325747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 325847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 325947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 326047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~((1 << 16) | (1 << 31)); 326147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 326247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 326347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 326447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 326547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 32668c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord /* 32678c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord * Gen-II/IIe PHY_MODE3 errata RM#2: 32688c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord * Achieves better receiver noise performance than the h/w default: 32698c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord */ 32708c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord m3 = readl(port_mmio + PHY_MODE3); 32718c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord m3 = (m3 & 0x1f) | (0x5555601 << 5); 3272bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 32730388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord /* Guideline 88F5182 (GL# SATA-S11) */ 32740388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord if (IS_SOC(hpriv)) 32750388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord m3 &= ~0x1c; 32760388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord 3277bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (fix_phy_mode4) { 3278ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord u32 m4 = readl(port_mmio + PHY_MODE4); 3279ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord /* 3280ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * Enforce reserved-bit restrictions on GenIIe devices only. 3281ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * For earlier chipsets, force only the internal config field 3282ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * (workaround for errata FEr SATA#10 part 1). 3283ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord */ 32848c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord if (IS_GEN_IIE(hpriv)) 3285ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES; 3286ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord else 3287ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE; 32888c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord writel(m4, port_mmio + PHY_MODE4); 3289bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3290b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord /* 3291b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * Workaround for 60x1-B2 errata SATA#13: 3292b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3, 3293b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * so we must always rewrite PHY_MODE3 after PHY_MODE4. 3294ba68460b8e019dfd9c73ab69f5ed163a8b24e296Mark Lord * Or ensure we use writelfl() when writing PHY_MODE4. 3295b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord */ 3296b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord writel(m3, port_mmio + PHY_MODE3); 3297bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3298bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik /* Revert values of pre-emphasis and signal amps to the saved ones */ 3299bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 3300bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3301bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 &= ~MV_M2_PREAMP_MASK; 33022a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].amps; 33032a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].pre; 330447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 3305bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3306e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* according to mvSata 3.6.1, some IIE values are fixed */ 3307e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (IS_GEN_IIE(hpriv)) { 3308e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 &= ~0xC30FF01F; 3309e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 |= 0x0000900F; 3310e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 3311e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 3312bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 3313bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 3314bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3315f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* TODO: use the generic LED interface to configure the SATA Presence */ 3316f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* & Acitivy LEDs on the board */ 3317f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 3318f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3319f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3320f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 3321f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3322f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3323f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 3324f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3325f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3326f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio; 3327f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara u32 tmp; 3328f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3329f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara port_mmio = mv_port_base(mmio, idx); 3330f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(port_mmio + PHY_MODE2); 3331f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3332f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3333f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3334f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3335f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3336f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 3337f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, port_mmio + (reg)) 3338f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 3339f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int port) 3340f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3341f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio = mv_port_base(mmio, port); 3342f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3343e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 3344f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3345f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x028); /* command */ 3346cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x101f, port_mmio + EDMA_CFG); 3347f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x004); /* timer */ 3348f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x008); /* irq err cause */ 3349f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); /* irq err mask */ 3350f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); /* rq bah */ 3351f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); /* rq inp */ 3352f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x018); /* rq outp */ 3353f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x01c); /* respq bah */ 3354f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x024); /* respq outp */ 3355f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x020); /* respq inp */ 3356f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x02c); /* test control */ 3357cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 3358f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3359f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3360f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 3361f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3362f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, hc_mmio + (reg)) 3363f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 3364f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3365f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3366f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *hc_mmio = mv_hc_base(mmio, 0); 3367f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3368f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); 3369f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); 3370f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); 3371f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3372f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3373f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3374f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 3375f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3376f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 3377f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc) 3378f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3379f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int port; 3380f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3381f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara for (port = 0; port < hpriv->n_ports; port++) 3382f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_hc_port(hpriv, mmio, port); 3383f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3384f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_one_hc(hpriv, mmio); 3385f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3386f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 3387f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3388f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3389f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 3390f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3391f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3392f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 3393f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3394f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3395f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 3396f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3397f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 3398f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3399f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 34008e7decdb8b132ee970a2636931b7653dec6af472Mark Lordstatic void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) 3401b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord{ 3402cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 ifcfg = readl(port_mmio + SATA_IFCFG); 3403b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 34048e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */ 3405b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (want_gen2i) 34068e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg |= (1 << 7); /* enable gen2i speed */ 3407cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(ifcfg, port_mmio + SATA_IFCFG); 3408b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord} 3409b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 3410e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 3411c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no) 3412c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 3413c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port_no); 3414c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 34158e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* 34168e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * The datasheet warns against setting EDMA_RESET when EDMA is active 34178e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * (but doesn't say what the problem might be). So we first try 34188e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * to disable the EDMA engine before doing the EDMA_RESET operation. 34198e7decdb8b132ee970a2636931b7653dec6af472Mark Lord */ 34200d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord mv_stop_edma_engine(port_mmio); 3421cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD); 3422c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3423b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (!IS_GEN_I(hpriv)) { 34248e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* Enable 3.0gb/s link speed: this survives EDMA_RESET */ 34258e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(port_mmio, 1); 3426c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 3427b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord /* 34288e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * Strobing EDMA_RESET here causes a hard reset of the SATA transport, 3429b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * link, and physical layers. It resets all SATA interface registers 3430cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord * (except for SATA_IFCFG), and issues a COMRESET to the dev. 3431c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik */ 3432cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD); 3433b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord udelay(25); /* allow reset propagation */ 3434cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, port_mmio + EDMA_CMD); 3435c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3436c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->ops->phy_errata(hpriv, mmio, port_no); 3437c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3438ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) 3439c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mdelay(1); 3440c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3441c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3442e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp) 344320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 3444e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (sata_pmp_supported(ap)) { 3445e49856d82a887ce365637176f9f99ab68076eae8Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 3446cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 reg = readl(port_mmio + SATA_IFCTL); 3447e49856d82a887ce365637176f9f99ab68076eae8Mark Lord int old = reg & 0xf; 344822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 3449e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (old != pmp) { 3450e49856d82a887ce365637176f9f99ab68076eae8Mark Lord reg = (reg & ~0xf) | pmp; 3451cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(reg, port_mmio + SATA_IFCTL); 3452e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 345322374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik } 345420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 345520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3456e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 3457e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 345822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik{ 3459e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 3460e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return sata_std_hardreset(link, class, deadline); 3461e49856d82a887ce365637176f9f99ab68076eae8Mark Lord} 3462bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3463e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 3464e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 3465e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 3466e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 3467e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return ata_sff_softreset(link, class, deadline); 346822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik} 346922374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 3470cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 3471bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned long deadline) 347231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 3473cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo struct ata_port *ap = link->ap; 3474bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 3475b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 3476f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 34770d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord int rc, attempts = 0, extra = 0; 34780d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord u32 sstatus; 34790d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord bool online; 348031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3481e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, ap->port_no); 3482b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 3483d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= 3484d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 3485bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 34860d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Workaround for errata FEr SATA#10 (part 2) */ 34870d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord do { 348817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord const unsigned long *timing = 348917c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord sata_ehc_deb_timing(&link->eh_context); 3490bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 349117c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord rc = sata_link_hardreset(link, timing, deadline + extra, 349217c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord &online, NULL); 34939dcffd99d0b1c0c1b8b2c0f85d240e791eca1055Mark Lord rc = online ? -EAGAIN : rc; 349417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord if (rc) 34950d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord return rc; 34960d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord sata_scr_read(link, SCR_STATUS, &sstatus); 34970d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 34980d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Force 1.5gb/s link speed and try again */ 34998e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(mv_ap_base(ap), 0); 35000d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (time_after(jiffies + HZ, deadline)) 35010d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord extra = HZ; /* only extend it once, max */ 35020d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } 35030d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); 350408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_save_cached_regs(ap); 350566e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord mv_edma_cfg(ap, 0, 0); 3506bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 350717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord return rc; 3508bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 3509bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3510bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap) 3511bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 35121cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord mv_stop_edma(ap); 3513c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_enable_port_irqs(ap, 0); 3514bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 3515bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3516bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap) 3517bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 3518f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 3519c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int port = ap->port_no; 3520c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int hardport = mv_hardport_from_port(port); 35211cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); 3522bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 3523c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 hc_irq_cause; 3524bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3525bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA errors on this port */ 3526cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 3527bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3528bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear pending irq events */ 3529cae6edc3b5a536119374a5439d9b253cb26f05e1Mark Lord hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 3530cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); 3531bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 353288e675e193159b9891c1c576de4348eaf490f5d0Mark Lord mv_enable_port_irqs(ap, ERR_IRQ); 353331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 353431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 353505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 353605b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_init - Perform some early initialization on a single port. 353705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port: libata data structure storing shadow register addresses 353805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port_mmio: base address of the port 353905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 354005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Initialize shadow register mmio addresses, clear outstanding 354105b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts on the port, and unmask interrupts for the future 354205b308e1df6d9d673daedb517969241f41278b52Brett Russ * start of the port. 354305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 354405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 354505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 354605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 354731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 354820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 3549cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord void __iomem *serr, *shd_base = port_mmio + SHD_BLK; 355031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 35518b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik /* PIO related setup 355231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 355331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 35548b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->error_addr = 355531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 355631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 355731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 355831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 355931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 356031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 35618b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->status_addr = 356231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 356331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* special case: control/altstatus doesn't have ATA_REG_ address */ 3564cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST; 356531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 356631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* unused: */ 35678d9db2d2fbae9e05022825c32f86e00c8e342860Randy Dunlap port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; 356820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 356931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding port interrupt conditions */ 3570cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord serr = port_mmio + mv_scr_offset(SCR_ERROR); 3571cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(readl(serr), serr); 3572cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 357331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3574646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord /* unmask all non-transient EDMA error interrupts */ 3575cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK); 357620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 35778b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 3578cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(port_mmio + EDMA_CFG), 3579cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(port_mmio + EDMA_ERR_IRQ_CAUSE), 3580cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(port_mmio + EDMA_ERR_IRQ_MASK)); 358120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 358220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3583616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic unsigned int mv_in_pcix_mode(struct ata_host *host) 3584616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 3585616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 3586616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 3587616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 3588616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 35891f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (IS_SOC(hpriv) || !IS_PCIE(hpriv)) 3590616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not PCI-X capable */ 3591cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord reg = readl(mmio + MV_PCI_MODE); 3592616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if ((reg & MV_PCI_MODE_MASK) == 0) 3593616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* conventional PCI mode */ 3594616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* chip is in PCI-X mode */ 3595616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 3596616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 3597616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic int mv_pci_cut_through_okay(struct ata_host *host) 3598616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 3599616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 3600616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 3601616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 3602616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 3603616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (!mv_in_pcix_mode(host)) { 3604cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord reg = readl(mmio + MV_PCI_COMMAND); 3605cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord if (reg & MV_PCI_COMMAND_MRDTRIG) 3606616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not okay */ 3607616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord } 3608616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* okay */ 3609616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 3610616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 361165ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lordstatic void mv_60x1b2_errata_pci7(struct ata_host *host) 361265ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord{ 361365ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord struct mv_host_priv *hpriv = host->private_data; 361465ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord void __iomem *mmio = hpriv->base; 361565ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord 361665ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord /* workaround for 60x1-B2 errata PCI#7 */ 361765ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord if (mv_in_pcix_mode(host)) { 3618cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 reg = readl(mmio + MV_PCI_COMMAND); 3619cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND); 362065ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord } 362165ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord} 362265ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord 36234447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_chip_id(struct ata_host *host, unsigned int board_idx) 3624bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 36254447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 36264447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 3627bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 3628bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 36295796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik switch (board_idx) { 363047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case chip_5080: 363147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 3632ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 363347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 363444c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 363547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x1: 363647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 363747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 363847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 363947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 364047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 364147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 364247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 364347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying 50XXB2 workarounds to unknown rev\n"); 364447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 364547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 364647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 364747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 364847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 3649bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_504x: 3650bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_508x: 365147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 3652ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 3653bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 365444c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 365547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x0: 365647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 365747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 365847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 365947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 366047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 366147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 366247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 366347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 366447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 366547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 3666bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3667bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3668bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3669bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_604x: 3670bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_608x: 367147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv6xxx_ops; 3672ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_II; 367347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 367444c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 367547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x7: 367665ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord mv_60x1b2_errata_pci7(host); 367747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 367847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 367947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x9: 368047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3681bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3682bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 3683bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 368447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 368547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 3686bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3687bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3688bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3689bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3690e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_7042: 3691616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH; 3692306b30f74d37f289033c696285e07ce0158a5d7bMark Lord if (pdev->vendor == PCI_VENDOR_ID_TTI && 3693306b30f74d37f289033c696285e07ce0158a5d7bMark Lord (pdev->device == 0x2300 || pdev->device == 0x2310)) 3694306b30f74d37f289033c696285e07ce0158a5d7bMark Lord { 36954e5200334e03e5620aa19d538300c13db270a063Mark Lord /* 36964e5200334e03e5620aa19d538300c13db270a063Mark Lord * Highpoint RocketRAID PCIe 23xx series cards: 36974e5200334e03e5620aa19d538300c13db270a063Mark Lord * 36984e5200334e03e5620aa19d538300c13db270a063Mark Lord * Unconfigured drives are treated as "Legacy" 36994e5200334e03e5620aa19d538300c13db270a063Mark Lord * by the BIOS, and it overwrites sector 8 with 37004e5200334e03e5620aa19d538300c13db270a063Mark Lord * a "Lgcy" metadata block prior to Linux boot. 37014e5200334e03e5620aa19d538300c13db270a063Mark Lord * 37024e5200334e03e5620aa19d538300c13db270a063Mark Lord * Configured drives (RAID or JBOD) leave sector 8 37034e5200334e03e5620aa19d538300c13db270a063Mark Lord * alone, but instead overwrite a high numbered 37044e5200334e03e5620aa19d538300c13db270a063Mark Lord * sector for the RAID metadata. This sector can 37054e5200334e03e5620aa19d538300c13db270a063Mark Lord * be determined exactly, by truncating the physical 37064e5200334e03e5620aa19d538300c13db270a063Mark Lord * drive capacity to a nice even GB value. 37074e5200334e03e5620aa19d538300c13db270a063Mark Lord * 37084e5200334e03e5620aa19d538300c13db270a063Mark Lord * RAID metadata is at: (dev->n_sectors & ~0xfffff) 37094e5200334e03e5620aa19d538300c13db270a063Mark Lord * 37104e5200334e03e5620aa19d538300c13db270a063Mark Lord * Warn the user, lest they think we're just buggy. 37114e5200334e03e5620aa19d538300c13db270a063Mark Lord */ 37124e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 37134e5200334e03e5620aa19d538300c13db270a063Mark Lord " BIOS CORRUPTS DATA on all attached drives," 37144e5200334e03e5620aa19d538300c13db270a063Mark Lord " regardless of if/how they are configured." 37154e5200334e03e5620aa19d538300c13db270a063Mark Lord " BEWARE!\n"); 37164e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": For data safety, do not" 37174e5200334e03e5620aa19d538300c13db270a063Mark Lord " use sectors 8-9 on \"Legacy\" drives," 37184e5200334e03e5620aa19d538300c13db270a063Mark Lord " and avoid the final two gigabytes on" 37194e5200334e03e5620aa19d538300c13db270a063Mark Lord " all RocketRAID BIOS initialized drives.\n"); 3720306b30f74d37f289033c696285e07ce0158a5d7bMark Lord } 37218e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* drop through */ 3722e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_6042: 3723e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hpriv->ops = &mv6xxx_ops; 3724e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_GEN_IIE; 3725616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (board_idx == chip_6042 && mv_pci_cut_through_okay(host)) 3726616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_CUT_THROUGH; 3727e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 372844c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 37295cf73bfb061552aa18d816d2859409be9ace5306Mark Lord case 0x2: /* Rev.B0: the first/only public release */ 3730e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3731e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3732e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik default: 3733e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 3734e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik "Applying 60X1C0 workarounds to unknown rev\n"); 3735e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3736e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3737e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 3738e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3739f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara case chip_soc: 3740f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->ops = &mv_soc_ops; 3741eb3a55a9f43f0f8e770c2abf70e65bdda2d5ff1eSaeed Bishara hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE | 3742eb3a55a9f43f0f8e770c2abf70e65bdda2d5ff1eSaeed Bishara MV_HP_ERRATA_60X1C0; 3743f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara break; 3744e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 3745bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 3746f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_ERR, host->dev, 37475796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik "BUG: invalid board index %u\n", board_idx); 3748bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 1; 3749bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3750bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3751bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik hpriv->hp_flags = hp_flags; 375202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord if (hp_flags & MV_HP_PCIE) { 3753cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->irq_cause_offset = PCIE_IRQ_CAUSE; 3754cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->irq_mask_offset = PCIE_IRQ_MASK; 375502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 375602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } else { 3757cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->irq_cause_offset = PCI_IRQ_CAUSE; 3758cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->irq_mask_offset = PCI_IRQ_MASK; 375902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 376002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } 3761bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3762bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 0; 3763bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 3764bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 376505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 376647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik * mv_init_host - Perform some early initialization of the host. 37674447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to initialize 37684447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @board_idx: controller index 376905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 377005b308e1df6d9d673daedb517969241f41278b52Brett Russ * If possible, do an early global reset of the host. Then do 377105b308e1df6d9d673daedb517969241f41278b52Brett Russ * our port init and clear/unmask all/relevant host interrupts. 377205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 377305b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 377405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 377505b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 37764447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_init_host(struct ata_host *host, unsigned int board_idx) 377720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 377820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ int rc = 0, n_hc, port, hc; 37794447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 3780f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 378147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 37824447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_chip_id(host, board_idx); 3783bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (rc) 3784352fab701ca4753dd005b67ce5e512be944eb591Mark Lord goto done; 3785f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 37861f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (IS_SOC(hpriv)) { 3787cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE; 3788cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK; 37891f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord } else { 3790cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE; 3791cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK; 3792f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 3793352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 37945d0fb2e730e2085021cf5c8b6d14983e92aea75bThomas Reitmayr /* initialize shadow irq mask with register's value */ 37955d0fb2e730e2085021cf5c8b6d14983e92aea75bThomas Reitmayr hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr); 37965d0fb2e730e2085021cf5c8b6d14983e92aea75bThomas Reitmayr 3797352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* global interrupt mask: 0 == mask everything */ 3798c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_set_main_irq_mask(host, ~0, 0); 3799bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 38004447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_hc = mv_get_hc_count(host->ports[0]->flags); 3801bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 38024447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) 380347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->read_preamp(hpriv, port, mmio); 380420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3805c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 380647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (rc) 380720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ goto done; 380820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3809522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik hpriv->ops->reset_flash(hpriv, mmio); 38107bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara hpriv->ops->reset_bus(host, mmio); 381147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->enable_leds(hpriv, mmio); 381220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 38134447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) { 3814cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo struct ata_port *ap = host->ports[port]; 38152a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 3816cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 3817cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo mv_port_init(&ap->ioaddr, port_mmio); 3818cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 38197bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 38201f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (!IS_SOC(hpriv)) { 3821f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int offset = port_mmio - mmio; 3822f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 3823f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 3824f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 38257bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 382620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 382720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 382820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hc; hc++) { 382931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 383031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 383131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 383231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ "(before clear)=0x%08x\n", hc, 3833cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(hc_mmio + HC_CFG), 3834cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(hc_mmio + HC_IRQ_CAUSE)); 383531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 383631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding hc interrupt conditions */ 3837cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, hc_mmio + HC_IRQ_CAUSE); 383820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 383920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 384044c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord if (!IS_SOC(hpriv)) { 384144c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord /* Clear any currently outstanding host interrupt conditions */ 3842cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, mmio + hpriv->irq_cause_offset); 384331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 384444c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord /* and unmask interrupt generation for host regs */ 3845cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset); 384644c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord } 384751de32d200b21333950abc52ea1e589bc4eecef7Mark Lord 38486be96ac15e4d913e1f48299db083ada5321803b2Mark Lord /* 38496be96ac15e4d913e1f48299db083ada5321803b2Mark Lord * enable only global host interrupts for now. 38506be96ac15e4d913e1f48299db083ada5321803b2Mark Lord * The per-port interrupts get done later as ports are set up. 38516be96ac15e4d913e1f48299db083ada5321803b2Mark Lord */ 38526be96ac15e4d913e1f48299db083ada5321803b2Mark Lord mv_set_main_irq_mask(host, 0, PCI_ERR); 38532b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_set_irq_coalescing(host, irq_coalescing_io_count, 38542b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord irq_coalescing_usecs); 3855f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharadone: 3856f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3857f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3858fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik 3859fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradleystatic int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 3860fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley{ 3861fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 3862fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRQB_Q_SZ, 0); 3863fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crqb_pool) 3864fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3865fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3866fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 3867fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRPB_Q_SZ, 0); 3868fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crpb_pool) 3869fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3870fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3871fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 3872fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_SG_TBL_SZ, 0); 3873fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->sg_tbl_pool) 3874fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3875fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3876fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return 0; 3877fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley} 3878fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 387915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhekstatic void mv_conf_mbus_windows(struct mv_host_priv *hpriv, 388015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_target_info *dram) 388115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek{ 388215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek int i; 388315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 388415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < 4; i++) { 388515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_CTRL(i)); 388615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_BASE(i)); 388715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 388815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 388915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < dram->num_cs; i++) { 389015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_window *cs = dram->cs + i; 389115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 389215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(((cs->size - 1) & 0xffff0000) | 389315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (cs->mbus_attr << 8) | 389415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (dram->mbus_dram_target_id << 4) | 1, 389515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek hpriv->base + WINDOW_CTRL(i)); 389615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(cs->base, hpriv->base + WINDOW_BASE(i)); 389715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 389815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek} 389915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 3900f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/** 3901f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_probe - handle a positive probe of an soc Marvell 3902f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * host 3903f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device found 3904f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 3905f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * LOCKING: 3906f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Inherited from caller. 3907f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3908f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev) 3909f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3910f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara static int printed_version; 3911f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct mv_sata_platform_data *mv_platform_data; 3912f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct ata_port_info *ppi[] = 3913f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { &mv_port_info[chip_soc], NULL }; 3914f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host; 3915f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv; 3916f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct resource *res; 3917f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports, rc; 391820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3919f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!printed_version++) 3920f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 3921bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3922f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 3923f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Simple resource validation .. 3924f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3925f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (unlikely(pdev->num_resources != 2)) { 3926f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_err(&pdev->dev, "invalid number of resources\n"); 3927f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 3928f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 3929f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3930f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 3931f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Get the register base first 3932f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3933f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3934f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (res == NULL) 3935f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 3936f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3937f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* allocate host */ 3938f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_platform_data = pdev->dev.platform_data; 3939f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara n_ports = mv_platform_data->n_ports; 3940f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3941f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 3942f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 3943f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3944f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!host || !hpriv) 3945f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -ENOMEM; 3946f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->private_data = hpriv; 3947f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 3948f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3949f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->iomap = NULL; 3950f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara hpriv->base = devm_ioremap(&pdev->dev, res->start, 3951f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara res->end - res->start + 1); 3952cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->base -= SATAHC0_REG_BASE; 3953f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 395415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek /* 395515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek * (Re-)program MBUS remapping windows if we are asked to. 395615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek */ 395715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek if (mv_platform_data->dram != NULL) 395815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek mv_conf_mbus_windows(hpriv, mv_platform_data->dram); 395915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 3960fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley rc = mv_create_dma_pools(hpriv, &pdev->dev); 3961fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (rc) 3962fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return rc; 3963fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3964f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* initialize adapter */ 3965f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = mv_init_host(host, chip_soc); 3966f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc) 3967f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3968f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3969f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, 3970f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, 3971f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->n_ports); 3972f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3973f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, 3974f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara IRQF_SHARED, &mv6_sht); 3975f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3976f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3977f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* 3978f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 3979f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_remove - unplug a platform interface 3980f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device 3981f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 3982f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * A platform bus SATA device has been unplugged. Perform the needed 3983f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * cleanup. Also called on module unload for any active devices. 3984f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3985f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev) 3986f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3987f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct device *dev = &pdev->dev; 3988f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host = dev_get_drvdata(dev); 3989f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3990f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_host_detach(host); 3991f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 399220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 399320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3994f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic struct platform_driver mv_platform_driver = { 3995f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_platform_probe, 3996f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .remove = __devexit_p(mv_platform_remove), 3997f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .driver = { 3998f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .name = DRV_NAME, 3999f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .owner = THIS_MODULE, 4000f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 4001f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 4002f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4003f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 40047bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 4005f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 4006f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent); 4007f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 40087bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 40097bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic struct pci_driver mv_pci_driver = { 40107bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .name = DRV_NAME, 40117bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .id_table = mv_pci_tbl, 4012f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_pci_init_one, 40137bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .remove = ata_pci_remove_one, 40147bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara}; 40157bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 40167bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* move to PCI layer or libata core? */ 40177bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int pci_go_64(struct pci_dev *pdev) 40187bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara{ 40197bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc; 40207bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 40216a35528a8346f6e6fd32ed7e51f04d1fa4ca2c01Yang Hongyang if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 40226a35528a8346f6e6fd32ed7e51f04d1fa4ca2c01Yang Hongyang rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 40237bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 4024284901a90a9e0b812ca3f5f852cbbfb60d10249dYang Hongyang rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 40257bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 40267bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 40277bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "64-bit DMA enable failed\n"); 40287bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 40297bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 40307bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 40317bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } else { 4032284901a90a9e0b812ca3f5f852cbbfb60d10249dYang Hongyang rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 40337bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 40347bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 40357bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit DMA enable failed\n"); 40367bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 40377bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 4038284901a90a9e0b812ca3f5f852cbbfb60d10249dYang Hongyang rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 40397bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 40407bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 40417bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit consistent DMA enable failed\n"); 40427bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 40437bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 40447bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 40457bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 40467bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 40477bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara} 40487bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 404905b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 405005b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_print_info - Dump key info to kernel log for perusal. 40514447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to print info about 405205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 405305b308e1df6d9d673daedb517969241f41278b52Brett Russ * FIXME: complete this. 405405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 405505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 405605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 405705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 40584447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic void mv_print_info(struct ata_host *host) 405931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 40604447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 40614447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 406244c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok u8 scc; 4063c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik const char *scc_s, *gen; 406431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 406531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Use this to determine the HW stepping of the chip so we know 406631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * what errata to workaround 406731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 406831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 406931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (scc == 0) 407031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "SCSI"; 407131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else if (scc == 0x01) 407231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "RAID"; 407331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else 4074c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik scc_s = "?"; 4075c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik 4076c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik if (IS_GEN_I(hpriv)) 4077c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "I"; 4078c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_II(hpriv)) 4079c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "II"; 4080c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_IIE(hpriv)) 4081c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "IIE"; 4082c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else 4083c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "?"; 408431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 4085a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, 4086c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 4087c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 408831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 408931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 409031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 409105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 4092f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_pci_init_one - handle a positive probe of a PCI Marvell host 409305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pdev: PCI device found 409405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ent: PCI device ID entry for the matched host 409505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 409605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 409705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 409805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 4099f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 4100f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent) 410120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 41022dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik static int printed_version; 410320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int board_idx = (unsigned int)ent->driver_data; 41044447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 41054447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct ata_host *host; 41064447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv; 41074447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo int n_ports, rc; 410820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4109a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik if (!printed_version++) 4110a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 411120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 41124447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* allocate host */ 41134447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 41144447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 41154447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 41164447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 41174447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (!host || !hpriv) 41184447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return -ENOMEM; 41194447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->private_data = hpriv; 4120f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 41214447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 41224447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* acquire resources */ 412324dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo rc = pcim_enable_device(pdev); 412424dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 412520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return rc; 412620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 41270d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 41280d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc == -EBUSY) 412924dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pcim_pin_device(pdev); 41300d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc) 413124dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 41324447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->iomap = pcim_iomap_table(pdev); 4133f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base = host->iomap[MV_PRIMARY_BAR]; 413420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4135d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik rc = pci_go_64(pdev); 4136d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik if (rc) 4137d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik return rc; 4138d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik 4139da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord rc = mv_create_dma_pools(hpriv, &pdev->dev); 4140da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (rc) 4141da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return rc; 4142da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 414320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* initialize adapter */ 41444447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_init_host(host, board_idx); 414524dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 414624dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 414720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 41486d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord /* Enable message-switched interrupts, if requested */ 41496d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord if (msi && pci_enable_msi(pdev) == 0) 41506d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord hpriv->hp_flags |= MV_HP_FLAG_MSI; 415120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 415231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 41534447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo mv_print_info(host); 415420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 41554447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo pci_set_master(pdev); 4156ea8b4db97aa41a66c05daa4055a1974692ccd52dJeff Garzik pci_try_set_mwi(pdev); 41574447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 4158c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 415920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 41607bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 416120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4162f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev); 4163f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev); 4164f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 416520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic int __init mv_init(void) 416620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 41677bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc = -ENODEV; 41687bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 41697bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_register_driver(&mv_pci_driver); 4170f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 4171f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 4172f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#endif 4173f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = platform_driver_register(&mv_platform_driver); 4174f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4175f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#ifdef CONFIG_PCI 4176f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 4177f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara pci_unregister_driver(&mv_pci_driver); 41787bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 41797bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 418020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 418120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 418220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic void __exit mv_exit(void) 418320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 41847bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 418520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ pci_unregister_driver(&mv_pci_driver); 41867bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 4187f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara platform_driver_unregister(&mv_platform_driver); 418820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 418920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 419020f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_AUTHOR("Brett Russ"); 419120f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 419220f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_LICENSE("GPL"); 419320f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DEVICE_TABLE(pci, mv_pci_tbl); 419420f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_VERSION(DRV_VERSION); 419517c5aab5b34e351531466e35b154ca86db7d46a9Mark LordMODULE_ALIAS("platform:" DRV_NAME); 419620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 419720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_init(mv_init); 419820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_exit(mv_exit); 4199