sata_mv.c revision 352fab701ca4753dd005b67ce5e512be944eb591
120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * sata_mv.c - Marvell SATA support 320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 4e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * Copyright 2008: Marvell Corporation, all rights reserved. 58b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * Copyright 2005: EMC Corporation, all rights reserved. 6e2b1be56c5656902744c2b52e8304126a40bb609Jeff Garzik * Copyright 2005 Red Hat, Inc. All rights reserved. 720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is free software; you can redistribute it and/or modify 1120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * it under the terms of the GNU General Public License as published by 1220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * the Free Software Foundation; version 2 of the License. 1320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is distributed in the hope that it will be useful, 1520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * but WITHOUT ANY WARRANTY; without even the implied warranty of 1620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * GNU General Public License for more details. 1820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * You should have received a copy of the GNU General Public License 2020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * along with this program; if not, write to the Free Software 2120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 2220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 254a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik/* 264a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik sata_mv TODO list: 274a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 284a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 1) Needs a full errata audit for all chipsets. I implemented most 294a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik of the errata workarounds found in the Marvell vendor driver, but 304a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik I distinctly remember a couple workarounds (one related to PCI-X) 314a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik are still needed. 324a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 331fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 2) Improve/fix IRQ and error handling sequences. 341fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 351fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 3) ATAPI support (Marvell claims the 60xx/70xx chips can do it). 361fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 371fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 4) Think about TCQ support here, and for libata in general 381fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord with controllers that suppport it via host-queuing hardware 391fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord (a software-only implementation could be a nightmare). 404a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 414a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 5) Investigate problems with PCI Message Signalled Interrupts (MSI). 424a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 43e49856d82a887ce365637176f9f99ab68076eae8Mark Lord 6) Cache frequently-accessed registers in mv_port_priv to reduce overhead. 444a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 4540f0bc2d77d2d9ead3812f4eec2eefc11455e5deMark Lord 7) Fix/reenable hot plug/unplug (should happen as a side-effect of (2) above). 464a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 474a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 8) Develop a low-power-consumption strategy, and implement it. 484a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 494a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 9) [Experiment, low priority] See if ATAPI can be supported using 504a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik "unknown FIS" or "vendor-specific FIS" support, or something creative 514a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik like that. 524a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 534a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 10) [Experiment, low priority] Investigate interrupt coalescing. 544a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik Quite often, especially with PCI Message Signalled Interrupts (MSI), 554a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik the overhead reduced by interrupt mitigation is quite often not 564a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik worth the latency cost. 574a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 584a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 11) [Experiment, Marvell value added] Is it possible to use target 594a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik mode to cross-connect two Linux boxes with Marvell cards? If so, 604a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik creating LibATA target mode support would be very interesting. 614a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 624a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik Target mode, for those without docs, is the ability to directly 634a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik connect two SATA controllers. 644a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 654a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik*/ 664a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 6720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/kernel.h> 6820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/module.h> 6920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/pci.h> 7020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/init.h> 7120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/blkdev.h> 7220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/delay.h> 7320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/interrupt.h> 748d8b60046d6a2328ca4b9031b4948084f775f607Andrew Morton#include <linux/dmapool.h> 7520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/dma-mapping.h> 76a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik#include <linux/device.h> 77f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/platform_device.h> 78f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/ata_platform.h> 7915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#include <linux/mbus.h> 8020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <scsi/scsi_host.h> 81193515d51ccb363165d6b09e9ba5c21089e34badJeff Garzik#include <scsi/scsi_cmnd.h> 826c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik#include <scsi/scsi_device.h> 8320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/libata.h> 8420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#define DRV_NAME "sata_mv" 861fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord#define DRV_VERSION "1.20" 8720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russenum { 8920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* BAR's are enumerated in terms of pci_resource_start() terms */ 9020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 9120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IO_BAR = 2, /* offset 0x18: IO space */ 9220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 9320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 9420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 9520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 9620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 9720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_BASE = 0, 9820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ 99615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08), 100615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88), 101615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c), 102615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc), 103615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0), 104615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 10520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC0_REG_BASE = 0x20000, 106522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_FLASH_CTL = 0x1046c, 107bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_GPIO_PORT_CTL = 0x104f0, 108bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_RESET_CFG = 0x180d8, 10920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 11020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 11120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 11220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 11320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 11420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 11531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH = 32, 11631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 11731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 11831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* CRQB needs alignment on a 1KB boundary. Size == 1KB 11931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * CRPB needs alignment on a 256B boundary. Size == 256B 12031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 12131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 12231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 12331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 124da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord MV_MAX_SG_CT = 256, 12531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 12631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 127352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ 12820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_HC_SHIFT = 2, 129352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ 130352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ 131352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ 13220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 13320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Host Flags */ 13420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 13520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ 1367bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara /* SoC integrated controllers, no PCI interface */ 137e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord MV_FLAG_SOC = (1 << 28), 1387bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 139c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 140bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI | 141bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ATA_FLAG_PIO_POLLING, 14247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE, 14320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 14431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_FLAG_READ = (1 << 0), 14531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_TAG_SHIFT = 1, 146c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 147e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 148c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 14931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_ADDR_SHIFT = 8, 15031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_CS = (0x2 << 11), 15131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_LAST = (1 << 15), 15231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRPB_FLAG_STATUS_SHIFT = 8, 154c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 155c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 15631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EPRD_FLAG_END_OF_TBL = (1 << 31), 15831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* PCI interface registers */ 16020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 16131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ PCI_COMMAND_OFS = 0xc00, 16231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 16320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MAIN_CMD_STS_OFS = 0xd30, 16420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ STOP_PCI_MASTER = (1 << 2), 16520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MASTER_EMPTY = (1 << 3), 16620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GLOB_SFT_RST = (1 << 4), 16720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 168522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MODE = 0xd00, 169522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 170522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_DISC_TIMER = 0xd04, 171522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MSI_TRIGGER = 0xc38, 172522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_SERR_MASK = 0xc28, 173522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_XBAR_TMOUT = 0x1d04, 174522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 175522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 176522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_ATTRIBUTE = 0x1d48, 177522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_COMMAND = 0x1d50, 178522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 17902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_CAUSE_OFS = 0x1d58, 18002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_MASK_OFS = 0x1d5c, 18120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 18220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 18302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_CAUSE_OFS = 0x1900, 18402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_MASK_OFS = 0x1910, 185646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 18602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 18720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, 18820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_IRQ_MASK_OFS = 0x1d64, 189f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_SOC_MAIN_IRQ_CAUSE_OFS = 0x20020, 190f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_SOC_MAIN_IRQ_MASK_OFS = 0x20024, 191352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ERR_IRQ = (1 << 0), /* shift by port # */ 192352fab701ca4753dd005b67ce5e512be944eb591Mark Lord DONE_IRQ = (1 << 1), /* shift by port # */ 19320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 19420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 19520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_ERR = (1 << 18), 19620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */ 19720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */ 198fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_0_3_COAL_DONE = (1 << 8), 199fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_4_7_COAL_DONE = (1 << 17), 20020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */ 20120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GPIO_INT = (1 << 22), 20220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SELF_INT = (1 << 23), 20320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TWSI_INT = (1 << 24), 20420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 205fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 206e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 2078b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | 20820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT | 20920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD), 210fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 211fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5), 212f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC), 21320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATAHC registers */ 21520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_CFG_OFS = 0, 21620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_IRQ_CAUSE_OFS = 0x14, 218352fab701ca4753dd005b67ce5e512be944eb591Mark Lord DMA_IRQ = (1 << 0), /* shift by port # */ 219352fab701ca4753dd005b67ce5e512be944eb591Mark Lord HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ 22020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ DEV_IRQ = (1 << 8), /* shift by port # */ 22120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 22220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Shadow block registers */ 22331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_BLK_OFS = 0x100, 22431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ 22520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 22620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATA registers */ 22720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ 22820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_ACTIVE_OFS = 0x350, 2290c58912e192fc3a4835d772aafa40b72552b819fMark Lord SATA_FIS_IRQ_CAUSE_OFS = 0x364, 23017c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 231e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord LTMODE_OFS = 0x30c, 23217c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 23317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 23447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik PHY_MODE3 = 0x310, 235bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE4 = 0x314, 236bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE2 = 0x330, 237e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFCTL_OFS = 0x344, 238e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFSTAT_OFS = 0x34c, 239e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord VENDOR_UNIQUE_FIS_OFS = 0x35c, 24017c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 241e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord FIS_CFG_OFS = 0x360, 24217c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord FIS_CFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 24317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 244c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_MODE = 0x74, 245c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_LT_MODE = 0x30, 246c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_CTL = 0x0C, 247e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_INTERFACE_CFG = 0x050, 248bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 249bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_M2_PREAMP_MASK = 0x7e0, 25020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Port registers */ 25220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_CFG_OFS = 0, 2530c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 2540c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 2550c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 2560c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 2570c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 258e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 259e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 26020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 26120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_CAUSE_OFS = 0x8, 26220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_MASK_OFS = 0xc, 2636c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 2646c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 2656c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV = (1 << 2), /* device error */ 2666c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 2676c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 2686c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 269c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 270c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 2716c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 272c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 2736c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 2746c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 2756c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 2766c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 277646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2786c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 279646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 280646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 281646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 282646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 283646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2846c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 285646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2866c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 287646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 288646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 289646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 290646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 291646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 292646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2936c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 294646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2956c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 296c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_OVERRUN_5 = (1 << 5), 297c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_UNDERRUN_5 = (1 << 6), 298646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 299646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 300646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 | 301646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 | 30240f0bc2d77d2d9ead3812f4eec2eefc11455e5deMark Lord EDMA_ERR_LNK_CTRL_TX | 30340f0bc2d77d2d9ead3812f4eec2eefc11455e5deMark Lord /* temporary, until we fix hotplug: */ 30440f0bc2d77d2d9ead3812f4eec2eefc11455e5deMark Lord (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON), 305646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 306bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 307bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 308bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 309bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 310bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SERR | 311bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS | 3126c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 313bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 314bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 315bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY | 316bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_CTRL_RX_2 | 317bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_RX | 318bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_TX | 319bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_TRANS_PROTO, 320e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 321bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 322bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 323bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 324bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 325bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_OVERRUN_5 | 326bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_UNDERRUN_5 | 327bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS_5 | 3286c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 329bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 330bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 331bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY, 33220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 33331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_BASE_HI_OFS = 0x10, 33431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ 33531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 33631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_OUT_PTR_OFS = 0x18, 33731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_PTR_SHIFT = 5, 33831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 33931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_BASE_HI_OFS = 0x1c, 34031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_IN_PTR_OFS = 0x20, 34131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ 34231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_PTR_SHIFT = 3, 34331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3440ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_CMD_OFS = 0x28, /* EDMA command register */ 3450ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_EN = (1 << 0), /* enable EDMA */ 3460ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 3470ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik ATA_RST = (1 << 2), /* reset trans/link/phy */ 34820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 349c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik EDMA_IORDY_TMOUT = 0x34, 350bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik EDMA_ARB_CFG = 0x38, 351bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 352352fab701ca4753dd005b67ce5e512be944eb591Mark Lord GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */ 353352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 35431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Host private flags (hp_flags) */ 35531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_HP_FLAG_MSI = (1 << 0), 35647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB0 = (1 << 1), 35747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB2 = (1 << 2), 35847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1B2 = (1 << 3), 35947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1C0 = (1 << 4), 360e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik MV_HP_ERRATA_XX42A0 = (1 << 5), 3610ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 3620ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 3630ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 36402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 36520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 36631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Port private flags (pp_flags) */ 3670ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 368721091685f853ba4e6c49f26f989db0b1a811250Mark Lord MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 36920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 37020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 371ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 372ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 373e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 3747bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC)) 375bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 37615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 37715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_BASE(i) (0x20034 + ((i) << 4)) 37815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 379095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzikenum { 380baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik /* DMA boundary 0xffff is required by the s/g splitting 381baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik * we need on /length/ in mv_fill-sg(). 382baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik */ 383baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik MV_DMA_BOUNDARY = 0xffffU, 384095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3850ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* mask of register bits containing lower 32 bits 3860ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik * of EDMA request queue DMA address 3870ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik */ 388095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 389095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3900ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* ditto, for response queue */ 391095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 392095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik}; 393095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 394522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikenum chip_type { 395522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_504x, 396522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_508x, 397522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_5080, 398522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_604x, 399522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_608x, 400e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_6042, 401e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_7042, 402f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara chip_soc, 403522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik}; 404522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 40531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ReQuest Block: 32B */ 40631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crqb { 407e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr; 408e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr_hi; 409e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ctrl_flags; 410e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ata_cmd[11]; 41131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 41220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 413e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstruct mv_crqb_iie { 414e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 415e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 416e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags; 417e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 len; 418e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 ata_cmd[4]; 419e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 420e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 42131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ResPonse Block: 8B */ 42231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crpb { 423e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 id; 424e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 flags; 425e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 tmstmp; 42620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 42720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 42831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 42931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_sg { 430e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 431e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags_size; 432e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 433e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 reserved; 43431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 43520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 43631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_port_priv { 43731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crqb *crqb; 43831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crqb_dma; 43931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crpb *crpb; 44031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crpb_dma; 441eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 442eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 443bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 444bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int req_idx; 445bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int resp_idx; 446bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 44731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 pp_flags; 44831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 44931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 450bca1c4eb9411533d613123618c0d127fae532595Jeff Garzikstruct mv_port_signal { 451bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 amps; 452bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 pre; 453bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik}; 454bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 45502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lordstruct mv_host_priv { 45602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 hp_flags; 45702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_port_signal signal[8]; 45802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord const struct mv_hw_ops *ops; 459f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports; 460f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *base; 461f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *main_cause_reg_addr; 462f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *main_mask_reg_addr; 46302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_cause_ofs; 46402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_mask_ofs; 46502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 unmask_all_irqs; 466da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord /* 467da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * These consistent DMA memory pools give us guaranteed 468da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * alignment for hardware-accessed data structures, 469da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * and less memory waste in accomplishing the alignment. 470da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord */ 471da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crqb_pool; 472da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crpb_pool; 473da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *sg_tbl_pool; 47402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord}; 47502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 47647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstruct mv_hw_ops { 4772a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 4782a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 47947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 48047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 48147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 482c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 483c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 484522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 4857bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 48647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 48747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 488da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 489da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 490da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 491da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 49231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap); 49331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap); 49431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc); 495e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc); 4969a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 497a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 498a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo unsigned long deadline); 499bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap); 500bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap); 501f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *dev); 50220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 5032a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5042a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 50547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 50647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 50747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 508c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 509c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 510522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 5117bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 51247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 5132a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5142a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 51547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 51647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 51747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 518c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 519c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 520522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 521f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 522f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 523f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 524f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 525f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 526f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc); 527f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 528f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 529f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 5307bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 531e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 532c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no); 533e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap); 534b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio); 535e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq); 53647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 537e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp); 538e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 539e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 540e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 541e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 54247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 543eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 544eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * because we have to allow room for worst case splitting of 545eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * PRDs for 64K boundaries in mv_fill_sg(). 546eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 547c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv5_sht = { 54868d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BASE_SHT(DRV_NAME), 549baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 550c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .dma_boundary = MV_DMA_BOUNDARY, 551c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik}; 552c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 553c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv6_sht = { 55468d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_NCQ_SHT(DRV_NAME), 555138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .can_queue = MV_MAX_Q_DEPTH - 1, 556baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 55720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .dma_boundary = MV_DMA_BOUNDARY, 55820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 55920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 560029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv5_ops = { 561029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &ata_sff_port_ops, 562c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 563c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_prep = mv_qc_prep, 564c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_issue = mv_qc_issue, 565c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 566bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .freeze = mv_eh_freeze, 567bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .thaw = mv_eh_thaw, 568a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .hardreset = mv_hardreset, 569a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .error_handler = ata_std_error_handler, /* avoid SFF EH */ 570029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .post_internal_cmd = ATA_OP_NULL, 571bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 572c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_read = mv5_scr_read, 573c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_write = mv5_scr_write, 574c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 575c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_start = mv_port_start, 576c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_stop = mv_port_stop, 577c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik}; 578c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 579029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv6_ops = { 580029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv5_ops, 581e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .qc_defer = sata_pmp_qc_defer_cmd_switch, 582f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord .dev_config = mv6_dev_config, 58320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_read = mv_scr_read, 58420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_write = mv_scr_write, 58520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 586e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_hardreset = mv_pmp_hardreset, 587e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_softreset = mv_softreset, 588e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .softreset = mv_softreset, 589e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .error_handler = sata_pmp_error_handler, 59020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 59120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 592029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv_iie_ops = { 593029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv6_ops, 594e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .qc_defer = ata_std_qc_defer, /* FIS-based switching */ 595029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .dev_config = ATA_OP_NULL, 596e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .qc_prep = mv_qc_prep_iie, 597e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 598e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 59998ac62defe529d04a192688f40d801a2d8fbcf98Arjan van de Venstatic const struct ata_port_info mv_port_info[] = { 60020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_504x */ 601cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik .flags = MV_COMMON_FLAGS, 60231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 603bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 604c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 60520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 60620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_508x */ 607c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 60831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 609bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 610c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 61120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 61247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik { /* chip_5080 */ 613c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 61447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 615bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 616c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 61747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik }, 61820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_604x */ 619138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 620e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 621138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 62231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 623bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 624c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 62520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 62620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_608x */ 627c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 628e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 629138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ | MV_FLAG_DUAL_HC, 63031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 631bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 632c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 63320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 634e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_6042 */ 635138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 636e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 637138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 638e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 639bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 640e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 641e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 642e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_7042 */ 643138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 644e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 645138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 646e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 647bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 648e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 649e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 650f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { /* chip_soc */ 65102c1f32f1c524d2a389989f2482121f7c7d9b164Mark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 652e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 65302c1f32f1c524d2a389989f2482121f7c7d9b164Mark Lord ATA_FLAG_NCQ | MV_FLAG_SOC, 65417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .pio_mask = 0x1f, /* pio0-4 */ 65517c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .udma_mask = ATA_UDMA6, 65617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .port_ops = &mv_iie_ops, 657f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 65820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 65920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 6603b7d697dfb7d03edb87e50b743a7ecff029618e9Jeff Garzikstatic const struct pci_device_id mv_pci_tbl[] = { 6612d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 6622d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 6632d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 6642d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 665cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox /* RocketRAID 1740/174x have different identifiers */ 666cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox { PCI_VDEVICE(TTI, 0x1740), chip_508x }, 667cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox { PCI_VDEVICE(TTI, 0x1742), chip_508x }, 6682d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 6692d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 6702d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 6712d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 6722d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 6732d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 6742d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 6752d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 6762d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 677d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger /* Adaptec 1430SA */ 678d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 679d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger 68002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Marvell 7042 support */ 6816a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 6826a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom 68302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Highpoint RocketRAID PCIe series */ 68402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 68502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 68602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 6872d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { } /* terminate list */ 68820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 68920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 69047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv5xxx_ops = { 69147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv5_phy_errata, 69247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv5_enable_leds, 69347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv5_read_preamp, 69447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv5_reset_hc, 695522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv5_reset_flash, 696522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv5_reset_bus, 69747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 69847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 69947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv6xxx_ops = { 70047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv6_phy_errata, 70147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv6_enable_leds, 70247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv6_read_preamp, 70347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv6_reset_hc, 704522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv6_reset_flash, 705522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv_reset_pci_bus, 70647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 70747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 708f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic const struct mv_hw_ops mv_soc_ops = { 709f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .phy_errata = mv6_phy_errata, 710f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .enable_leds = mv_soc_enable_leds, 711f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .read_preamp = mv_soc_read_preamp, 712f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_hc = mv_soc_reset_hc, 713f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_flash = mv_soc_reset_flash, 714f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_bus = mv_soc_reset_bus, 715f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 716f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 71720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 71820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Functions 71920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 72020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 72120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void writelfl(unsigned long data, void __iomem *addr) 72220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 72320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writel(data, addr); 72420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ (void) readl(addr); /* flush to avoid PCI posted write */ 72520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 72620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 727c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hc_from_port(unsigned int port) 728c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 729c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port >> MV_PORT_HC_SHIFT; 730c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 731c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 732c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hardport_from_port(unsigned int port) 733c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 734c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port & MV_PORT_MASK; 735c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 736c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 737352fab701ca4753dd005b67ce5e512be944eb591Mark Lordstatic inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 738352fab701ca4753dd005b67ce5e512be944eb591Mark Lord{ 739352fab701ca4753dd005b67ce5e512be944eb591Mark Lord return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 740352fab701ca4753dd005b67ce5e512be944eb591Mark Lord} 741352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 742c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline void __iomem *mv_hc_base_from_port(void __iomem *base, 743c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 744c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 745c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base(base, mv_hc_from_port(port)); 746c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 747c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 74820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 74920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 750c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base_from_port(base, port) + 7518b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik MV_SATAHC_ARBTR_REG_SZ + 752c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 75320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 75420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 755e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 756e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord{ 757e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 758e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 759e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 760e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord return hc_mmio + ofs; 761e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord} 762e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 763f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic inline void __iomem *mv_host_base(struct ata_host *host) 764f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 765f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 766f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return hpriv->base; 767f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 768f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 76920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_ap_base(struct ata_port *ap) 77020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 771f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return mv_port_base(mv_host_base(ap->host), ap->port_no); 77220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 77320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 774cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic inline int mv_get_hc_count(unsigned long port_flags) 77531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 776cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 77731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 77831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 779c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic void mv_set_edma_ptrs(void __iomem *port_mmio, 780c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_host_priv *hpriv, 781c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp) 782c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik{ 783bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 index; 784bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 785c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 786c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize request queue 787c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 788bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik index = (pp->req_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_REQ_Q_PTR_SHIFT; 789bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 790c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crqb_dma & 0x3ff); 791c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); 792bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 793c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 794c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 795c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) 796bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & 0xffffffff) | index, 797c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 798c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik else 799bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 800c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 801c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 802c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize response queue 803c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 804bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik index = (pp->resp_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_RSP_Q_PTR_SHIFT; 805bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 806c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crpb_dma & 0xff); 807c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); 808c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 809c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) 810bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & 0xffffffff) | index, 811c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 812c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik else 813bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 814c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 815bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 816c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 817c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik} 818c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 81905b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 82005b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_start_dma - Enable eDMA engine 82105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @base: port base address 82205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pp: port private data 82305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 824beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * Verify the local cache of the eDMA state is accurate with a 825beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * WARN_ON. 82605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 82705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 82805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 82905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 8300c58912e192fc3a4835d772aafa40b72552b819fMark Lordstatic void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio, 831721091685f853ba4e6c49f26f989db0b1a811250Mark Lord struct mv_port_priv *pp, u8 protocol) 83220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 833721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int want_ncq = (protocol == ATA_PROT_NCQ); 834721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 835721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 836721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 837721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq != using_ncq) 838b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 839721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } 840c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 8410c58912e192fc3a4835d772aafa40b72552b819fMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 842352fab701ca4753dd005b67ce5e512be944eb591Mark Lord int hardport = mv_hardport_from_port(ap->port_no); 8430c58912e192fc3a4835d772aafa40b72552b819fMark Lord void __iomem *hc_mmio = mv_hc_base_from_port( 844352fab701ca4753dd005b67ce5e512be944eb591Mark Lord mv_host_base(ap->host), hardport); 8450c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 hc_irq_cause, ipending; 8460c58912e192fc3a4835d772aafa40b72552b819fMark Lord 847bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA event indicators, if any */ 848f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 849bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 8500c58912e192fc3a4835d772aafa40b72552b819fMark Lord /* clear EDMA interrupt indicator, if any */ 8510c58912e192fc3a4835d772aafa40b72552b819fMark Lord hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 852352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ipending = (DEV_IRQ | DMA_IRQ) << hardport; 8530c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (hc_irq_cause & ipending) { 8540c58912e192fc3a4835d772aafa40b72552b819fMark Lord writelfl(hc_irq_cause & ~ipending, 8550c58912e192fc3a4835d772aafa40b72552b819fMark Lord hc_mmio + HC_IRQ_CAUSE_OFS); 8560c58912e192fc3a4835d772aafa40b72552b819fMark Lord } 8570c58912e192fc3a4835d772aafa40b72552b819fMark Lord 858e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_edma_cfg(ap, want_ncq); 8590c58912e192fc3a4835d772aafa40b72552b819fMark Lord 8600c58912e192fc3a4835d772aafa40b72552b819fMark Lord /* clear FIS IRQ Cause */ 8610c58912e192fc3a4835d772aafa40b72552b819fMark Lord writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 8620c58912e192fc3a4835d772aafa40b72552b819fMark Lord 863f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord mv_set_edma_ptrs(port_mmio, hpriv, pp); 864bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 865f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS); 866afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 867afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 86820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 86920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 87005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 871e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * mv_stop_edma_engine - Disable eDMA engine 872b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * @port_mmio: io base address 87305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 87405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 87505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 87605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 877b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio) 87820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 879b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord int i; 88031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 881b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Disable eDMA. The disable bit auto clears. */ 882b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); 8838b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 884b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Wait for the chip to confirm eDMA is off. */ 885b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord for (i = 10000; i > 0; i--) { 886b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord u32 reg = readl(port_mmio + EDMA_CMD_OFS); 8874537deb5e90b717a725b3d74b58b4bb1d28443d0Jeff Garzik if (!(reg & EDMA_EN)) 888b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 889b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord udelay(10); 89031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 891b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 89220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 89320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 894e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap) 8950ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik{ 896b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord void __iomem *port_mmio = mv_ap_base(ap); 897b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 8980ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 899b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 900b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 901b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 902b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (mv_stop_edma_engine(port_mmio)) { 903b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); 904b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 905b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord } 906b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 9070ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik} 9080ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 9098a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#ifdef ATA_DEBUG 91031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_mem(void __iomem *start, unsigned bytes) 91120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 91231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 91331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 91431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%p: ", start + b); 91531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 9162dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", readl(start + b)); 91731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 91831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 91931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 92031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 92131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 9228a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#endif 9238a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik 92431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 92531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 92631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 92731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 92831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 dw; 92931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 93031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%02x: ", b); 93131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 9322dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik (void) pci_read_config_dword(pdev, b, &dw); 9332dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", dw); 93431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 93531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 93631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 93731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 93831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 93931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 94031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_all_regs(void __iomem *mmio_base, int port, 94131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct pci_dev *pdev) 94231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 94331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 9448b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik void __iomem *hc_base = mv_hc_base(mmio_base, 94531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port >> MV_PORT_HC_SHIFT); 94631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_base; 94731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int start_port, num_ports, p, start_hc, num_hcs, hc; 94831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 94931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (0 > port) { 95031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = start_port = 0; 95131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = 8; /* shld be benign for 4 port devs */ 95231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_hcs = 2; 95331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } else { 95431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = port >> MV_PORT_HC_SHIFT; 95531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_port = port; 95631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = num_hcs = 1; 95731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 9588b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik DPRINTK("All registers for port(s) %u-%u:\n", start_port, 95931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports > 1 ? num_ports - 1 : start_port); 96031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 96131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (NULL != pdev) { 96231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI config space regs:\n"); 96331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 96431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 96531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI regs:\n"); 96631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xc00, 0x3c); 96731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xd00, 0x34); 96831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xf00, 0x4); 96931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0x1d00, 0x6c); 97031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 971d220c37e0a3c9a47ae00e87e044d963b3ea040bcDan Aloni hc_base = mv_hc_base(mmio_base, hc); 97231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("HC regs (HC %i):\n", hc); 97331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(hc_base, 0x1c); 97431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 97531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (p = start_port; p < start_port + num_ports; p++) { 97631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port_base = mv_port_base(mmio_base, p); 9772dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("EDMA regs (port %i):\n", p); 97831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base, 0x54); 9792dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("SATA regs (port %i):\n", p); 98031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base+0x300, 0x60); 98131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 98231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 98320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 98420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 98520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic unsigned int mv_scr_offset(unsigned int sc_reg_in) 98620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 98720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs; 98820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 98920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ switch (sc_reg_in) { 99020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_STATUS: 99120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_CONTROL: 99220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ERROR: 99320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); 99420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 99520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ACTIVE: 99620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_ACTIVE_OFS; /* active is not with the others */ 99720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 99820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ default: 99920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = 0xffffffffU; 100020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 100120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 100220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return ofs; 100320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 100420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1005da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 100620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 100720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 100820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1009da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 1010da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(mv_ap_base(ap) + ofs); 1011da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1012da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1013da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 101420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 101520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1016da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 101720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 101820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 101920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1020da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 102120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writelfl(val, mv_ap_base(ap) + ofs); 1022da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1023da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1024da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 102520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 102620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1027f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *adev) 1028f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord{ 1029f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord /* 1030e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Deal with Gen-II ("mv6") hardware quirks/restrictions: 1031e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * 1032e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Gen-II does not support NCQ over a port multiplier 1033e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * (no FIS-based switching). 1034e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * 1035f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord * We don't have hob_nsect when doing NCQ commands on Gen-II. 1036f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord * See mv_qc_prep() for more info. 1037f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord */ 1038e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (adev->flags & ATA_DFLAG_NCQ) { 1039352fab701ca4753dd005b67ce5e512be944eb591Mark Lord if (sata_pmp_attached(adev->link->ap)) { 1040e49856d82a887ce365637176f9f99ab68076eae8Mark Lord adev->flags &= ~ATA_DFLAG_NCQ; 1041352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ata_dev_printk(adev, KERN_INFO, 1042352fab701ca4753dd005b67ce5e512be944eb591Mark Lord "NCQ disabled for command-based switching\n"); 1043352fab701ca4753dd005b67ce5e512be944eb591Mark Lord } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) { 1044352fab701ca4753dd005b67ce5e512be944eb591Mark Lord adev->max_sectors = GEN_II_NCQ_MAX_SECTORS; 1045352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ata_dev_printk(adev, KERN_INFO, 1046352fab701ca4753dd005b67ce5e512be944eb591Mark Lord "max_sectors limited to %u for NCQ\n", 1047352fab701ca4753dd005b67ce5e512be944eb591Mark Lord adev->max_sectors); 1048352fab701ca4753dd005b67ce5e512be944eb591Mark Lord } 1049e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 1050f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1051f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 1052e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_config_fbs(void __iomem *port_mmio, int enable_fbs) 1053e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 1054e49856d82a887ce365637176f9f99ab68076eae8Mark Lord u32 old_fcfg, new_fcfg, old_ltmode, new_ltmode; 1055e49856d82a887ce365637176f9f99ab68076eae8Mark Lord /* 1056e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Various bit settings required for operation 1057e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * in FIS-based switching (fbs) mode on GenIIe: 1058e49856d82a887ce365637176f9f99ab68076eae8Mark Lord */ 1059e49856d82a887ce365637176f9f99ab68076eae8Mark Lord old_fcfg = readl(port_mmio + FIS_CFG_OFS); 1060e49856d82a887ce365637176f9f99ab68076eae8Mark Lord old_ltmode = readl(port_mmio + LTMODE_OFS); 1061e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (enable_fbs) { 1062e49856d82a887ce365637176f9f99ab68076eae8Mark Lord new_fcfg = old_fcfg | FIS_CFG_SINGLE_SYNC; 1063e49856d82a887ce365637176f9f99ab68076eae8Mark Lord new_ltmode = old_ltmode | LTMODE_BIT8; 1064e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } else { /* disable fbs */ 1065e49856d82a887ce365637176f9f99ab68076eae8Mark Lord new_fcfg = old_fcfg & ~FIS_CFG_SINGLE_SYNC; 1066e49856d82a887ce365637176f9f99ab68076eae8Mark Lord new_ltmode = old_ltmode & ~LTMODE_BIT8; 1067e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 1068e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (new_fcfg != old_fcfg) 1069e49856d82a887ce365637176f9f99ab68076eae8Mark Lord writelfl(new_fcfg, port_mmio + FIS_CFG_OFS); 1070e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (new_ltmode != old_ltmode) 1071e49856d82a887ce365637176f9f99ab68076eae8Mark Lord writelfl(new_ltmode, port_mmio + LTMODE_OFS); 1072f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1073f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 1074e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq) 1075e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 10760c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 cfg; 1077e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_port_priv *pp = ap->private_data; 1078e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1079e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1080e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1081e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* set up non-NCQ EDMA configuration */ 10820c58912e192fc3a4835d772aafa40b72552b819fMark Lord cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 1083e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 10840c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (IS_GEN_I(hpriv)) 1085e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 8); /* enab config burst size mask */ 1086e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 10870c58912e192fc3a4835d772aafa40b72552b819fMark Lord else if (IS_GEN_II(hpriv)) 1088e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1089e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1090e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik else if (IS_GEN_IIE(hpriv)) { 1091e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 1092e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 22); /* enab 4-entry host queue cache */ 1093e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 18); /* enab early completion */ 1094e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */ 1095e49856d82a887ce365637176f9f99ab68076eae8Mark Lord 1096e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (want_ncq && sata_pmp_attached(ap)) { 1097e49856d82a887ce365637176f9f99ab68076eae8Mark Lord cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ 1098e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_config_fbs(port_mmio, 1); 1099e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } else { 1100e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_config_fbs(port_mmio, 0); 1101e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 1102e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 1103e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1104721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq) { 1105721091685f853ba4e6c49f26f989db0b1a811250Mark Lord cfg |= EDMA_CFG_NCQ; 1106721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 1107721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } else 1108721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN; 1109721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1110e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik writelfl(cfg, port_mmio + EDMA_CFG_OFS); 1111e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1112e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1113da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordstatic void mv_port_free_dma_mem(struct ata_port *ap) 1114da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord{ 1115da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1116da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_port_priv *pp = ap->private_data; 1117eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord int tag; 1118da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1119da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crqb) { 1120da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1121da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = NULL; 1122da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1123da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crpb) { 1124da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1125da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = NULL; 1126da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1127eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1128eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1129eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we have one unique sg_tbl per NCQ tag. 1130eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1131eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1132eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (pp->sg_tbl[tag]) { 1133eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) 1134eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_pool_free(hpriv->sg_tbl_pool, 1135eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag], 1136eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag]); 1137eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = NULL; 1138eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1139da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1140da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord} 1141da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 114205b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 114305b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_start - Port specific init/start routine. 114405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 114505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 114605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Allocate and point to DMA memory, init port private memory, 114705b308e1df6d9d673daedb517969241f41278b52Brett Russ * zero indices. 114805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 114905b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 115005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 115105b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 115231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap) 115331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1154cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct device *dev = ap->host->dev; 1155cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 115631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp; 1157dde2020754aeb14e17052d61784dcb37f252aac2James Bottomley int tag; 115831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 115924dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 11606037d6bbdff65eb5a84fe35e140f4da4f7cc103aJeff Garzik if (!pp) 116124dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return -ENOMEM; 1162da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord ap->private_data = pp; 116331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1164da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1165da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crqb) 1166da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 1167da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crqb, 0, MV_CRQB_Q_SZ); 116831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1169da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1170da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crpb) 1171da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord goto out_port_free_dma_mem; 1172da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crpb, 0, MV_CRPB_Q_SZ); 117331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1174eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1175eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1176eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we need one unique sg_tbl per NCQ tag. 1177eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1178eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1179eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) { 1180eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1181eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1182eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (!pp->sg_tbl[tag]) 1183eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord goto out_port_free_dma_mem; 1184eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } else { 1185eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = pp->sg_tbl[0]; 1186eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1187eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1188eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 118931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 1190da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1191da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordout_port_free_dma_mem: 1192da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 1193da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 119431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 119531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 119605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 119705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_stop - Port specific cleanup/stop routine. 119805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 119905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 120005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Stop DMA, cleanup port memory. 120105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 120205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 1203cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine uses the host lock to protect the DMA stop. 120405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 120531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap) 120631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1207e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma(ap); 1208da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 120931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 121031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 121105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 121205b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 121305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command whose SG list to source from 121405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 121505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Populate the SG list and mark the last entry. 121605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 121705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 121805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 121905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 12206c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzikstatic void mv_fill_sg(struct ata_queued_cmd *qc) 122131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 122231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = qc->ap->private_data; 1223972c26bdd6b58e7534473c4f7928584578cf43f4Jeff Garzik struct scatterlist *sg; 12243be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik struct mv_sg *mv_sg, *last_sg = NULL; 1225ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo unsigned int si; 122631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1227eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord mv_sg = pp->sg_tbl[qc->tag]; 1228ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 1229d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik dma_addr_t addr = sg_dma_address(sg); 1230d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik u32 sg_len = sg_dma_len(sg); 123122374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 12324007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson while (sg_len) { 12334007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 offset = addr & 0xffff; 12344007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 len = sg_len; 123522374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 12364007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson if ((offset + sg_len > 0x10000)) 12374007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson len = 0x10000 - offset; 12384007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 12394007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 12404007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 12416c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik mv_sg->flags_size = cpu_to_le32(len & 0xffff); 12424007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 12434007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson sg_len -= len; 12444007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson addr += len; 12454007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 12463be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg = mv_sg; 12474007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg++; 12484007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson } 124931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 12503be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik 12513be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik if (likely(last_sg)) 12523be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 125331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 125431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 12555796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzikstatic void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 125631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1257559eedad7f7764dacca33980127b4615011230e4Mark Lord u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 125831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ (last ? CRQB_CMD_LAST : 0); 1259559eedad7f7764dacca33980127b4615011230e4Mark Lord *cmdw = cpu_to_le16(tmp); 126031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 126131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 126205b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 126305b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_prep - Host specific command preparation. 126405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to prepare 126505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 126605b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 126705b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it handles prep of the CRQB 126805b308e1df6d9d673daedb517969241f41278b52Brett Russ * (command request block), does some sanity checking, and calls 126905b308e1df6d9d673daedb517969241f41278b52Brett Russ * the SG load routine. 127005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 127105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 127205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 127305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 127431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc) 127531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 127631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_port *ap = qc->ap; 127731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = ap->private_data; 1278e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 *cw; 127931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_taskfile *tf; 128031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u16 flags = 0; 1281a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 128231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1283138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1284138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 128531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 128620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 128731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Fill in command request block 128831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1289e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 129031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= CRQB_FLAG_READ; 1291beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 129231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= qc->tag << CRQB_TAG_SHIFT; 1293e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 129431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1295bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1296bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = pp->req_idx & MV_MAX_Q_DEPTH_MASK; 1297a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1298a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr = 1299eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1300a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr_hi = 1301eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1302a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 130331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1304a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord cw = &pp->crqb[in_index].ata_cmd[0]; 130531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ tf = &qc->tf; 130631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 130731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Sadly, the CRQB cannot accomodate all registers--there are 130831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * only 11 bytes...so we must pick and choose required 130931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * registers based on the command. So, we drop feature and 131031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * hob_feature for [RW] DMA commands, but they are needed for 131131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * NCQ. NCQ will drop hob_nsect. 131220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 131331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ switch (tf->command) { 131431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ: 131531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ_EXT: 131631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE: 131731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE_EXT: 1318c15d85c8f3f73b5f20aae7928e25b6996f16b328Jens Axboe case ATA_CMD_WRITE_FUA_EXT: 131931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 132031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 132131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_READ: 132231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_WRITE: 13238b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 132431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 132531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 132631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ default: 132731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* The only other commands EDMA supports in non-queued and 132831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 132931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * of which are defined/used by Linux. If we get here, this 133031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * driver needs work. 133131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * 133231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * FIXME: modify libata to give qc_prep a return value and 133331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * return error here. 133431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 133531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ BUG_ON(tf->command); 133631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 133731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 133831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 133931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 134031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 134131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 134231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 134331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 134431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 134531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 134631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 134731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1348e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 1349e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1350e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik mv_fill_sg(qc); 1351e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1352e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1353e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik/** 1354e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * mv_qc_prep_iie - Host specific command preparation. 1355e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * @qc: queued command to prepare 1356e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1357e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * This routine simply redirects to the general purpose routine 1358e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * if command is not DMA. Else, it handles prep of the CRQB 1359e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * (command request block), does some sanity checking, and calls 1360e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * the SG load routine. 1361e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1362e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * LOCKING: 1363e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * Inherited from caller. 1364e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik */ 1365e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc) 1366e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 1367e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_port *ap = qc->ap; 1368e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_port_priv *pp = ap->private_data; 1369e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_crqb_iie *crqb; 1370e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_taskfile *tf; 1371a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 1372e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik u32 flags = 0; 1373e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1374138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1375138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 1376e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1377e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1378e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* Fill in Gen IIE command request block */ 1379e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 1380e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= CRQB_FLAG_READ; 1381e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1382beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 1383e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= qc->tag << CRQB_TAG_SHIFT; 13848c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord flags |= qc->tag << CRQB_HOSTQ_SHIFT; 1385e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 1386e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1387bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1388bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = pp->req_idx & MV_MAX_Q_DEPTH_MASK; 1389a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1390a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 1391eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1392eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1393e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->flags = cpu_to_le32(flags); 1394e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1395e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik tf = &qc->tf; 1396e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[0] = cpu_to_le32( 1397e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->command << 16) | 1398e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->feature << 24) 1399e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1400e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[1] = cpu_to_le32( 1401e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbal << 0) | 1402e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbam << 8) | 1403e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbah << 16) | 1404e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->device << 24) 1405e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1406e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[2] = cpu_to_le32( 1407e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbal << 0) | 1408e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbam << 8) | 1409e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbah << 16) | 1410e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_feature << 24) 1411e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1412e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[3] = cpu_to_le32( 1413e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->nsect << 0) | 1414e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_nsect << 8) 1415e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1416e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1417e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 141831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 141931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_fill_sg(qc); 142031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 142131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 142205b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 142305b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_issue - Initiate a command to the host 142405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to start 142505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 142605b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 142705b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it sanity checks our local 142805b308e1df6d9d673daedb517969241f41278b52Brett Russ * caches of the request producer/consumer indices then enables 142905b308e1df6d9d673daedb517969241f41278b52Brett Russ * DMA and bumps the request producer index. 143005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 143105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 143205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 143305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 14349a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 143531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1436c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct ata_port *ap = qc->ap; 1437c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 1438c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1439bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 in_index; 144031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1441138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1442138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) { 144317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord /* 144417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord * We're about to send a non-EDMA capable command to the 144531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * port. Turn off EDMA so there won't be problems accessing 144631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * shadow block, etc registers. 144731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1448b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 1449e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(ap, qc->dev->link->pmp); 14509363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo return ata_sff_qc_issue(qc); 145131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 145231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1453721091685f853ba4e6c49f26f989db0b1a811250Mark Lord mv_start_dma(ap, port_mmio, pp, qc->tf.protocol); 1454bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1455bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->req_idx++; 145631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1457bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = (pp->req_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_REQ_Q_PTR_SHIFT; 145831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 145931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* and write the request in pointer to kick the EDMA to life */ 1460bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 1461bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 146231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 146331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 146431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 146531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 146605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 146705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_err_intr - Handle error interrupts on the port 146805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 14699b358e305c1d783c8a4ebf00344e95deb9e38f3dMark Lord * @reset_allowed: bool: 0 == don't trigger from reset here 147005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 147105b308e1df6d9d673daedb517969241f41278b52Brett Russ * In most cases, just clear the interrupt and move on. However, 1472e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * some cases require an eDMA reset, which also performs a COMRESET. 1473e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * The SERR case requires a clear of pending errors in the SATA 1474e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * SERROR register. Finally, if the port disabled DMA, 1475e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * update our cached copy to match. 147605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 147705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 147805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 147905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 1480bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc) 148131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 148231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 1483bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 edma_err_cause, eh_freeze_mask, serr = 0; 1484bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1485bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 1486bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int edma_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); 1487bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int action = 0, err_mask = 0; 14889af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_eh_info *ehi = &ap->link.eh_info; 148920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1490bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 149120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1492bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!edma_enabled) { 1493bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* just a guess: do we need to do this? should we 1494bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * expand this, and do it in all cases? 1495bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1496936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_read(&ap->link, SCR_ERROR, &serr); 1497936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 149820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 1499bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1500bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 1501bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1502352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ata_ehi_push_desc(ehi, "edma_err_cause=%08x", edma_err_cause); 1503bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1504bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 1505352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * All generations share these EDMA error cause bits: 1506bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1507bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_DEV) 1508bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_DEV; 1509bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 15106c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 1511bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR)) { 1512bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_ATA_BUS; 1513cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1514b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "parity error"); 1515bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1516bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 1517bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_hotplugged(ehi); 1518bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 1519b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo "dev disconnect" : "dev connect"); 1520cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1521bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1522bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1523352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 1524352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Gen-I has a different SELF_DIS bit, 1525352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * different FREEZE bits, and no SERR bit: 1526352fab701ca4753dd005b67ce5e512be944eb591Mark Lord */ 1527ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) { 1528bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE_5; 1529bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 1530bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1531b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 1532bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1533bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 1534bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE; 1535bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS) { 1536bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1537b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 1538bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1539bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SERR) { 1540936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_read(&ap->link, SCR_ERROR, &serr); 1541936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 1542bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_ATA_BUS; 1543cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1544bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1545afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 154620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 154720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Clear EDMA now that SERR cleanup done */ 15483606a380692cf958355a40fc1aa336800c17baf1Mark Lord writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 154920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1550bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!err_mask) { 1551bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_OTHER; 1552cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1553bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1554bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1555bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->serror |= serr; 1556bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->action |= action; 1557bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1558bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 1559bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 1560bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1561bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 1562bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1563bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & eh_freeze_mask) 1564bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 1565bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1566bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_abort(ap); 1567bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1568bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1569bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_intr_pio(struct ata_port *ap) 1570bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 1571bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 1572bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u8 ata_status; 1573bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1574bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* ignore spurious intr if drive still BUSY */ 1575bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_status = readb(ap->ioaddr.status_addr); 1576bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (unlikely(ata_status & ATA_BUSY)) 1577bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1578bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1579bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get active ATA command */ 15809af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 1581bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (unlikely(!qc)) /* no active tag */ 1582bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1583bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc->tf.flags & ATA_TFLAG_POLLING) /* polling; we don't own qc */ 1584bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1585bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1586bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* and finally, complete the ATA command */ 1587bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= ac_err_mask(ata_status); 1588bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_qc_complete(qc); 1589bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1590bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1591bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_intr_edma(struct ata_port *ap) 1592bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 1593bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 1594bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 1595bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1596bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 1597bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 out_index, in_index; 1598bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik bool work_done = false; 1599bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1600bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get h/w response queue pointer */ 1601bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) 1602bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 1603bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1604bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik while (1) { 1605bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u16 status; 16066c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik unsigned int tag; 1607bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1608bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get s/w response queue last-read pointer, and compare */ 1609bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik out_index = pp->resp_idx & MV_MAX_Q_DEPTH_MASK; 1610bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (in_index == out_index) 1611bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik break; 1612bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1613bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 50xx: get active ATA command */ 16140ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik if (IS_GEN_I(hpriv)) 16159af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo tag = ap->link.active_tag; 1616bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 16176c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik /* Gen II/IIE: get active ATA command via tag, to enable 16186c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik * support for queueing. this works transparently for 16196c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik * queued and non-queued modes. 1620bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 16218c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord else 16228c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord tag = le16_to_cpu(pp->crpb[out_index].id) & 0x1f; 1623bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 16246c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik qc = ata_qc_from_tag(ap, tag); 1625bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1626cb92441973ebd71d556fc7cdd9e597582327dd71Mark Lord /* For non-NCQ mode, the lower 8 bits of status 1627cb92441973ebd71d556fc7cdd9e597582327dd71Mark Lord * are from EDMA_ERR_IRQ_CAUSE_OFS, 1628cb92441973ebd71d556fc7cdd9e597582327dd71Mark Lord * which should be zero if all went well. 1629bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1630bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik status = le16_to_cpu(pp->crpb[out_index].flags); 1631cb92441973ebd71d556fc7cdd9e597582327dd71Mark Lord if ((status & 0xff) && !(pp->pp_flags & MV_PP_FLAG_NCQ_EN)) { 1632bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_err_intr(ap, qc); 1633bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1634bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1635bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1636bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* and finally, complete the ATA command */ 1637bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) { 1638bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= 1639bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ac_err_mask(status >> CRPB_FLAG_STATUS_SHIFT); 1640bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_qc_complete(qc); 1641bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1642bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 16430ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* advance software response queue pointer, to 1644bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * indicate (after the loop completes) to hardware 1645bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * that we have consumed a response queue entry. 1646bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1647bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik work_done = true; 1648bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->resp_idx++; 1649bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1650bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1651352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Update the software queue position index in hardware */ 1652bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (work_done) 1653bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 1654bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik (out_index << EDMA_RSP_Q_PTR_SHIFT), 1655bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 165620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 165720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 165805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 165905b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_host_intr - Handle all interrupts on the given host controller 1660cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * @host: host specific structure 166105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @relevant: port error bits relevant to this host controller 166205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @hc: which host controller we're to look at 166305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 166405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read then write clear the HC interrupt status then walk each 166505b308e1df6d9d673daedb517969241f41278b52Brett Russ * port connected to the HC and see if it needs servicing. Port 166605b308e1df6d9d673daedb517969241f41278b52Brett Russ * success ints are reported in the HC interrupt status reg, the 166705b308e1df6d9d673daedb517969241f41278b52Brett Russ * port error ints are reported in the higher level main 166805b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupt status register and thus are passed in via the 166905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 'relevant' argument. 167005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 167105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 167205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 167305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 1674cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc) 167520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1676f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 1677f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 167820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 167920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ u32 hc_irq_cause; 1680f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int port, port0, last_port; 168120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1682351772658a4d1acc0221a6e30676bb0594e74812Jeff Garzik if (hc == 0) 168320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ port0 = 0; 1684351772658a4d1acc0221a6e30676bb0594e74812Jeff Garzik else 168520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ port0 = MV_PORTS_PER_HC; 168620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1687f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) 1688f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara last_port = port0 + MV_PORTS_PER_HC; 1689f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara else 1690f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara last_port = port0 + hpriv->n_ports; 169120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* we'll need the HC success int register in most cases */ 169220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 1693bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!hc_irq_cause) 1694bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik return; 1695bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1696bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 169720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 169820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n", 16992dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik hc, relevant, hc_irq_cause); 170020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 17018f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu for (port = port0; port < last_port; port++) { 1702cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_port *ap = host->ports[port]; 17038f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu struct mv_port_priv *pp; 1704352fab701ca4753dd005b67ce5e512be944eb591Mark Lord int have_err_bits, hardport, shift; 170555d8ca4f8094246da6e71889a4e04bfafaa78b10Jeff Garzik 1706bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if ((!ap) || (ap->flags & ATA_FLAG_DISABLED)) 1707a2c91a8819e315e9fd1aef3ff57badb6c1be3f80Jeff Garzik continue; 1708a2c91a8819e315e9fd1aef3ff57badb6c1be3f80Jeff Garzik 17098f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu pp = ap->private_data; 17108f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu 171131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ shift = port << 1; /* (port * 2) */ 1712e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord if (port >= MV_PORTS_PER_HC) 171320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ shift++; /* skip bit 8 in the HC Main IRQ reg */ 1714e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 1715352fab701ca4753dd005b67ce5e512be944eb591Mark Lord have_err_bits = ((ERR_IRQ << shift) & relevant); 1716bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1717bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (unlikely(have_err_bits)) { 1718bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 17198b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 17209af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 1721bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 1722bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik continue; 1723bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1724bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_err_intr(ap, qc); 1725bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik continue; 1726bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1727bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1728352fab701ca4753dd005b67ce5e512be944eb591Mark Lord hardport = mv_hardport_from_port(port); /* range 0..3 */ 1729bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1730bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 1731352fab701ca4753dd005b67ce5e512be944eb591Mark Lord if ((DMA_IRQ << hardport) & hc_irq_cause) 1732bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_intr_edma(ap); 1733bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 1734352fab701ca4753dd005b67ce5e512be944eb591Mark Lord if ((DEV_IRQ << hardport) & hc_irq_cause) 1735bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_intr_pio(ap); 173620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 173720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 173820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ VPRINTK("EXIT\n"); 173920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 174020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1741bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_pci_error(struct ata_host *host, void __iomem *mmio) 1742bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 174302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 1744bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_port *ap; 1745bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 1746bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_eh_info *ehi; 1747bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int i, err_mask, printed = 0; 1748bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 err_cause; 1749bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 175002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord err_cause = readl(mmio + hpriv->irq_cause_ofs); 1751bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1752bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", 1753bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_cause); 1754bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1755bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik DPRINTK("All regs @ PCI error\n"); 1756bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 1757bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 175802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord writelfl(0, mmio + hpriv->irq_cause_ofs); 1759bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1760bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik for (i = 0; i < host->n_ports; i++) { 1761bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ap = host->ports[i]; 1762936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo if (!ata_link_offline(&ap->link)) { 17639af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo ehi = &ap->link.eh_info; 1764bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 1765bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!printed++) 1766bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, 1767bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik "PCI err cause 0x%08x", err_cause); 1768bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_HOST_BUS; 1769cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo ehi->action = ATA_EH_RESET; 17709af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 1771bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 1772bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 1773bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1774bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 1775bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1776bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 1777bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1778bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1779bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1780bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 178105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1782c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * mv_interrupt - Main interrupt event handler 178305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @irq: unused 178405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @dev_instance: private data; in this case the host structure 178505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 178605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read the read only register to determine if any host 178705b308e1df6d9d673daedb517969241f41278b52Brett Russ * controllers have pending interrupts. If so, call lower level 178805b308e1df6d9d673daedb517969241f41278b52Brett Russ * routine to handle. Also check for PCI errors which are only 178905b308e1df6d9d673daedb517969241f41278b52Brett Russ * reported here. 179005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 17918b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * LOCKING: 1792cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine holds the host lock while processing pending 179305b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts. 179405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 17957d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t mv_interrupt(int irq, void *dev_instance) 179620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1797cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = dev_instance; 1798f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 179920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int hc, handled = 0, n_hcs; 1800f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 1801352fab701ca4753dd005b67ce5e512be944eb591Mark Lord u32 main_cause, main_mask; 180220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1803646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord spin_lock(&host->lock); 1804352fab701ca4753dd005b67ce5e512be944eb591Mark Lord main_cause = readl(hpriv->main_cause_reg_addr); 1805352fab701ca4753dd005b67ce5e512be944eb591Mark Lord main_mask = readl(hpriv->main_mask_reg_addr); 1806352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 1807352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Deal with cases where we either have nothing pending, or have read 1808352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * a bogus register value which can indicate HW removal or PCI fault. 180920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 1810352fab701ca4753dd005b67ce5e512be944eb591Mark Lord if (!(main_cause & main_mask) || (main_cause == 0xffffffffU)) 1811646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord goto out_unlock; 181220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1813cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik n_hcs = mv_get_hc_count(host->ports[0]->flags); 181420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1815352fab701ca4753dd005b67ce5e512be944eb591Mark Lord if (unlikely((main_cause & PCI_ERR) && HAS_PCI(host))) { 1816bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_pci_error(host, mmio); 1817bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik handled = 1; 1818bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik goto out_unlock; /* skip all other HC irq handling */ 1819bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1820bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 182120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hcs; hc++) { 1822352fab701ca4753dd005b67ce5e512be944eb591Mark Lord u32 relevant = main_cause & (HC0_IRQ_PEND << (hc * HC_SHIFT)); 182320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ if (relevant) { 1824cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik mv_host_intr(host, relevant, hc); 1825bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik handled = 1; 182620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 182720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 1828615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 1829bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikout_unlock: 1830cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik spin_unlock(&host->lock); 183120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return IRQ_RETVAL(handled); 183220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 183320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1834c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic unsigned int mv5_scr_offset(unsigned int sc_reg_in) 1835c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1836c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs; 1837c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1838c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik switch (sc_reg_in) { 1839c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_STATUS: 1840c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_ERROR: 1841c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_CONTROL: 1842c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = sc_reg_in * sizeof(u32); 1843c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 1844c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik default: 1845c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = 0xffffffffU; 1846c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 1847c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 1848c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return ofs; 1849c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1850c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1851da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 1852c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1853f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 1854f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 18550d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 1856c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 1857c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1858da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 1859da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(addr + ofs); 1860da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1861da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1862da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 1863c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1864c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1865da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 1866c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1867f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 1868f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 18690d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 1870c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 1871c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1872da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 18730d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo writelfl(val, addr + ofs); 1874da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1875da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1876da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 1877c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1878c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 18797bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 1880522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 18817bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara struct pci_dev *pdev = to_pci_dev(host->dev); 1882522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik int early_5080; 1883522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 188444c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 1885522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1886522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik if (!early_5080) { 1887522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 1888522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= (1 << 0); 1889522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 1890522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik } 1891522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 18927bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara mv_reset_pci_bus(host, mmio); 1893522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 1894522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1895522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 1896522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 1897522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(0x0fcfffff, mmio + MV_FLASH_CTL); 1898522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 1899522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 190047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 1901ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 1902ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 1903c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 1904c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 1905c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1906c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 1907c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1908c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 1909c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 1910ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 1911ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 191247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 1913ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 1914522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp; 1915522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1916522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(0, mmio + MV_GPIO_PORT_CTL); 1917522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1918522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 1919522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1920522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 1921522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= ~(1 << 0); 1922522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 1923ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 1924ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 19252a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 19262a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 1927bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 1928c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, port); 1929c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 1930c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 1931c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 1932c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1933c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik if (fix_apm_sq) { 1934c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_LT_MODE); 1935c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= (1 << 19); 1936c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_LT_MODE); 1937c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1938c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_CTL); 1939c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~0x3; 1940c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x1; 1941c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_CTL); 1942c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 1943c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1944c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 1945c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~mask; 1946c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].pre; 1947c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].amps; 1948c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_MODE); 1949bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 1950bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 1951c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1952c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 1953c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, port_mmio + (reg)) 1954c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 1955c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 1956c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1957c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 1958c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1959b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* 1960b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * The datasheet warns against setting ATA_RST when EDMA is active 1961b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * (but doesn't say what the problem might be). So we first try 1962b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * to disable the EDMA engine before doing the ATA_RST operation. 1963b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord */ 1964e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 1965c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1966c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x028); /* command */ 1967c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(0x11f, port_mmio + EDMA_CFG_OFS); 1968c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x004); /* timer */ 1969c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x008); /* irq err cause */ 1970c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); /* irq err mask */ 1971c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); /* rq bah */ 1972c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); /* rq inp */ 1973c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); /* rq outp */ 1974c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x01c); /* respq bah */ 1975c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x024); /* respq outp */ 1976c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x020); /* respq inp */ 1977c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x02c); /* test control */ 1978c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 1979c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1980c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 1981c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1982c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, hc_mmio + (reg)) 1983c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 1984c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc) 198547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik{ 1986c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 1987c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 1988c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1989c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); 1990c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); 1991c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); 1992c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); 1993c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1994c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(hc_mmio + 0x20); 1995c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= 0x1c1c1c1c; 1996c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x03030303; 1997c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, hc_mmio + 0x20); 1998c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1999c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 2000c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2001c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2002c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 2003c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2004c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc, port; 2005c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2006c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (hc = 0; hc < n_hc; hc++) { 2007c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (port = 0; port < MV_PORTS_PER_HC; port++) 2008c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_hc_port(hpriv, mmio, 2009c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (hc * MV_PORTS_PER_HC) + port); 2010c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2011c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_one_hc(hpriv, mmio, hc); 2012c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2013c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2014c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return 0; 201547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik} 201647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 2017101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 2018101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#define ZERO(reg) writel(0, mmio + (reg)) 20197bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 2020101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 202102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 2022101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 2023101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2024101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp = readl(mmio + MV_PCI_MODE); 2025101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0xff00ffff; 2026101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(tmp, mmio + MV_PCI_MODE); 2027101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2028101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_DISC_TIMER); 2029101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_MSI_TRIGGER); 2030101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); 2031101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(HC_MAIN_IRQ_MASK_OFS); 2032101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_SERR_MASK); 203302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_cause_ofs); 203402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_mask_ofs); 2035101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_LOW_ADDRESS); 2036101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_HIGH_ADDRESS); 2037101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_ATTRIBUTE); 2038101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_COMMAND); 2039101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2040101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 2041101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2042101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 2043101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 2044101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 2045101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2046101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik mv5_reset_flash(hpriv, mmio); 2047101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2048101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp = readl(mmio + MV_GPIO_PORT_CTL); 2049101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0x3; 2050101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp |= (1 << 5) | (1 << 6); 2051101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(tmp, mmio + MV_GPIO_PORT_CTL); 2052101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2053101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2054101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik/** 2055101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * mv6_reset_hc - Perform the 6xxx global soft reset 2056101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * @mmio: base address of the HBA 2057101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2058101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * This routine only applies to 6xxx parts. 2059101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2060101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * LOCKING: 2061101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * Inherited from caller. 2062101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2063c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2064c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 2065101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 2066101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; 2067101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik int i, rc = 0; 2068101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 t; 2069101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2070101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* Following procedure defined in PCI "main command and status 2071101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * register" table. 2072101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2073101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2074101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | STOP_PCI_MASTER, reg); 2075101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2076101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik for (i = 0; i < 1000; i++) { 2077101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2078101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 20792dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik if (PCI_MASTER_EMPTY & t) 2080101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik break; 2081101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2082101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(PCI_MASTER_EMPTY & t)) { 2083101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 2084101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2085101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2086101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2087101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2088101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* set reset */ 2089101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2090101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2091101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | GLOB_SFT_RST, reg); 2092101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2093101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2094101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 2095101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2096101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(GLOB_SFT_RST & t)) { 2097101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 2098101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2099101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2100101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2101101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2102101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 2103101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2104101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2105101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 2106101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2107101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2108101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while ((GLOB_SFT_RST & t) && (i-- > 0)); 2109101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2110101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (GLOB_SFT_RST & t) { 2111101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 2112101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2113101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2114094e50b2f74146d8ee924fea4808e58c4ed2f163Mark Lord /* 2115094e50b2f74146d8ee924fea4808e58c4ed2f163Mark Lord * Temporary: wait 3 seconds before port-probing can happen, 2116094e50b2f74146d8ee924fea4808e58c4ed2f163Mark Lord * so that we don't miss finding sleepy SilXXXX port-multipliers. 2117094e50b2f74146d8ee924fea4808e58c4ed2f163Mark Lord * This can go away once hotplug is fully/correctly implemented. 2118094e50b2f74146d8ee924fea4808e58c4ed2f163Mark Lord */ 2119094e50b2f74146d8ee924fea4808e58c4ed2f163Mark Lord if (rc == 0) 2120094e50b2f74146d8ee924fea4808e58c4ed2f163Mark Lord msleep(3000); 2121101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikdone: 2122101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik return rc; 2123101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2124101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 212547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 2126ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 2127ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 2128ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *port_mmio; 2129ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik u32 tmp; 2130ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2131ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(mmio + MV_RESET_CFG); 2132ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik if ((tmp & (1 << 0)) == 0) { 213347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->signal[idx].amps = 0x7 << 8; 2134ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = 0x1 << 5; 2135ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik return; 2136ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik } 2137ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2138ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik port_mmio = mv_port_base(mmio, idx); 2139ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(port_mmio + PHY_MODE2); 2140ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2141ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2142ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2143ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2144ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 214547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 2146ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 214747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(0x00000060, mmio + MV_GPIO_PORT_CTL); 2148ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2149ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2150c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 21512a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 2152bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 2153c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2154c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2155bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 215647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik int fix_phy_mode2 = 215747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 2158bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik int fix_phy_mode4 = 215947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 216047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik u32 m2, tmp; 216147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 216247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (fix_phy_mode2) { 216347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 216447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 216547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 |= (1 << 31); 216647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 216747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 216847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 216947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 217047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 217147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~((1 << 16) | (1 << 31)); 217247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 217347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 217447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 217547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 217647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 217747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik /* who knows what this magic does */ 217847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp = readl(port_mmio + PHY_MODE3); 217947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp &= ~0x7F800000; 218047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp |= 0x2A800000; 218147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(tmp, port_mmio + PHY_MODE3); 2182bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2183bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (fix_phy_mode4) { 218447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik u32 m4; 2185bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2186bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m4 = readl(port_mmio + PHY_MODE4); 218747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 218847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (hp_flags & MV_HP_ERRATA_60X1B2) 2189e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord tmp = readl(port_mmio + PHY_MODE3); 2190bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2191e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* workaround for errata FEr SATA#10 (part 1) */ 2192bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m4 = (m4 & ~(1 << 1)) | (1 << 0); 2193bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2194bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m4, port_mmio + PHY_MODE4); 219547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 219647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (hp_flags & MV_HP_ERRATA_60X1B2) 2197e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord writel(tmp, port_mmio + PHY_MODE3); 2198bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2199bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2200bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik /* Revert values of pre-emphasis and signal amps to the saved ones */ 2201bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 2202bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2203bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 &= ~MV_M2_PREAMP_MASK; 22042a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].amps; 22052a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].pre; 220647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 2207bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2208e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* according to mvSata 3.6.1, some IIE values are fixed */ 2209e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (IS_GEN_IIE(hpriv)) { 2210e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 &= ~0xC30FF01F; 2211e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 |= 0x0000900F; 2212e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 2213e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2214bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 2215bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2216bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2217f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* TODO: use the generic LED interface to configure the SATA Presence */ 2218f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* & Acitivy LEDs on the board */ 2219f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 2220f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2221f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2222f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2223f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2224f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2225f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 2226f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2227f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2228f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio; 2229f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara u32 tmp; 2230f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2231f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara port_mmio = mv_port_base(mmio, idx); 2232f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(port_mmio + PHY_MODE2); 2233f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2234f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2235f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2236f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2237f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2238f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2239f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, port_mmio + (reg)) 2240f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 2241f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int port) 2242f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2243f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio = mv_port_base(mmio, port); 2244f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2245b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* 2246b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * The datasheet warns against setting ATA_RST when EDMA is active 2247b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * (but doesn't say what the problem might be). So we first try 2248b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * to disable the EDMA engine before doing the ATA_RST operation. 2249b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord */ 2250e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 2251f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2252f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x028); /* command */ 2253f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0x101f, port_mmio + EDMA_CFG_OFS); 2254f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x004); /* timer */ 2255f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x008); /* irq err cause */ 2256f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); /* irq err mask */ 2257f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); /* rq bah */ 2258f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); /* rq inp */ 2259f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x018); /* rq outp */ 2260f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x01c); /* respq bah */ 2261f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x024); /* respq outp */ 2262f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x020); /* respq inp */ 2263f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x02c); /* test control */ 2264f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 2265f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2266f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2267f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2268f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2269f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, hc_mmio + (reg)) 2270f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 2271f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2272f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2273f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *hc_mmio = mv_hc_base(mmio, 0); 2274f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2275f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); 2276f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); 2277f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); 2278f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2279f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2280f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2281f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2282f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2283f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 2284f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc) 2285f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2286f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int port; 2287f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2288f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara for (port = 0; port < hpriv->n_ports; port++) 2289f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_hc_port(hpriv, mmio, port); 2290f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2291f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_one_hc(hpriv, mmio); 2292f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2293f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 2294f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2295f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2296f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 2297f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2298f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2299f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2300f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2301f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2302f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 2303f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2304f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2305f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2306f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2307b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lordstatic void mv_setup_ifctl(void __iomem *port_mmio, int want_gen2i) 2308b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord{ 2309b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord u32 ifctl = readl(port_mmio + SATA_INTERFACE_CFG); 2310b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 2311b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord ifctl = (ifctl & 0xf7f) | 0x9b1000; /* from chip spec */ 2312b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (want_gen2i) 2313b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord ifctl |= (1 << 7); /* enable gen2i speed */ 2314b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord writelfl(ifctl, port_mmio + SATA_INTERFACE_CFG); 2315b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord} 2316b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 2317b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord/* 2318b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * Caller must ensure that EDMA is not active, 2319b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * by first doing mv_stop_edma() where needed. 2320b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord */ 2321e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 2322c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no) 2323c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2324c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port_no); 2325c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 23260d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord mv_stop_edma_engine(port_mmio); 2327c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); 2328c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2329b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (!IS_GEN_I(hpriv)) { 2330b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord /* Enable 3.0gb/s link speed */ 2331b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord mv_setup_ifctl(port_mmio, 1); 2332c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2333b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord /* 2334b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * Strobing ATA_RST here causes a hard reset of the SATA transport, 2335b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * link, and physical layers. It resets all SATA interface registers 2336b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev. 2337c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik */ 2338b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); 2339b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord udelay(25); /* allow reset propagation */ 2340c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writelfl(0, port_mmio + EDMA_CMD_OFS); 2341c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2342c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->ops->phy_errata(hpriv, mmio, port_no); 2343c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2344ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) 2345c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mdelay(1); 2346c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2347c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2348e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp) 234920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2350e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (sata_pmp_supported(ap)) { 2351e49856d82a887ce365637176f9f99ab68076eae8Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 2352e49856d82a887ce365637176f9f99ab68076eae8Mark Lord u32 reg = readl(port_mmio + SATA_IFCTL_OFS); 2353e49856d82a887ce365637176f9f99ab68076eae8Mark Lord int old = reg & 0xf; 235422374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 2355e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (old != pmp) { 2356e49856d82a887ce365637176f9f99ab68076eae8Mark Lord reg = (reg & ~0xf) | pmp; 2357e49856d82a887ce365637176f9f99ab68076eae8Mark Lord writelfl(reg, port_mmio + SATA_IFCTL_OFS); 2358e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 235922374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik } 236020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 236120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2362e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 2363e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 236422374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik{ 2365e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 2366e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return sata_std_hardreset(link, class, deadline); 2367e49856d82a887ce365637176f9f99ab68076eae8Mark Lord} 2368bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2369e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 2370e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 2371e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 2372e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 2373e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return ata_sff_softreset(link, class, deadline); 237422374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik} 237522374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 2376cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 2377bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned long deadline) 237831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 2379cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo struct ata_port *ap = link->ap; 2380bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2381b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 2382f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 23830d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord int rc, attempts = 0, extra = 0; 23840d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord u32 sstatus; 23850d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord bool online; 238631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2387e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, ap->port_no); 2388b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2389bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 23900d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Workaround for errata FEr SATA#10 (part 2) */ 23910d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord do { 239217c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord const unsigned long *timing = 239317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord sata_ehc_deb_timing(&link->eh_context); 2394bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 239517c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord rc = sata_link_hardreset(link, timing, deadline + extra, 239617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord &online, NULL); 239717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord if (rc) 23980d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord return rc; 23990d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord sata_scr_read(link, SCR_STATUS, &sstatus); 24000d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 24010d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Force 1.5gb/s link speed and try again */ 24020d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord mv_setup_ifctl(mv_ap_base(ap), 0); 24030d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (time_after(jiffies + HZ, deadline)) 24040d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord extra = HZ; /* only extend it once, max */ 24050d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } 24060d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); 2407bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 240817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord return rc; 2409bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2410bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2411bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap) 2412bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2413f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 2414bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int hc = (ap->port_no > 3) ? 1 : 0; 2415bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int shift; 2416352fab701ca4753dd005b67ce5e512be944eb591Mark Lord u32 main_mask; 2417bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2418bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* FIXME: handle coalescing completion events properly */ 2419bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2420bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik shift = ap->port_no * 2; 2421bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (hc > 0) 2422bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik shift++; 2423bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2424bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* disable assertion of portN err, done events */ 2425352fab701ca4753dd005b67ce5e512be944eb591Mark Lord main_mask = readl(hpriv->main_mask_reg_addr); 2426352fab701ca4753dd005b67ce5e512be944eb591Mark Lord main_mask &= ~((DONE_IRQ | ERR_IRQ) << shift); 2427352fab701ca4753dd005b67ce5e512be944eb591Mark Lord writelfl(main_mask, hpriv->main_mask_reg_addr); 2428bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2429bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2430bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap) 2431bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2432f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 2433f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 2434bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int hc = (ap->port_no > 3) ? 1 : 0; 2435bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 2436bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 2437bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int shift, hc_port_no = ap->port_no; 2438352fab701ca4753dd005b67ce5e512be944eb591Mark Lord u32 main_mask, hc_irq_cause; 2439bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2440bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* FIXME: handle coalescing completion events properly */ 2441bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2442bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik shift = ap->port_no * 2; 2443bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (hc > 0) { 2444bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik shift++; 2445bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_port_no -= 4; 2446bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2447bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2448bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA errors on this port */ 2449bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2450bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2451bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear pending irq events */ 2452bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 2453352fab701ca4753dd005b67ce5e512be944eb591Mark Lord hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hc_port_no); 2454bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writel(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 2455bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2456bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* enable assertion of portN err, done events */ 2457352fab701ca4753dd005b67ce5e512be944eb591Mark Lord main_mask = readl(hpriv->main_mask_reg_addr); 2458352fab701ca4753dd005b67ce5e512be944eb591Mark Lord main_mask |= ((DONE_IRQ | ERR_IRQ) << shift); 2459352fab701ca4753dd005b67ce5e512be944eb591Mark Lord writelfl(main_mask, hpriv->main_mask_reg_addr); 246031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 246131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 246205b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 246305b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_init - Perform some early initialization on a single port. 246405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port: libata data structure storing shadow register addresses 246505b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port_mmio: base address of the port 246605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 246705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Initialize shadow register mmio addresses, clear outstanding 246805b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts on the port, and unmask interrupts for the future 246905b308e1df6d9d673daedb517969241f41278b52Brett Russ * start of the port. 247005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 247105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 247205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 247305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 247431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 247520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 24760d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *shd_base = port_mmio + SHD_BLK_OFS; 247731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ unsigned serr_ofs; 247831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 24798b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik /* PIO related setup 248031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 248131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 24828b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->error_addr = 248331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 248431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 248531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 248631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 248731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 248831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 24898b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->status_addr = 249031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 249131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* special case: control/altstatus doesn't have ATA_REG_ address */ 249231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; 249331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 249431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* unused: */ 24958d9db2d2fbae9e05022825c32f86e00c8e342860Randy Dunlap port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; 249620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 249731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding port interrupt conditions */ 249831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ serr_ofs = mv_scr_offset(SCR_ERROR); 249931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); 250031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 250131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2502646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord /* unmask all non-transient EDMA error interrupts */ 2503646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS); 250420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25058b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 250631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_CFG_OFS), 250731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), 250831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); 250920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 251020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25114447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_chip_id(struct ata_host *host, unsigned int board_idx) 2512bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 25134447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 25144447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 2515bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 2516bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 25175796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik switch (board_idx) { 251847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case chip_5080: 251947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 2520ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 252147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 252244c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 252347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x1: 252447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 252547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 252647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 252747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 252847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 252947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 253047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 253147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying 50XXB2 workarounds to unknown rev\n"); 253247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 253347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 253447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 253547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 253647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 2537bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_504x: 2538bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_508x: 253947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 2540ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 2541bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 254244c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 254347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x0: 254447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 254547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 254647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 254747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 254847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 254947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 255047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 255147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 255247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 255347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 2554bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2555bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2556bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2557bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_604x: 2558bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_608x: 255947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv6xxx_ops; 2560ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_II; 256147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 256244c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 256347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x7: 256447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 256547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 256647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x9: 256747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2568bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2569bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 2570bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 257147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 257247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 2573bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2574bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2575bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2576bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2577e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_7042: 257802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hp_flags |= MV_HP_PCIE; 2579306b30f74d37f289033c696285e07ce0158a5d7bMark Lord if (pdev->vendor == PCI_VENDOR_ID_TTI && 2580306b30f74d37f289033c696285e07ce0158a5d7bMark Lord (pdev->device == 0x2300 || pdev->device == 0x2310)) 2581306b30f74d37f289033c696285e07ce0158a5d7bMark Lord { 25824e5200334e03e5620aa19d538300c13db270a063Mark Lord /* 25834e5200334e03e5620aa19d538300c13db270a063Mark Lord * Highpoint RocketRAID PCIe 23xx series cards: 25844e5200334e03e5620aa19d538300c13db270a063Mark Lord * 25854e5200334e03e5620aa19d538300c13db270a063Mark Lord * Unconfigured drives are treated as "Legacy" 25864e5200334e03e5620aa19d538300c13db270a063Mark Lord * by the BIOS, and it overwrites sector 8 with 25874e5200334e03e5620aa19d538300c13db270a063Mark Lord * a "Lgcy" metadata block prior to Linux boot. 25884e5200334e03e5620aa19d538300c13db270a063Mark Lord * 25894e5200334e03e5620aa19d538300c13db270a063Mark Lord * Configured drives (RAID or JBOD) leave sector 8 25904e5200334e03e5620aa19d538300c13db270a063Mark Lord * alone, but instead overwrite a high numbered 25914e5200334e03e5620aa19d538300c13db270a063Mark Lord * sector for the RAID metadata. This sector can 25924e5200334e03e5620aa19d538300c13db270a063Mark Lord * be determined exactly, by truncating the physical 25934e5200334e03e5620aa19d538300c13db270a063Mark Lord * drive capacity to a nice even GB value. 25944e5200334e03e5620aa19d538300c13db270a063Mark Lord * 25954e5200334e03e5620aa19d538300c13db270a063Mark Lord * RAID metadata is at: (dev->n_sectors & ~0xfffff) 25964e5200334e03e5620aa19d538300c13db270a063Mark Lord * 25974e5200334e03e5620aa19d538300c13db270a063Mark Lord * Warn the user, lest they think we're just buggy. 25984e5200334e03e5620aa19d538300c13db270a063Mark Lord */ 25994e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 26004e5200334e03e5620aa19d538300c13db270a063Mark Lord " BIOS CORRUPTS DATA on all attached drives," 26014e5200334e03e5620aa19d538300c13db270a063Mark Lord " regardless of if/how they are configured." 26024e5200334e03e5620aa19d538300c13db270a063Mark Lord " BEWARE!\n"); 26034e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": For data safety, do not" 26044e5200334e03e5620aa19d538300c13db270a063Mark Lord " use sectors 8-9 on \"Legacy\" drives," 26054e5200334e03e5620aa19d538300c13db270a063Mark Lord " and avoid the final two gigabytes on" 26064e5200334e03e5620aa19d538300c13db270a063Mark Lord " all RocketRAID BIOS initialized drives.\n"); 2607306b30f74d37f289033c696285e07ce0158a5d7bMark Lord } 2608e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_6042: 2609e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hpriv->ops = &mv6xxx_ops; 2610e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_GEN_IIE; 2611e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 261244c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 2613e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case 0x0: 2614e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_XX42A0; 2615e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2616e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case 0x1: 2617e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2618e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2619e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik default: 2620e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 2621e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik "Applying 60X1C0 workarounds to unknown rev\n"); 2622e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2623e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2624e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 2625e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2626f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara case chip_soc: 2627f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->ops = &mv_soc_ops; 2628f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hp_flags |= MV_HP_ERRATA_60X1C0; 2629f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara break; 2630e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2631bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 2632f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_ERR, host->dev, 26335796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik "BUG: invalid board index %u\n", board_idx); 2634bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 1; 2635bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2636bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2637bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik hpriv->hp_flags = hp_flags; 263802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord if (hp_flags & MV_HP_PCIE) { 263902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS; 264002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS; 264102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 264202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } else { 264302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS; 264402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS; 264502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 264602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } 2647bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2648bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 0; 2649bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2650bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 265105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 265247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik * mv_init_host - Perform some early initialization of the host. 26534447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to initialize 26544447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @board_idx: controller index 265505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 265605b308e1df6d9d673daedb517969241f41278b52Brett Russ * If possible, do an early global reset of the host. Then do 265705b308e1df6d9d673daedb517969241f41278b52Brett Russ * our port init and clear/unmask all/relevant host interrupts. 265805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 265905b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 266005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 266105b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 26624447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_init_host(struct ata_host *host, unsigned int board_idx) 266320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 266420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ int rc = 0, n_hc, port, hc; 26654447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 2666f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 266747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 26684447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_chip_id(host, board_idx); 2669bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (rc) 2670352fab701ca4753dd005b67ce5e512be944eb591Mark Lord goto done; 2671f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2672f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2673352fab701ca4753dd005b67ce5e512be944eb591Mark Lord hpriv->main_cause_reg_addr = mmio + HC_MAIN_IRQ_CAUSE_OFS; 2674352fab701ca4753dd005b67ce5e512be944eb591Mark Lord hpriv->main_mask_reg_addr = mmio + HC_MAIN_IRQ_MASK_OFS; 2675f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } else { 2676352fab701ca4753dd005b67ce5e512be944eb591Mark Lord hpriv->main_cause_reg_addr = mmio + HC_SOC_MAIN_IRQ_CAUSE_OFS; 2677352fab701ca4753dd005b67ce5e512be944eb591Mark Lord hpriv->main_mask_reg_addr = mmio + HC_SOC_MAIN_IRQ_MASK_OFS; 2678f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2679352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 2680352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* global interrupt mask: 0 == mask everything */ 2681f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0, hpriv->main_mask_reg_addr); 2682bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 26834447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_hc = mv_get_hc_count(host->ports[0]->flags); 2684bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 26854447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) 268647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->read_preamp(hpriv, port, mmio); 268720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2688c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 268947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (rc) 269020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ goto done; 269120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2692522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik hpriv->ops->reset_flash(hpriv, mmio); 26937bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara hpriv->ops->reset_bus(host, mmio); 269447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->enable_leds(hpriv, mmio); 269520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 26964447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) { 2697cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo struct ata_port *ap = host->ports[port]; 26982a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2699cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 2700cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo mv_port_init(&ap->ioaddr, port_mmio); 2701cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 27027bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 2703f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2704f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int offset = port_mmio - mmio; 2705f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 2706f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 2707f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 27087bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 270920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 271020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 271120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hc; hc++) { 271231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 271331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 271431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 271531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ "(before clear)=0x%08x\n", hc, 271631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_CFG_OFS), 271731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_IRQ_CAUSE_OFS)); 271831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 271931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding hc interrupt conditions */ 272031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); 272120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 272220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2723f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2724f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* Clear any currently outstanding host interrupt conditions */ 2725f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(0, mmio + hpriv->irq_cause_ofs); 272631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2727f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* and unmask interrupt generation for host regs */ 2728f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs); 2729f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (IS_GEN_I(hpriv)) 2730f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS_5, 2731f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr); 2732f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara else 2733f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS, 2734f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr); 2735f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2736f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x " 2737f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "PCI int cause/mask=0x%08x/0x%08x\n", 2738f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_cause_reg_addr), 2739f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_mask_reg_addr), 2740f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(mmio + hpriv->irq_cause_ofs), 2741f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(mmio + hpriv->irq_mask_ofs)); 2742f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } else { 2743f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS_SOC, 2744f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr); 2745f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n", 2746f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_cause_reg_addr), 2747f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_mask_reg_addr)); 2748f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2749f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharadone: 2750f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 2751f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2752fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik 2753fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradleystatic int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 2754fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley{ 2755fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 2756fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRQB_Q_SZ, 0); 2757fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crqb_pool) 2758fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2759fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2760fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 2761fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRPB_Q_SZ, 0); 2762fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crpb_pool) 2763fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2764fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2765fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 2766fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_SG_TBL_SZ, 0); 2767fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->sg_tbl_pool) 2768fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2769fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2770fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return 0; 2771fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley} 2772fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 277315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhekstatic void mv_conf_mbus_windows(struct mv_host_priv *hpriv, 277415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_target_info *dram) 277515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek{ 277615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek int i; 277715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 277815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < 4; i++) { 277915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_CTRL(i)); 278015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_BASE(i)); 278115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 278215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 278315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < dram->num_cs; i++) { 278415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_window *cs = dram->cs + i; 278515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 278615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(((cs->size - 1) & 0xffff0000) | 278715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (cs->mbus_attr << 8) | 278815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (dram->mbus_dram_target_id << 4) | 1, 278915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek hpriv->base + WINDOW_CTRL(i)); 279015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(cs->base, hpriv->base + WINDOW_BASE(i)); 279115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 279215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek} 279315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 2794f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/** 2795f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_probe - handle a positive probe of an soc Marvell 2796f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * host 2797f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device found 2798f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2799f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * LOCKING: 2800f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Inherited from caller. 2801f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2802f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev) 2803f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2804f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara static int printed_version; 2805f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct mv_sata_platform_data *mv_platform_data; 2806f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct ata_port_info *ppi[] = 2807f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { &mv_port_info[chip_soc], NULL }; 2808f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host; 2809f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv; 2810f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct resource *res; 2811f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports, rc; 281220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2813f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!printed_version++) 2814f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 2815bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2816f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 2817f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Simple resource validation .. 2818f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2819f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (unlikely(pdev->num_resources != 2)) { 2820f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_err(&pdev->dev, "invalid number of resources\n"); 2821f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 2822f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2823f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2824f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 2825f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Get the register base first 2826f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2827f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2828f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (res == NULL) 2829f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 2830f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2831f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* allocate host */ 2832f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_platform_data = pdev->dev.platform_data; 2833f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara n_ports = mv_platform_data->n_ports; 2834f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2835f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 2836f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 2837f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2838f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!host || !hpriv) 2839f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -ENOMEM; 2840f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->private_data = hpriv; 2841f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 2842f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2843f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->iomap = NULL; 2844f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara hpriv->base = devm_ioremap(&pdev->dev, res->start, 2845f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara res->end - res->start + 1); 2846f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base -= MV_SATAHC0_REG_BASE; 2847f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 284815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek /* 284915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek * (Re-)program MBUS remapping windows if we are asked to. 285015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek */ 285115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek if (mv_platform_data->dram != NULL) 285215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek mv_conf_mbus_windows(hpriv, mv_platform_data->dram); 285315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 2854fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley rc = mv_create_dma_pools(hpriv, &pdev->dev); 2855fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (rc) 2856fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return rc; 2857fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2858f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* initialize adapter */ 2859f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = mv_init_host(host, chip_soc); 2860f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc) 2861f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 2862f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2863f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, 2864f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, 2865f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->n_ports); 2866f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2867f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, 2868f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara IRQF_SHARED, &mv6_sht); 2869f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2870f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2871f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* 2872f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2873f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_remove - unplug a platform interface 2874f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device 2875f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2876f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * A platform bus SATA device has been unplugged. Perform the needed 2877f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * cleanup. Also called on module unload for any active devices. 2878f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2879f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev) 2880f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2881f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct device *dev = &pdev->dev; 2882f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host = dev_get_drvdata(dev); 2883f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2884f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_host_detach(host); 2885f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 288620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 288720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2888f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic struct platform_driver mv_platform_driver = { 2889f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_platform_probe, 2890f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .remove = __devexit_p(mv_platform_remove), 2891f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .driver = { 2892f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .name = DRV_NAME, 2893f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .owner = THIS_MODULE, 2894f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 2895f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 2896f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2897f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 28987bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 2899f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 2900f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent); 2901f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 29027bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29037bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic struct pci_driver mv_pci_driver = { 29047bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .name = DRV_NAME, 29057bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .id_table = mv_pci_tbl, 2906f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_pci_init_one, 29077bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .remove = ata_pci_remove_one, 29087bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara}; 29097bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29107bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* 29117bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara * module options 29127bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara */ 29137bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int msi; /* Use PCI msi; either zero (off, default) or non-zero */ 29147bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29157bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29167bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* move to PCI layer or libata core? */ 29177bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int pci_go_64(struct pci_dev *pdev) 29187bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara{ 29197bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc; 29207bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29217bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 29227bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 29237bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29247bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 29257bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29267bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 29277bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "64-bit DMA enable failed\n"); 29287bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29297bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29307bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29317bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } else { 29327bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 29337bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29347bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 29357bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit DMA enable failed\n"); 29367bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29377bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29387bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 29397bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29407bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 29417bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit consistent DMA enable failed\n"); 29427bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29437bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29447bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29457bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29467bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29477bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara} 29487bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 294905b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 295005b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_print_info - Dump key info to kernel log for perusal. 29514447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to print info about 295205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 295305b308e1df6d9d673daedb517969241f41278b52Brett Russ * FIXME: complete this. 295405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 295505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 295605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 295705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 29584447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic void mv_print_info(struct ata_host *host) 295931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 29604447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 29614447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 296244c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok u8 scc; 2963c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik const char *scc_s, *gen; 296431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 296531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Use this to determine the HW stepping of the chip so we know 296631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * what errata to workaround 296731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 296831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 296931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (scc == 0) 297031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "SCSI"; 297131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else if (scc == 0x01) 297231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "RAID"; 297331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else 2974c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik scc_s = "?"; 2975c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik 2976c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik if (IS_GEN_I(hpriv)) 2977c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "I"; 2978c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_II(hpriv)) 2979c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "II"; 2980c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_IIE(hpriv)) 2981c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "IIE"; 2982c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else 2983c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "?"; 298431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2985a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, 2986c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 2987c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 298831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 298931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 299031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 299105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2992f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_pci_init_one - handle a positive probe of a PCI Marvell host 299305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pdev: PCI device found 299405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ent: PCI device ID entry for the matched host 299505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 299605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 299705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 299805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 2999f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 3000f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent) 300120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 30022dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik static int printed_version; 300320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int board_idx = (unsigned int)ent->driver_data; 30044447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 30054447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct ata_host *host; 30064447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv; 30074447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo int n_ports, rc; 300820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3009a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik if (!printed_version++) 3010a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 301120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30124447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* allocate host */ 30134447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 30144447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 30154447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 30164447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 30174447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (!host || !hpriv) 30184447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return -ENOMEM; 30194447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->private_data = hpriv; 3020f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 30214447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 30224447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* acquire resources */ 302324dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo rc = pcim_enable_device(pdev); 302424dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 302520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return rc; 302620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30270d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 30280d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc == -EBUSY) 302924dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pcim_pin_device(pdev); 30300d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc) 303124dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 30324447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->iomap = pcim_iomap_table(pdev); 3033f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base = host->iomap[MV_PRIMARY_BAR]; 303420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3035d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik rc = pci_go_64(pdev); 3036d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik if (rc) 3037d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik return rc; 3038d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik 3039da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord rc = mv_create_dma_pools(hpriv, &pdev->dev); 3040da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (rc) 3041da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return rc; 3042da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 304320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* initialize adapter */ 30444447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_init_host(host, board_idx); 304524dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 304624dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 304720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 304831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Enable interrupts */ 30496a59dcf8678cbc4106a8a6e158d7408a87691358Tejun Heo if (msi && pci_enable_msi(pdev)) 305031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_intx(pdev, 1); 305120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 305231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 30534447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo mv_print_info(host); 305420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30554447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo pci_set_master(pdev); 3056ea8b4db97aa41a66c05daa4055a1974692ccd52dJeff Garzik pci_try_set_mwi(pdev); 30574447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 3058c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 305920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 30607bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 306120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3062f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev); 3063f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev); 3064f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 306520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic int __init mv_init(void) 306620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 30677bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc = -ENODEV; 30687bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 30697bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_register_driver(&mv_pci_driver); 3070f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 3071f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3072f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#endif 3073f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = platform_driver_register(&mv_platform_driver); 3074f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3075f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#ifdef CONFIG_PCI 3076f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 3077f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara pci_unregister_driver(&mv_pci_driver); 30787bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 30797bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 308020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 308120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 308220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic void __exit mv_exit(void) 308320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 30847bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 308520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ pci_unregister_driver(&mv_pci_driver); 30867bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 3087f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara platform_driver_unregister(&mv_platform_driver); 308820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 308920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 309020f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_AUTHOR("Brett Russ"); 309120f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 309220f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_LICENSE("GPL"); 309320f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DEVICE_TABLE(pci, mv_pci_tbl); 309420f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_VERSION(DRV_VERSION); 309517c5aab5b34e351531466e35b154ca86db7d46a9Mark LordMODULE_ALIAS("platform:" DRV_NAME); 309620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30977bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 3098ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzikmodule_param(msi, int, 0444); 3099ddef9bb367b19383df627e388cb4c01c86ddba6cJeff GarzikMODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 31007bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 3101ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzik 310220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_init(mv_init); 310320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_exit(mv_exit); 3104