sata_mv.c revision 37b9046a3e433a0b0c39ad1e81ec187d5be800ba
120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * sata_mv.c - Marvell SATA support 320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 4e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * Copyright 2008: Marvell Corporation, all rights reserved. 58b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * Copyright 2005: EMC Corporation, all rights reserved. 6e2b1be56c5656902744c2b52e8304126a40bb609Jeff Garzik * Copyright 2005 Red Hat, Inc. All rights reserved. 720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is free software; you can redistribute it and/or modify 1120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * it under the terms of the GNU General Public License as published by 1220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * the Free Software Foundation; version 2 of the License. 1320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is distributed in the hope that it will be useful, 1520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * but WITHOUT ANY WARRANTY; without even the implied warranty of 1620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * GNU General Public License for more details. 1820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * You should have received a copy of the GNU General Public License 2020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * along with this program; if not, write to the Free Software 2120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 2220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 254a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik/* 2685afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * sata_mv TODO list: 2785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 2885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Errata workaround for NCQ device errors. 2985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> More errata workarounds for PCI-X. 3185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3285afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Complete a full errata audit for all chipsets to identify others. 3385afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3485afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it). 3585afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3685afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Investigate problems with PCI Message Signalled Interrupts (MSI). 3785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead. 3985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 4085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Develop a low-power-consumption strategy, and implement it. 4185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 4285afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> [Experiment, low priority] Investigate interrupt coalescing. 4385afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * Quite often, especially with PCI Message Signalled Interrupts (MSI), 4485afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * the overhead reduced by interrupt mitigation is quite often not 4585afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * worth the latency cost. 4685afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 4785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> [Experiment, Marvell value added] Is it possible to use target 4885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * mode to cross-connect two Linux boxes with Marvell cards? If so, 4985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * creating LibATA target mode support would be very interesting. 5085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 5185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * Target mode, for those without docs, is the ability to directly 5285afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * connect two SATA ports. 5385afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord */ 544a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 5520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/kernel.h> 5620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/module.h> 5720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/pci.h> 5820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/init.h> 5920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/blkdev.h> 6020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/delay.h> 6120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/interrupt.h> 628d8b60046d6a2328ca4b9031b4948084f775f607Andrew Morton#include <linux/dmapool.h> 6320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/dma-mapping.h> 64a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik#include <linux/device.h> 65f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/platform_device.h> 66f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/ata_platform.h> 6715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#include <linux/mbus.h> 6820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <scsi/scsi_host.h> 69193515d51ccb363165d6b09e9ba5c21089e34badJeff Garzik#include <scsi/scsi_cmnd.h> 706c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik#include <scsi/scsi_device.h> 7120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/libata.h> 7220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#define DRV_NAME "sata_mv" 741fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord#define DRV_VERSION "1.20" 7520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russenum { 7720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* BAR's are enumerated in terms of pci_resource_start() terms */ 7820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 7920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IO_BAR = 2, /* offset 0x18: IO space */ 8020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 8120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 8320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 8420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_BASE = 0, 8620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ 87615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08), 88615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88), 89615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c), 90615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc), 91615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0), 92615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 9320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC0_REG_BASE = 0x20000, 948e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_FLASH_CTL_OFS = 0x1046c, 958e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_GPIO_PORT_CTL_OFS = 0x104f0, 968e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_RESET_CFG_OFS = 0x180d8, 9720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 9820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 9920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 10020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 10120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 10220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 10331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH = 32, 10431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 10531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 10631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* CRQB needs alignment on a 1KB boundary. Size == 1KB 10731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * CRPB needs alignment on a 256B boundary. Size == 256B 10831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 10931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 11031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 11131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 112da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord MV_MAX_SG_CT = 256, 11331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 11431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 115352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ 11620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_HC_SHIFT = 2, 117352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ 118352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ 119352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ 12020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 12120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Host Flags */ 12220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 12320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ 1247bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara /* SoC integrated controllers, no PCI interface */ 125e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord MV_FLAG_SOC = (1 << 28), 1267bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 127c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 128bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI | 129bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ATA_FLAG_PIO_POLLING, 13047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE, 13120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 13231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_FLAG_READ = (1 << 0), 13331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_TAG_SHIFT = 1, 134c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 135e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 136c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 13731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_ADDR_SHIFT = 8, 13831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_CS = (0x2 << 11), 13931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_LAST = (1 << 15), 14031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRPB_FLAG_STATUS_SHIFT = 8, 142c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 143c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 14431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EPRD_FLAG_END_OF_TBL = (1 << 31), 14631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* PCI interface registers */ 14820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 14931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ PCI_COMMAND_OFS = 0xc00, 1508e7decdb8b132ee970a2636931b7653dec6af472Mark Lord PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */ 15131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MAIN_CMD_STS_OFS = 0xd30, 15320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ STOP_PCI_MASTER = (1 << 2), 15420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MASTER_EMPTY = (1 << 3), 15520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GLOB_SFT_RST = (1 << 4), 15620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1578e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_MODE_OFS = 0xd00, 1588e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_MODE_MASK = 0x30, 1598e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 160522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 161522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_DISC_TIMER = 0xd04, 162522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MSI_TRIGGER = 0xc38, 163522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_SERR_MASK = 0xc28, 1648e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_XBAR_TMOUT_OFS = 0x1d04, 165522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 166522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 167522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_ATTRIBUTE = 0x1d48, 168522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_COMMAND = 0x1d50, 169522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 17002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_CAUSE_OFS = 0x1d58, 17102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_MASK_OFS = 0x1d5c, 17220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 17320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 17402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_CAUSE_OFS = 0x1900, 17502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_MASK_OFS = 0x1910, 176646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 17702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 1787368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */ 1797368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, 1807368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64, 1817368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020, 1827368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024, 183352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ERR_IRQ = (1 << 0), /* shift by port # */ 184352fab701ca4753dd005b67ce5e512be944eb591Mark Lord DONE_IRQ = (1 << 1), /* shift by port # */ 18520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 18620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 18720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_ERR = (1 << 18), 18820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */ 18920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */ 190fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_0_3_COAL_DONE = (1 << 8), 191fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_4_7_COAL_DONE = (1 << 17), 19220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */ 19320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GPIO_INT = (1 << 22), 19420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SELF_INT = (1 << 23), 19520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TWSI_INT = (1 << 24), 19620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 197fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 198e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 1998b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | 200f9f7fe014fc7197a5f36f9d9859cbb27c3bdd2abMark Lord PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 20120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT | 20220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD), 203fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 204fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5), 205f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC), 20620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 20720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATAHC registers */ 20820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_CFG_OFS = 0, 20920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_IRQ_CAUSE_OFS = 0x14, 211352fab701ca4753dd005b67ce5e512be944eb591Mark Lord DMA_IRQ = (1 << 0), /* shift by port # */ 212352fab701ca4753dd005b67ce5e512be944eb591Mark Lord HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ 21320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ DEV_IRQ = (1 << 8), /* shift by port # */ 21420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Shadow block registers */ 21631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_BLK_OFS = 0x100, 21731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ 21820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATA registers */ 22020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ 22120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_ACTIVE_OFS = 0x350, 2220c58912e192fc3a4835d772aafa40b72552b819fMark Lord SATA_FIS_IRQ_CAUSE_OFS = 0x364, 22317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 224e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord LTMODE_OFS = 0x30c, 22517c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 22617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 22747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik PHY_MODE3 = 0x310, 228bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE4 = 0x314, 229bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE2 = 0x330, 230e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFCTL_OFS = 0x344, 2318e7decdb8b132ee970a2636931b7653dec6af472Mark Lord SATA_TESTCTL_OFS = 0x348, 232e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFSTAT_OFS = 0x34c, 233e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord VENDOR_UNIQUE_FIS_OFS = 0x35c, 23417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 2358e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_OFS = 0x360, 2368e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */ 2378e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 23817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 239c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_MODE = 0x74, 2408e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV5_LTMODE_OFS = 0x30, 2418e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV5_PHY_CTL_OFS = 0x0C, 2428e7decdb8b132ee970a2636931b7653dec6af472Mark Lord SATA_INTERFACE_CFG_OFS = 0x050, 243bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 244bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_M2_PREAMP_MASK = 0x7e0, 24520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 24620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Port registers */ 24720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_CFG_OFS = 0, 2480c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 2490c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 2500c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 2510c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 2520c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 253e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 254e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 25520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_CAUSE_OFS = 0x8, 25720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_MASK_OFS = 0xc, 2586c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 2596c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 2606c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV = (1 << 2), /* device error */ 2616c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 2626c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 2636c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 264c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 265c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 2666c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 267c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 2686c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 2696c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 2706c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 2716c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 272646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2736c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 274646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 275646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 276646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 277646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 278646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2796c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 280646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2816c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 282646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 283646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 284646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 285646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 286646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 287646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2886c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 289646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2906c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 291c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_OVERRUN_5 = (1 << 5), 292c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_UNDERRUN_5 = (1 << 6), 293646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 294646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 295646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 | 296646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 | 29785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord EDMA_ERR_LNK_CTRL_TX, 298646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 299bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 300bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 301bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 302bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 303bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SERR | 304bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS | 3056c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 306bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 307bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 308bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY | 309bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_CTRL_RX_2 | 310bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_RX | 311bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_TX | 312bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_TRANS_PROTO, 313e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 314bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 315bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 316bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 317bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 318bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_OVERRUN_5 | 319bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_UNDERRUN_5 | 320bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS_5 | 3216c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 322bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 323bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 324bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY, 32520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 32631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_BASE_HI_OFS = 0x10, 32731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ 32831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 32931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_OUT_PTR_OFS = 0x18, 33031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_PTR_SHIFT = 5, 33131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 33231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_BASE_HI_OFS = 0x1c, 33331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_IN_PTR_OFS = 0x20, 33431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ 33531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_PTR_SHIFT = 3, 33631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3370ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_CMD_OFS = 0x28, /* EDMA command register */ 3380ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_EN = (1 << 0), /* enable EDMA */ 3390ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 3408e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */ 3418e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 3428e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_OFS = 0x30, /* EDMA engine status */ 3438e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */ 3448e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */ 34520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3468e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_IORDY_TMOUT_OFS = 0x34, 3478e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_ARB_CFG_OFS = 0x38, 3488e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 3498e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */ 350bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 351352fab701ca4753dd005b67ce5e512be944eb591Mark Lord GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */ 352352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 35331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Host private flags (hp_flags) */ 35431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_HP_FLAG_MSI = (1 << 0), 35547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB0 = (1 << 1), 35647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB2 = (1 << 2), 35747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1B2 = (1 << 3), 35847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1C0 = (1 << 4), 359e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik MV_HP_ERRATA_XX42A0 = (1 << 5), 3600ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 3610ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 3620ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 36302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 364616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ 36520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 36631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Port private flags (pp_flags) */ 3670ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 368721091685f853ba4e6c49f26f989db0b1a811250Mark Lord MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 36900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */ 37020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 37120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 372ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 373ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 374e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 3758e7decdb8b132ee970a2636931b7653dec6af472Mark Lord#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) 3767bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC)) 377bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 37815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 37915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_BASE(i) (0x20034 + ((i) << 4)) 38015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 381095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzikenum { 382baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik /* DMA boundary 0xffff is required by the s/g splitting 383baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik * we need on /length/ in mv_fill-sg(). 384baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik */ 385baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik MV_DMA_BOUNDARY = 0xffffU, 386095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3870ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* mask of register bits containing lower 32 bits 3880ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik * of EDMA request queue DMA address 3890ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik */ 390095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 391095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3920ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* ditto, for response queue */ 393095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 394095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik}; 395095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 396522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikenum chip_type { 397522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_504x, 398522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_508x, 399522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_5080, 400522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_604x, 401522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_608x, 402e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_6042, 403e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_7042, 404f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara chip_soc, 405522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik}; 406522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 40731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ReQuest Block: 32B */ 40831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crqb { 409e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr; 410e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr_hi; 411e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ctrl_flags; 412e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ata_cmd[11]; 41331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 41420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 415e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstruct mv_crqb_iie { 416e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 417e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 418e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags; 419e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 len; 420e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 ata_cmd[4]; 421e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 422e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 42331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ResPonse Block: 8B */ 42431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crpb { 425e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 id; 426e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 flags; 427e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 tmstmp; 42820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 42920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 43031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 43131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_sg { 432e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 433e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags_size; 434e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 435e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 reserved; 43631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 43720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 43831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_port_priv { 43931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crqb *crqb; 44031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crqb_dma; 44131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crpb *crpb; 44231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crpb_dma; 443eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 444eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 445bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 446bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int req_idx; 447bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int resp_idx; 448bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 44931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 pp_flags; 45031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 45131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 452bca1c4eb9411533d613123618c0d127fae532595Jeff Garzikstruct mv_port_signal { 453bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 amps; 454bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 pre; 455bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik}; 456bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 45702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lordstruct mv_host_priv { 45802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 hp_flags; 45902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_port_signal signal[8]; 46002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord const struct mv_hw_ops *ops; 461f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports; 462f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *base; 4637368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_cause_addr; 4647368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_mask_addr; 46502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_cause_ofs; 46602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_mask_ofs; 46702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 unmask_all_irqs; 468da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord /* 469da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * These consistent DMA memory pools give us guaranteed 470da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * alignment for hardware-accessed data structures, 471da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * and less memory waste in accomplishing the alignment. 472da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord */ 473da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crqb_pool; 474da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crpb_pool; 475da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *sg_tbl_pool; 47602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord}; 47702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 47847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstruct mv_hw_ops { 4792a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 4802a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 48147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 48247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 48347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 484c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 485c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 486522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 4877bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 48847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 48947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 490da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 491da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 492da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 493da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 49431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap); 49531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap); 4963e4a139107e497a741c26f8a377a10f214d63ec1Mark Lordstatic int mv_qc_defer(struct ata_queued_cmd *qc); 49731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc); 498e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc); 4999a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 500a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 501a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo unsigned long deadline); 502bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap); 503bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap); 504f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *dev); 50520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 5062a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5072a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 50847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 50947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 51047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 511c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 512c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 513522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 5147bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 51547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 5162a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5172a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 51847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 51947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 52047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 521c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 522c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 523522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 524f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 525f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 526f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 527f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 528f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 529f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc); 530f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 531f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 532f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 5337bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 534e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 535c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no); 536e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap); 537b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio); 538e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq); 53947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 540e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp); 541e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 542e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 543e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 544e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 54547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 546eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 547eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * because we have to allow room for worst case splitting of 548eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * PRDs for 64K boundaries in mv_fill_sg(). 549eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 550c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv5_sht = { 55168d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BASE_SHT(DRV_NAME), 552baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 553c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .dma_boundary = MV_DMA_BOUNDARY, 554c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik}; 555c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 556c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv6_sht = { 55768d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_NCQ_SHT(DRV_NAME), 558138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .can_queue = MV_MAX_Q_DEPTH - 1, 559baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 56020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .dma_boundary = MV_DMA_BOUNDARY, 56120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 56220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 563029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv5_ops = { 564029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &ata_sff_port_ops, 565c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 5663e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord .qc_defer = mv_qc_defer, 567c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_prep = mv_qc_prep, 568c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_issue = mv_qc_issue, 569c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 570bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .freeze = mv_eh_freeze, 571bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .thaw = mv_eh_thaw, 572a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .hardreset = mv_hardreset, 573a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .error_handler = ata_std_error_handler, /* avoid SFF EH */ 574029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .post_internal_cmd = ATA_OP_NULL, 575bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 576c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_read = mv5_scr_read, 577c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_write = mv5_scr_write, 578c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 579c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_start = mv_port_start, 580c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_stop = mv_port_stop, 581c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik}; 582c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 583029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv6_ops = { 584029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv5_ops, 585f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord .dev_config = mv6_dev_config, 58620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_read = mv_scr_read, 58720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_write = mv_scr_write, 58820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 589e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_hardreset = mv_pmp_hardreset, 590e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_softreset = mv_softreset, 591e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .softreset = mv_softreset, 592e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .error_handler = sata_pmp_error_handler, 59320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 59420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 595029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv_iie_ops = { 596029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv6_ops, 597029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .dev_config = ATA_OP_NULL, 598e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .qc_prep = mv_qc_prep_iie, 599e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 600e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 60198ac62defe529d04a192688f40d801a2d8fbcf98Arjan van de Venstatic const struct ata_port_info mv_port_info[] = { 60220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_504x */ 603cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik .flags = MV_COMMON_FLAGS, 60431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 605bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 606c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 60720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 60820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_508x */ 609c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 61031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 611bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 612c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 61320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 61447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik { /* chip_5080 */ 615c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 61647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 617bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 618c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 61947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik }, 62020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_604x */ 621138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 622e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 623138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 62431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 625bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 626c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 62720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 62820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_608x */ 629c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 630e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 631138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ | MV_FLAG_DUAL_HC, 63231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 633bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 634c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 63520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 636e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_6042 */ 637138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 638e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 639138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 640e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 641bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 642e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 643e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 644e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_7042 */ 645138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 646e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 647138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 648e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 649bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 650e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 651e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 652f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { /* chip_soc */ 65302c1f32f1c524d2a389989f2482121f7c7d9b164Mark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 654e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 65502c1f32f1c524d2a389989f2482121f7c7d9b164Mark Lord ATA_FLAG_NCQ | MV_FLAG_SOC, 65617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .pio_mask = 0x1f, /* pio0-4 */ 65717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .udma_mask = ATA_UDMA6, 65817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .port_ops = &mv_iie_ops, 659f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 66020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 66120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 6623b7d697dfb7d03edb87e50b743a7ecff029618e9Jeff Garzikstatic const struct pci_device_id mv_pci_tbl[] = { 6632d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 6642d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 6652d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 6662d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 667cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox /* RocketRAID 1740/174x have different identifiers */ 668cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox { PCI_VDEVICE(TTI, 0x1740), chip_508x }, 669cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox { PCI_VDEVICE(TTI, 0x1742), chip_508x }, 6702d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 6712d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 6722d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 6732d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 6742d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 6752d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 6762d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 6772d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 6782d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 679d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger /* Adaptec 1430SA */ 680d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 681d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger 68202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Marvell 7042 support */ 6836a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 6846a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom 68502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Highpoint RocketRAID PCIe series */ 68602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 68702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 68802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 6892d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { } /* terminate list */ 69020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 69120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 69247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv5xxx_ops = { 69347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv5_phy_errata, 69447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv5_enable_leds, 69547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv5_read_preamp, 69647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv5_reset_hc, 697522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv5_reset_flash, 698522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv5_reset_bus, 69947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 70047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 70147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv6xxx_ops = { 70247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv6_phy_errata, 70347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv6_enable_leds, 70447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv6_read_preamp, 70547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv6_reset_hc, 706522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv6_reset_flash, 707522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv_reset_pci_bus, 70847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 70947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 710f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic const struct mv_hw_ops mv_soc_ops = { 711f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .phy_errata = mv6_phy_errata, 712f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .enable_leds = mv_soc_enable_leds, 713f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .read_preamp = mv_soc_read_preamp, 714f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_hc = mv_soc_reset_hc, 715f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_flash = mv_soc_reset_flash, 716f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_bus = mv_soc_reset_bus, 717f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 718f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 71920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 72020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Functions 72120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 72220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 72320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void writelfl(unsigned long data, void __iomem *addr) 72420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 72520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writel(data, addr); 72620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ (void) readl(addr); /* flush to avoid PCI posted write */ 72720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 72820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 729c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hc_from_port(unsigned int port) 730c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 731c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port >> MV_PORT_HC_SHIFT; 732c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 733c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 734c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hardport_from_port(unsigned int port) 735c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 736c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port & MV_PORT_MASK; 737c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 738c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 7391cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord/* 7401cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Consolidate some rather tricky bit shift calculations. 7411cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * This is hot-path stuff, so not a function. 7421cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Simple code, with two return values, so macro rather than inline. 7431cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 7441cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * port is the sole input, in range 0..7. 7457368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * shift is one output, for use with main_irq_cause / main_irq_mask registers. 7467368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * hardport is the other output, in range 0..3. 7471cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 7481cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Note that port and hardport may be the same variable in some cases. 7491cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord */ 7501cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ 7511cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord{ \ 7521cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift = mv_hc_from_port(port) * HC_SHIFT; \ 7531cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord hardport = mv_hardport_from_port(port); \ 7541cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift += hardport * 2; \ 7551cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord} 7561cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord 757352fab701ca4753dd005b67ce5e512be944eb591Mark Lordstatic inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 758352fab701ca4753dd005b67ce5e512be944eb591Mark Lord{ 759352fab701ca4753dd005b67ce5e512be944eb591Mark Lord return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 760352fab701ca4753dd005b67ce5e512be944eb591Mark Lord} 761352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 762c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline void __iomem *mv_hc_base_from_port(void __iomem *base, 763c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 764c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 765c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base(base, mv_hc_from_port(port)); 766c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 767c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 76820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 76920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 770c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base_from_port(base, port) + 7718b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik MV_SATAHC_ARBTR_REG_SZ + 772c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 77320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 77420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 775e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 776e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord{ 777e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 778e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 779e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 780e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord return hc_mmio + ofs; 781e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord} 782e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 783f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic inline void __iomem *mv_host_base(struct ata_host *host) 784f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 785f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 786f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return hpriv->base; 787f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 788f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 78920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_ap_base(struct ata_port *ap) 79020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 791f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return mv_port_base(mv_host_base(ap->host), ap->port_no); 79220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 79320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 794cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic inline int mv_get_hc_count(unsigned long port_flags) 79531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 796cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 79731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 79831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 799c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic void mv_set_edma_ptrs(void __iomem *port_mmio, 800c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_host_priv *hpriv, 801c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp) 802c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik{ 803bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 index; 804bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 805c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 806c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize request queue 807c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 808fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 809fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 810bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 811c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crqb_dma & 0x3ff); 812c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); 813bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 814c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 815c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 816c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) 817bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & 0xffffffff) | index, 818c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 819c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik else 820bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 821c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 822c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 823c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize response queue 824c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 825fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 826fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; 827bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 828c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crpb_dma & 0xff); 829c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); 830c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 831c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) 832bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & 0xffffffff) | index, 833c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 834c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik else 835bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 836c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 837bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 838c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 839c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik} 840c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 84105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 84205b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_start_dma - Enable eDMA engine 84305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @base: port base address 84405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pp: port private data 84505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 846beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * Verify the local cache of the eDMA state is accurate with a 847beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * WARN_ON. 84805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 84905b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 85005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 85105b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 8520c58912e192fc3a4835d772aafa40b72552b819fMark Lordstatic void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio, 853721091685f853ba4e6c49f26f989db0b1a811250Mark Lord struct mv_port_priv *pp, u8 protocol) 85420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 855721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int want_ncq = (protocol == ATA_PROT_NCQ); 856721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 857721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 858721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 859721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq != using_ncq) 860b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 861721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } 862c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 8630c58912e192fc3a4835d772aafa40b72552b819fMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 864352fab701ca4753dd005b67ce5e512be944eb591Mark Lord int hardport = mv_hardport_from_port(ap->port_no); 8650c58912e192fc3a4835d772aafa40b72552b819fMark Lord void __iomem *hc_mmio = mv_hc_base_from_port( 866352fab701ca4753dd005b67ce5e512be944eb591Mark Lord mv_host_base(ap->host), hardport); 8670c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 hc_irq_cause, ipending; 8680c58912e192fc3a4835d772aafa40b72552b819fMark Lord 869bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA event indicators, if any */ 870f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 871bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 8720c58912e192fc3a4835d772aafa40b72552b819fMark Lord /* clear EDMA interrupt indicator, if any */ 8730c58912e192fc3a4835d772aafa40b72552b819fMark Lord hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 874352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ipending = (DEV_IRQ | DMA_IRQ) << hardport; 8750c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (hc_irq_cause & ipending) { 8760c58912e192fc3a4835d772aafa40b72552b819fMark Lord writelfl(hc_irq_cause & ~ipending, 8770c58912e192fc3a4835d772aafa40b72552b819fMark Lord hc_mmio + HC_IRQ_CAUSE_OFS); 8780c58912e192fc3a4835d772aafa40b72552b819fMark Lord } 8790c58912e192fc3a4835d772aafa40b72552b819fMark Lord 880e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_edma_cfg(ap, want_ncq); 8810c58912e192fc3a4835d772aafa40b72552b819fMark Lord 8820c58912e192fc3a4835d772aafa40b72552b819fMark Lord /* clear FIS IRQ Cause */ 8830c58912e192fc3a4835d772aafa40b72552b819fMark Lord writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 8840c58912e192fc3a4835d772aafa40b72552b819fMark Lord 885f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord mv_set_edma_ptrs(port_mmio, hpriv, pp); 886bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 887f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS); 888afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 889afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 89020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 89120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8929b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lordstatic void mv_wait_for_edma_empty_idle(struct ata_port *ap) 8939b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord{ 8949b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 8959b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE); 8969b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const int per_loop = 5, timeout = (15 * 1000 / per_loop); 8979b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord int i; 8989b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 8999b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord /* 9009b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord * Wait for the EDMA engine to finish transactions in progress. 9019b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord */ 9029b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord for (i = 0; i < timeout; ++i) { 9039b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS); 9049b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord if ((edma_stat & empty_idle) == empty_idle) 9059b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord break; 9069b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord udelay(per_loop); 9079b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord } 9089b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */ 9099b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord} 9109b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 91105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 912e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * mv_stop_edma_engine - Disable eDMA engine 913b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * @port_mmio: io base address 91405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 91505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 91605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 91705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 918b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio) 91920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 920b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord int i; 92131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 922b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Disable eDMA. The disable bit auto clears. */ 923b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); 9248b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 925b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Wait for the chip to confirm eDMA is off. */ 926b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord for (i = 10000; i > 0; i--) { 927b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord u32 reg = readl(port_mmio + EDMA_CMD_OFS); 9284537deb5e90b717a725b3d74b58b4bb1d28443d0Jeff Garzik if (!(reg & EDMA_EN)) 929b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 930b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord udelay(10); 93131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 932b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 93320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 93420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 935e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap) 9360ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik{ 937b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord void __iomem *port_mmio = mv_ap_base(ap); 938b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 9390ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 940b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 941b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 942b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 9439b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord mv_wait_for_edma_empty_idle(ap); 944b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (mv_stop_edma_engine(port_mmio)) { 945b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); 946b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 947b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord } 948b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 9490ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik} 9500ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 9518a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#ifdef ATA_DEBUG 95231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_mem(void __iomem *start, unsigned bytes) 95320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 95431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 95531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 95631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%p: ", start + b); 95731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 9582dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", readl(start + b)); 95931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 96031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 96131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 96231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 96331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 9648a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#endif 9658a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik 96631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 96731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 96831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 96931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 97031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 dw; 97131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 97231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%02x: ", b); 97331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 9742dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik (void) pci_read_config_dword(pdev, b, &dw); 9752dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", dw); 97631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 97731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 97831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 97931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 98031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 98131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 98231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_all_regs(void __iomem *mmio_base, int port, 98331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct pci_dev *pdev) 98431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 98531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 9868b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik void __iomem *hc_base = mv_hc_base(mmio_base, 98731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port >> MV_PORT_HC_SHIFT); 98831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_base; 98931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int start_port, num_ports, p, start_hc, num_hcs, hc; 99031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 99131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (0 > port) { 99231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = start_port = 0; 99331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = 8; /* shld be benign for 4 port devs */ 99431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_hcs = 2; 99531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } else { 99631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = port >> MV_PORT_HC_SHIFT; 99731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_port = port; 99831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = num_hcs = 1; 99931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 10008b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik DPRINTK("All registers for port(s) %u-%u:\n", start_port, 100131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports > 1 ? num_ports - 1 : start_port); 100231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 100331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (NULL != pdev) { 100431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI config space regs:\n"); 100531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 100631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 100731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI regs:\n"); 100831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xc00, 0x3c); 100931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xd00, 0x34); 101031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xf00, 0x4); 101131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0x1d00, 0x6c); 101231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 1013d220c37e0a3c9a47ae00e87e044d963b3ea040bcDan Aloni hc_base = mv_hc_base(mmio_base, hc); 101431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("HC regs (HC %i):\n", hc); 101531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(hc_base, 0x1c); 101631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 101731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (p = start_port; p < start_port + num_ports; p++) { 101831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port_base = mv_port_base(mmio_base, p); 10192dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("EDMA regs (port %i):\n", p); 102031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base, 0x54); 10212dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("SATA regs (port %i):\n", p); 102231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base+0x300, 0x60); 102331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 102431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 102520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 102620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 102720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic unsigned int mv_scr_offset(unsigned int sc_reg_in) 102820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 102920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs; 103020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 103120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ switch (sc_reg_in) { 103220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_STATUS: 103320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_CONTROL: 103420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ERROR: 103520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); 103620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 103720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ACTIVE: 103820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_ACTIVE_OFS; /* active is not with the others */ 103920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 104020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ default: 104120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = 0xffffffffU; 104220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 104320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 104420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return ofs; 104520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 104620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1047da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 104820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 104920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 105020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1051da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 1052da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(mv_ap_base(ap) + ofs); 1053da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1054da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1055da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 105620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 105720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1058da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 105920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 106020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 106120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1062da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 106320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writelfl(val, mv_ap_base(ap) + ofs); 1064da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1065da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1066da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 106720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 106820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1069f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *adev) 1070f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord{ 1071f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord /* 1072e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Deal with Gen-II ("mv6") hardware quirks/restrictions: 1073e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * 1074e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Gen-II does not support NCQ over a port multiplier 1075e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * (no FIS-based switching). 1076e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * 1077f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord * We don't have hob_nsect when doing NCQ commands on Gen-II. 1078f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord * See mv_qc_prep() for more info. 1079f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord */ 1080e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (adev->flags & ATA_DFLAG_NCQ) { 1081352fab701ca4753dd005b67ce5e512be944eb591Mark Lord if (sata_pmp_attached(adev->link->ap)) { 1082e49856d82a887ce365637176f9f99ab68076eae8Mark Lord adev->flags &= ~ATA_DFLAG_NCQ; 1083352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ata_dev_printk(adev, KERN_INFO, 1084352fab701ca4753dd005b67ce5e512be944eb591Mark Lord "NCQ disabled for command-based switching\n"); 1085352fab701ca4753dd005b67ce5e512be944eb591Mark Lord } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) { 1086352fab701ca4753dd005b67ce5e512be944eb591Mark Lord adev->max_sectors = GEN_II_NCQ_MAX_SECTORS; 1087352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ata_dev_printk(adev, KERN_INFO, 1088352fab701ca4753dd005b67ce5e512be944eb591Mark Lord "max_sectors limited to %u for NCQ\n", 1089352fab701ca4753dd005b67ce5e512be944eb591Mark Lord adev->max_sectors); 1090352fab701ca4753dd005b67ce5e512be944eb591Mark Lord } 1091e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 1092f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1093f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 10943e4a139107e497a741c26f8a377a10f214d63ec1Mark Lordstatic int mv_qc_defer(struct ata_queued_cmd *qc) 10953e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord{ 10963e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct ata_link *link = qc->dev->link; 10973e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct ata_port *ap = link->ap; 10983e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct mv_port_priv *pp = ap->private_data; 10993e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 11003e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord /* 11013e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * If the port is completely idle, then allow the new qc. 11023e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord */ 11033e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (ap->nr_active_links == 0) 11043e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return 0; 11053e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 11063e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 11073e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord /* 11083e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * The port is operating in host queuing mode (EDMA). 11093e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * It can accomodate a new qc if the qc protocol 11103e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * is compatible with the current host queue mode. 11113e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord */ 11123e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { 11133e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord /* 11143e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * The host queue (EDMA) is in NCQ mode. 11153e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * If the new qc is also an NCQ command, 11163e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * then allow the new qc. 11173e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord */ 11183e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (qc->tf.protocol == ATA_PROT_NCQ) 11193e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return 0; 11203e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord } else { 11213e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord /* 11223e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * The host queue (EDMA) is in non-NCQ, DMA mode. 11233e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * If the new qc is also a non-NCQ, DMA command, 11243e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * then allow the new qc. 11253e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord */ 11263e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (qc->tf.protocol == ATA_PROT_DMA) 11273e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return 0; 11283e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord } 11293e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord } 11303e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return ATA_DEFER_PORT; 11313e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord} 11323e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 113300f42eabb204c68fa64ef72de834e74aca15c81fMark Lordstatic void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs) 1134e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 113500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord u32 new_fiscfg, old_fiscfg; 113600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord u32 new_ltmode, old_ltmode; 113700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord u32 new_haltcond, old_haltcond; 113800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 113900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord old_fiscfg = readl(port_mmio + FISCFG_OFS); 114000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord old_ltmode = readl(port_mmio + LTMODE_OFS); 114100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS); 114200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 114300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR); 114400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord new_ltmode = old_ltmode & ~LTMODE_BIT8; 114500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord new_haltcond = old_haltcond | EDMA_ERR_DEV; 114600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 114700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (want_fbs) { 114800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC; 114900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord new_ltmode = old_ltmode | LTMODE_BIT8; 1150e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 115100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 11528e7decdb8b132ee970a2636931b7653dec6af472Mark Lord if (new_fiscfg != old_fiscfg) 11538e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(new_fiscfg, port_mmio + FISCFG_OFS); 1154e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (new_ltmode != old_ltmode) 1155e49856d82a887ce365637176f9f99ab68076eae8Mark Lord writelfl(new_ltmode, port_mmio + LTMODE_OFS); 115600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (new_haltcond != old_haltcond) 115700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS); 1158f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1159f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 1160dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lordstatic void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq) 1161dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord{ 1162dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1163dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord u32 old, new; 1164dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord 1165dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord /* workaround for 88SX60x1 FEr SATA#25 (part 1) */ 1166dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS); 1167dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord if (want_ncq) 1168dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord new = old | (1 << 22); 1169dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord else 1170dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord new = old & ~(1 << 22); 1171dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord if (new != old) 1172dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS); 1173dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord} 1174dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord 1175e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq) 1176e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 11770c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 cfg; 1178e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_port_priv *pp = ap->private_data; 1179e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1180e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1181e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1182e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* set up non-NCQ EDMA configuration */ 11830c58912e192fc3a4835d772aafa40b72552b819fMark Lord cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 118400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord pp->pp_flags &= ~MV_PP_FLAG_FBS_EN; 1185e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 11860c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (IS_GEN_I(hpriv)) 1187e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 8); /* enab config burst size mask */ 1188e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1189dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord else if (IS_GEN_II(hpriv)) { 1190e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1191dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord mv_60x1_errata_sata25(ap, want_ncq); 1192e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1193dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord } else if (IS_GEN_IIE(hpriv)) { 119400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord int want_fbs = sata_pmp_attached(ap); 119500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord /* 119600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * Possible future enhancement: 119700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * 119800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * The chip can use FBS with non-NCQ, if we allow it, 119900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * But first we need to have the error handling in place 120000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * for this mode (datasheet section 7.3.15.4.2.3). 120100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * So disallow non-NCQ FBS for now. 120200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord */ 120300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord want_fbs &= want_ncq; 120400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 120500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord mv_config_fbs(port_mmio, want_ncq, want_fbs); 120600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 120700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (want_fbs) { 120800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord pp->pp_flags |= MV_PP_FLAG_FBS_EN; 120900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ 121000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord } 121100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 1212e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 1213e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 22); /* enab 4-entry host queue cache */ 1214616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (HAS_PCI(ap->host)) 1215616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord cfg |= (1 << 18); /* enab early completion */ 1216616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (hpriv->hp_flags & MV_HP_CUT_THROUGH) 1217616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ 1218e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 1219e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1220721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq) { 1221721091685f853ba4e6c49f26f989db0b1a811250Mark Lord cfg |= EDMA_CFG_NCQ; 1222721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 1223721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } else 1224721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN; 1225721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1226e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik writelfl(cfg, port_mmio + EDMA_CFG_OFS); 1227e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1228e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1229da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordstatic void mv_port_free_dma_mem(struct ata_port *ap) 1230da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord{ 1231da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1232da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_port_priv *pp = ap->private_data; 1233eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord int tag; 1234da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1235da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crqb) { 1236da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1237da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = NULL; 1238da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1239da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crpb) { 1240da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1241da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = NULL; 1242da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1243eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1244eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1245eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we have one unique sg_tbl per NCQ tag. 1246eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1247eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1248eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (pp->sg_tbl[tag]) { 1249eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) 1250eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_pool_free(hpriv->sg_tbl_pool, 1251eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag], 1252eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag]); 1253eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = NULL; 1254eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1255da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1256da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord} 1257da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 125805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 125905b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_start - Port specific init/start routine. 126005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 126105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 126205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Allocate and point to DMA memory, init port private memory, 126305b308e1df6d9d673daedb517969241f41278b52Brett Russ * zero indices. 126405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 126505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 126605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 126705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 126831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap) 126931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1270cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct device *dev = ap->host->dev; 1271cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 127231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp; 1273dde2020754aeb14e17052d61784dcb37f252aac2James Bottomley int tag; 127431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 127524dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 12766037d6bbdff65eb5a84fe35e140f4da4f7cc103aJeff Garzik if (!pp) 127724dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return -ENOMEM; 1278da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord ap->private_data = pp; 127931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1280da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1281da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crqb) 1282da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 1283da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crqb, 0, MV_CRQB_Q_SZ); 128431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1285da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1286da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crpb) 1287da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord goto out_port_free_dma_mem; 1288da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crpb, 0, MV_CRPB_Q_SZ); 128931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1290eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1291eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1292eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we need one unique sg_tbl per NCQ tag. 1293eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1294eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1295eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) { 1296eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1297eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1298eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (!pp->sg_tbl[tag]) 1299eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord goto out_port_free_dma_mem; 1300eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } else { 1301eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = pp->sg_tbl[0]; 1302eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1303eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1304eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 130531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 1306da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1307da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordout_port_free_dma_mem: 1308da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 1309da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 131031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 131131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 131205b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 131305b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_stop - Port specific cleanup/stop routine. 131405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 131505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 131605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Stop DMA, cleanup port memory. 131705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 131805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 1319cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine uses the host lock to protect the DMA stop. 132005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 132131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap) 132231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1323e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma(ap); 1324da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 132531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 132631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 132705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 132805b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 132905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command whose SG list to source from 133005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 133105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Populate the SG list and mark the last entry. 133205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 133305b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 133405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 133505b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 13366c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzikstatic void mv_fill_sg(struct ata_queued_cmd *qc) 133731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 133831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = qc->ap->private_data; 1339972c26bdd6b58e7534473c4f7928584578cf43f4Jeff Garzik struct scatterlist *sg; 13403be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik struct mv_sg *mv_sg, *last_sg = NULL; 1341ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo unsigned int si; 134231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1343eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord mv_sg = pp->sg_tbl[qc->tag]; 1344ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 1345d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik dma_addr_t addr = sg_dma_address(sg); 1346d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik u32 sg_len = sg_dma_len(sg); 134722374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 13484007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson while (sg_len) { 13494007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 offset = addr & 0xffff; 13504007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 len = sg_len; 135122374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 13524007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson if ((offset + sg_len > 0x10000)) 13534007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson len = 0x10000 - offset; 13544007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 13554007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 13564007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 13576c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik mv_sg->flags_size = cpu_to_le32(len & 0xffff); 13584007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 13594007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson sg_len -= len; 13604007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson addr += len; 13614007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 13623be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg = mv_sg; 13634007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg++; 13644007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson } 136531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 13663be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik 13673be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik if (likely(last_sg)) 13683be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 136931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 137031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 13715796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzikstatic void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 137231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1373559eedad7f7764dacca33980127b4615011230e4Mark Lord u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 137431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ (last ? CRQB_CMD_LAST : 0); 1375559eedad7f7764dacca33980127b4615011230e4Mark Lord *cmdw = cpu_to_le16(tmp); 137631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 137731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 137805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 137905b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_prep - Host specific command preparation. 138005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to prepare 138105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 138205b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 138305b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it handles prep of the CRQB 138405b308e1df6d9d673daedb517969241f41278b52Brett Russ * (command request block), does some sanity checking, and calls 138505b308e1df6d9d673daedb517969241f41278b52Brett Russ * the SG load routine. 138605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 138705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 138805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 138905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 139031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc) 139131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 139231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_port *ap = qc->ap; 139331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = ap->private_data; 1394e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 *cw; 139531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_taskfile *tf; 139631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u16 flags = 0; 1397a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 139831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1399138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1400138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 140131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 140220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 140331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Fill in command request block 140431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1405e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 140631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= CRQB_FLAG_READ; 1407beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 140831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= qc->tag << CRQB_TAG_SHIFT; 1409e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 141031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1411bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1412fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 1413a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1414a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr = 1415eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1416a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr_hi = 1417eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1418a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 141931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1420a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord cw = &pp->crqb[in_index].ata_cmd[0]; 142131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ tf = &qc->tf; 142231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 142331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Sadly, the CRQB cannot accomodate all registers--there are 142431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * only 11 bytes...so we must pick and choose required 142531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * registers based on the command. So, we drop feature and 142631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * hob_feature for [RW] DMA commands, but they are needed for 142731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * NCQ. NCQ will drop hob_nsect. 142820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 142931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ switch (tf->command) { 143031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ: 143131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ_EXT: 143231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE: 143331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE_EXT: 1434c15d85c8f3f73b5f20aae7928e25b6996f16b328Jens Axboe case ATA_CMD_WRITE_FUA_EXT: 143531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 143631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 143731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_READ: 143831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_WRITE: 14398b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 144031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 144131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 144231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ default: 144331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* The only other commands EDMA supports in non-queued and 144431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 144531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * of which are defined/used by Linux. If we get here, this 144631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * driver needs work. 144731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * 144831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * FIXME: modify libata to give qc_prep a return value and 144931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * return error here. 145031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 145131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ BUG_ON(tf->command); 145231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 145331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 145431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 145531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 145631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 145731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 145831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 145931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 146031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 146131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 146231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 146331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1464e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 1465e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1466e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik mv_fill_sg(qc); 1467e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1468e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1469e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik/** 1470e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * mv_qc_prep_iie - Host specific command preparation. 1471e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * @qc: queued command to prepare 1472e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1473e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * This routine simply redirects to the general purpose routine 1474e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * if command is not DMA. Else, it handles prep of the CRQB 1475e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * (command request block), does some sanity checking, and calls 1476e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * the SG load routine. 1477e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1478e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * LOCKING: 1479e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * Inherited from caller. 1480e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik */ 1481e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc) 1482e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 1483e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_port *ap = qc->ap; 1484e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_port_priv *pp = ap->private_data; 1485e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_crqb_iie *crqb; 1486e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_taskfile *tf; 1487a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 1488e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik u32 flags = 0; 1489e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1490138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1491138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 1492e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1493e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1494e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* Fill in Gen IIE command request block */ 1495e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 1496e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= CRQB_FLAG_READ; 1497e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1498beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 1499e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= qc->tag << CRQB_TAG_SHIFT; 15008c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord flags |= qc->tag << CRQB_HOSTQ_SHIFT; 1501e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 1502e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1503bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1504fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 1505a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1506a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 1507eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1508eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1509e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->flags = cpu_to_le32(flags); 1510e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1511e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik tf = &qc->tf; 1512e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[0] = cpu_to_le32( 1513e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->command << 16) | 1514e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->feature << 24) 1515e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1516e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[1] = cpu_to_le32( 1517e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbal << 0) | 1518e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbam << 8) | 1519e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbah << 16) | 1520e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->device << 24) 1521e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1522e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[2] = cpu_to_le32( 1523e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbal << 0) | 1524e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbam << 8) | 1525e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbah << 16) | 1526e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_feature << 24) 1527e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1528e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[3] = cpu_to_le32( 1529e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->nsect << 0) | 1530e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_nsect << 8) 1531e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1532e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1533e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 153431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 153531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_fill_sg(qc); 153631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 153731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 153805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 153905b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_issue - Initiate a command to the host 154005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to start 154105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 154205b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 154305b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it sanity checks our local 154405b308e1df6d9d673daedb517969241f41278b52Brett Russ * caches of the request producer/consumer indices then enables 154505b308e1df6d9d673daedb517969241f41278b52Brett Russ * DMA and bumps the request producer index. 154605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 154705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 154805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 154905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 15509a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 155131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1552c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct ata_port *ap = qc->ap; 1553c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 1554c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1555bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 in_index; 155631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1557138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1558138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) { 155917c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord /* 156017c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord * We're about to send a non-EDMA capable command to the 156131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * port. Turn off EDMA so there won't be problems accessing 156231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * shadow block, etc registers. 156331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1564b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 1565e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(ap, qc->dev->link->pmp); 15669363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo return ata_sff_qc_issue(qc); 156731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 156831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1569721091685f853ba4e6c49f26f989db0b1a811250Mark Lord mv_start_dma(ap, port_mmio, pp, qc->tf.protocol); 1570bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1571fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; 1572fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 157331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 157431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* and write the request in pointer to kick the EDMA to life */ 1575bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 1576bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 157731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 157831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 157931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 158031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15818f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lordstatic struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) 15828f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 15838f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct mv_port_priv *pp = ap->private_data; 15848f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc; 15858f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 15868f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 15878f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord return NULL; 15888f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord qc = ata_qc_from_tag(ap, ap->link.active_tag); 15898f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 15908f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord qc = NULL; 15918f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord return qc; 15928f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 15938f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 15948f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lordstatic void mv_unexpected_intr(struct ata_port *ap) 15958f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 15968f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct mv_port_priv *pp = ap->private_data; 15978f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_eh_info *ehi = &ap->link.eh_info; 15988f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord char *when = ""; 15998f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 16008f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord /* 16018f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord * We got a device interrupt from something that 16028f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord * was supposed to be using EDMA or polling. 16038f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord */ 16048f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_ehi_clear_desc(ehi); 16058f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 16068f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord when = " while EDMA enabled"; 16078f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } else { 16088f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 16098f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 16108f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord when = " while polling"; 16118f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } 16128f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_ehi_push_desc(ehi, "unexpected device interrupt%s", when); 16138f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->err_mask |= AC_ERR_OTHER; 16148f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->action |= ATA_EH_RESET; 16158f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_port_freeze(ap); 16168f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 16178f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 161805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 161905b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_err_intr - Handle error interrupts on the port 162005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 16218d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * @qc: affected command (non-NCQ), or NULL 162205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 16238d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Most cases require a full reset of the chip's state machine, 16248d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * which also performs a COMRESET. 16258d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Also, if the port disabled DMA, update our cached copy to match. 162605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 162705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 162805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 162905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 163037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lordstatic void mv_err_intr(struct ata_port *ap) 163131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 163231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 1633bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 edma_err_cause, eh_freeze_mask, serr = 0; 1634bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1635bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 1636bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int action = 0, err_mask = 0; 16379af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_eh_info *ehi = &ap->link.eh_info; 163837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord struct ata_queued_cmd *qc; 163937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord int abort = 0; 164020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 16418d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord /* 164237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Read and clear the SError and err_cause bits. 16438d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord */ 164437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord sata_scr_read(&ap->link, SCR_ERROR, &serr); 164537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 164637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord 1647bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 16488d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 1649bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 165037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_port_printk(ap, KERN_INFO, "%s: err_cause=%08x pp_flags=0x%x\n", 165137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord __func__, edma_err_cause, pp->pp_flags); 1652bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 165337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord qc = mv_get_active_qc(ap); 165437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_clear_desc(ehi); 165537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x", 165637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord edma_err_cause, pp->pp_flags); 1657bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 1658352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * All generations share these EDMA error cause bits: 1659bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 166037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (edma_err_cause & EDMA_ERR_DEV) { 1661bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_DEV; 166237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord action |= ATA_EH_RESET; 166337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_push_desc(ehi, "dev error"); 166437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 1665bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 16666c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 1667bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR)) { 1668bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_ATA_BUS; 1669cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1670b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "parity error"); 1671bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1672bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 1673bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_hotplugged(ehi); 1674bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 1675b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo "dev disconnect" : "dev connect"); 1676cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1677bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1678bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1679352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 1680352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Gen-I has a different SELF_DIS bit, 1681352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * different FREEZE bits, and no SERR bit: 1682352fab701ca4753dd005b67ce5e512be944eb591Mark Lord */ 1683ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) { 1684bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE_5; 1685bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 1686bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1687b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 1688bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1689bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 1690bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE; 1691bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS) { 1692bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1693b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 1694bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1695bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SERR) { 16968d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord ata_ehi_push_desc(ehi, "SError=%08x", serr); 16978d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord err_mask |= AC_ERR_ATA_BUS; 1698cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1699bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1700afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 170120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1702bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!err_mask) { 1703bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_OTHER; 1704cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1705bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1706bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1707bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->serror |= serr; 1708bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->action |= action; 1709bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1710bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 1711bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 1712bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1713bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 1714bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 171537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (err_mask == AC_ERR_DEV) { 171637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* 171737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Cannot do ata_port_freeze() here, 171837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * because it would kill PIO access, 171937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * which is needed for further diagnosis. 172037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord */ 172137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord mv_eh_freeze(ap); 172237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord abort = 1; 172337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } else if (edma_err_cause & eh_freeze_mask) { 172437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* 172537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Note to self: ata_port_freeze() calls ata_port_abort() 172637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord */ 1727bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 172837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } else { 172937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord abort = 1; 173037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 173137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord 173237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (abort) { 173337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (qc) 173437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_link_abort(qc->dev->link); 173537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord else 173637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_port_abort(ap); 173737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 1738bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1739bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1740fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_response(struct ata_port *ap, 1741fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response, unsigned int tag, int ncq_enabled) 1742fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord{ 1743fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag); 1744fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 1745fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (qc) { 1746fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 ata_status; 1747fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u16 edma_status = le16_to_cpu(response->flags); 1748fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 1749fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * edma_status from a response queue entry: 1750fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only). 1751fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * MSB is saved ATA status from command completion. 1752fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 1753fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (!ncq_enabled) { 1754fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; 1755fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (err_cause) { 1756fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 1757fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * Error will be seen/handled by mv_err_intr(). 1758fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * So do nothing at all here. 1759fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 1760fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord return; 1761fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 1762fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 1763fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; 176437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (!ac_err_mask(ata_status)) 176537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_qc_complete(qc); 176637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* else: leave it for mv_err_intr() */ 1767fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 1768fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n", 1769fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord __func__, tag); 1770fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 1771fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord} 1772fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 1773fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) 1774bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 1775bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 1776bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 1777fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u32 in_index; 1778bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik bool work_done = false; 1779fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); 1780bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1781fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Get the hardware queue position index */ 1782bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) 1783bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 1784bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1785fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Process new responses from since the last time we looked */ 1786fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord while (in_index != pp->resp_idx) { 17876c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik unsigned int tag; 1788fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response = &pp->crpb[pp->resp_idx]; 1789bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1790fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; 1791bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1792fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (IS_GEN_I(hpriv)) { 1793fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 50xx: no NCQ, only one command active at a time */ 17949af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo tag = ap->link.active_tag; 1795fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 1796fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Gen II/IIE: get command tag from CRPB entry */ 1797fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord tag = le16_to_cpu(response->id) & 0x1f; 1798bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1799fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord mv_process_crpb_response(ap, response, tag, ncq_enabled); 1800bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik work_done = true; 1801bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1802bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1803352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Update the software queue position index in hardware */ 1804bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (work_done) 1805bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 1806fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), 1807bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 180820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 180920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 181005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 181105b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_host_intr - Handle all interrupts on the given host controller 1812cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * @host: host specific structure 18137368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * @main_irq_cause: Main interrupt cause register for the chip. 181405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 181505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 181605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 181705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 18187368f91926a2870a8c3f9546d86535ce71ae0757Mark Lordstatic int mv_host_intr(struct ata_host *host, u32 main_irq_cause) 181920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1820f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 1821a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord void __iomem *mmio = hpriv->base, *hc_mmio = NULL; 1822a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord u32 hc_irq_cause = 0; 1823a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0, port; 182420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1825a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord for (port = 0; port < hpriv->n_ports; port++) { 1826cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_port *ap = host->ports[port]; 18278f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu struct mv_port_priv *pp; 1828a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int shift, hardport, port_cause; 1829a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord /* 1830a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * When we move to the second hc, flag our cached 1831a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * copies of hc_mmio (and hc_irq_cause) as invalid again. 1832a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord */ 1833a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord if (port == MV_PORTS_PER_HC) 1834a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord hc_mmio = NULL; 1835a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord /* 1836a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * Do nothing if port is not interrupting or is disabled: 1837a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord */ 1838a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 18397368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ); 1840a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord if (!port_cause || !ap || (ap->flags & ATA_FLAG_DISABLED)) 1841a2c91a8819e315e9fd1aef3ff57badb6c1be3f80Jeff Garzik continue; 1842a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord /* 1843a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * Each hc within the host has its own hc_irq_cause register. 1844a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * We defer reading it until we know we need it, right now: 1845a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * 1846a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * FIXME later: we don't really need to read this register 1847a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * (some logic changes required below if we go that way), 1848a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * because it doesn't tell us anything new. But we do need 1849a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * to write to it, outside the top of this loop, 1850a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * to reset the interrupt triggers for next time. 1851a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord */ 1852a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord if (!hc_mmio) { 1853a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord hc_mmio = mv_hc_base_from_port(mmio, port); 1854a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 1855a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 1856a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = 1; 1857a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord } 18588f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord /* 18598f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord * Process completed CRPB response(s) before other events. 18608f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord */ 1861a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord pp = ap->private_data; 18628f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (hc_irq_cause & (DMA_IRQ << hardport)) { 18638f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) 1864fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord mv_process_crpb_entries(ap, pp); 18658f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } 18668f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord /* 18678f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord * Handle chip-reported errors, or continue on to handle PIO. 18688f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord */ 18698f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (unlikely(port_cause & ERR_IRQ)) { 187037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord mv_err_intr(ap); 18718f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } else if (hc_irq_cause & (DEV_IRQ << hardport)) { 18728f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 18738f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc = mv_get_active_qc(ap); 18748f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (qc) { 18758f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_sff_host_intr(ap, qc); 18768f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord continue; 18778f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } 18788f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } 18798f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord mv_unexpected_intr(ap); 188020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 188120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 1882a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return handled; 188320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 188420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1885a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lordstatic int mv_pci_error(struct ata_host *host, void __iomem *mmio) 1886bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 188702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 1888bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_port *ap; 1889bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 1890bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_eh_info *ehi; 1891bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int i, err_mask, printed = 0; 1892bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 err_cause; 1893bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 189402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord err_cause = readl(mmio + hpriv->irq_cause_ofs); 1895bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1896bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", 1897bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_cause); 1898bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1899bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik DPRINTK("All regs @ PCI error\n"); 1900bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 1901bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 190202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord writelfl(0, mmio + hpriv->irq_cause_ofs); 1903bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1904bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik for (i = 0; i < host->n_ports; i++) { 1905bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ap = host->ports[i]; 1906936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo if (!ata_link_offline(&ap->link)) { 19079af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo ehi = &ap->link.eh_info; 1908bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 1909bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!printed++) 1910bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, 1911bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik "PCI err cause 0x%08x", err_cause); 1912bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_HOST_BUS; 1913cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo ehi->action = ATA_EH_RESET; 19149af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 1915bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 1916bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 1917bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1918bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 1919bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1920bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 1921bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1922bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1923a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return 1; /* handled */ 1924bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1925bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 192605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1927c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * mv_interrupt - Main interrupt event handler 192805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @irq: unused 192905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @dev_instance: private data; in this case the host structure 193005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 193105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read the read only register to determine if any host 193205b308e1df6d9d673daedb517969241f41278b52Brett Russ * controllers have pending interrupts. If so, call lower level 193305b308e1df6d9d673daedb517969241f41278b52Brett Russ * routine to handle. Also check for PCI errors which are only 193405b308e1df6d9d673daedb517969241f41278b52Brett Russ * reported here. 193505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 19368b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * LOCKING: 1937cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine holds the host lock while processing pending 193805b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts. 193905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 19407d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t mv_interrupt(int irq, void *dev_instance) 194120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1942cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = dev_instance; 1943f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 1944a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0; 19457368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord u32 main_irq_cause, main_irq_mask; 194620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1947646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord spin_lock(&host->lock); 19487368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_cause = readl(hpriv->main_irq_cause_addr); 19497368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_mask = readl(hpriv->main_irq_mask_addr); 1950352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 1951352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Deal with cases where we either have nothing pending, or have read 1952352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * a bogus register value which can indicate HW removal or PCI fault. 195320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 19547368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord if ((main_irq_cause & main_irq_mask) && (main_irq_cause != 0xffffffffU)) { 19557368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord if (unlikely((main_irq_cause & PCI_ERR) && HAS_PCI(host))) 1956a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = mv_pci_error(host, hpriv->base); 1957a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord else 19587368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord handled = mv_host_intr(host, main_irq_cause); 1959bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1960cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik spin_unlock(&host->lock); 196120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return IRQ_RETVAL(handled); 196220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 196320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1964c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic unsigned int mv5_scr_offset(unsigned int sc_reg_in) 1965c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1966c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs; 1967c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1968c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik switch (sc_reg_in) { 1969c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_STATUS: 1970c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_ERROR: 1971c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_CONTROL: 1972c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = sc_reg_in * sizeof(u32); 1973c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 1974c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik default: 1975c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = 0xffffffffU; 1976c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 1977c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 1978c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return ofs; 1979c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1980c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1981da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 1982c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1983f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 1984f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 19850d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 1986c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 1987c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1988da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 1989da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(addr + ofs); 1990da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1991da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1992da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 1993c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1994c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1995da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 1996c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1997f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 1998f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 19990d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 2000c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 2001c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2002da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 20030d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo writelfl(val, addr + ofs); 2004da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 2005da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 2006da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 2007c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2008c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 20097bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 2010522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 20117bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara struct pci_dev *pdev = to_pci_dev(host->dev); 2012522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik int early_5080; 2013522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 201444c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 2015522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2016522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik if (!early_5080) { 2017522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 2018522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= (1 << 0); 2019522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 2020522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik } 2021522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 20227bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara mv_reset_pci_bus(host, mmio); 2023522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 2024522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2025522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 2026522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 20278e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS); 2028522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 2029522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 203047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 2031ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 2032ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 2033c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 2034c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 2035c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2036c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 2037c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2038c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 2039c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 2040ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2041ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 204247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 2043ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 2044522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp; 2045522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 20468e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0, mmio + MV_GPIO_PORT_CTL_OFS); 2047522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2048522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 2049522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2050522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 2051522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= ~(1 << 0); 2052522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 2053ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2054ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 20552a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 20562a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 2057bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 2058c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, port); 2059c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 2060c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 2061c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 2062c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2063c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik if (fix_apm_sq) { 20648e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(phy_mmio + MV5_LTMODE_OFS); 2065c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= (1 << 19); 20668e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, phy_mmio + MV5_LTMODE_OFS); 2067c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 20688e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(phy_mmio + MV5_PHY_CTL_OFS); 2069c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~0x3; 2070c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x1; 20718e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, phy_mmio + MV5_PHY_CTL_OFS); 2072c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2073c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2074c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 2075c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~mask; 2076c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].pre; 2077c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].amps; 2078c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_MODE); 2079bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2080bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2081c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2082c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 2083c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, port_mmio + (reg)) 2084c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 2085c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 2086c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2087c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2088c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2089e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 2090c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2091c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x028); /* command */ 2092c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(0x11f, port_mmio + EDMA_CFG_OFS); 2093c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x004); /* timer */ 2094c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x008); /* irq err cause */ 2095c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); /* irq err mask */ 2096c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); /* rq bah */ 2097c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); /* rq inp */ 2098c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); /* rq outp */ 2099c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x01c); /* respq bah */ 2100c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x024); /* respq outp */ 2101c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x020); /* respq inp */ 2102c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x02c); /* test control */ 21038e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS); 2104c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2105c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 2106c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2107c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, hc_mmio + (reg)) 2108c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2109c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc) 211047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik{ 2111c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 2112c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 2113c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2114c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); 2115c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); 2116c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); 2117c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); 2118c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2119c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(hc_mmio + 0x20); 2120c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= 0x1c1c1c1c; 2121c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x03030303; 2122c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, hc_mmio + 0x20); 2123c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2124c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 2125c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2126c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2127c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 2128c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2129c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc, port; 2130c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2131c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (hc = 0; hc < n_hc; hc++) { 2132c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (port = 0; port < MV_PORTS_PER_HC; port++) 2133c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_hc_port(hpriv, mmio, 2134c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (hc * MV_PORTS_PER_HC) + port); 2135c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2136c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_one_hc(hpriv, mmio, hc); 2137c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2138c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2139c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return 0; 214047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik} 214147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 2142101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 2143101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#define ZERO(reg) writel(0, mmio + (reg)) 21447bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 2145101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 214602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 2147101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 2148101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 21498e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(mmio + MV_PCI_MODE_OFS); 2150101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0xff00ffff; 21518e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, mmio + MV_PCI_MODE_OFS); 2152101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2153101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_DISC_TIMER); 2154101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_MSI_TRIGGER); 21558e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS); 21567368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord ZERO(PCI_HC_MAIN_IRQ_MASK_OFS); 2157101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_SERR_MASK); 215802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_cause_ofs); 215902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_mask_ofs); 2160101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_LOW_ADDRESS); 2161101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_HIGH_ADDRESS); 2162101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_ATTRIBUTE); 2163101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_COMMAND); 2164101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2165101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 2166101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2167101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 2168101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 2169101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 2170101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2171101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik mv5_reset_flash(hpriv, mmio); 2172101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 21738e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS); 2174101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0x3; 2175101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp |= (1 << 5) | (1 << 6); 21768e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS); 2177101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2178101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2179101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik/** 2180101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * mv6_reset_hc - Perform the 6xxx global soft reset 2181101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * @mmio: base address of the HBA 2182101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2183101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * This routine only applies to 6xxx parts. 2184101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2185101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * LOCKING: 2186101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * Inherited from caller. 2187101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2188c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2189c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 2190101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 2191101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; 2192101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik int i, rc = 0; 2193101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 t; 2194101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2195101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* Following procedure defined in PCI "main command and status 2196101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * register" table. 2197101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2198101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2199101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | STOP_PCI_MASTER, reg); 2200101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2201101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik for (i = 0; i < 1000; i++) { 2202101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2203101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 22042dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik if (PCI_MASTER_EMPTY & t) 2205101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik break; 2206101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2207101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(PCI_MASTER_EMPTY & t)) { 2208101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 2209101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2210101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2211101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2212101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2213101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* set reset */ 2214101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2215101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2216101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | GLOB_SFT_RST, reg); 2217101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2218101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2219101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 2220101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2221101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(GLOB_SFT_RST & t)) { 2222101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 2223101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2224101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2225101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2226101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2227101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 2228101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2229101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2230101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 2231101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2232101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2233101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while ((GLOB_SFT_RST & t) && (i-- > 0)); 2234101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2235101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (GLOB_SFT_RST & t) { 2236101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 2237101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2238101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2239101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikdone: 2240101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik return rc; 2241101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2242101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 224347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 2244ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 2245ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 2246ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *port_mmio; 2247ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik u32 tmp; 2248ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 22498e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(mmio + MV_RESET_CFG_OFS); 2250ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik if ((tmp & (1 << 0)) == 0) { 225147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->signal[idx].amps = 0x7 << 8; 2252ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = 0x1 << 5; 2253ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik return; 2254ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik } 2255ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2256ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik port_mmio = mv_port_base(mmio, idx); 2257ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(port_mmio + PHY_MODE2); 2258ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2259ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2260ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2261ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2262ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 226347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 2264ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 22658e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS); 2266ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2267ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2268c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 22692a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 2270bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 2271c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2272c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2273bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 227447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik int fix_phy_mode2 = 227547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 2276bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik int fix_phy_mode4 = 227747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 227847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik u32 m2, tmp; 227947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 228047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (fix_phy_mode2) { 228147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 228247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 228347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 |= (1 << 31); 228447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 228547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 228647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 228747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 228847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 228947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~((1 << 16) | (1 << 31)); 229047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 229147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 229247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 229347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 229447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 229547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik /* who knows what this magic does */ 229647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp = readl(port_mmio + PHY_MODE3); 229747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp &= ~0x7F800000; 229847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp |= 0x2A800000; 229947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(tmp, port_mmio + PHY_MODE3); 2300bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2301bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (fix_phy_mode4) { 230247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik u32 m4; 2303bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2304bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m4 = readl(port_mmio + PHY_MODE4); 230547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 230647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (hp_flags & MV_HP_ERRATA_60X1B2) 2307e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord tmp = readl(port_mmio + PHY_MODE3); 2308bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2309e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* workaround for errata FEr SATA#10 (part 1) */ 2310bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m4 = (m4 & ~(1 << 1)) | (1 << 0); 2311bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2312bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m4, port_mmio + PHY_MODE4); 231347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 231447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (hp_flags & MV_HP_ERRATA_60X1B2) 2315e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord writel(tmp, port_mmio + PHY_MODE3); 2316bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2317bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2318bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik /* Revert values of pre-emphasis and signal amps to the saved ones */ 2319bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 2320bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2321bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 &= ~MV_M2_PREAMP_MASK; 23222a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].amps; 23232a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].pre; 232447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 2325bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2326e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* according to mvSata 3.6.1, some IIE values are fixed */ 2327e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (IS_GEN_IIE(hpriv)) { 2328e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 &= ~0xC30FF01F; 2329e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 |= 0x0000900F; 2330e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 2331e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2332bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 2333bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2334bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2335f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* TODO: use the generic LED interface to configure the SATA Presence */ 2336f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* & Acitivy LEDs on the board */ 2337f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 2338f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2339f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2340f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2341f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2342f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2343f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 2344f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2345f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2346f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio; 2347f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara u32 tmp; 2348f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2349f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara port_mmio = mv_port_base(mmio, idx); 2350f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(port_mmio + PHY_MODE2); 2351f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2352f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2353f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2354f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2355f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2356f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2357f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, port_mmio + (reg)) 2358f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 2359f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int port) 2360f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2361f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio = mv_port_base(mmio, port); 2362f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2363e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 2364f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2365f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x028); /* command */ 2366f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0x101f, port_mmio + EDMA_CFG_OFS); 2367f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x004); /* timer */ 2368f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x008); /* irq err cause */ 2369f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); /* irq err mask */ 2370f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); /* rq bah */ 2371f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); /* rq inp */ 2372f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x018); /* rq outp */ 2373f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x01c); /* respq bah */ 2374f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x024); /* respq outp */ 2375f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x020); /* respq inp */ 2376f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x02c); /* test control */ 23778e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS); 2378f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2379f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2380f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2381f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2382f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, hc_mmio + (reg)) 2383f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 2384f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2385f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2386f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *hc_mmio = mv_hc_base(mmio, 0); 2387f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2388f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); 2389f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); 2390f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); 2391f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2392f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2393f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2394f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2395f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2396f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 2397f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc) 2398f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2399f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int port; 2400f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2401f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara for (port = 0; port < hpriv->n_ports; port++) 2402f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_hc_port(hpriv, mmio, port); 2403f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2404f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_one_hc(hpriv, mmio); 2405f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2406f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 2407f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2408f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2409f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 2410f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2411f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2412f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2413f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2414f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2415f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 2416f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2417f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2418f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2419f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 24208e7decdb8b132ee970a2636931b7653dec6af472Mark Lordstatic void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) 2421b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord{ 24228e7decdb8b132ee970a2636931b7653dec6af472Mark Lord u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS); 2423b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 24248e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */ 2425b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (want_gen2i) 24268e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg |= (1 << 7); /* enable gen2i speed */ 24278e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS); 2428b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord} 2429b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 2430e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 2431c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no) 2432c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2433c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port_no); 2434c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 24358e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* 24368e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * The datasheet warns against setting EDMA_RESET when EDMA is active 24378e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * (but doesn't say what the problem might be). So we first try 24388e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * to disable the EDMA engine before doing the EDMA_RESET operation. 24398e7decdb8b132ee970a2636931b7653dec6af472Mark Lord */ 24400d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord mv_stop_edma_engine(port_mmio); 24418e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS); 2442c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2443b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (!IS_GEN_I(hpriv)) { 24448e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* Enable 3.0gb/s link speed: this survives EDMA_RESET */ 24458e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(port_mmio, 1); 2446c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2447b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord /* 24488e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * Strobing EDMA_RESET here causes a hard reset of the SATA transport, 2449b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * link, and physical layers. It resets all SATA interface registers 2450b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev. 2451c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik */ 24528e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS); 2453b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord udelay(25); /* allow reset propagation */ 2454c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writelfl(0, port_mmio + EDMA_CMD_OFS); 2455c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2456c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->ops->phy_errata(hpriv, mmio, port_no); 2457c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2458ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) 2459c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mdelay(1); 2460c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2461c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2462e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp) 246320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2464e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (sata_pmp_supported(ap)) { 2465e49856d82a887ce365637176f9f99ab68076eae8Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 2466e49856d82a887ce365637176f9f99ab68076eae8Mark Lord u32 reg = readl(port_mmio + SATA_IFCTL_OFS); 2467e49856d82a887ce365637176f9f99ab68076eae8Mark Lord int old = reg & 0xf; 246822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 2469e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (old != pmp) { 2470e49856d82a887ce365637176f9f99ab68076eae8Mark Lord reg = (reg & ~0xf) | pmp; 2471e49856d82a887ce365637176f9f99ab68076eae8Mark Lord writelfl(reg, port_mmio + SATA_IFCTL_OFS); 2472e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 247322374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik } 247420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 247520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2476e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 2477e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 247822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik{ 2479e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 2480e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return sata_std_hardreset(link, class, deadline); 2481e49856d82a887ce365637176f9f99ab68076eae8Mark Lord} 2482bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2483e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 2484e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 2485e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 2486e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 2487e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return ata_sff_softreset(link, class, deadline); 248822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik} 248922374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 2490cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 2491bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned long deadline) 249231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 2493cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo struct ata_port *ap = link->ap; 2494bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2495b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 2496f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 24970d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord int rc, attempts = 0, extra = 0; 24980d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord u32 sstatus; 24990d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord bool online; 250031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2501e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, ap->port_no); 2502b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2503bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 25040d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Workaround for errata FEr SATA#10 (part 2) */ 25050d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord do { 250617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord const unsigned long *timing = 250717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord sata_ehc_deb_timing(&link->eh_context); 2508bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 250917c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord rc = sata_link_hardreset(link, timing, deadline + extra, 251017c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord &online, NULL); 251117c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord if (rc) 25120d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord return rc; 25130d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord sata_scr_read(link, SCR_STATUS, &sstatus); 25140d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 25150d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Force 1.5gb/s link speed and try again */ 25168e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(mv_ap_base(ap), 0); 25170d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (time_after(jiffies + HZ, deadline)) 25180d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord extra = HZ; /* only extend it once, max */ 25190d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } 25200d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); 2521bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 252217c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord return rc; 2523bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2524bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2525bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap) 2526bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2527f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 25281cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord unsigned int shift, hardport, port = ap->port_no; 25297368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord u32 main_irq_mask; 2530bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2531bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* FIXME: handle coalescing completion events properly */ 2532bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 25331cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord mv_stop_edma(ap); 25341cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2535bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2536bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* disable assertion of portN err, done events */ 25377368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_mask = readl(hpriv->main_irq_mask_addr); 25387368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_mask &= ~((DONE_IRQ | ERR_IRQ) << shift); 25397368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord writelfl(main_irq_mask, hpriv->main_irq_mask_addr); 2540bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2541bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2542bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap) 2543bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2544f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 25451cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord unsigned int shift, hardport, port = ap->port_no; 25461cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); 2547bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 25487368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord u32 main_irq_mask, hc_irq_cause; 2549bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2550bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* FIXME: handle coalescing completion events properly */ 2551bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 25521cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2553bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2554bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA errors on this port */ 2555bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2556bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2557bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear pending irq events */ 2558bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 25591cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport); 25601cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 2561bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2562bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* enable assertion of portN err, done events */ 25637368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_mask = readl(hpriv->main_irq_mask_addr); 25647368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_mask |= ((DONE_IRQ | ERR_IRQ) << shift); 25657368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord writelfl(main_irq_mask, hpriv->main_irq_mask_addr); 256631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 256731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 256805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 256905b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_init - Perform some early initialization on a single port. 257005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port: libata data structure storing shadow register addresses 257105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port_mmio: base address of the port 257205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 257305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Initialize shadow register mmio addresses, clear outstanding 257405b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts on the port, and unmask interrupts for the future 257505b308e1df6d9d673daedb517969241f41278b52Brett Russ * start of the port. 257605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 257705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 257805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 257905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 258031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 258120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 25820d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *shd_base = port_mmio + SHD_BLK_OFS; 258331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ unsigned serr_ofs; 258431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 25858b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik /* PIO related setup 258631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 258731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 25888b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->error_addr = 258931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 259031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 259131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 259231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 259331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 259431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 25958b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->status_addr = 259631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 259731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* special case: control/altstatus doesn't have ATA_REG_ address */ 259831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; 259931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 260031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* unused: */ 26018d9db2d2fbae9e05022825c32f86e00c8e342860Randy Dunlap port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; 260220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 260331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding port interrupt conditions */ 260431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ serr_ofs = mv_scr_offset(SCR_ERROR); 260531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); 260631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 260731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2608646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord /* unmask all non-transient EDMA error interrupts */ 2609646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS); 261020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 26118b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 261231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_CFG_OFS), 261331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), 261431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); 261520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 261620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2617616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic unsigned int mv_in_pcix_mode(struct ata_host *host) 2618616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 2619616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 2620616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 2621616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 2622616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 2623616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (!HAS_PCI(host) || !IS_PCIE(hpriv)) 2624616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not PCI-X capable */ 2625616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord reg = readl(mmio + MV_PCI_MODE_OFS); 2626616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if ((reg & MV_PCI_MODE_MASK) == 0) 2627616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* conventional PCI mode */ 2628616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* chip is in PCI-X mode */ 2629616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 2630616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 2631616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic int mv_pci_cut_through_okay(struct ata_host *host) 2632616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 2633616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 2634616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 2635616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 2636616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 2637616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (!mv_in_pcix_mode(host)) { 2638616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord reg = readl(mmio + PCI_COMMAND_OFS); 2639616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (reg & PCI_COMMAND_MRDTRIG) 2640616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not okay */ 2641616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord } 2642616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* okay */ 2643616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 2644616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 26454447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_chip_id(struct ata_host *host, unsigned int board_idx) 2646bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 26474447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 26484447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 2649bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 2650bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 26515796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik switch (board_idx) { 265247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case chip_5080: 265347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 2654ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 265547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 265644c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 265747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x1: 265847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 265947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 266047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 266147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 266247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 266347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 266447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 266547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying 50XXB2 workarounds to unknown rev\n"); 266647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 266747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 266847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 266947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 267047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 2671bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_504x: 2672bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_508x: 267347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 2674ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 2675bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 267644c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 267747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x0: 267847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 267947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 268047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 268147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 268247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 268347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 268447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 268547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 268647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 268747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 2688bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2689bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2690bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2691bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_604x: 2692bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_608x: 269347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv6xxx_ops; 2694ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_II; 269547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 269644c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 269747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x7: 269847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 269947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 270047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x9: 270147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2702bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2703bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 2704bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 270547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 270647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 2707bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2708bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2709bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2710bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2711e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_7042: 2712616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH; 2713306b30f74d37f289033c696285e07ce0158a5d7bMark Lord if (pdev->vendor == PCI_VENDOR_ID_TTI && 2714306b30f74d37f289033c696285e07ce0158a5d7bMark Lord (pdev->device == 0x2300 || pdev->device == 0x2310)) 2715306b30f74d37f289033c696285e07ce0158a5d7bMark Lord { 27164e5200334e03e5620aa19d538300c13db270a063Mark Lord /* 27174e5200334e03e5620aa19d538300c13db270a063Mark Lord * Highpoint RocketRAID PCIe 23xx series cards: 27184e5200334e03e5620aa19d538300c13db270a063Mark Lord * 27194e5200334e03e5620aa19d538300c13db270a063Mark Lord * Unconfigured drives are treated as "Legacy" 27204e5200334e03e5620aa19d538300c13db270a063Mark Lord * by the BIOS, and it overwrites sector 8 with 27214e5200334e03e5620aa19d538300c13db270a063Mark Lord * a "Lgcy" metadata block prior to Linux boot. 27224e5200334e03e5620aa19d538300c13db270a063Mark Lord * 27234e5200334e03e5620aa19d538300c13db270a063Mark Lord * Configured drives (RAID or JBOD) leave sector 8 27244e5200334e03e5620aa19d538300c13db270a063Mark Lord * alone, but instead overwrite a high numbered 27254e5200334e03e5620aa19d538300c13db270a063Mark Lord * sector for the RAID metadata. This sector can 27264e5200334e03e5620aa19d538300c13db270a063Mark Lord * be determined exactly, by truncating the physical 27274e5200334e03e5620aa19d538300c13db270a063Mark Lord * drive capacity to a nice even GB value. 27284e5200334e03e5620aa19d538300c13db270a063Mark Lord * 27294e5200334e03e5620aa19d538300c13db270a063Mark Lord * RAID metadata is at: (dev->n_sectors & ~0xfffff) 27304e5200334e03e5620aa19d538300c13db270a063Mark Lord * 27314e5200334e03e5620aa19d538300c13db270a063Mark Lord * Warn the user, lest they think we're just buggy. 27324e5200334e03e5620aa19d538300c13db270a063Mark Lord */ 27334e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 27344e5200334e03e5620aa19d538300c13db270a063Mark Lord " BIOS CORRUPTS DATA on all attached drives," 27354e5200334e03e5620aa19d538300c13db270a063Mark Lord " regardless of if/how they are configured." 27364e5200334e03e5620aa19d538300c13db270a063Mark Lord " BEWARE!\n"); 27374e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": For data safety, do not" 27384e5200334e03e5620aa19d538300c13db270a063Mark Lord " use sectors 8-9 on \"Legacy\" drives," 27394e5200334e03e5620aa19d538300c13db270a063Mark Lord " and avoid the final two gigabytes on" 27404e5200334e03e5620aa19d538300c13db270a063Mark Lord " all RocketRAID BIOS initialized drives.\n"); 2741306b30f74d37f289033c696285e07ce0158a5d7bMark Lord } 27428e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* drop through */ 2743e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_6042: 2744e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hpriv->ops = &mv6xxx_ops; 2745e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_GEN_IIE; 2746616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (board_idx == chip_6042 && mv_pci_cut_through_okay(host)) 2747616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_CUT_THROUGH; 2748e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 274944c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 2750e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case 0x0: 2751e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_XX42A0; 2752e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2753e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case 0x1: 2754e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2755e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2756e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik default: 2757e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 2758e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik "Applying 60X1C0 workarounds to unknown rev\n"); 2759e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2760e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2761e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 2762e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2763f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara case chip_soc: 2764f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->ops = &mv_soc_ops; 2765f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hp_flags |= MV_HP_ERRATA_60X1C0; 2766f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara break; 2767e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2768bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 2769f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_ERR, host->dev, 27705796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik "BUG: invalid board index %u\n", board_idx); 2771bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 1; 2772bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2773bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2774bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik hpriv->hp_flags = hp_flags; 277502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord if (hp_flags & MV_HP_PCIE) { 277602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS; 277702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS; 277802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 277902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } else { 278002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS; 278102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS; 278202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 278302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } 2784bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2785bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 0; 2786bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2787bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 278805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 278947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik * mv_init_host - Perform some early initialization of the host. 27904447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to initialize 27914447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @board_idx: controller index 279205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 279305b308e1df6d9d673daedb517969241f41278b52Brett Russ * If possible, do an early global reset of the host. Then do 279405b308e1df6d9d673daedb517969241f41278b52Brett Russ * our port init and clear/unmask all/relevant host interrupts. 279505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 279605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 279705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 279805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 27994447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_init_host(struct ata_host *host, unsigned int board_idx) 280020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 280120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ int rc = 0, n_hc, port, hc; 28024447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 2803f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 280447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 28054447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_chip_id(host, board_idx); 2806bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (rc) 2807352fab701ca4753dd005b67ce5e512be944eb591Mark Lord goto done; 2808f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2809f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 28107368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS; 28117368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS; 2812f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } else { 28137368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS; 28147368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS; 2815f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2816352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 2817352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* global interrupt mask: 0 == mask everything */ 28187368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord writel(0, hpriv->main_irq_mask_addr); 2819bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 28204447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_hc = mv_get_hc_count(host->ports[0]->flags); 2821bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 28224447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) 282347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->read_preamp(hpriv, port, mmio); 282420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2825c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 282647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (rc) 282720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ goto done; 282820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2829522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik hpriv->ops->reset_flash(hpriv, mmio); 28307bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara hpriv->ops->reset_bus(host, mmio); 283147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->enable_leds(hpriv, mmio); 283220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 28334447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) { 2834cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo struct ata_port *ap = host->ports[port]; 28352a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2836cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 2837cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo mv_port_init(&ap->ioaddr, port_mmio); 2838cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 28397bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 2840f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2841f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int offset = port_mmio - mmio; 2842f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 2843f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 2844f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 28457bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 284620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 284720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 284820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hc; hc++) { 284931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 285031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 285131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 285231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ "(before clear)=0x%08x\n", hc, 285331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_CFG_OFS), 285431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_IRQ_CAUSE_OFS)); 285531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 285631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding hc interrupt conditions */ 285731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); 285820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 285920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2860f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2861f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* Clear any currently outstanding host interrupt conditions */ 2862f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(0, mmio + hpriv->irq_cause_ofs); 286331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2864f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* and unmask interrupt generation for host regs */ 2865f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs); 2866f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (IS_GEN_I(hpriv)) 2867f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS_5, 28687368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_mask_addr); 2869f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara else 2870f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS, 28717368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_mask_addr); 2872f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2873f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x " 2874f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "PCI int cause/mask=0x%08x/0x%08x\n", 28757368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord readl(hpriv->main_irq_cause_addr), 28767368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord readl(hpriv->main_irq_mask_addr), 2877f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(mmio + hpriv->irq_cause_ofs), 2878f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(mmio + hpriv->irq_mask_ofs)); 2879f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } else { 2880f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS_SOC, 28817368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_mask_addr); 2882f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n", 28837368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord readl(hpriv->main_irq_cause_addr), 28847368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord readl(hpriv->main_irq_mask_addr)); 2885f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2886f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharadone: 2887f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 2888f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2889fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik 2890fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradleystatic int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 2891fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley{ 2892fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 2893fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRQB_Q_SZ, 0); 2894fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crqb_pool) 2895fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2896fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2897fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 2898fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRPB_Q_SZ, 0); 2899fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crpb_pool) 2900fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2901fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2902fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 2903fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_SG_TBL_SZ, 0); 2904fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->sg_tbl_pool) 2905fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2906fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2907fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return 0; 2908fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley} 2909fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 291015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhekstatic void mv_conf_mbus_windows(struct mv_host_priv *hpriv, 291115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_target_info *dram) 291215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek{ 291315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek int i; 291415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 291515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < 4; i++) { 291615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_CTRL(i)); 291715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_BASE(i)); 291815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 291915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 292015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < dram->num_cs; i++) { 292115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_window *cs = dram->cs + i; 292215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 292315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(((cs->size - 1) & 0xffff0000) | 292415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (cs->mbus_attr << 8) | 292515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (dram->mbus_dram_target_id << 4) | 1, 292615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek hpriv->base + WINDOW_CTRL(i)); 292715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(cs->base, hpriv->base + WINDOW_BASE(i)); 292815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 292915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek} 293015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 2931f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/** 2932f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_probe - handle a positive probe of an soc Marvell 2933f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * host 2934f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device found 2935f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2936f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * LOCKING: 2937f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Inherited from caller. 2938f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2939f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev) 2940f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2941f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara static int printed_version; 2942f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct mv_sata_platform_data *mv_platform_data; 2943f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct ata_port_info *ppi[] = 2944f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { &mv_port_info[chip_soc], NULL }; 2945f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host; 2946f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv; 2947f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct resource *res; 2948f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports, rc; 294920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2950f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!printed_version++) 2951f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 2952bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2953f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 2954f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Simple resource validation .. 2955f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2956f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (unlikely(pdev->num_resources != 2)) { 2957f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_err(&pdev->dev, "invalid number of resources\n"); 2958f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 2959f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2960f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2961f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 2962f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Get the register base first 2963f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2964f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2965f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (res == NULL) 2966f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 2967f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2968f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* allocate host */ 2969f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_platform_data = pdev->dev.platform_data; 2970f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara n_ports = mv_platform_data->n_ports; 2971f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2972f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 2973f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 2974f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2975f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!host || !hpriv) 2976f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -ENOMEM; 2977f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->private_data = hpriv; 2978f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 2979f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2980f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->iomap = NULL; 2981f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara hpriv->base = devm_ioremap(&pdev->dev, res->start, 2982f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara res->end - res->start + 1); 2983f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base -= MV_SATAHC0_REG_BASE; 2984f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 298515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek /* 298615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek * (Re-)program MBUS remapping windows if we are asked to. 298715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek */ 298815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek if (mv_platform_data->dram != NULL) 298915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek mv_conf_mbus_windows(hpriv, mv_platform_data->dram); 299015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 2991fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley rc = mv_create_dma_pools(hpriv, &pdev->dev); 2992fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (rc) 2993fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return rc; 2994fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2995f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* initialize adapter */ 2996f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = mv_init_host(host, chip_soc); 2997f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc) 2998f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 2999f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3000f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, 3001f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, 3002f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->n_ports); 3003f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3004f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, 3005f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara IRQF_SHARED, &mv6_sht); 3006f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3007f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3008f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* 3009f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 3010f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_remove - unplug a platform interface 3011f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device 3012f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 3013f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * A platform bus SATA device has been unplugged. Perform the needed 3014f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * cleanup. Also called on module unload for any active devices. 3015f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3016f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev) 3017f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3018f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct device *dev = &pdev->dev; 3019f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host = dev_get_drvdata(dev); 3020f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3021f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_host_detach(host); 3022f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 302320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 302420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3025f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic struct platform_driver mv_platform_driver = { 3026f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_platform_probe, 3027f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .remove = __devexit_p(mv_platform_remove), 3028f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .driver = { 3029f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .name = DRV_NAME, 3030f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .owner = THIS_MODULE, 3031f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 3032f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 3033f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3034f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 30357bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 3036f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 3037f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent); 3038f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 30397bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 30407bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic struct pci_driver mv_pci_driver = { 30417bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .name = DRV_NAME, 30427bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .id_table = mv_pci_tbl, 3043f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_pci_init_one, 30447bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .remove = ata_pci_remove_one, 30457bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara}; 30467bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 30477bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* 30487bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara * module options 30497bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara */ 30507bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int msi; /* Use PCI msi; either zero (off, default) or non-zero */ 30517bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 30527bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 30537bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* move to PCI layer or libata core? */ 30547bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int pci_go_64(struct pci_dev *pdev) 30557bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara{ 30567bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc; 30577bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 30587bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 30597bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 30607bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 30617bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 30627bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 30637bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 30647bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "64-bit DMA enable failed\n"); 30657bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 30667bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 30677bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 30687bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } else { 30697bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 30707bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 30717bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 30727bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit DMA enable failed\n"); 30737bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 30747bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 30757bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 30767bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 30777bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 30787bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit consistent DMA enable failed\n"); 30797bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 30807bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 30817bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 30827bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 30837bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 30847bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara} 30857bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 308605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 308705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_print_info - Dump key info to kernel log for perusal. 30884447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to print info about 308905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 309005b308e1df6d9d673daedb517969241f41278b52Brett Russ * FIXME: complete this. 309105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 309205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 309305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 309405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 30954447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic void mv_print_info(struct ata_host *host) 309631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 30974447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 30984447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 309944c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok u8 scc; 3100c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik const char *scc_s, *gen; 310131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 310231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Use this to determine the HW stepping of the chip so we know 310331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * what errata to workaround 310431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 310531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 310631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (scc == 0) 310731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "SCSI"; 310831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else if (scc == 0x01) 310931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "RAID"; 311031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else 3111c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik scc_s = "?"; 3112c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik 3113c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik if (IS_GEN_I(hpriv)) 3114c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "I"; 3115c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_II(hpriv)) 3116c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "II"; 3117c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_IIE(hpriv)) 3118c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "IIE"; 3119c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else 3120c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "?"; 312131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3122a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, 3123c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 3124c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 312531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 312631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 312731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 312805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 3129f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_pci_init_one - handle a positive probe of a PCI Marvell host 313005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pdev: PCI device found 313105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ent: PCI device ID entry for the matched host 313205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 313305b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 313405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 313505b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 3136f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 3137f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent) 313820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 31392dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik static int printed_version; 314020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int board_idx = (unsigned int)ent->driver_data; 31414447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 31424447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct ata_host *host; 31434447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv; 31444447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo int n_ports, rc; 314520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3146a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik if (!printed_version++) 3147a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 314820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 31494447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* allocate host */ 31504447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 31514447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 31524447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 31534447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 31544447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (!host || !hpriv) 31554447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return -ENOMEM; 31564447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->private_data = hpriv; 3157f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 31584447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 31594447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* acquire resources */ 316024dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo rc = pcim_enable_device(pdev); 316124dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 316220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return rc; 316320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 31640d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 31650d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc == -EBUSY) 316624dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pcim_pin_device(pdev); 31670d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc) 316824dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 31694447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->iomap = pcim_iomap_table(pdev); 3170f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base = host->iomap[MV_PRIMARY_BAR]; 317120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3172d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik rc = pci_go_64(pdev); 3173d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik if (rc) 3174d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik return rc; 3175d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik 3176da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord rc = mv_create_dma_pools(hpriv, &pdev->dev); 3177da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (rc) 3178da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return rc; 3179da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 318020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* initialize adapter */ 31814447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_init_host(host, board_idx); 318224dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 318324dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 318420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 318531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Enable interrupts */ 31866a59dcf8678cbc4106a8a6e158d7408a87691358Tejun Heo if (msi && pci_enable_msi(pdev)) 318731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_intx(pdev, 1); 318820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 318931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 31904447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo mv_print_info(host); 319120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 31924447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo pci_set_master(pdev); 3193ea8b4db97aa41a66c05daa4055a1974692ccd52dJeff Garzik pci_try_set_mwi(pdev); 31944447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 3195c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 319620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 31977bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 319820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3199f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev); 3200f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev); 3201f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 320220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic int __init mv_init(void) 320320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 32047bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc = -ENODEV; 32057bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 32067bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_register_driver(&mv_pci_driver); 3207f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 3208f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3209f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#endif 3210f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = platform_driver_register(&mv_platform_driver); 3211f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3212f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#ifdef CONFIG_PCI 3213f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 3214f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara pci_unregister_driver(&mv_pci_driver); 32157bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 32167bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 321720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 321820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 321920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic void __exit mv_exit(void) 322020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 32217bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 322220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ pci_unregister_driver(&mv_pci_driver); 32237bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 3224f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara platform_driver_unregister(&mv_platform_driver); 322520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 322620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 322720f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_AUTHOR("Brett Russ"); 322820f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 322920f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_LICENSE("GPL"); 323020f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DEVICE_TABLE(pci, mv_pci_tbl); 323120f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_VERSION(DRV_VERSION); 323217c5aab5b34e351531466e35b154ca86db7d46a9Mark LordMODULE_ALIAS("platform:" DRV_NAME); 323320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 32347bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 3235ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzikmodule_param(msi, int, 0444); 3236ddef9bb367b19383df627e388cb4c01c86ddba6cJeff GarzikMODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 32377bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 3238ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzik 323920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_init(mv_init); 324020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_exit(mv_exit); 3241