sata_mv.c revision 3bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675b
120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * sata_mv.c - Marvell SATA support 320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 4e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * Copyright 2008: Marvell Corporation, all rights reserved. 58b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * Copyright 2005: EMC Corporation, all rights reserved. 6e2b1be56c5656902744c2b52e8304126a40bb609Jeff Garzik * Copyright 2005 Red Hat, Inc. All rights reserved. 720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is free software; you can redistribute it and/or modify 1120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * it under the terms of the GNU General Public License as published by 1220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * the Free Software Foundation; version 2 of the License. 1320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is distributed in the hope that it will be useful, 1520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * but WITHOUT ANY WARRANTY; without even the implied warranty of 1620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * GNU General Public License for more details. 1820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * You should have received a copy of the GNU General Public License 2020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * along with this program; if not, write to the Free Software 2120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 2220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 254a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik/* 2685afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * sata_mv TODO list: 2785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 2885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Errata workaround for NCQ device errors. 2985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> More errata workarounds for PCI-X. 3185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3285afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Complete a full errata audit for all chipsets to identify others. 3385afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3485afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it). 3585afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3685afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Investigate problems with PCI Message Signalled Interrupts (MSI). 3785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead. 3985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 4085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Develop a low-power-consumption strategy, and implement it. 4185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 4285afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> [Experiment, low priority] Investigate interrupt coalescing. 4385afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * Quite often, especially with PCI Message Signalled Interrupts (MSI), 4485afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * the overhead reduced by interrupt mitigation is quite often not 4585afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * worth the latency cost. 4685afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 4785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> [Experiment, Marvell value added] Is it possible to use target 4885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * mode to cross-connect two Linux boxes with Marvell cards? If so, 4985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * creating LibATA target mode support would be very interesting. 5085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 5185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * Target mode, for those without docs, is the ability to directly 5285afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * connect two SATA ports. 5385afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord */ 544a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 5520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/kernel.h> 5620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/module.h> 5720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/pci.h> 5820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/init.h> 5920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/blkdev.h> 6020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/delay.h> 6120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/interrupt.h> 628d8b60046d6a2328ca4b9031b4948084f775f607Andrew Morton#include <linux/dmapool.h> 6320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/dma-mapping.h> 64a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik#include <linux/device.h> 65f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/platform_device.h> 66f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/ata_platform.h> 6715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#include <linux/mbus.h> 68c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord#include <linux/bitops.h> 6920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <scsi/scsi_host.h> 70193515d51ccb363165d6b09e9ba5c21089e34badJeff Garzik#include <scsi/scsi_cmnd.h> 716c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik#include <scsi/scsi_device.h> 7220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/libata.h> 7320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#define DRV_NAME "sata_mv" 750388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord#define DRV_VERSION "1.24" 7620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russenum { 7820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* BAR's are enumerated in terms of pci_resource_start() terms */ 7920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 8020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IO_BAR = 2, /* offset 0x18: IO space */ 8120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 8220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 8420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 8520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_BASE = 0, 8720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ 88615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08), 89615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88), 90615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c), 91615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc), 92615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0), 93615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 9420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC0_REG_BASE = 0x20000, 958e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_FLASH_CTL_OFS = 0x1046c, 968e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_GPIO_PORT_CTL_OFS = 0x104f0, 978e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_RESET_CFG_OFS = 0x180d8, 9820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 9920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 10020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 10120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 10220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 10320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 10431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH = 32, 10531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 10631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 10731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* CRQB needs alignment on a 1KB boundary. Size == 1KB 10831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * CRPB needs alignment on a 256B boundary. Size == 256B 10931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 11031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 11131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 11231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 113da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord MV_MAX_SG_CT = 256, 11431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 11531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 116352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ 11720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_HC_SHIFT = 2, 118352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ 119352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ 120352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ 12120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 12220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Host Flags */ 12320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 12420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ 1257bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 126c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 127bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI | 128bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ATA_FLAG_PIO_POLLING, 129ad3aef51e17b9c6a90a9014805f1645e8e441c17Mark Lord 13047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE, 13120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 132ad3aef51e17b9c6a90a9014805f1645e8e441c17Mark Lord MV_GENIIE_FLAGS = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 133ad3aef51e17b9c6a90a9014805f1645e8e441c17Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 134c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord ATA_FLAG_NCQ | ATA_FLAG_AN, 135ad3aef51e17b9c6a90a9014805f1645e8e441c17Mark Lord 13631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_FLAG_READ = (1 << 0), 13731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_TAG_SHIFT = 1, 138c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 139e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 140c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 14131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_ADDR_SHIFT = 8, 14231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_CS = (0x2 << 11), 14331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_LAST = (1 << 15), 14431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRPB_FLAG_STATUS_SHIFT = 8, 146c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 147c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 14831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EPRD_FLAG_END_OF_TBL = (1 << 31), 15031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* PCI interface registers */ 15220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 15331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ PCI_COMMAND_OFS = 0xc00, 1548e7decdb8b132ee970a2636931b7653dec6af472Mark Lord PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */ 15531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MAIN_CMD_STS_OFS = 0xd30, 15720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ STOP_PCI_MASTER = (1 << 2), 15820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MASTER_EMPTY = (1 << 3), 15920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GLOB_SFT_RST = (1 << 4), 16020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1618e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_MODE_OFS = 0xd00, 1628e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_MODE_MASK = 0x30, 1638e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 164522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 165522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_DISC_TIMER = 0xd04, 166522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MSI_TRIGGER = 0xc38, 167522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_SERR_MASK = 0xc28, 1688e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_XBAR_TMOUT_OFS = 0x1d04, 169522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 170522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 171522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_ATTRIBUTE = 0x1d48, 172522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_COMMAND = 0x1d50, 173522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 17402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_CAUSE_OFS = 0x1d58, 17502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_MASK_OFS = 0x1d5c, 17620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 17720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 17802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_CAUSE_OFS = 0x1900, 17902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_MASK_OFS = 0x1910, 180646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 18102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 1827368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */ 1837368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, 1847368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64, 1857368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020, 1867368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024, 187352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ERR_IRQ = (1 << 0), /* shift by port # */ 188352fab701ca4753dd005b67ce5e512be944eb591Mark Lord DONE_IRQ = (1 << 1), /* shift by port # */ 18920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 19020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 19120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_ERR = (1 << 18), 19220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */ 19320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */ 194fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_0_3_COAL_DONE = (1 << 8), 195fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_4_7_COAL_DONE = (1 << 17), 19620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */ 19720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GPIO_INT = (1 << 22), 19820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SELF_INT = (1 << 23), 19920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TWSI_INT = (1 << 24), 20020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 201fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 202e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 20320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 20420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATAHC registers */ 20520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_CFG_OFS = 0, 20620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 20720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_IRQ_CAUSE_OFS = 0x14, 208352fab701ca4753dd005b67ce5e512be944eb591Mark Lord DMA_IRQ = (1 << 0), /* shift by port # */ 209352fab701ca4753dd005b67ce5e512be944eb591Mark Lord HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ 21020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ DEV_IRQ = (1 << 8), /* shift by port # */ 21120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Shadow block registers */ 21331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_BLK_OFS = 0x100, 21431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ 21520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATA registers */ 21720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ 21820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_ACTIVE_OFS = 0x350, 2190c58912e192fc3a4835d772aafa40b72552b819fMark Lord SATA_FIS_IRQ_CAUSE_OFS = 0x364, 220c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord SATA_FIS_IRQ_AN = (1 << 9), /* async notification */ 22117c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 222e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord LTMODE_OFS = 0x30c, 22317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 22417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 22547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik PHY_MODE3 = 0x310, 226bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE4 = 0x314, 227ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */ 228ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */ 229ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */ 230ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */ 231ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord 232bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE2 = 0x330, 233e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFCTL_OFS = 0x344, 2348e7decdb8b132ee970a2636931b7653dec6af472Mark Lord SATA_TESTCTL_OFS = 0x348, 235e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFSTAT_OFS = 0x34c, 236e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord VENDOR_UNIQUE_FIS_OFS = 0x35c, 23717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 2388e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_OFS = 0x360, 2398e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */ 2408e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 24117c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 242c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_MODE = 0x74, 2438e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV5_LTMODE_OFS = 0x30, 2448e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV5_PHY_CTL_OFS = 0x0C, 2458e7decdb8b132ee970a2636931b7653dec6af472Mark Lord SATA_INTERFACE_CFG_OFS = 0x050, 246bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 247bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_M2_PREAMP_MASK = 0x7e0, 24820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 24920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Port registers */ 25020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_CFG_OFS = 0, 2510c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 2520c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 2530c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 2540c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 2550c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 256e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 257e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 25820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_CAUSE_OFS = 0x8, 26020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_MASK_OFS = 0xc, 2616c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 2626c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 2636c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV = (1 << 2), /* device error */ 2646c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 2656c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 2666c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 267c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 268c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 2696c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 270c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 2716c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 2726c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 2736c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 2746c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 275646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2766c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 277646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 278646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 279646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 280646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 281646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2826c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 283646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2846c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 285646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 286646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 287646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 288646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 289646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 290646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2916c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 292646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2936c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 294c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_OVERRUN_5 = (1 << 5), 295c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_UNDERRUN_5 = (1 << 6), 296646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 297646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 298646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 | 299646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 | 30085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord EDMA_ERR_LNK_CTRL_TX, 301646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 302bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 303bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 304bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 305bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 306bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SERR | 307bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS | 3086c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 309bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 310bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 311bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY | 312bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_CTRL_RX_2 | 313bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_RX | 314bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_TX | 315bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_TRANS_PROTO, 316e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 317bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 318bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 319bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 320bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 321bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_OVERRUN_5 | 322bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_UNDERRUN_5 | 323bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS_5 | 3246c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 325bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 326bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 327bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY, 32820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 32931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_BASE_HI_OFS = 0x10, 33031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ 33131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 33231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_OUT_PTR_OFS = 0x18, 33331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_PTR_SHIFT = 5, 33431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 33531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_BASE_HI_OFS = 0x1c, 33631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_IN_PTR_OFS = 0x20, 33731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ 33831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_PTR_SHIFT = 3, 33931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3400ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_CMD_OFS = 0x28, /* EDMA command register */ 3410ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_EN = (1 << 0), /* enable EDMA */ 3420ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 3438e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */ 3448e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 3458e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_OFS = 0x30, /* EDMA engine status */ 3468e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */ 3478e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */ 34820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3498e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_IORDY_TMOUT_OFS = 0x34, 3508e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_ARB_CFG_OFS = 0x38, 3518e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 3528e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */ 353bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 354352fab701ca4753dd005b67ce5e512be944eb591Mark Lord GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */ 355352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 35631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Host private flags (hp_flags) */ 35731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_HP_FLAG_MSI = (1 << 0), 35847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB0 = (1 << 1), 35947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB2 = (1 << 2), 36047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1B2 = (1 << 3), 36147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1C0 = (1 << 4), 3620ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 3630ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 3640ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 36502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 366616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ 3671f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */ 36820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 36931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Port private flags (pp_flags) */ 3700ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 371721091685f853ba4e6c49f26f989db0b1a811250Mark Lord MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 37200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */ 37329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */ 37420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 37520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 376ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 377ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 378e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 3798e7decdb8b132ee970a2636931b7653dec6af472Mark Lord#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) 3801f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC) 381bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 38215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 38315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_BASE(i) (0x20034 + ((i) << 4)) 38415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 385095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzikenum { 386baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik /* DMA boundary 0xffff is required by the s/g splitting 387baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik * we need on /length/ in mv_fill-sg(). 388baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik */ 389baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik MV_DMA_BOUNDARY = 0xffffU, 390095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3910ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* mask of register bits containing lower 32 bits 3920ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik * of EDMA request queue DMA address 3930ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik */ 394095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 395095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3960ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* ditto, for response queue */ 397095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 398095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik}; 399095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 400522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikenum chip_type { 401522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_504x, 402522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_508x, 403522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_5080, 404522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_604x, 405522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_608x, 406e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_6042, 407e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_7042, 408f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara chip_soc, 409522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik}; 410522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 41131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ReQuest Block: 32B */ 41231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crqb { 413e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr; 414e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr_hi; 415e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ctrl_flags; 416e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ata_cmd[11]; 41731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 41820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 419e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstruct mv_crqb_iie { 420e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 421e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 422e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags; 423e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 len; 424e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 ata_cmd[4]; 425e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 426e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 42731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ResPonse Block: 8B */ 42831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crpb { 429e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 id; 430e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 flags; 431e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 tmstmp; 43220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 43320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 43431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 43531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_sg { 436e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 437e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags_size; 438e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 439e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 reserved; 44031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 44120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 44231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_port_priv { 44331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crqb *crqb; 44431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crqb_dma; 44531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crpb *crpb; 44631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crpb_dma; 447eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 448eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 449bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 450bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int req_idx; 451bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int resp_idx; 452bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 45331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 pp_flags; 45429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int delayed_eh_pmp_map; 45531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 45631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 457bca1c4eb9411533d613123618c0d127fae532595Jeff Garzikstruct mv_port_signal { 458bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 amps; 459bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 pre; 460bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik}; 461bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 46202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lordstruct mv_host_priv { 46302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 hp_flags; 46496e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord u32 main_irq_mask; 46502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_port_signal signal[8]; 46602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord const struct mv_hw_ops *ops; 467f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports; 468f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *base; 4697368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_cause_addr; 4707368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_mask_addr; 47102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_cause_ofs; 47202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_mask_ofs; 47302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 unmask_all_irqs; 474da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord /* 475da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * These consistent DMA memory pools give us guaranteed 476da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * alignment for hardware-accessed data structures, 477da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * and less memory waste in accomplishing the alignment. 478da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord */ 479da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crqb_pool; 480da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crpb_pool; 481da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *sg_tbl_pool; 48202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord}; 48302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 48447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstruct mv_hw_ops { 4852a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 4862a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 48747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 48847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 48947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 490c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 491c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 492522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 4937bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 49447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 49547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 496da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 497da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 498da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 499da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 50031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap); 50131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap); 5023e4a139107e497a741c26f8a377a10f214d63ec1Mark Lordstatic int mv_qc_defer(struct ata_queued_cmd *qc); 50331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc); 504e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc); 5059a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 506a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 507a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo unsigned long deadline); 508bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap); 509bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap); 510f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *dev); 51120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 5122a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5132a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 51447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 51547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 51647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 517c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 518c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 519522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 5207bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 52147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 5222a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5232a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 52447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 52547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 52647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 527c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 528c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 529522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 530f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 531f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 532f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 533f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 534f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 535f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc); 536f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 537f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 538f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 5397bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 540e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 541c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no); 542e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap); 543b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio); 544e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq); 54547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 546e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp); 547e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 548e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 549e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 550e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 55129d187bb1e30682e228ce461c487d78d945c3e4fMark Lordstatic void mv_pmp_error_handler(struct ata_port *ap); 5524c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic void mv_process_crpb_entries(struct ata_port *ap, 5534c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp); 55447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 555eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 556eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * because we have to allow room for worst case splitting of 557eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * PRDs for 64K boundaries in mv_fill_sg(). 558eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 559c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv5_sht = { 56068d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BASE_SHT(DRV_NAME), 561baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 562c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .dma_boundary = MV_DMA_BOUNDARY, 563c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik}; 564c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 565c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv6_sht = { 56668d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_NCQ_SHT(DRV_NAME), 567138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .can_queue = MV_MAX_Q_DEPTH - 1, 568baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 56920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .dma_boundary = MV_DMA_BOUNDARY, 57020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 57120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 572029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv5_ops = { 573029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &ata_sff_port_ops, 574c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 5753e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord .qc_defer = mv_qc_defer, 576c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_prep = mv_qc_prep, 577c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_issue = mv_qc_issue, 578c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 579bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .freeze = mv_eh_freeze, 580bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .thaw = mv_eh_thaw, 581a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .hardreset = mv_hardreset, 582a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .error_handler = ata_std_error_handler, /* avoid SFF EH */ 583029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .post_internal_cmd = ATA_OP_NULL, 584bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 585c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_read = mv5_scr_read, 586c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_write = mv5_scr_write, 587c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 588c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_start = mv_port_start, 589c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_stop = mv_port_stop, 590c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik}; 591c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 592029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv6_ops = { 593029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv5_ops, 594f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord .dev_config = mv6_dev_config, 59520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_read = mv_scr_read, 59620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_write = mv_scr_write, 59720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 598e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_hardreset = mv_pmp_hardreset, 599e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_softreset = mv_softreset, 600e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .softreset = mv_softreset, 60129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord .error_handler = mv_pmp_error_handler, 60220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 60320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 604029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv_iie_ops = { 605029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv6_ops, 606029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .dev_config = ATA_OP_NULL, 607e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .qc_prep = mv_qc_prep_iie, 608e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 609e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 61098ac62defe529d04a192688f40d801a2d8fbcf98Arjan van de Venstatic const struct ata_port_info mv_port_info[] = { 61120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_504x */ 612cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik .flags = MV_COMMON_FLAGS, 61331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 614bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 615c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 61620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 61720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_508x */ 618c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 61931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 620bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 621c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 62220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 62347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik { /* chip_5080 */ 624c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 62547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 626bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 627c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 62847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik }, 62920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_604x */ 630138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 631e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 632138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 63331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 634bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 635c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 63620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 63720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_608x */ 638c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 639e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 640138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ | MV_FLAG_DUAL_HC, 64131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 642bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 643c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 64420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 645e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_6042 */ 646ad3aef51e17b9c6a90a9014805f1645e8e441c17Mark Lord .flags = MV_GENIIE_FLAGS, 647e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 648bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 649e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 650e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 651e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_7042 */ 652ad3aef51e17b9c6a90a9014805f1645e8e441c17Mark Lord .flags = MV_GENIIE_FLAGS, 653e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 654bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 655e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 656e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 657f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { /* chip_soc */ 6581f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord .flags = MV_GENIIE_FLAGS, 65917c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .pio_mask = 0x1f, /* pio0-4 */ 66017c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .udma_mask = ATA_UDMA6, 66117c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .port_ops = &mv_iie_ops, 662f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 66320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 66420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 6653b7d697dfb7d03edb87e50b743a7ecff029618e9Jeff Garzikstatic const struct pci_device_id mv_pci_tbl[] = { 6662d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 6672d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 6682d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 6692d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 670cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox /* RocketRAID 1740/174x have different identifiers */ 671cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox { PCI_VDEVICE(TTI, 0x1740), chip_508x }, 672cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox { PCI_VDEVICE(TTI, 0x1742), chip_508x }, 6732d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 6742d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 6752d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 6762d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 6772d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 6782d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 6792d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 6802d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 6812d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 682d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger /* Adaptec 1430SA */ 683d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 684d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger 68502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Marvell 7042 support */ 6866a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 6876a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom 68802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Highpoint RocketRAID PCIe series */ 68902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 69002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 69102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 6922d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { } /* terminate list */ 69320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 69420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 69547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv5xxx_ops = { 69647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv5_phy_errata, 69747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv5_enable_leds, 69847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv5_read_preamp, 69947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv5_reset_hc, 700522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv5_reset_flash, 701522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv5_reset_bus, 70247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 70347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 70447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv6xxx_ops = { 70547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv6_phy_errata, 70647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv6_enable_leds, 70747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv6_read_preamp, 70847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv6_reset_hc, 709522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv6_reset_flash, 710522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv_reset_pci_bus, 71147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 71247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 713f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic const struct mv_hw_ops mv_soc_ops = { 714f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .phy_errata = mv6_phy_errata, 715f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .enable_leds = mv_soc_enable_leds, 716f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .read_preamp = mv_soc_read_preamp, 717f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_hc = mv_soc_reset_hc, 718f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_flash = mv_soc_reset_flash, 719f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_bus = mv_soc_reset_bus, 720f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 721f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 72220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 72320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Functions 72420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 72520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 72620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void writelfl(unsigned long data, void __iomem *addr) 72720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 72820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writel(data, addr); 72920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ (void) readl(addr); /* flush to avoid PCI posted write */ 73020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 73120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 732c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hc_from_port(unsigned int port) 733c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 734c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port >> MV_PORT_HC_SHIFT; 735c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 736c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 737c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hardport_from_port(unsigned int port) 738c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 739c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port & MV_PORT_MASK; 740c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 741c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 7421cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord/* 7431cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Consolidate some rather tricky bit shift calculations. 7441cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * This is hot-path stuff, so not a function. 7451cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Simple code, with two return values, so macro rather than inline. 7461cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 7471cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * port is the sole input, in range 0..7. 7487368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * shift is one output, for use with main_irq_cause / main_irq_mask registers. 7497368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * hardport is the other output, in range 0..3. 7501cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 7511cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Note that port and hardport may be the same variable in some cases. 7521cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord */ 7531cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ 7541cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord{ \ 7551cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift = mv_hc_from_port(port) * HC_SHIFT; \ 7561cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord hardport = mv_hardport_from_port(port); \ 7571cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift += hardport * 2; \ 7581cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord} 7591cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord 760352fab701ca4753dd005b67ce5e512be944eb591Mark Lordstatic inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 761352fab701ca4753dd005b67ce5e512be944eb591Mark Lord{ 762352fab701ca4753dd005b67ce5e512be944eb591Mark Lord return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 763352fab701ca4753dd005b67ce5e512be944eb591Mark Lord} 764352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 765c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline void __iomem *mv_hc_base_from_port(void __iomem *base, 766c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 767c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 768c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base(base, mv_hc_from_port(port)); 769c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 770c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 77120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 77220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 773c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base_from_port(base, port) + 7748b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik MV_SATAHC_ARBTR_REG_SZ + 775c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 77620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 77720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 778e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 779e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord{ 780e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 781e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 782e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 783e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord return hc_mmio + ofs; 784e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord} 785e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 786f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic inline void __iomem *mv_host_base(struct ata_host *host) 787f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 788f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 789f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return hpriv->base; 790f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 791f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 79220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_ap_base(struct ata_port *ap) 79320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 794f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return mv_port_base(mv_host_base(ap->host), ap->port_no); 79520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 79620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 797cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic inline int mv_get_hc_count(unsigned long port_flags) 79831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 799cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 80031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 80131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 802c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic void mv_set_edma_ptrs(void __iomem *port_mmio, 803c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_host_priv *hpriv, 804c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp) 805c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik{ 806bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 index; 807bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 808c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 809c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize request queue 810c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 811fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 812fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 813bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 814c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crqb_dma & 0x3ff); 815c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); 816bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 817c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 8185cf73bfb061552aa18d816d2859409be9ace5306Mark Lord writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 819c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 820c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 821c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize response queue 822c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 823fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 824fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; 825bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 826c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crpb_dma & 0xff); 827c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); 8285cf73bfb061552aa18d816d2859409be9ace5306Mark Lord writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 829bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 830c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 831c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik} 832c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 833c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lordstatic void mv_set_main_irq_mask(struct ata_host *host, 834c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 disable_bits, u32 enable_bits) 835c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord{ 836c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord struct mv_host_priv *hpriv = host->private_data; 837c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 old_mask, new_mask; 838c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 83996e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord old_mask = hpriv->main_irq_mask; 840c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord new_mask = (old_mask & ~disable_bits) | enable_bits; 84196e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord if (new_mask != old_mask) { 84296e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord hpriv->main_irq_mask = new_mask; 843c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord writelfl(new_mask, hpriv->main_irq_mask_addr); 84496e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord } 845c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord} 846c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 847c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lordstatic void mv_enable_port_irqs(struct ata_port *ap, 848c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int port_bits) 849c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord{ 850c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int shift, hardport, port = ap->port_no; 851c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 disable_bits, enable_bits; 852c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 853c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 854c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 855c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord disable_bits = (DONE_IRQ | ERR_IRQ) << shift; 856c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord enable_bits = port_bits << shift; 857c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); 858c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord} 859c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 86005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 86105b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_start_dma - Enable eDMA engine 86205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @base: port base address 86305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pp: port private data 86405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 865beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * Verify the local cache of the eDMA state is accurate with a 866beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * WARN_ON. 86705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 86805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 86905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 87005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 8710c58912e192fc3a4835d772aafa40b72552b819fMark Lordstatic void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio, 872721091685f853ba4e6c49f26f989db0b1a811250Mark Lord struct mv_port_priv *pp, u8 protocol) 87320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 874721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int want_ncq = (protocol == ATA_PROT_NCQ); 875721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 876721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 877721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 878721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq != using_ncq) 879b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 880721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } 881c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 8820c58912e192fc3a4835d772aafa40b72552b819fMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 883352fab701ca4753dd005b67ce5e512be944eb591Mark Lord int hardport = mv_hardport_from_port(ap->port_no); 8840c58912e192fc3a4835d772aafa40b72552b819fMark Lord void __iomem *hc_mmio = mv_hc_base_from_port( 885352fab701ca4753dd005b67ce5e512be944eb591Mark Lord mv_host_base(ap->host), hardport); 8860c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 hc_irq_cause, ipending; 8870c58912e192fc3a4835d772aafa40b72552b819fMark Lord 888bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA event indicators, if any */ 889f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 890bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 8910c58912e192fc3a4835d772aafa40b72552b819fMark Lord /* clear EDMA interrupt indicator, if any */ 8920c58912e192fc3a4835d772aafa40b72552b819fMark Lord hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 893352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ipending = (DEV_IRQ | DMA_IRQ) << hardport; 8940c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (hc_irq_cause & ipending) { 8950c58912e192fc3a4835d772aafa40b72552b819fMark Lord writelfl(hc_irq_cause & ~ipending, 8960c58912e192fc3a4835d772aafa40b72552b819fMark Lord hc_mmio + HC_IRQ_CAUSE_OFS); 8970c58912e192fc3a4835d772aafa40b72552b819fMark Lord } 8980c58912e192fc3a4835d772aafa40b72552b819fMark Lord 899e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_edma_cfg(ap, want_ncq); 9000c58912e192fc3a4835d772aafa40b72552b819fMark Lord 9010c58912e192fc3a4835d772aafa40b72552b819fMark Lord /* clear FIS IRQ Cause */ 902e40060772d85f3534d3d517197696e24bb01f45bMark Lord if (IS_GEN_IIE(hpriv)) 903e40060772d85f3534d3d517197696e24bb01f45bMark Lord writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 9040c58912e192fc3a4835d772aafa40b72552b819fMark Lord 905f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord mv_set_edma_ptrs(port_mmio, hpriv, pp); 90688e675e193159b9891c1c576de4348eaf490f5d0Mark Lord mv_enable_port_irqs(ap, DONE_IRQ|ERR_IRQ); 907bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 908f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS); 909afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 910afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 91120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 91220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 9139b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lordstatic void mv_wait_for_edma_empty_idle(struct ata_port *ap) 9149b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord{ 9159b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 9169b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE); 9179b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const int per_loop = 5, timeout = (15 * 1000 / per_loop); 9189b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord int i; 9199b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 9209b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord /* 9219b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord * Wait for the EDMA engine to finish transactions in progress. 922c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * No idea what a good "timeout" value might be, but measurements 923c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * indicate that it often requires hundreds of microseconds 924c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * with two drives in-use. So we use the 15msec value above 925c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * as a rough guess at what even more drives might require. 9269b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord */ 9279b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord for (i = 0; i < timeout; ++i) { 9289b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS); 9299b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord if ((edma_stat & empty_idle) == empty_idle) 9309b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord break; 9319b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord udelay(per_loop); 9329b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord } 9339b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */ 9349b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord} 9359b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 93605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 937e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * mv_stop_edma_engine - Disable eDMA engine 938b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * @port_mmio: io base address 93905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 94005b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 94105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 94205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 943b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio) 94420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 945b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord int i; 94631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 947b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Disable eDMA. The disable bit auto clears. */ 948b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); 9498b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 950b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Wait for the chip to confirm eDMA is off. */ 951b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord for (i = 10000; i > 0; i--) { 952b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord u32 reg = readl(port_mmio + EDMA_CMD_OFS); 9534537deb5e90b717a725b3d74b58b4bb1d28443d0Jeff Garzik if (!(reg & EDMA_EN)) 954b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 955b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord udelay(10); 95631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 957b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 95820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 95920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 960e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap) 9610ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik{ 962b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord void __iomem *port_mmio = mv_ap_base(ap); 963b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 9640ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 965b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 966b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 967b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 9689b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord mv_wait_for_edma_empty_idle(ap); 969b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (mv_stop_edma_engine(port_mmio)) { 970b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); 971b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 972b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord } 973b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 9740ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik} 9750ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 9768a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#ifdef ATA_DEBUG 97731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_mem(void __iomem *start, unsigned bytes) 97820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 97931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 98031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 98131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%p: ", start + b); 98231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 9832dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", readl(start + b)); 98431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 98531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 98631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 98731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 98831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 9898a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#endif 9908a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik 99131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 99231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 99331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 99431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 99531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 dw; 99631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 99731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%02x: ", b); 99831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 9992dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik (void) pci_read_config_dword(pdev, b, &dw); 10002dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", dw); 100131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 100231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 100331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 100431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 100531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 100631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 100731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_all_regs(void __iomem *mmio_base, int port, 100831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct pci_dev *pdev) 100931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 101031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 10118b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik void __iomem *hc_base = mv_hc_base(mmio_base, 101231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port >> MV_PORT_HC_SHIFT); 101331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_base; 101431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int start_port, num_ports, p, start_hc, num_hcs, hc; 101531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 101631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (0 > port) { 101731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = start_port = 0; 101831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = 8; /* shld be benign for 4 port devs */ 101931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_hcs = 2; 102031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } else { 102131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = port >> MV_PORT_HC_SHIFT; 102231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_port = port; 102331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = num_hcs = 1; 102431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 10258b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik DPRINTK("All registers for port(s) %u-%u:\n", start_port, 102631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports > 1 ? num_ports - 1 : start_port); 102731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 102831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (NULL != pdev) { 102931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI config space regs:\n"); 103031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 103131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 103231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI regs:\n"); 103331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xc00, 0x3c); 103431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xd00, 0x34); 103531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xf00, 0x4); 103631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0x1d00, 0x6c); 103731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 1038d220c37e0a3c9a47ae00e87e044d963b3ea040bcDan Aloni hc_base = mv_hc_base(mmio_base, hc); 103931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("HC regs (HC %i):\n", hc); 104031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(hc_base, 0x1c); 104131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 104231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (p = start_port; p < start_port + num_ports; p++) { 104331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port_base = mv_port_base(mmio_base, p); 10442dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("EDMA regs (port %i):\n", p); 104531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base, 0x54); 10462dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("SATA regs (port %i):\n", p); 104731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base+0x300, 0x60); 104831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 104931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 105020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 105120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 105220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic unsigned int mv_scr_offset(unsigned int sc_reg_in) 105320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 105420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs; 105520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 105620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ switch (sc_reg_in) { 105720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_STATUS: 105820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_CONTROL: 105920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ERROR: 106020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); 106120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 106220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ACTIVE: 106320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_ACTIVE_OFS; /* active is not with the others */ 106420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 106520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ default: 106620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = 0xffffffffU; 106720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 106820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 106920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return ofs; 107020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 107120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1072da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 107320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 107420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 107520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1076da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 1077da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(mv_ap_base(ap) + ofs); 1078da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1079da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1080da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 108120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 108220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1083da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 108420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 108520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 108620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1087da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 108820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writelfl(val, mv_ap_base(ap) + ofs); 1089da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1090da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1091da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 109220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 109320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1094f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *adev) 1095f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord{ 1096f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord /* 1097e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Deal with Gen-II ("mv6") hardware quirks/restrictions: 1098e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * 1099e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Gen-II does not support NCQ over a port multiplier 1100e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * (no FIS-based switching). 1101e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * 1102f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord * We don't have hob_nsect when doing NCQ commands on Gen-II. 1103f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord * See mv_qc_prep() for more info. 1104f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord */ 1105e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (adev->flags & ATA_DFLAG_NCQ) { 1106352fab701ca4753dd005b67ce5e512be944eb591Mark Lord if (sata_pmp_attached(adev->link->ap)) { 1107e49856d82a887ce365637176f9f99ab68076eae8Mark Lord adev->flags &= ~ATA_DFLAG_NCQ; 1108352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ata_dev_printk(adev, KERN_INFO, 1109352fab701ca4753dd005b67ce5e512be944eb591Mark Lord "NCQ disabled for command-based switching\n"); 1110352fab701ca4753dd005b67ce5e512be944eb591Mark Lord } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) { 1111352fab701ca4753dd005b67ce5e512be944eb591Mark Lord adev->max_sectors = GEN_II_NCQ_MAX_SECTORS; 1112352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ata_dev_printk(adev, KERN_INFO, 1113352fab701ca4753dd005b67ce5e512be944eb591Mark Lord "max_sectors limited to %u for NCQ\n", 1114352fab701ca4753dd005b67ce5e512be944eb591Mark Lord adev->max_sectors); 1115352fab701ca4753dd005b67ce5e512be944eb591Mark Lord } 1116e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 1117f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1118f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 11193e4a139107e497a741c26f8a377a10f214d63ec1Mark Lordstatic int mv_qc_defer(struct ata_queued_cmd *qc) 11203e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord{ 11213e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct ata_link *link = qc->dev->link; 11223e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct ata_port *ap = link->ap; 11233e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct mv_port_priv *pp = ap->private_data; 11243e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 11253e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord /* 112629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * Don't allow new commands if we're in a delayed EH state 112729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * for NCQ and/or FIS-based switching. 112829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord */ 112929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 113029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord return ATA_DEFER_PORT; 113129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord /* 11323e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * If the port is completely idle, then allow the new qc. 11333e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord */ 11343e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (ap->nr_active_links == 0) 11353e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return 0; 11363e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 11373e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 11383e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord /* 11393e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * The port is operating in host queuing mode (EDMA). 11403e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * It can accomodate a new qc if the qc protocol 11413e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * is compatible with the current host queue mode. 11423e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord */ 11433e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { 11443e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord /* 11453e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * The host queue (EDMA) is in NCQ mode. 11463e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * If the new qc is also an NCQ command, 11473e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * then allow the new qc. 11483e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord */ 11493e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (qc->tf.protocol == ATA_PROT_NCQ) 11503e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return 0; 11513e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord } else { 11523e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord /* 11533e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * The host queue (EDMA) is in non-NCQ, DMA mode. 11543e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * If the new qc is also a non-NCQ, DMA command, 11553e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * then allow the new qc. 11563e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord */ 11573e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (qc->tf.protocol == ATA_PROT_DMA) 11583e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return 0; 11593e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord } 11603e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord } 11613e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return ATA_DEFER_PORT; 11623e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord} 11633e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 116400f42eabb204c68fa64ef72de834e74aca15c81fMark Lordstatic void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs) 1165e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 116600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord u32 new_fiscfg, old_fiscfg; 116700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord u32 new_ltmode, old_ltmode; 116800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord u32 new_haltcond, old_haltcond; 116900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 117000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord old_fiscfg = readl(port_mmio + FISCFG_OFS); 117100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord old_ltmode = readl(port_mmio + LTMODE_OFS); 117200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS); 117300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 117400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR); 117500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord new_ltmode = old_ltmode & ~LTMODE_BIT8; 117600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord new_haltcond = old_haltcond | EDMA_ERR_DEV; 117700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 117800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (want_fbs) { 117900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC; 118000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord new_ltmode = old_ltmode | LTMODE_BIT8; 11814c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (want_ncq) 11824c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord new_haltcond &= ~EDMA_ERR_DEV; 11834c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord else 11844c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord new_fiscfg |= FISCFG_WAIT_DEV_ERR; 1185e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 118600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 11878e7decdb8b132ee970a2636931b7653dec6af472Mark Lord if (new_fiscfg != old_fiscfg) 11888e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(new_fiscfg, port_mmio + FISCFG_OFS); 1189e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (new_ltmode != old_ltmode) 1190e49856d82a887ce365637176f9f99ab68076eae8Mark Lord writelfl(new_ltmode, port_mmio + LTMODE_OFS); 119100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (new_haltcond != old_haltcond) 119200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS); 1193f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1194f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 1195dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lordstatic void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq) 1196dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord{ 1197dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1198dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord u32 old, new; 1199dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord 1200dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord /* workaround for 88SX60x1 FEr SATA#25 (part 1) */ 1201dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS); 1202dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord if (want_ncq) 1203dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord new = old | (1 << 22); 1204dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord else 1205dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord new = old & ~(1 << 22); 1206dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord if (new != old) 1207dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS); 1208dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord} 1209dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord 1210e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq) 1211e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 12120c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 cfg; 1213e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_port_priv *pp = ap->private_data; 1214e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1215e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1216e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1217e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* set up non-NCQ EDMA configuration */ 12180c58912e192fc3a4835d772aafa40b72552b819fMark Lord cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 121900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord pp->pp_flags &= ~MV_PP_FLAG_FBS_EN; 1220e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 12210c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (IS_GEN_I(hpriv)) 1222e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 8); /* enab config burst size mask */ 1223e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1224dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord else if (IS_GEN_II(hpriv)) { 1225e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1226dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord mv_60x1_errata_sata25(ap, want_ncq); 1227e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1228dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord } else if (IS_GEN_IIE(hpriv)) { 122900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord int want_fbs = sata_pmp_attached(ap); 123000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord /* 123100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * Possible future enhancement: 123200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * 123300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * The chip can use FBS with non-NCQ, if we allow it, 123400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * But first we need to have the error handling in place 123500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * for this mode (datasheet section 7.3.15.4.2.3). 123600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * So disallow non-NCQ FBS for now. 123700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord */ 123800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord want_fbs &= want_ncq; 123900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 124000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord mv_config_fbs(port_mmio, want_ncq, want_fbs); 124100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 124200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (want_fbs) { 124300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord pp->pp_flags |= MV_PP_FLAG_FBS_EN; 124400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ 124500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord } 124600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 1247e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 1248e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 22); /* enab 4-entry host queue cache */ 12491f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (!IS_SOC(hpriv)) 1250616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord cfg |= (1 << 18); /* enab early completion */ 1251616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (hpriv->hp_flags & MV_HP_CUT_THROUGH) 1252616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ 1253e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 1254e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1255721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq) { 1256721091685f853ba4e6c49f26f989db0b1a811250Mark Lord cfg |= EDMA_CFG_NCQ; 1257721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 1258721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } else 1259721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN; 1260721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1261e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik writelfl(cfg, port_mmio + EDMA_CFG_OFS); 1262e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1263e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1264da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordstatic void mv_port_free_dma_mem(struct ata_port *ap) 1265da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord{ 1266da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1267da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_port_priv *pp = ap->private_data; 1268eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord int tag; 1269da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1270da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crqb) { 1271da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1272da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = NULL; 1273da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1274da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crpb) { 1275da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1276da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = NULL; 1277da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1278eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1279eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1280eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we have one unique sg_tbl per NCQ tag. 1281eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1282eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1283eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (pp->sg_tbl[tag]) { 1284eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) 1285eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_pool_free(hpriv->sg_tbl_pool, 1286eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag], 1287eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag]); 1288eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = NULL; 1289eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1290da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1291da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord} 1292da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 129305b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 129405b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_start - Port specific init/start routine. 129505b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 129605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 129705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Allocate and point to DMA memory, init port private memory, 129805b308e1df6d9d673daedb517969241f41278b52Brett Russ * zero indices. 129905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 130005b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 130105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 130205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 130331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap) 130431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1305cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct device *dev = ap->host->dev; 1306cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 130731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp; 1308dde2020754aeb14e17052d61784dcb37f252aac2James Bottomley int tag; 130931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 131024dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 13116037d6bbdff65eb5a84fe35e140f4da4f7cc103aJeff Garzik if (!pp) 131224dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return -ENOMEM; 1313da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord ap->private_data = pp; 131431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1315da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1316da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crqb) 1317da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 1318da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crqb, 0, MV_CRQB_Q_SZ); 131931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1320da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1321da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crpb) 1322da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord goto out_port_free_dma_mem; 1323da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crpb, 0, MV_CRPB_Q_SZ); 132431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 13253bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */ 13263bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) 13273bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord ap->flags |= ATA_FLAG_AN; 1328eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1329eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1330eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we need one unique sg_tbl per NCQ tag. 1331eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1332eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1333eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) { 1334eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1335eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1336eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (!pp->sg_tbl[tag]) 1337eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord goto out_port_free_dma_mem; 1338eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } else { 1339eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = pp->sg_tbl[0]; 1340eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1341eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1342eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 134331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 1344da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1345da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordout_port_free_dma_mem: 1346da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 1347da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 134831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 134931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 135005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 135105b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_stop - Port specific cleanup/stop routine. 135205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 135305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 135405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Stop DMA, cleanup port memory. 135505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 135605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 1357cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine uses the host lock to protect the DMA stop. 135805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 135931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap) 136031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1361e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma(ap); 136288e675e193159b9891c1c576de4348eaf490f5d0Mark Lord mv_enable_port_irqs(ap, 0); 1363da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 136431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 136531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 136605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 136705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 136805b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command whose SG list to source from 136905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 137005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Populate the SG list and mark the last entry. 137105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 137205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 137305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 137405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 13756c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzikstatic void mv_fill_sg(struct ata_queued_cmd *qc) 137631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 137731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = qc->ap->private_data; 1378972c26bdd6b58e7534473c4f7928584578cf43f4Jeff Garzik struct scatterlist *sg; 13793be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik struct mv_sg *mv_sg, *last_sg = NULL; 1380ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo unsigned int si; 138131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1382eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord mv_sg = pp->sg_tbl[qc->tag]; 1383ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 1384d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik dma_addr_t addr = sg_dma_address(sg); 1385d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik u32 sg_len = sg_dma_len(sg); 138622374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 13874007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson while (sg_len) { 13884007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 offset = addr & 0xffff; 13894007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 len = sg_len; 139022374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 13914007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson if ((offset + sg_len > 0x10000)) 13924007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson len = 0x10000 - offset; 13934007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 13944007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 13954007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 13966c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik mv_sg->flags_size = cpu_to_le32(len & 0xffff); 13974007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 13984007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson sg_len -= len; 13994007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson addr += len; 14004007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 14013be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg = mv_sg; 14024007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg++; 14034007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson } 140431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 14053be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik 14063be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik if (likely(last_sg)) 14073be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 140831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 140931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14105796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzikstatic void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 141131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1412559eedad7f7764dacca33980127b4615011230e4Mark Lord u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 141331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ (last ? CRQB_CMD_LAST : 0); 1414559eedad7f7764dacca33980127b4615011230e4Mark Lord *cmdw = cpu_to_le16(tmp); 141531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 141631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 141705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 141805b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_prep - Host specific command preparation. 141905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to prepare 142005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 142105b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 142205b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it handles prep of the CRQB 142305b308e1df6d9d673daedb517969241f41278b52Brett Russ * (command request block), does some sanity checking, and calls 142405b308e1df6d9d673daedb517969241f41278b52Brett Russ * the SG load routine. 142505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 142605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 142705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 142805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 142931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc) 143031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 143131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_port *ap = qc->ap; 143231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = ap->private_data; 1433e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 *cw; 143431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_taskfile *tf; 143531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u16 flags = 0; 1436a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 143731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1438138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1439138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 144031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 144120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 144231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Fill in command request block 144331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1444e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 144531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= CRQB_FLAG_READ; 1446beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 144731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= qc->tag << CRQB_TAG_SHIFT; 1448e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 144931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1450bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1451fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 1452a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1453a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr = 1454eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1455a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr_hi = 1456eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1457a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 145831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1459a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord cw = &pp->crqb[in_index].ata_cmd[0]; 146031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ tf = &qc->tf; 146131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 146231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Sadly, the CRQB cannot accomodate all registers--there are 146331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * only 11 bytes...so we must pick and choose required 146431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * registers based on the command. So, we drop feature and 146531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * hob_feature for [RW] DMA commands, but they are needed for 146631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * NCQ. NCQ will drop hob_nsect. 146720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 146831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ switch (tf->command) { 146931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ: 147031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ_EXT: 147131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE: 147231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE_EXT: 1473c15d85c8f3f73b5f20aae7928e25b6996f16b328Jens Axboe case ATA_CMD_WRITE_FUA_EXT: 147431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 147531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 147631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_READ: 147731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_WRITE: 14788b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 147931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 148031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 148131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ default: 148231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* The only other commands EDMA supports in non-queued and 148331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 148431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * of which are defined/used by Linux. If we get here, this 148531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * driver needs work. 148631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * 148731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * FIXME: modify libata to give qc_prep a return value and 148831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * return error here. 148931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 149031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ BUG_ON(tf->command); 149131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 149231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 149331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 149431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 149531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 149631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 149731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 149831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 149931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 150031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 150131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 150231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1503e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 1504e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1505e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik mv_fill_sg(qc); 1506e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1507e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1508e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik/** 1509e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * mv_qc_prep_iie - Host specific command preparation. 1510e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * @qc: queued command to prepare 1511e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1512e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * This routine simply redirects to the general purpose routine 1513e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * if command is not DMA. Else, it handles prep of the CRQB 1514e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * (command request block), does some sanity checking, and calls 1515e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * the SG load routine. 1516e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1517e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * LOCKING: 1518e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * Inherited from caller. 1519e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik */ 1520e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc) 1521e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 1522e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_port *ap = qc->ap; 1523e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_port_priv *pp = ap->private_data; 1524e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_crqb_iie *crqb; 1525e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_taskfile *tf; 1526a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 1527e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik u32 flags = 0; 1528e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1529138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1530138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 1531e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1532e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1533e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* Fill in Gen IIE command request block */ 1534e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 1535e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= CRQB_FLAG_READ; 1536e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1537beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 1538e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= qc->tag << CRQB_TAG_SHIFT; 15398c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord flags |= qc->tag << CRQB_HOSTQ_SHIFT; 1540e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 1541e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1542bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1543fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 1544a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1545a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 1546eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1547eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1548e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->flags = cpu_to_le32(flags); 1549e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1550e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik tf = &qc->tf; 1551e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[0] = cpu_to_le32( 1552e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->command << 16) | 1553e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->feature << 24) 1554e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1555e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[1] = cpu_to_le32( 1556e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbal << 0) | 1557e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbam << 8) | 1558e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbah << 16) | 1559e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->device << 24) 1560e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1561e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[2] = cpu_to_le32( 1562e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbal << 0) | 1563e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbam << 8) | 1564e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbah << 16) | 1565e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_feature << 24) 1566e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1567e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[3] = cpu_to_le32( 1568e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->nsect << 0) | 1569e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_nsect << 8) 1570e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1571e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1572e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 157331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 157431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_fill_sg(qc); 157531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 157631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 157705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 157805b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_issue - Initiate a command to the host 157905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to start 158005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 158105b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 158205b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it sanity checks our local 158305b308e1df6d9d673daedb517969241f41278b52Brett Russ * caches of the request producer/consumer indices then enables 158405b308e1df6d9d673daedb517969241f41278b52Brett Russ * DMA and bumps the request producer index. 158505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 158605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 158705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 158805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 15899a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 159031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1591c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct ata_port *ap = qc->ap; 1592c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 1593c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1594bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 in_index; 159531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1596138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1597138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) { 159817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord /* 159917c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord * We're about to send a non-EDMA capable command to the 160031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * port. Turn off EDMA so there won't be problems accessing 160131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * shadow block, etc registers. 160231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1603b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 160488e675e193159b9891c1c576de4348eaf490f5d0Mark Lord mv_enable_port_irqs(ap, ERR_IRQ); 1605e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(ap, qc->dev->link->pmp); 16069363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo return ata_sff_qc_issue(qc); 160731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 160831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1609721091685f853ba4e6c49f26f989db0b1a811250Mark Lord mv_start_dma(ap, port_mmio, pp, qc->tf.protocol); 1610bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1611fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; 1612fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 161331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 161431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* and write the request in pointer to kick the EDMA to life */ 1615bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 1616bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 161731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 161831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 161931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 162031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 16218f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lordstatic struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) 16228f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 16238f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct mv_port_priv *pp = ap->private_data; 16248f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc; 16258f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 16268f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 16278f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord return NULL; 16288f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord qc = ata_qc_from_tag(ap, ap->link.active_tag); 16298f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 16308f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord qc = NULL; 16318f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord return qc; 16328f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 16338f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 163429d187bb1e30682e228ce461c487d78d945c3e4fMark Lordstatic void mv_pmp_error_handler(struct ata_port *ap) 163529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord{ 163629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int pmp, pmp_map; 163729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord struct mv_port_priv *pp = ap->private_data; 163829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord 163929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { 164029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord /* 164129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * Perform NCQ error analysis on failed PMPs 164229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * before we freeze the port entirely. 164329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * 164429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * The failed PMPs are marked earlier by mv_pmp_eh_prep(). 164529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord */ 164629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pmp_map = pp->delayed_eh_pmp_map; 164729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; 164829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord for (pmp = 0; pmp_map != 0; pmp++) { 164929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int this_pmp = (1 << pmp); 165029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pmp_map & this_pmp) { 165129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord struct ata_link *link = &ap->pmp_link[pmp]; 165229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pmp_map &= ~this_pmp; 165329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord ata_eh_analyze_ncq_error(link); 165429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 165529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 165629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord ata_port_freeze(ap); 165729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 165829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord sata_pmp_error_handler(ap); 165929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord} 166029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord 16614c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic unsigned int mv_get_err_pmp_map(struct ata_port *ap) 16624c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 16634c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 16644c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 16654c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return readl(port_mmio + SATA_TESTCTL_OFS) >> 16; 16664c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 16674c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 16684c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map) 16694c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 16704c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct ata_eh_info *ehi; 16714c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int pmp; 16724c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 16734c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 16744c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Initialize EH info for PMPs which saw device errors 16754c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 16764c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi = &ap->link.eh_info; 16774c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord for (pmp = 0; pmp_map != 0; pmp++) { 16784c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int this_pmp = (1 << pmp); 16794c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pmp_map & this_pmp) { 16804c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct ata_link *link = &ap->pmp_link[pmp]; 16814c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 16824c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pmp_map &= ~this_pmp; 16834c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi = &link->eh_info; 16844c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_ehi_clear_desc(ehi); 16854c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_ehi_push_desc(ehi, "dev err"); 16864c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi->err_mask |= AC_ERR_DEV; 16874c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi->action |= ATA_EH_RESET; 16884c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_link_abort(link); 16894c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 16904c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 16914c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 16924c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 169306aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lordstatic int mv_req_q_empty(struct ata_port *ap) 169406aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord{ 169506aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 169606aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord u32 in_ptr, out_ptr; 169706aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord 169806aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS) 169906aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 170006aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) 170106aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 170206aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord return (in_ptr == out_ptr); /* 1 == queue_is_empty */ 170306aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord} 170406aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord 17054c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_fbs_ncq_dev_err(struct ata_port *ap) 17064c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 17074c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp = ap->private_data; 17084c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord int failed_links; 17094c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int old_map, new_map; 17104c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 17114c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 17124c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device error during FBS+NCQ operation: 17134c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 17144c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Set a port flag to prevent further I/O being enqueued. 17154c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Leave the EDMA running to drain outstanding commands from this port. 17164c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Perform the post-mortem/EH only when all responses are complete. 17174c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2). 17184c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 17194c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { 17204c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; 17214c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->delayed_eh_pmp_map = 0; 17224c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 17234c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord old_map = pp->delayed_eh_pmp_map; 17244c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord new_map = old_map | mv_get_err_pmp_map(ap); 17254c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 17264c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (old_map != new_map) { 17274c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->delayed_eh_pmp_map = new_map; 17284c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_pmp_eh_prep(ap, new_map & ~old_map); 17294c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 1730c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord failed_links = hweight16(new_map); 17314c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 17324c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x " 17334c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "failed_links=%d nr_active_links=%d\n", 17344c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, pp->delayed_eh_pmp_map, 17354c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ap->qc_active, failed_links, 17364c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ap->nr_active_links); 17374c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 173806aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { 17394c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_process_crpb_entries(ap, pp); 17404c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_stop_edma(ap); 17414c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_eh_freeze(ap); 17424c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__); 17434c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 1; /* handled */ 17444c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 17454c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__); 17464c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 1; /* handled */ 17474c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 17484c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 17494c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap) 17504c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 17514c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 17524c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Possible future enhancement: 17534c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 17544c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * FBS+non-NCQ operation is not yet implemented. 17554c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * See related notes in mv_edma_cfg(). 17564c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 17574c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device error during FBS+non-NCQ operation: 17584c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 17594c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * We need to snapshot the shadow registers for each failed command. 17604c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3). 17614c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 17624c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 17634c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 17644c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 17654c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause) 17664c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 17674c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp = ap->private_data; 17684c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 17694c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 17704c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* EDMA was not active: not handled */ 17714c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) 17724c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* FBS was not active: not handled */ 17734c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 17744c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(edma_err_cause & EDMA_ERR_DEV)) 17754c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* non DEV error: not handled */ 17764c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT; 17774c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS)) 17784c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* other problems: not handled */ 17794c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 17804c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { 17814c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 17824c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * EDMA should NOT have self-disabled for this case. 17834c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * If it did, then something is wrong elsewhere, 17844c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * and we cannot handle it here. 17854c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 17864c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & EDMA_ERR_SELF_DIS) { 17874c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_WARNING, 17884c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "%s: err_cause=0x%x pp_flags=0x%x\n", 17894c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, edma_err_cause, pp->pp_flags); 17904c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 17914c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 17924c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return mv_handle_fbs_ncq_dev_err(ap); 17934c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } else { 17944c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 17954c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * EDMA should have self-disabled for this case. 17964c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * If it did not, then something is wrong elsewhere, 17974c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * and we cannot handle it here. 17984c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 17994c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) { 18004c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_WARNING, 18014c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "%s: err_cause=0x%x pp_flags=0x%x\n", 18024c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, edma_err_cause, pp->pp_flags); 18034c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 18044c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 18054c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return mv_handle_fbs_non_ncq_dev_err(ap); 18064c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 18074c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 18084c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 18094c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 1810a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lordstatic void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled) 18118f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 18128f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_eh_info *ehi = &ap->link.eh_info; 1813a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord char *when = "idle"; 18148f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 18158f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_ehi_clear_desc(ehi); 1816a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (!ap || (ap->flags & ATA_FLAG_DISABLED)) { 1817a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "disabled"; 1818a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } else if (edma_was_enabled) { 1819a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "EDMA enabled"; 18208f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } else { 18218f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 18228f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 1823a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "polling"; 18248f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } 1825a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when); 18268f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->err_mask |= AC_ERR_OTHER; 18278f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->action |= ATA_EH_RESET; 18288f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_port_freeze(ap); 18298f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 18308f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 183105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 183205b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_err_intr - Handle error interrupts on the port 183305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 18348d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * @qc: affected command (non-NCQ), or NULL 183505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 18368d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Most cases require a full reset of the chip's state machine, 18378d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * which also performs a COMRESET. 18388d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Also, if the port disabled DMA, update our cached copy to match. 183905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 184005b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 184105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 184205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 184337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lordstatic void mv_err_intr(struct ata_port *ap) 184431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 184531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 1846bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 edma_err_cause, eh_freeze_mask, serr = 0; 1847e40060772d85f3534d3d517197696e24bb01f45bMark Lord u32 fis_cause = 0; 1848bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1849bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 1850bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int action = 0, err_mask = 0; 18519af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_eh_info *ehi = &ap->link.eh_info; 185237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord struct ata_queued_cmd *qc; 185337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord int abort = 0; 185420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 18558d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord /* 185637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Read and clear the SError and err_cause bits. 1857e40060772d85f3534d3d517197696e24bb01f45bMark Lord * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear 1858e40060772d85f3534d3d517197696e24bb01f45bMark Lord * the FIS_IRQ_CAUSE register before clearing edma_err_cause. 18598d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord */ 186037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord sata_scr_read(&ap->link, SCR_ERROR, &serr); 186137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 186237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord 1863bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 1864e40060772d85f3534d3d517197696e24bb01f45bMark Lord if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 1865e40060772d85f3534d3d517197696e24bb01f45bMark Lord fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 1866e40060772d85f3534d3d517197696e24bb01f45bMark Lord writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 1867e40060772d85f3534d3d517197696e24bb01f45bMark Lord } 18688d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 1869bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 18704c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & EDMA_ERR_DEV) { 18714c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 18724c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device errors during FIS-based switching operation 18734c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * require special handling. 18744c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 18754c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (mv_handle_dev_err(ap, edma_err_cause)) 18764c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return; 18774c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 18784c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 187937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord qc = mv_get_active_qc(ap); 188037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_clear_desc(ehi); 188137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x", 188237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord edma_err_cause, pp->pp_flags); 1883e40060772d85f3534d3d517197696e24bb01f45bMark Lord 1884c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 1885e40060772d85f3534d3d517197696e24bb01f45bMark Lord ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause); 1886c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord if (fis_cause & SATA_FIS_IRQ_AN) { 1887c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord u32 ec = edma_err_cause & 1888c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT); 1889c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord sata_async_notification(ap); 1890c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord if (!ec) 1891c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord return; /* Just an AN; no need for the nukes */ 1892c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord ata_ehi_push_desc(ehi, "SDB notify"); 1893c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord } 1894c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord } 1895bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 1896352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * All generations share these EDMA error cause bits: 1897bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 189837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (edma_err_cause & EDMA_ERR_DEV) { 1899bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_DEV; 190037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord action |= ATA_EH_RESET; 190137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_push_desc(ehi, "dev error"); 190237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 1903bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 19046c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 1905bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR)) { 1906bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_ATA_BUS; 1907cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1908b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "parity error"); 1909bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1910bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 1911bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_hotplugged(ehi); 1912bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 1913b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo "dev disconnect" : "dev connect"); 1914cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1915bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1916bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1917352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 1918352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Gen-I has a different SELF_DIS bit, 1919352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * different FREEZE bits, and no SERR bit: 1920352fab701ca4753dd005b67ce5e512be944eb591Mark Lord */ 1921ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) { 1922bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE_5; 1923bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 1924bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1925b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 1926bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1927bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 1928bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE; 1929bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS) { 1930bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1931b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 1932bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1933bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SERR) { 19348d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord ata_ehi_push_desc(ehi, "SError=%08x", serr); 19358d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord err_mask |= AC_ERR_ATA_BUS; 1936cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1937bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1938afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 193920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1940bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!err_mask) { 1941bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_OTHER; 1942cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1943bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1944bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1945bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->serror |= serr; 1946bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->action |= action; 1947bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1948bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 1949bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 1950bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1951bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 1952bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 195337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (err_mask == AC_ERR_DEV) { 195437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* 195537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Cannot do ata_port_freeze() here, 195637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * because it would kill PIO access, 195737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * which is needed for further diagnosis. 195837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord */ 195937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord mv_eh_freeze(ap); 196037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord abort = 1; 196137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } else if (edma_err_cause & eh_freeze_mask) { 196237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* 196337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Note to self: ata_port_freeze() calls ata_port_abort() 196437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord */ 1965bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 196637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } else { 196737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord abort = 1; 196837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 196937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord 197037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (abort) { 197137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (qc) 197237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_link_abort(qc->dev->link); 197337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord else 197437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_port_abort(ap); 197537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 1976bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1977bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1978fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_response(struct ata_port *ap, 1979fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response, unsigned int tag, int ncq_enabled) 1980fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord{ 1981fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag); 1982fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 1983fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (qc) { 1984fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 ata_status; 1985fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u16 edma_status = le16_to_cpu(response->flags); 1986fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 1987fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * edma_status from a response queue entry: 1988fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only). 1989fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * MSB is saved ATA status from command completion. 1990fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 1991fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (!ncq_enabled) { 1992fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; 1993fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (err_cause) { 1994fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 1995fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * Error will be seen/handled by mv_err_intr(). 1996fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * So do nothing at all here. 1997fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 1998fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord return; 1999fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2000fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2001fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; 200237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (!ac_err_mask(ata_status)) 200337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_qc_complete(qc); 200437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* else: leave it for mv_err_intr() */ 2005fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 2006fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n", 2007fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord __func__, tag); 2008fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2009fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord} 2010fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 2011fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) 2012bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2013bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 2014bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2015fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u32 in_index; 2016bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik bool work_done = false; 2017fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); 2018bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2019fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Get the hardware queue position index */ 2020bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) 2021bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2022bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2023fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Process new responses from since the last time we looked */ 2024fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord while (in_index != pp->resp_idx) { 20256c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik unsigned int tag; 2026fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response = &pp->crpb[pp->resp_idx]; 2027bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2028fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2029bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2030fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (IS_GEN_I(hpriv)) { 2031fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 50xx: no NCQ, only one command active at a time */ 20329af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo tag = ap->link.active_tag; 2033fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 2034fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Gen II/IIE: get command tag from CRPB entry */ 2035fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord tag = le16_to_cpu(response->id) & 0x1f; 2036bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2037fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord mv_process_crpb_response(ap, response, tag, ncq_enabled); 2038bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik work_done = true; 2039bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2040bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2041352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Update the software queue position index in hardware */ 2042bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (work_done) 2043bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 2044fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), 2045bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 204620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 204720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2048a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lordstatic void mv_port_intr(struct ata_port *ap, u32 port_cause) 2049a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord{ 2050a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord struct mv_port_priv *pp; 2051a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord int edma_was_enabled; 2052a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord 2053a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (!ap || (ap->flags & ATA_FLAG_DISABLED)) { 2054a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_unexpected_intr(ap, 0); 2055a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord return; 2056a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2057a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2058a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Grab a snapshot of the EDMA_EN flag setting, 2059a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * so that we have a consistent view for this port, 2060a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * even if something we call of our routines changes it. 2061a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2062a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord pp = ap->private_data; 2063a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); 2064a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2065a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Process completed CRPB response(s) before other events. 2066a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2067a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (edma_was_enabled && (port_cause & DONE_IRQ)) { 2068a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_process_crpb_entries(ap, pp); 20694c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 20704c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_handle_fbs_ncq_dev_err(ap); 2071a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2072a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2073a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Handle chip-reported errors, or continue on to handle PIO. 2074a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2075a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (unlikely(port_cause & ERR_IRQ)) { 2076a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_err_intr(ap); 2077a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } else if (!edma_was_enabled) { 2078a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord struct ata_queued_cmd *qc = mv_get_active_qc(ap); 2079a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (qc) 2080a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord ata_sff_host_intr(ap, qc); 2081a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord else 2082a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_unexpected_intr(ap, edma_was_enabled); 2083a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2084a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord} 2085a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord 208605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 208705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_host_intr - Handle all interrupts on the given host controller 2088cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * @host: host specific structure 20897368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * @main_irq_cause: Main interrupt cause register for the chip. 209005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 209105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 209205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 209305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 20947368f91926a2870a8c3f9546d86535ce71ae0757Mark Lordstatic int mv_host_intr(struct ata_host *host, u32 main_irq_cause) 209520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2096f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 2097eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord void __iomem *mmio = hpriv->base, *hc_mmio; 2098a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0, port; 209920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2100a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord for (port = 0; port < hpriv->n_ports; port++) { 2101cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_port *ap = host->ports[port]; 2102eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord unsigned int p, shift, hardport, port_cause; 2103eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord 2104a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2105a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord /* 2106eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * Each hc within the host has its own hc_irq_cause register, 2107eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * where the interrupting ports bits get ack'd. 2108a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord */ 2109eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (hardport == 0) { /* first port on this hc ? */ 2110eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND; 2111eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord u32 port_mask, ack_irqs; 2112eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord /* 2113eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * Skip this entire hc if nothing pending for any ports 2114eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord */ 2115eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (!hc_cause) { 2116eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord port += MV_PORTS_PER_HC - 1; 2117eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord continue; 2118eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord } 2119eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord /* 2120eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * We don't need/want to read the hc_irq_cause register, 2121eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * because doing so hurts performance, and 2122eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * main_irq_cause already gives us everything we need. 2123eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * 2124eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * But we do have to *write* to the hc_irq_cause to ack 2125eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * the ports that we are handling this time through. 2126eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * 2127eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * This requires that we create a bitmap for those 2128eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * ports which interrupted us, and use that bitmap 2129eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * to ack (only) those ports via hc_irq_cause. 2130eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord */ 2131eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord ack_irqs = 0; 2132eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord for (p = 0; p < MV_PORTS_PER_HC; ++p) { 2133eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if ((port + p) >= hpriv->n_ports) 2134eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord break; 2135eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2); 2136eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (hc_cause & port_mask) 2137eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord ack_irqs |= (DMA_IRQ | DEV_IRQ) << p; 2138eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord } 2139a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord hc_mmio = mv_hc_base_from_port(mmio, port); 2140eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS); 2141a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = 1; 2142a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord } 21438f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord /* 2144a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Handle interrupts signalled for this port: 21458f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord */ 2146a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ); 2147a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (port_cause) 2148a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_port_intr(ap, port_cause); 214920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 2150a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return handled; 215120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 215220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2153a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lordstatic int mv_pci_error(struct ata_host *host, void __iomem *mmio) 2154bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 215502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 2156bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_port *ap; 2157bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 2158bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_eh_info *ehi; 2159bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int i, err_mask, printed = 0; 2160bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 err_cause; 2161bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 216202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord err_cause = readl(mmio + hpriv->irq_cause_ofs); 2163bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2164bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", 2165bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_cause); 2166bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2167bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik DPRINTK("All regs @ PCI error\n"); 2168bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 2169bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 217002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord writelfl(0, mmio + hpriv->irq_cause_ofs); 2171bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2172bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik for (i = 0; i < host->n_ports; i++) { 2173bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ap = host->ports[i]; 2174936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo if (!ata_link_offline(&ap->link)) { 21759af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo ehi = &ap->link.eh_info; 2176bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 2177bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!printed++) 2178bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, 2179bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik "PCI err cause 0x%08x", err_cause); 2180bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_HOST_BUS; 2181cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo ehi->action = ATA_EH_RESET; 21829af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 2183bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 2184bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 2185bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 2186bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 2187bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2188bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 2189bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2190bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2191a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return 1; /* handled */ 2192bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2193bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 219405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2195c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * mv_interrupt - Main interrupt event handler 219605b308e1df6d9d673daedb517969241f41278b52Brett Russ * @irq: unused 219705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @dev_instance: private data; in this case the host structure 219805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 219905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read the read only register to determine if any host 220005b308e1df6d9d673daedb517969241f41278b52Brett Russ * controllers have pending interrupts. If so, call lower level 220105b308e1df6d9d673daedb517969241f41278b52Brett Russ * routine to handle. Also check for PCI errors which are only 220205b308e1df6d9d673daedb517969241f41278b52Brett Russ * reported here. 220305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 22048b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * LOCKING: 2205cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine holds the host lock while processing pending 220605b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts. 220705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 22087d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t mv_interrupt(int irq, void *dev_instance) 220920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2210cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = dev_instance; 2211f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 2212a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0; 221396e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord u32 main_irq_cause, pending_irqs; 221420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2215646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord spin_lock(&host->lock); 22167368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_cause = readl(hpriv->main_irq_cause_addr); 221796e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord pending_irqs = main_irq_cause & hpriv->main_irq_mask; 2218352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 2219352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Deal with cases where we either have nothing pending, or have read 2220352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * a bogus register value which can indicate HW removal or PCI fault. 222120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2222a44253d24a97ec3efe601267274a5fb64d8696c1Mark Lord if (pending_irqs && main_irq_cause != 0xffffffffU) { 22231f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv))) 2224a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = mv_pci_error(host, hpriv->base); 2225a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord else 2226a44253d24a97ec3efe601267274a5fb64d8696c1Mark Lord handled = mv_host_intr(host, pending_irqs); 2227bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2228cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik spin_unlock(&host->lock); 222920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return IRQ_RETVAL(handled); 223020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 223120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2232c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic unsigned int mv5_scr_offset(unsigned int sc_reg_in) 2233c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2234c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs; 2235c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2236c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik switch (sc_reg_in) { 2237c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_STATUS: 2238c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_ERROR: 2239c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_CONTROL: 2240c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = sc_reg_in * sizeof(u32); 2241c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 2242c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik default: 2243c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = 0xffffffffU; 2244c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 2245c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2246c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return ofs; 2247c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2248c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2249da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 2250c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2251f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 2252f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 22530d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 2254c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 2255c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2256da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 2257da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(addr + ofs); 2258da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 2259da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 2260da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 2261c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2262c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2263da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 2264c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2265f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 2266f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 22670d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 2268c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 2269c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2270da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 22710d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo writelfl(val, addr + ofs); 2272da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 2273da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 2274da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 2275c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2276c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 22777bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 2278522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 22797bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara struct pci_dev *pdev = to_pci_dev(host->dev); 2280522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik int early_5080; 2281522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 228244c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 2283522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2284522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik if (!early_5080) { 2285522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 2286522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= (1 << 0); 2287522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 2288522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik } 2289522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 22907bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara mv_reset_pci_bus(host, mmio); 2291522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 2292522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2293522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 2294522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 22958e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS); 2296522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 2297522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 229847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 2299ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 2300ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 2301c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 2302c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 2303c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2304c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 2305c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2306c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 2307c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 2308ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2309ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 231047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 2311ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 2312522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp; 2313522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 23148e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0, mmio + MV_GPIO_PORT_CTL_OFS); 2315522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2316522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 2317522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 2318522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 2319522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= ~(1 << 0); 2320522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 2321ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2322ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 23232a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 23242a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 2325bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 2326c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, port); 2327c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 2328c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 2329c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 2330c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2331c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik if (fix_apm_sq) { 23328e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(phy_mmio + MV5_LTMODE_OFS); 2333c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= (1 << 19); 23348e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, phy_mmio + MV5_LTMODE_OFS); 2335c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 23368e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(phy_mmio + MV5_PHY_CTL_OFS); 2337c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~0x3; 2338c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x1; 23398e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, phy_mmio + MV5_PHY_CTL_OFS); 2340c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2341c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2342c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 2343c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~mask; 2344c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].pre; 2345c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].amps; 2346c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_MODE); 2347bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2348bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2349c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2350c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 2351c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, port_mmio + (reg)) 2352c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 2353c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 2354c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2355c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2356c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2357e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 2358c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2359c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x028); /* command */ 2360c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(0x11f, port_mmio + EDMA_CFG_OFS); 2361c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x004); /* timer */ 2362c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x008); /* irq err cause */ 2363c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); /* irq err mask */ 2364c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); /* rq bah */ 2365c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); /* rq inp */ 2366c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); /* rq outp */ 2367c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x01c); /* respq bah */ 2368c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x024); /* respq outp */ 2369c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x020); /* respq inp */ 2370c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x02c); /* test control */ 23718e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS); 2372c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2373c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 2374c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2375c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, hc_mmio + (reg)) 2376c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2377c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc) 237847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik{ 2379c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 2380c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 2381c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2382c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); 2383c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); 2384c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); 2385c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); 2386c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2387c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(hc_mmio + 0x20); 2388c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= 0x1c1c1c1c; 2389c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x03030303; 2390c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, hc_mmio + 0x20); 2391c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2392c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 2393c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2394c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2395c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 2396c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2397c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc, port; 2398c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2399c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (hc = 0; hc < n_hc; hc++) { 2400c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (port = 0; port < MV_PORTS_PER_HC; port++) 2401c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_hc_port(hpriv, mmio, 2402c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (hc * MV_PORTS_PER_HC) + port); 2403c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2404c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_one_hc(hpriv, mmio, hc); 2405c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2406c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2407c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return 0; 240847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik} 240947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 2410101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 2411101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#define ZERO(reg) writel(0, mmio + (reg)) 24127bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 2413101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 241402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 2415101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 2416101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 24178e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(mmio + MV_PCI_MODE_OFS); 2418101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0xff00ffff; 24198e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, mmio + MV_PCI_MODE_OFS); 2420101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2421101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_DISC_TIMER); 2422101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_MSI_TRIGGER); 24238e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS); 2424101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_SERR_MASK); 242502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_cause_ofs); 242602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_mask_ofs); 2427101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_LOW_ADDRESS); 2428101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_HIGH_ADDRESS); 2429101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_ATTRIBUTE); 2430101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_COMMAND); 2431101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2432101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 2433101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2434101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 2435101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 2436101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 2437101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2438101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik mv5_reset_flash(hpriv, mmio); 2439101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 24408e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS); 2441101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0x3; 2442101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp |= (1 << 5) | (1 << 6); 24438e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS); 2444101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2445101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2446101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik/** 2447101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * mv6_reset_hc - Perform the 6xxx global soft reset 2448101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * @mmio: base address of the HBA 2449101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2450101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * This routine only applies to 6xxx parts. 2451101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2452101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * LOCKING: 2453101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * Inherited from caller. 2454101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2455c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2456c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 2457101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 2458101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; 2459101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik int i, rc = 0; 2460101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 t; 2461101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2462101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* Following procedure defined in PCI "main command and status 2463101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * register" table. 2464101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2465101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2466101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | STOP_PCI_MASTER, reg); 2467101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2468101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik for (i = 0; i < 1000; i++) { 2469101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2470101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 24712dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik if (PCI_MASTER_EMPTY & t) 2472101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik break; 2473101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2474101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(PCI_MASTER_EMPTY & t)) { 2475101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 2476101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2477101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2478101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2479101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2480101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* set reset */ 2481101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2482101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2483101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | GLOB_SFT_RST, reg); 2484101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2485101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2486101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 2487101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2488101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(GLOB_SFT_RST & t)) { 2489101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 2490101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2491101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2492101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2493101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2494101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 2495101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2496101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2497101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 2498101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2499101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2500101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while ((GLOB_SFT_RST & t) && (i-- > 0)); 2501101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2502101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (GLOB_SFT_RST & t) { 2503101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 2504101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2505101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2506101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikdone: 2507101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik return rc; 2508101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2509101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 251047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 2511ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 2512ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 2513ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *port_mmio; 2514ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik u32 tmp; 2515ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 25168e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(mmio + MV_RESET_CFG_OFS); 2517ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik if ((tmp & (1 << 0)) == 0) { 251847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->signal[idx].amps = 0x7 << 8; 2519ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = 0x1 << 5; 2520ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik return; 2521ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik } 2522ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2523ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik port_mmio = mv_port_base(mmio, idx); 2524ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(port_mmio + PHY_MODE2); 2525ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2526ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2527ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2528ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2529ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 253047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 2531ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 25328e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS); 2533ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2534ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2535c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 25362a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 2537bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 2538c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2539c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2540bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 254147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik int fix_phy_mode2 = 254247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 2543bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik int fix_phy_mode4 = 254447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 25458c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord u32 m2, m3; 254647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 254747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (fix_phy_mode2) { 254847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 254947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 255047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 |= (1 << 31); 255147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 255247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 255347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 255447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 255547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 255647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~((1 << 16) | (1 << 31)); 255747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 255847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 255947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 256047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 256147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 25628c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord /* 25638c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord * Gen-II/IIe PHY_MODE3 errata RM#2: 25648c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord * Achieves better receiver noise performance than the h/w default: 25658c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord */ 25668c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord m3 = readl(port_mmio + PHY_MODE3); 25678c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord m3 = (m3 & 0x1f) | (0x5555601 << 5); 2568bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 25690388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord /* Guideline 88F5182 (GL# SATA-S11) */ 25700388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord if (IS_SOC(hpriv)) 25710388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord m3 &= ~0x1c; 25720388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord 2573bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (fix_phy_mode4) { 2574ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord u32 m4 = readl(port_mmio + PHY_MODE4); 2575ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord /* 2576ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * Enforce reserved-bit restrictions on GenIIe devices only. 2577ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * For earlier chipsets, force only the internal config field 2578ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * (workaround for errata FEr SATA#10 part 1). 2579ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord */ 25808c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord if (IS_GEN_IIE(hpriv)) 2581ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES; 2582ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord else 2583ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE; 25848c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord writel(m4, port_mmio + PHY_MODE4); 2585bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2586b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord /* 2587b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * Workaround for 60x1-B2 errata SATA#13: 2588b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3, 2589b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * so we must always rewrite PHY_MODE3 after PHY_MODE4. 2590b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord */ 2591b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord writel(m3, port_mmio + PHY_MODE3); 2592bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2593bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik /* Revert values of pre-emphasis and signal amps to the saved ones */ 2594bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 2595bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2596bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 &= ~MV_M2_PREAMP_MASK; 25972a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].amps; 25982a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].pre; 259947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 2600bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2601e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* according to mvSata 3.6.1, some IIE values are fixed */ 2602e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (IS_GEN_IIE(hpriv)) { 2603e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 &= ~0xC30FF01F; 2604e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 |= 0x0000900F; 2605e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 2606e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2607bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 2608bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2609bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2610f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* TODO: use the generic LED interface to configure the SATA Presence */ 2611f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* & Acitivy LEDs on the board */ 2612f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 2613f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2614f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2615f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2616f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2617f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2618f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 2619f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2620f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2621f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio; 2622f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara u32 tmp; 2623f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2624f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara port_mmio = mv_port_base(mmio, idx); 2625f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(port_mmio + PHY_MODE2); 2626f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2627f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2628f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2629f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2630f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2631f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2632f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, port_mmio + (reg)) 2633f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 2634f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int port) 2635f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2636f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio = mv_port_base(mmio, port); 2637f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2638e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 2639f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2640f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x028); /* command */ 2641f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0x101f, port_mmio + EDMA_CFG_OFS); 2642f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x004); /* timer */ 2643f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x008); /* irq err cause */ 2644f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); /* irq err mask */ 2645f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); /* rq bah */ 2646f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); /* rq inp */ 2647f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x018); /* rq outp */ 2648f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x01c); /* respq bah */ 2649f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x024); /* respq outp */ 2650f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x020); /* respq inp */ 2651f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x02c); /* test control */ 26528e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS); 2653f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2654f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2655f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2656f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2657f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, hc_mmio + (reg)) 2658f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 2659f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2660f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2661f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *hc_mmio = mv_hc_base(mmio, 0); 2662f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2663f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); 2664f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); 2665f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); 2666f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2667f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2668f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2669f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2670f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2671f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 2672f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc) 2673f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2674f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int port; 2675f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2676f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara for (port = 0; port < hpriv->n_ports; port++) 2677f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_hc_port(hpriv, mmio, port); 2678f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2679f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_one_hc(hpriv, mmio); 2680f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2681f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 2682f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2683f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2684f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 2685f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2686f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2687f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2688f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2689f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2690f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 2691f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2692f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2693f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2694f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 26958e7decdb8b132ee970a2636931b7653dec6af472Mark Lordstatic void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) 2696b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord{ 26978e7decdb8b132ee970a2636931b7653dec6af472Mark Lord u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS); 2698b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 26998e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */ 2700b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (want_gen2i) 27018e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg |= (1 << 7); /* enable gen2i speed */ 27028e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS); 2703b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord} 2704b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 2705e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 2706c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no) 2707c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2708c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port_no); 2709c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 27108e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* 27118e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * The datasheet warns against setting EDMA_RESET when EDMA is active 27128e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * (but doesn't say what the problem might be). So we first try 27138e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * to disable the EDMA engine before doing the EDMA_RESET operation. 27148e7decdb8b132ee970a2636931b7653dec6af472Mark Lord */ 27150d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord mv_stop_edma_engine(port_mmio); 27168e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS); 2717c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2718b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (!IS_GEN_I(hpriv)) { 27198e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* Enable 3.0gb/s link speed: this survives EDMA_RESET */ 27208e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(port_mmio, 1); 2721c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2722b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord /* 27238e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * Strobing EDMA_RESET here causes a hard reset of the SATA transport, 2724b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * link, and physical layers. It resets all SATA interface registers 2725b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev. 2726c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik */ 27278e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS); 2728b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord udelay(25); /* allow reset propagation */ 2729c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writelfl(0, port_mmio + EDMA_CMD_OFS); 2730c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2731c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->ops->phy_errata(hpriv, mmio, port_no); 2732c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2733ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) 2734c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mdelay(1); 2735c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2736c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2737e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp) 273820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2739e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (sata_pmp_supported(ap)) { 2740e49856d82a887ce365637176f9f99ab68076eae8Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 2741e49856d82a887ce365637176f9f99ab68076eae8Mark Lord u32 reg = readl(port_mmio + SATA_IFCTL_OFS); 2742e49856d82a887ce365637176f9f99ab68076eae8Mark Lord int old = reg & 0xf; 274322374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 2744e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (old != pmp) { 2745e49856d82a887ce365637176f9f99ab68076eae8Mark Lord reg = (reg & ~0xf) | pmp; 2746e49856d82a887ce365637176f9f99ab68076eae8Mark Lord writelfl(reg, port_mmio + SATA_IFCTL_OFS); 2747e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 274822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik } 274920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 275020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2751e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 2752e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 275322374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik{ 2754e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 2755e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return sata_std_hardreset(link, class, deadline); 2756e49856d82a887ce365637176f9f99ab68076eae8Mark Lord} 2757bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2758e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 2759e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 2760e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 2761e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 2762e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return ata_sff_softreset(link, class, deadline); 276322374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik} 276422374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 2765cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 2766bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned long deadline) 276731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 2768cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo struct ata_port *ap = link->ap; 2769bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2770b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 2771f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 27720d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord int rc, attempts = 0, extra = 0; 27730d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord u32 sstatus; 27740d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord bool online; 277531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2776e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, ap->port_no); 2777b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2778bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 27790d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Workaround for errata FEr SATA#10 (part 2) */ 27800d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord do { 278117c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord const unsigned long *timing = 278217c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord sata_ehc_deb_timing(&link->eh_context); 2783bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 278417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord rc = sata_link_hardreset(link, timing, deadline + extra, 278517c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord &online, NULL); 27869dcffd99d0b1c0c1b8b2c0f85d240e791eca1055Mark Lord rc = online ? -EAGAIN : rc; 278717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord if (rc) 27880d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord return rc; 27890d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord sata_scr_read(link, SCR_STATUS, &sstatus); 27900d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 27910d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Force 1.5gb/s link speed and try again */ 27928e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(mv_ap_base(ap), 0); 27930d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (time_after(jiffies + HZ, deadline)) 27940d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord extra = HZ; /* only extend it once, max */ 27950d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } 27960d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); 2797bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 279817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord return rc; 2799bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2800bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2801bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap) 2802bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 28031cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord mv_stop_edma(ap); 2804c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_enable_port_irqs(ap, 0); 2805bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2806bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2807bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap) 2808bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2809f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 2810c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int port = ap->port_no; 2811c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int hardport = mv_hardport_from_port(port); 28121cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); 2813bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 2814c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 hc_irq_cause; 2815bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2816bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA errors on this port */ 2817bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2818bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2819bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear pending irq events */ 2820bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 28211cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport); 28221cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 2823bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 282488e675e193159b9891c1c576de4348eaf490f5d0Mark Lord mv_enable_port_irqs(ap, ERR_IRQ); 282531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 282631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 282705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 282805b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_init - Perform some early initialization on a single port. 282905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port: libata data structure storing shadow register addresses 283005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port_mmio: base address of the port 283105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 283205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Initialize shadow register mmio addresses, clear outstanding 283305b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts on the port, and unmask interrupts for the future 283405b308e1df6d9d673daedb517969241f41278b52Brett Russ * start of the port. 283505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 283605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 283705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 283805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 283931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 284020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 28410d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *shd_base = port_mmio + SHD_BLK_OFS; 284231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ unsigned serr_ofs; 284331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 28448b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik /* PIO related setup 284531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 284631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 28478b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->error_addr = 284831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 284931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 285031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 285131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 285231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 285331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 28548b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->status_addr = 285531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 285631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* special case: control/altstatus doesn't have ATA_REG_ address */ 285731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; 285831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 285931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* unused: */ 28608d9db2d2fbae9e05022825c32f86e00c8e342860Randy Dunlap port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; 286120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 286231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding port interrupt conditions */ 286331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ serr_ofs = mv_scr_offset(SCR_ERROR); 286431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); 286531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 286631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2867646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord /* unmask all non-transient EDMA error interrupts */ 2868646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS); 286920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 28708b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 287131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_CFG_OFS), 287231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), 287331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); 287420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 287520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2876616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic unsigned int mv_in_pcix_mode(struct ata_host *host) 2877616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 2878616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 2879616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 2880616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 2881616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 28821f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (IS_SOC(hpriv) || !IS_PCIE(hpriv)) 2883616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not PCI-X capable */ 2884616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord reg = readl(mmio + MV_PCI_MODE_OFS); 2885616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if ((reg & MV_PCI_MODE_MASK) == 0) 2886616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* conventional PCI mode */ 2887616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* chip is in PCI-X mode */ 2888616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 2889616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 2890616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic int mv_pci_cut_through_okay(struct ata_host *host) 2891616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 2892616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 2893616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 2894616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 2895616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 2896616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (!mv_in_pcix_mode(host)) { 2897616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord reg = readl(mmio + PCI_COMMAND_OFS); 2898616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (reg & PCI_COMMAND_MRDTRIG) 2899616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not okay */ 2900616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord } 2901616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* okay */ 2902616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 2903616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 29044447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_chip_id(struct ata_host *host, unsigned int board_idx) 2905bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 29064447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 29074447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 2908bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 2909bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 29105796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik switch (board_idx) { 291147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case chip_5080: 291247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 2913ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 291447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 291544c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 291647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x1: 291747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 291847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 291947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 292047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 292147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 292247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 292347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 292447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying 50XXB2 workarounds to unknown rev\n"); 292547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 292647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 292747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 292847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 292947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 2930bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_504x: 2931bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_508x: 293247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 2933ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 2934bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 293544c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 293647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x0: 293747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 293847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 293947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 294047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 294147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 294247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 294347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 294447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 294547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 294647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 2947bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2948bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2949bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2950bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_604x: 2951bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_608x: 295247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv6xxx_ops; 2953ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_II; 295447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 295544c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 295647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x7: 295747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 295847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 295947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x9: 296047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2961bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2962bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 2963bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 296447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 296547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 2966bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2967bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2968bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2969bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2970e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_7042: 2971616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH; 2972306b30f74d37f289033c696285e07ce0158a5d7bMark Lord if (pdev->vendor == PCI_VENDOR_ID_TTI && 2973306b30f74d37f289033c696285e07ce0158a5d7bMark Lord (pdev->device == 0x2300 || pdev->device == 0x2310)) 2974306b30f74d37f289033c696285e07ce0158a5d7bMark Lord { 29754e5200334e03e5620aa19d538300c13db270a063Mark Lord /* 29764e5200334e03e5620aa19d538300c13db270a063Mark Lord * Highpoint RocketRAID PCIe 23xx series cards: 29774e5200334e03e5620aa19d538300c13db270a063Mark Lord * 29784e5200334e03e5620aa19d538300c13db270a063Mark Lord * Unconfigured drives are treated as "Legacy" 29794e5200334e03e5620aa19d538300c13db270a063Mark Lord * by the BIOS, and it overwrites sector 8 with 29804e5200334e03e5620aa19d538300c13db270a063Mark Lord * a "Lgcy" metadata block prior to Linux boot. 29814e5200334e03e5620aa19d538300c13db270a063Mark Lord * 29824e5200334e03e5620aa19d538300c13db270a063Mark Lord * Configured drives (RAID or JBOD) leave sector 8 29834e5200334e03e5620aa19d538300c13db270a063Mark Lord * alone, but instead overwrite a high numbered 29844e5200334e03e5620aa19d538300c13db270a063Mark Lord * sector for the RAID metadata. This sector can 29854e5200334e03e5620aa19d538300c13db270a063Mark Lord * be determined exactly, by truncating the physical 29864e5200334e03e5620aa19d538300c13db270a063Mark Lord * drive capacity to a nice even GB value. 29874e5200334e03e5620aa19d538300c13db270a063Mark Lord * 29884e5200334e03e5620aa19d538300c13db270a063Mark Lord * RAID metadata is at: (dev->n_sectors & ~0xfffff) 29894e5200334e03e5620aa19d538300c13db270a063Mark Lord * 29904e5200334e03e5620aa19d538300c13db270a063Mark Lord * Warn the user, lest they think we're just buggy. 29914e5200334e03e5620aa19d538300c13db270a063Mark Lord */ 29924e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 29934e5200334e03e5620aa19d538300c13db270a063Mark Lord " BIOS CORRUPTS DATA on all attached drives," 29944e5200334e03e5620aa19d538300c13db270a063Mark Lord " regardless of if/how they are configured." 29954e5200334e03e5620aa19d538300c13db270a063Mark Lord " BEWARE!\n"); 29964e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": For data safety, do not" 29974e5200334e03e5620aa19d538300c13db270a063Mark Lord " use sectors 8-9 on \"Legacy\" drives," 29984e5200334e03e5620aa19d538300c13db270a063Mark Lord " and avoid the final two gigabytes on" 29994e5200334e03e5620aa19d538300c13db270a063Mark Lord " all RocketRAID BIOS initialized drives.\n"); 3000306b30f74d37f289033c696285e07ce0158a5d7bMark Lord } 30018e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* drop through */ 3002e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_6042: 3003e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hpriv->ops = &mv6xxx_ops; 3004e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_GEN_IIE; 3005616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (board_idx == chip_6042 && mv_pci_cut_through_okay(host)) 3006616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_CUT_THROUGH; 3007e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 300844c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 30095cf73bfb061552aa18d816d2859409be9ace5306Mark Lord case 0x2: /* Rev.B0: the first/only public release */ 3010e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3011e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3012e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik default: 3013e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 3014e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik "Applying 60X1C0 workarounds to unknown rev\n"); 3015e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3016e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3017e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 3018e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3019f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara case chip_soc: 3020f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->ops = &mv_soc_ops; 30211f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord hp_flags |= MV_HP_FLAG_SOC | MV_HP_ERRATA_60X1C0; 3022f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara break; 3023e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 3024bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 3025f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_ERR, host->dev, 30265796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik "BUG: invalid board index %u\n", board_idx); 3027bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 1; 3028bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3029bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3030bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik hpriv->hp_flags = hp_flags; 303102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord if (hp_flags & MV_HP_PCIE) { 303202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS; 303302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS; 303402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 303502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } else { 303602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS; 303702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS; 303802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 303902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } 3040bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3041bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 0; 3042bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 3043bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 304405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 304547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik * mv_init_host - Perform some early initialization of the host. 30464447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to initialize 30474447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @board_idx: controller index 304805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 304905b308e1df6d9d673daedb517969241f41278b52Brett Russ * If possible, do an early global reset of the host. Then do 305005b308e1df6d9d673daedb517969241f41278b52Brett Russ * our port init and clear/unmask all/relevant host interrupts. 305105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 305205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 305305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 305405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 30554447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_init_host(struct ata_host *host, unsigned int board_idx) 305620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 305720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ int rc = 0, n_hc, port, hc; 30584447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 3059f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 306047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 30614447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_chip_id(host, board_idx); 3062bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (rc) 3063352fab701ca4753dd005b67ce5e512be944eb591Mark Lord goto done; 3064f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 30651f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (IS_SOC(hpriv)) { 30667368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS; 30677368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS; 30681f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord } else { 30691f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS; 30701f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS; 3071f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 3072352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 3073352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* global interrupt mask: 0 == mask everything */ 3074c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_set_main_irq_mask(host, ~0, 0); 3075bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 30764447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_hc = mv_get_hc_count(host->ports[0]->flags); 3077bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 30784447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) 307947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->read_preamp(hpriv, port, mmio); 308020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3081c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 308247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (rc) 308320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ goto done; 308420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3085522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik hpriv->ops->reset_flash(hpriv, mmio); 30867bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara hpriv->ops->reset_bus(host, mmio); 308747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->enable_leds(hpriv, mmio); 308820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30894447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) { 3090cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo struct ata_port *ap = host->ports[port]; 30912a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 3092cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 3093cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo mv_port_init(&ap->ioaddr, port_mmio); 3094cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 30957bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 30961f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (!IS_SOC(hpriv)) { 3097f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int offset = port_mmio - mmio; 3098f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 3099f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 3100f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 31017bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 310220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 310320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 310420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hc; hc++) { 310531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 310631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 310731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 310831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ "(before clear)=0x%08x\n", hc, 310931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_CFG_OFS), 311031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_IRQ_CAUSE_OFS)); 311131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 311231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding hc interrupt conditions */ 311331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); 311420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 311520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 31161f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (!IS_SOC(hpriv)) { 3117f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* Clear any currently outstanding host interrupt conditions */ 3118f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(0, mmio + hpriv->irq_cause_ofs); 311931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3120f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* and unmask interrupt generation for host regs */ 3121f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs); 312251de32d200b21333950abc52ea1e589bc4eecef7Mark Lord 312351de32d200b21333950abc52ea1e589bc4eecef7Mark Lord /* 312451de32d200b21333950abc52ea1e589bc4eecef7Mark Lord * enable only global host interrupts for now. 312551de32d200b21333950abc52ea1e589bc4eecef7Mark Lord * The per-port interrupts get done later as ports are set up. 312651de32d200b21333950abc52ea1e589bc4eecef7Mark Lord */ 3127c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_set_main_irq_mask(host, 0, PCI_ERR); 3128f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 3129f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharadone: 3130f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3131f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3132fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik 3133fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradleystatic int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 3134fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley{ 3135fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 3136fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRQB_Q_SZ, 0); 3137fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crqb_pool) 3138fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3139fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3140fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 3141fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRPB_Q_SZ, 0); 3142fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crpb_pool) 3143fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3144fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3145fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 3146fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_SG_TBL_SZ, 0); 3147fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->sg_tbl_pool) 3148fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3149fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3150fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return 0; 3151fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley} 3152fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 315315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhekstatic void mv_conf_mbus_windows(struct mv_host_priv *hpriv, 315415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_target_info *dram) 315515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek{ 315615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek int i; 315715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 315815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < 4; i++) { 315915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_CTRL(i)); 316015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_BASE(i)); 316115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 316215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 316315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < dram->num_cs; i++) { 316415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_window *cs = dram->cs + i; 316515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 316615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(((cs->size - 1) & 0xffff0000) | 316715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (cs->mbus_attr << 8) | 316815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (dram->mbus_dram_target_id << 4) | 1, 316915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek hpriv->base + WINDOW_CTRL(i)); 317015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(cs->base, hpriv->base + WINDOW_BASE(i)); 317115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 317215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek} 317315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 3174f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/** 3175f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_probe - handle a positive probe of an soc Marvell 3176f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * host 3177f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device found 3178f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 3179f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * LOCKING: 3180f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Inherited from caller. 3181f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3182f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev) 3183f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3184f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara static int printed_version; 3185f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct mv_sata_platform_data *mv_platform_data; 3186f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct ata_port_info *ppi[] = 3187f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { &mv_port_info[chip_soc], NULL }; 3188f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host; 3189f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv; 3190f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct resource *res; 3191f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports, rc; 319220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3193f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!printed_version++) 3194f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 3195bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3196f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 3197f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Simple resource validation .. 3198f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3199f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (unlikely(pdev->num_resources != 2)) { 3200f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_err(&pdev->dev, "invalid number of resources\n"); 3201f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 3202f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 3203f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3204f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 3205f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Get the register base first 3206f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3207f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3208f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (res == NULL) 3209f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 3210f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3211f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* allocate host */ 3212f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_platform_data = pdev->dev.platform_data; 3213f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara n_ports = mv_platform_data->n_ports; 3214f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3215f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 3216f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 3217f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3218f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!host || !hpriv) 3219f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -ENOMEM; 3220f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->private_data = hpriv; 3221f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 3222f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3223f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->iomap = NULL; 3224f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara hpriv->base = devm_ioremap(&pdev->dev, res->start, 3225f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara res->end - res->start + 1); 3226f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base -= MV_SATAHC0_REG_BASE; 3227f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 322815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek /* 322915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek * (Re-)program MBUS remapping windows if we are asked to. 323015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek */ 323115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek if (mv_platform_data->dram != NULL) 323215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek mv_conf_mbus_windows(hpriv, mv_platform_data->dram); 323315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 3234fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley rc = mv_create_dma_pools(hpriv, &pdev->dev); 3235fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (rc) 3236fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return rc; 3237fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3238f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* initialize adapter */ 3239f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = mv_init_host(host, chip_soc); 3240f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc) 3241f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3242f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3243f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, 3244f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, 3245f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->n_ports); 3246f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3247f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, 3248f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara IRQF_SHARED, &mv6_sht); 3249f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3250f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3251f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* 3252f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 3253f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_remove - unplug a platform interface 3254f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device 3255f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 3256f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * A platform bus SATA device has been unplugged. Perform the needed 3257f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * cleanup. Also called on module unload for any active devices. 3258f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3259f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev) 3260f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3261f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct device *dev = &pdev->dev; 3262f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host = dev_get_drvdata(dev); 3263f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3264f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_host_detach(host); 3265f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 326620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 326720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3268f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic struct platform_driver mv_platform_driver = { 3269f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_platform_probe, 3270f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .remove = __devexit_p(mv_platform_remove), 3271f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .driver = { 3272f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .name = DRV_NAME, 3273f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .owner = THIS_MODULE, 3274f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 3275f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 3276f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3277f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 32787bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 3279f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 3280f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent); 3281f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 32827bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 32837bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic struct pci_driver mv_pci_driver = { 32847bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .name = DRV_NAME, 32857bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .id_table = mv_pci_tbl, 3286f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_pci_init_one, 32877bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .remove = ata_pci_remove_one, 32887bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara}; 32897bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 32907bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* 32917bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara * module options 32927bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara */ 32937bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int msi; /* Use PCI msi; either zero (off, default) or non-zero */ 32947bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 32957bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 32967bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* move to PCI layer or libata core? */ 32977bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int pci_go_64(struct pci_dev *pdev) 32987bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara{ 32997bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc; 33007bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 33017bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 33027bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 33037bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 33047bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 33057bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 33067bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 33077bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "64-bit DMA enable failed\n"); 33087bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 33097bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 33107bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 33117bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } else { 33127bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 33137bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 33147bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 33157bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit DMA enable failed\n"); 33167bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 33177bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 33187bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 33197bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 33207bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 33217bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit consistent DMA enable failed\n"); 33227bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 33237bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 33247bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 33257bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 33267bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 33277bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara} 33287bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 332905b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 333005b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_print_info - Dump key info to kernel log for perusal. 33314447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to print info about 333205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 333305b308e1df6d9d673daedb517969241f41278b52Brett Russ * FIXME: complete this. 333405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 333505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 333605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 333705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 33384447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic void mv_print_info(struct ata_host *host) 333931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 33404447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 33414447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 334244c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok u8 scc; 3343c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik const char *scc_s, *gen; 334431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 334531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Use this to determine the HW stepping of the chip so we know 334631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * what errata to workaround 334731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 334831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 334931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (scc == 0) 335031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "SCSI"; 335131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else if (scc == 0x01) 335231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "RAID"; 335331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else 3354c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik scc_s = "?"; 3355c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik 3356c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik if (IS_GEN_I(hpriv)) 3357c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "I"; 3358c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_II(hpriv)) 3359c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "II"; 3360c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_IIE(hpriv)) 3361c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "IIE"; 3362c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else 3363c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "?"; 336431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3365a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, 3366c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 3367c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 336831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 336931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 337031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 337105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 3372f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_pci_init_one - handle a positive probe of a PCI Marvell host 337305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pdev: PCI device found 337405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ent: PCI device ID entry for the matched host 337505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 337605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 337705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 337805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 3379f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 3380f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent) 338120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 33822dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik static int printed_version; 338320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int board_idx = (unsigned int)ent->driver_data; 33844447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 33854447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct ata_host *host; 33864447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv; 33874447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo int n_ports, rc; 338820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3389a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik if (!printed_version++) 3390a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 339120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 33924447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* allocate host */ 33934447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 33944447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 33954447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 33964447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 33974447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (!host || !hpriv) 33984447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return -ENOMEM; 33994447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->private_data = hpriv; 3400f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 34014447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 34024447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* acquire resources */ 340324dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo rc = pcim_enable_device(pdev); 340424dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 340520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return rc; 340620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 34070d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 34080d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc == -EBUSY) 340924dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pcim_pin_device(pdev); 34100d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc) 341124dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 34124447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->iomap = pcim_iomap_table(pdev); 3413f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base = host->iomap[MV_PRIMARY_BAR]; 341420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3415d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik rc = pci_go_64(pdev); 3416d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik if (rc) 3417d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik return rc; 3418d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik 3419da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord rc = mv_create_dma_pools(hpriv, &pdev->dev); 3420da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (rc) 3421da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return rc; 3422da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 342320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* initialize adapter */ 34244447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_init_host(host, board_idx); 342524dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 342624dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 342720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 342831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Enable interrupts */ 34296a59dcf8678cbc4106a8a6e158d7408a87691358Tejun Heo if (msi && pci_enable_msi(pdev)) 343031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_intx(pdev, 1); 343120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 343231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 34334447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo mv_print_info(host); 343420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 34354447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo pci_set_master(pdev); 3436ea8b4db97aa41a66c05daa4055a1974692ccd52dJeff Garzik pci_try_set_mwi(pdev); 34374447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 3438c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 343920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 34407bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 344120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3442f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev); 3443f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev); 3444f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 344520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic int __init mv_init(void) 344620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 34477bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc = -ENODEV; 34487bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 34497bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_register_driver(&mv_pci_driver); 3450f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 3451f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3452f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#endif 3453f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = platform_driver_register(&mv_platform_driver); 3454f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3455f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#ifdef CONFIG_PCI 3456f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 3457f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara pci_unregister_driver(&mv_pci_driver); 34587bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 34597bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 346020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 346120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 346220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic void __exit mv_exit(void) 346320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 34647bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 346520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ pci_unregister_driver(&mv_pci_driver); 34667bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 3467f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara platform_driver_unregister(&mv_platform_driver); 346820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 346920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 347020f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_AUTHOR("Brett Russ"); 347120f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 347220f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_LICENSE("GPL"); 347320f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DEVICE_TABLE(pci, mv_pci_tbl); 347420f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_VERSION(DRV_VERSION); 347517c5aab5b34e351531466e35b154ca86db7d46a9Mark LordMODULE_ALIAS("platform:" DRV_NAME); 347620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 34777bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 3478ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzikmodule_param(msi, int, 0444); 3479ddef9bb367b19383df627e388cb4c01c86ddba6cJeff GarzikMODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 34807bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 3481ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzik 348220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_init(mv_init); 348320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_exit(mv_exit); 3484