sata_mv.c revision 8930ff254a3a80d4477c3391ade07d6dd2a036c7
120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * sata_mv.c - Marvell SATA support 320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * Copyright 2008-2009: Marvell Corporation, all rights reserved. 58b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * Copyright 2005: EMC Corporation, all rights reserved. 6e2b1be56c5656902744c2b52e8304126a40bb609Jeff Garzik * Copyright 2005 Red Hat, Inc. All rights reserved. 720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 840f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * Originally written by Brett Russ. 940f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>. 1040f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * 1120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 1220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is free software; you can redistribute it and/or modify 1420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * it under the terms of the GNU General Public License as published by 1520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * the Free Software Foundation; version 2 of the License. 1620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is distributed in the hope that it will be useful, 1820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * but WITHOUT ANY WARRANTY; without even the implied warranty of 1920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 2020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * GNU General Public License for more details. 2120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * You should have received a copy of the GNU General Public License 2320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * along with this program; if not, write to the Free Software 2420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 2520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 284a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik/* 2985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * sata_mv TODO list: 3085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Develop a low-power-consumption strategy, and implement it. 3285afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 332b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds. 3485afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3585afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> [Experiment, Marvell value added] Is it possible to use target 3685afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * mode to cross-connect two Linux boxes with Marvell cards? If so, 3785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * creating LibATA target mode support would be very interesting. 3885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * Target mode, for those without docs, is the ability to directly 4085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * connect two SATA ports. 4185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord */ 424a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 4365ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord/* 4465ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * 80x1-B2 errata PCI#11: 4565ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * 4665ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * Users of the 6041/6081 Rev.B2 chips (current is C0) 4765ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * should be careful to insert those cards only onto PCI-X bus #0, 4865ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * and only in device slots 0..7, not higher. The chips may not 4965ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord * work correctly otherwise (note: this is a pretty rare condition). 5065ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord */ 5165ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord 5220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/kernel.h> 5320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/module.h> 5420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/pci.h> 5520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/init.h> 5620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/blkdev.h> 5720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/delay.h> 5820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/interrupt.h> 598d8b60046d6a2328ca4b9031b4948084f775f607Andrew Morton#include <linux/dmapool.h> 6020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/dma-mapping.h> 61a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik#include <linux/device.h> 62c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#include <linux/clk.h> 63f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/platform_device.h> 64f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/ata_platform.h> 6515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#include <linux/mbus.h> 66c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord#include <linux/bitops.h> 675a0e3ad6af8660be21ca98a971cd00f331318c05Tejun Heo#include <linux/gfp.h> 6820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <scsi/scsi_host.h> 69193515d51ccb363165d6b09e9ba5c21089e34badJeff Garzik#include <scsi/scsi_cmnd.h> 706c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik#include <scsi/scsi_device.h> 7120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/libata.h> 7220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#define DRV_NAME "sata_mv" 74cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord#define DRV_VERSION "1.28" 7520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7640f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord/* 7740f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * module options 7840f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord */ 7940f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord 8040f21b1124a9552bc093469280eb8239dc5f73d7Mark Lordstatic int msi; 8140f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord#ifdef CONFIG_PCI 8240f21b1124a9552bc093469280eb8239dc5f73d7Mark Lordmodule_param(msi, int, S_IRUGO); 8340f21b1124a9552bc093469280eb8239dc5f73d7Mark LordMODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 8440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord#endif 8540f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord 862b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic int irq_coalescing_io_count; 872b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordmodule_param(irq_coalescing_io_count, int, S_IRUGO); 882b748a0a344847fe6b924407bbe153e1878c9f09Mark LordMODULE_PARM_DESC(irq_coalescing_io_count, 892b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord "IRQ coalescing I/O count threshold (0..255)"); 902b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 912b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic int irq_coalescing_usecs; 922b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordmodule_param(irq_coalescing_usecs, int, S_IRUGO); 932b748a0a344847fe6b924407bbe153e1878c9f09Mark LordMODULE_PARM_DESC(irq_coalescing_usecs, 942b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord "IRQ coalescing time threshold in usecs"); 952b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 9620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russenum { 9720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* BAR's are enumerated in terms of pci_resource_start() terms */ 9820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 9920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IO_BAR = 2, /* offset 0x18: IO space */ 10020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 10120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 10220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 10320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 10420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1052b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */ 1062b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */ 1072b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */ 1082b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord MAX_COAL_IO_COUNT = 255, /* completed I/O count */ 1092b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 11020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_BASE = 0, 111615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 1122b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 1132b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Per-chip ("all ports") interrupt coalescing feature. 1142b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * This is only for GEN_II / GEN_IIE hardware. 1152b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * 1162b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Coalescing defers the interrupt until either the IO_THRESHOLD 1172b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. 1182b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 119cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord COAL_REG_BASE = 0x18000, 120cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08), 1212b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */ 1222b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 123cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc), 124cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0), 1252b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 1262b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 1272b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Registers for the (unused here) transaction coalescing feature: 1282b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 129cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88), 130cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c), 1312b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 132cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATAHC0_REG_BASE = 0x20000, 133cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord FLASH_CTL = 0x1046c, 134cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord GPIO_PORT_CTL = 0x104f0, 135cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord RESET_CFG = 0x180d8, 13620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 13720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 13820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 13920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 14020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 14120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 14231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH = 32, 14331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 14431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* CRQB needs alignment on a 1KB boundary. Size == 1KB 14631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * CRPB needs alignment on a 256B boundary. Size == 256B 14731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 14831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 14931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 15031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 151da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord MV_MAX_SG_CT = 256, 15231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 15331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 154352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ 15520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_HC_SHIFT = 2, 156352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ 157352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ 158352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ 15920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 16020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Host Flags */ 16120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 1627bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 163c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 16491b1a84c10869e2e46a576e5367de3166bff8eccMark Lord ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING, 165ad3aef51e17b9c6a90a9014805f1645e8e441c17Mark Lord 16691b1a84c10869e2e46a576e5367de3166bff8eccMark Lord MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI, 16720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 16840f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ | 16940f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA, 17091b1a84c10869e2e46a576e5367de3166bff8eccMark Lord 17191b1a84c10869e2e46a576e5367de3166bff8eccMark Lord MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN, 172ad3aef51e17b9c6a90a9014805f1645e8e441c17Mark Lord 17331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_FLAG_READ = (1 << 0), 17431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_TAG_SHIFT = 1, 175c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 176e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 177c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 17831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_ADDR_SHIFT = 8, 17931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_CS = (0x2 << 11), 18031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_LAST = (1 << 15), 18131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 18231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRPB_FLAG_STATUS_SHIFT = 8, 183c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 184c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 18531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 18631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EPRD_FLAG_END_OF_TBL = (1 << 31), 18731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 18820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* PCI interface registers */ 18920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 190cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_COMMAND = 0xc00, 191cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */ 192cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */ 19331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 194cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_MAIN_CMD_STS = 0xd30, 19520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ STOP_PCI_MASTER = (1 << 2), 19620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MASTER_EMPTY = (1 << 3), 19720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GLOB_SFT_RST = (1 << 4), 19820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 199cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_MODE = 0xd00, 2008e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_MODE_MASK = 0x30, 2018e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 202522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 203522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_DISC_TIMER = 0xd04, 204522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MSI_TRIGGER = 0xc38, 205522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_SERR_MASK = 0xc28, 206cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV_PCI_XBAR_TMOUT = 0x1d04, 207522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 208522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 209522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_ATTRIBUTE = 0x1d48, 210522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_COMMAND = 0x1d50, 211522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 212cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_IRQ_CAUSE = 0x1d58, 213cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_IRQ_MASK = 0x1d5c, 21420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 21520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 216cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCIE_IRQ_CAUSE = 0x1900, 217cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCIE_IRQ_MASK = 0x1910, 218646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 21902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 2207368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */ 221cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_HC_MAIN_IRQ_CAUSE = 0x1d60, 222cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PCI_HC_MAIN_IRQ_MASK = 0x1d64, 223cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SOC_HC_MAIN_IRQ_CAUSE = 0x20020, 224cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SOC_HC_MAIN_IRQ_MASK = 0x20024, 22540f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord ERR_IRQ = (1 << 0), /* shift by (2 * port #) */ 22640f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord DONE_IRQ = (1 << 1), /* shift by (2 * port #) */ 22720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 22820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 2292b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */ 2302b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */ 23120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_ERR = (1 << 18), 23240f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */ 23340f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */ 23440f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */ 23540f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */ 23640f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */ 23720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GPIO_INT = (1 << 22), 23820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SELF_INT = (1 << 23), 23920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TWSI_INT = (1 << 24), 24020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 241fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 242e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 24320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 24420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATAHC registers */ 245cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord HC_CFG = 0x00, 24620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 247cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord HC_IRQ_CAUSE = 0x14, 248352fab701ca4753dd005b67ce5e512be944eb591Mark Lord DMA_IRQ = (1 << 0), /* shift by port # */ 249352fab701ca4753dd005b67ce5e512be944eb591Mark Lord HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ 25020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ DEV_IRQ = (1 << 8), /* shift by port # */ 25120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2522b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 2532b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Per-HC (Host-Controller) interrupt coalescing feature. 2542b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * This is present on all chip generations. 2552b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * 2562b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Coalescing defers the interrupt until either the IO_THRESHOLD 2572b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. 2582b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 259cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord HC_IRQ_COAL_IO_THRESHOLD = 0x000c, 260cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord HC_IRQ_COAL_TIME_THRESHOLD = 0x0010, 2612b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 262cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SOC_LED_CTRL = 0x2c, 263000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */ 264000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */ 265000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord /* with dev activity LED */ 266000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 26720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Shadow block registers */ 268cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SHD_BLK = 0x100, 269cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */ 27020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 27120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATA registers */ 272cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_STATUS = 0x300, /* ctrl, err regs follow status */ 273cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_ACTIVE = 0x350, 274cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord FIS_IRQ_CAUSE = 0x364, 275cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */ 27617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 277cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord LTMODE = 0x30c, /* requires read-after-write */ 27817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 27917c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 280cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PHY_MODE2 = 0x330, 28147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik PHY_MODE3 = 0x310, 282cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord 283cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord PHY_MODE4 = 0x314, /* requires read-after-write */ 284ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */ 285ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */ 286ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */ 287ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */ 288ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord 289cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_IFCTL = 0x344, 290cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_TESTCTL = 0x348, 291cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_IFSTAT = 0x34c, 292cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord VENDOR_UNIQUE_FIS = 0x35c, 29317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 294cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord FISCFG = 0x360, 2958e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */ 2968e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 29717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 29829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr PHY_MODE9_GEN2 = 0x398, 29929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr PHY_MODE9_GEN1 = 0x39c, 30029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr PHYCFG_OFS = 0x3a0, /* only in 65n devices */ 30129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 302c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_MODE = 0x74, 303cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV5_LTMODE = 0x30, 304cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord MV5_PHY_CTL = 0x0C, 305cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord SATA_IFCFG = 0x050, 306bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 307bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_M2_PREAMP_MASK = 0x7e0, 30820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Port registers */ 310cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_CFG = 0, 3110c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 3120c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 3130c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 3140c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 3150c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 316e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 317e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 31820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 319cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_ERR_IRQ_CAUSE = 0x8, 320cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_ERR_IRQ_MASK = 0xc, 3216c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 3226c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 3236c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV = (1 << 2), /* device error */ 3246c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 3256c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 3266c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 327c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 328c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 3296c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 330c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 3316c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 3326c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 3336c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 3346c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 335646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3366c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 337646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 338646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 339646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 340646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 341646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3426c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 343646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3446c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 345646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 346646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 347646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 348646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 349646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 350646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3516c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 352646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 3536c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 354c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_OVERRUN_5 = (1 << 5), 355c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_UNDERRUN_5 = (1 << 6), 356646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 357646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 358646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 | 359646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 | 36085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord EDMA_ERR_LNK_CTRL_TX, 361646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 362bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 363bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 364bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 365bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 366bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SERR | 367bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS | 3686c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 369bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 370bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 371bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY | 372bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_CTRL_RX_2 | 373bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_RX | 374bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_TX | 375bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_TRANS_PROTO, 376e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 377bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 378bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 379bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 380bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 381bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_OVERRUN_5 | 382bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_UNDERRUN_5 | 383bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS_5 | 3846c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 385bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 386bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 387bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY, 38820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 389cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_REQ_Q_BASE_HI = 0x10, 390cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */ 39131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 392cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_REQ_Q_OUT_PTR = 0x18, 39331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_PTR_SHIFT = 5, 39431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 395cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_RSP_Q_BASE_HI = 0x1c, 396cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_RSP_Q_IN_PTR = 0x20, 397cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */ 39831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_PTR_SHIFT = 3, 39931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 400cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_CMD = 0x28, /* EDMA command register */ 4010ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_EN = (1 << 0), /* enable EDMA */ 4020ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 4038e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */ 4048e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 405cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_STATUS = 0x30, /* EDMA engine status */ 4068e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */ 4078e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */ 40820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 409cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_IORDY_TMOUT = 0x34, 410cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_ARB_CFG = 0x38, 4118e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 412cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */ 413cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */ 414da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 415cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord BMDMA_CMD = 0x224, /* bmdma command register */ 416cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord BMDMA_STATUS = 0x228, /* bmdma status register */ 417cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */ 418cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */ 419da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 42031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Host private flags (hp_flags) */ 42131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_HP_FLAG_MSI = (1 << 0), 42247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB0 = (1 << 1), 42347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB2 = (1 << 2), 42447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1B2 = (1 << 3), 42547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1C0 = (1 << 4), 4260ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 4270ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 4280ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 42902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 430616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ 4311f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */ 432000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */ 43320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 43431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Port private flags (pp_flags) */ 4350ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 436721091685f853ba4e6c49f26f989db0b1a811250Mark Lord MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 43700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */ 43829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */ 439d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */ 44020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 44120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 442ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 443ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 444e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 4458e7decdb8b132ee970a2636931b7653dec6af472Mark Lord#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) 4461f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC) 447bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 44815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 44915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_BASE(i) (0x20034 + ((i) << 4)) 45015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 451095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzikenum { 452baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik /* DMA boundary 0xffff is required by the s/g splitting 453baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik * we need on /length/ in mv_fill-sg(). 454baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik */ 455baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik MV_DMA_BOUNDARY = 0xffffU, 456095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 4570ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* mask of register bits containing lower 32 bits 4580ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik * of EDMA request queue DMA address 4590ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik */ 460095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 461095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 4620ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* ditto, for response queue */ 463095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 464095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik}; 465095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 466522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikenum chip_type { 467522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_504x, 468522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_508x, 469522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_5080, 470522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_604x, 471522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_608x, 472e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_6042, 473e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_7042, 474f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara chip_soc, 475522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik}; 476522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 47731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ReQuest Block: 32B */ 47831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crqb { 479e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr; 480e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr_hi; 481e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ctrl_flags; 482e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ata_cmd[11]; 48331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 48420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 485e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstruct mv_crqb_iie { 486e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 487e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 488e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags; 489e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 len; 490e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 ata_cmd[4]; 491e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 492e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 49331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ResPonse Block: 8B */ 49431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crpb { 495e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 id; 496e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 flags; 497e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 tmstmp; 49820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 49920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 50031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 50131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_sg { 502e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 503e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags_size; 504e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 505e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 reserved; 50631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 50720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 50808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord/* 50908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * We keep a local cache of a few frequently accessed port 51008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * registers here, to avoid having to read them (very slow) 51108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * when switching between EDMA and non-EDMA modes. 51208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord */ 51308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstruct mv_cached_regs { 51408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 fiscfg; 51508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 ltmode; 51608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 haltcond; 517c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord u32 unknown_rsvd; 51808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord}; 51908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 52031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_port_priv { 52131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crqb *crqb; 52231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crqb_dma; 52331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crpb *crpb; 52431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crpb_dma; 525eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 526eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 527bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 528bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int req_idx; 529bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int resp_idx; 530bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 53131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 pp_flags; 53208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord struct mv_cached_regs cached; 53329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int delayed_eh_pmp_map; 53431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 53531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 536bca1c4eb9411533d613123618c0d127fae532595Jeff Garzikstruct mv_port_signal { 537bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 amps; 538bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 pre; 539bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik}; 540bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 54102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lordstruct mv_host_priv { 54202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 hp_flags; 5431bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bishara unsigned int board_idx; 54496e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord u32 main_irq_mask; 54502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_port_signal signal[8]; 54602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord const struct mv_hw_ops *ops; 547f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports; 548f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *base; 5497368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_cause_addr; 5507368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_mask_addr; 551cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 irq_cause_offset; 552cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 irq_mask_offset; 55302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 unmask_all_irqs; 554c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara 555c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#if defined(CONFIG_HAVE_CLK) 556c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara struct clk *clk; 557c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#endif 558da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord /* 559da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * These consistent DMA memory pools give us guaranteed 560da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * alignment for hardware-accessed data structures, 561da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * and less memory waste in accomplishing the alignment. 562da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord */ 563da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crqb_pool; 564da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crpb_pool; 565da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *sg_tbl_pool; 56602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord}; 56702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 56847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstruct mv_hw_ops { 5692a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 5702a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 57147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 57247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 57347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 574c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 575c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 576522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 5777bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 57847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 57947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 58082ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 58182ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 58282ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 58382ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 58431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap); 58531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap); 5863e4a139107e497a741c26f8a377a10f214d63ec1Mark Lordstatic int mv_qc_defer(struct ata_queued_cmd *qc); 58731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc); 588e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc); 5899a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 590a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 591a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo unsigned long deadline); 592bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap); 593bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap); 594f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *dev); 59520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 5962a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5972a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 59847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 59947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 60047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 601c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 602c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 603522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 6047bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 60547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 6062a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 6072a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 60847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 60947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 61047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 611c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 612c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 613522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 614f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 615f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 616f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 617f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 618f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 619f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc); 620f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 621f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 622f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 62329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayrstatic void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, 62429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr void __iomem *mmio, unsigned int port); 6257bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 626e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 627c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no); 628e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap); 629b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio); 63000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma); 63147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 632e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp); 633e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 634e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 635e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 636e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 63729d187bb1e30682e228ce461c487d78d945c3e4fMark Lordstatic void mv_pmp_error_handler(struct ata_port *ap); 6384c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic void mv_process_crpb_entries(struct ata_port *ap, 6394c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp); 64047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 641da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_sff_irq_clear(struct ata_port *ap); 642da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic int mv_check_atapi_dma(struct ata_queued_cmd *qc); 643da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_setup(struct ata_queued_cmd *qc); 644da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_start(struct ata_queued_cmd *qc); 645da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_stop(struct ata_queued_cmd *qc); 646da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic u8 mv_bmdma_status(struct ata_port *ap); 647d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lordstatic u8 mv_sff_check_status(struct ata_port *ap); 648da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 649eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 650eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * because we have to allow room for worst case splitting of 651eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * PRDs for 64K boundaries in mv_fill_sg(). 652eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 653c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv5_sht = { 65468d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BASE_SHT(DRV_NAME), 655baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 656c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .dma_boundary = MV_DMA_BOUNDARY, 657c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik}; 658c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 659c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv6_sht = { 66068d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_NCQ_SHT(DRV_NAME), 661138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .can_queue = MV_MAX_Q_DEPTH - 1, 662baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 66320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .dma_boundary = MV_DMA_BOUNDARY, 66420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 66520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 666029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv5_ops = { 667029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &ata_sff_port_ops, 668c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 669c96f1732e25362d10ee7bcac1df8412a2e6b7d23Alan Cox .lost_interrupt = ATA_OP_NULL, 670c96f1732e25362d10ee7bcac1df8412a2e6b7d23Alan Cox 6713e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord .qc_defer = mv_qc_defer, 672c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_prep = mv_qc_prep, 673c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_issue = mv_qc_issue, 674c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 675bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .freeze = mv_eh_freeze, 676bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .thaw = mv_eh_thaw, 677a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .hardreset = mv_hardreset, 678a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .error_handler = ata_std_error_handler, /* avoid SFF EH */ 679029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .post_internal_cmd = ATA_OP_NULL, 680bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 681c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_read = mv5_scr_read, 682c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_write = mv5_scr_write, 683c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 684c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_start = mv_port_start, 685c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_stop = mv_port_stop, 686c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik}; 687c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 688029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv6_ops = { 6898930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .inherits = &ata_bmdma_port_ops, 6908930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo 6918930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .lost_interrupt = ATA_OP_NULL, 6928930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo 6938930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .qc_defer = mv_qc_defer, 6948930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .qc_prep = mv_qc_prep, 6958930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .qc_issue = mv_qc_issue, 6968930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo 697f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord .dev_config = mv6_dev_config, 69820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 6998930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .freeze = mv_eh_freeze, 7008930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .thaw = mv_eh_thaw, 7018930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .hardreset = mv_hardreset, 7028930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .softreset = mv_softreset, 703e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_hardreset = mv_pmp_hardreset, 704e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_softreset = mv_softreset, 70529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord .error_handler = mv_pmp_error_handler, 706da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 7078930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .scr_read = mv_scr_read, 7088930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .scr_write = mv_scr_write, 7098930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo 71040f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord .sff_check_status = mv_sff_check_status, 711da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .sff_irq_clear = mv_sff_irq_clear, 712da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .check_atapi_dma = mv_check_atapi_dma, 713da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_setup = mv_bmdma_setup, 714da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_start = mv_bmdma_start, 715da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_stop = mv_bmdma_stop, 716da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord .bmdma_status = mv_bmdma_status, 7178930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo 7188930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .port_start = mv_port_start, 7198930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .port_stop = mv_port_stop, 7208930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo 7218930ff254a3a80d4477c3391ade07d6dd2a036c7Tejun Heo .mode_filter = ATA_OP_NULL, /* will be removed soon */ 72220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 72320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 724029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv_iie_ops = { 725029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv6_ops, 726029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .dev_config = ATA_OP_NULL, 727e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .qc_prep = mv_qc_prep_iie, 728e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 729e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 73098ac62defe529d04a192688f40d801a2d8fbcf98Arjan van de Venstatic const struct ata_port_info mv_port_info[] = { 73120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_504x */ 73291b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_I_FLAGS, 733c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 734bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 735c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 73620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 73720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_508x */ 73891b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 739c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 740bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 741c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 74220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 74347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik { /* chip_5080 */ 74491b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 745c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 746bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 747c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 74847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik }, 74920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_604x */ 75091b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_II_FLAGS, 751c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 752bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 753c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 75420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 75520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_608x */ 75691b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC, 757c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 758bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 759c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 76020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 761e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_6042 */ 76291b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_IIE_FLAGS, 763c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 764bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 765e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 766e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 767e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_7042 */ 76891b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_IIE_FLAGS, 769c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 770bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 771e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 772e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 773f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { /* chip_soc */ 77491b1a84c10869e2e46a576e5367de3166bff8eccMark Lord .flags = MV_GEN_IIE_FLAGS, 775c361acbc59c434315f8649ab06e5b7d5b297d1b7Mark Lord .pio_mask = ATA_PIO4, 77617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .udma_mask = ATA_UDMA6, 77717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .port_ops = &mv_iie_ops, 778f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 77920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 78020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7813b7d697dfb7d03edb87e50b743a7ecff029618e9Jeff Garzikstatic const struct pci_device_id mv_pci_tbl[] = { 7822d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 7832d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 7842d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 7852d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 78646c5784c8fa736c2bb42fe681189b86e99abdc2eMark Lord /* RocketRAID 1720/174x have different identifiers */ 78746c5784c8fa736c2bb42fe681189b86e99abdc2eMark Lord { PCI_VDEVICE(TTI, 0x1720), chip_6042 }, 7884462254ac6be9150aae87d54d388fc348d6fceadMark Lord { PCI_VDEVICE(TTI, 0x1740), chip_6042 }, 7894462254ac6be9150aae87d54d388fc348d6fceadMark Lord { PCI_VDEVICE(TTI, 0x1742), chip_6042 }, 7902d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 7912d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 7922d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 7932d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 7942d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 7952d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 7962d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 7972d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 7982d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 799d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger /* Adaptec 1430SA */ 800d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 801d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger 80202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Marvell 7042 support */ 8036a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 8046a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom 80502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Highpoint RocketRAID PCIe series */ 80602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 80702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 80802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 8092d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { } /* terminate list */ 81020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 81120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 81247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv5xxx_ops = { 81347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv5_phy_errata, 81447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv5_enable_leds, 81547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv5_read_preamp, 81647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv5_reset_hc, 817522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv5_reset_flash, 818522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv5_reset_bus, 81947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 82047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 82147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv6xxx_ops = { 82247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv6_phy_errata, 82347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv6_enable_leds, 82447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv6_read_preamp, 82547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv6_reset_hc, 826522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv6_reset_flash, 827522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv_reset_pci_bus, 82847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 82947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 830f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic const struct mv_hw_ops mv_soc_ops = { 831f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .phy_errata = mv6_phy_errata, 832f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .enable_leds = mv_soc_enable_leds, 833f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .read_preamp = mv_soc_read_preamp, 834f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_hc = mv_soc_reset_hc, 835f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_flash = mv_soc_reset_flash, 836f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_bus = mv_soc_reset_bus, 837f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 838f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 83929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayrstatic const struct mv_hw_ops mv_soc_65n_ops = { 84029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr .phy_errata = mv_soc_65n_phy_errata, 84129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr .enable_leds = mv_soc_enable_leds, 84229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr .reset_hc = mv_soc_reset_hc, 84329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr .reset_flash = mv_soc_reset_flash, 84429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr .reset_bus = mv_soc_reset_bus, 84529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr}; 84629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 84720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 84820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Functions 84920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 85020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 85120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void writelfl(unsigned long data, void __iomem *addr) 85220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 85320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writel(data, addr); 85420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ (void) readl(addr); /* flush to avoid PCI posted write */ 85520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 85620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 857c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hc_from_port(unsigned int port) 858c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 859c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port >> MV_PORT_HC_SHIFT; 860c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 861c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 862c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hardport_from_port(unsigned int port) 863c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 864c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port & MV_PORT_MASK; 865c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 866c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 8671cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord/* 8681cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Consolidate some rather tricky bit shift calculations. 8691cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * This is hot-path stuff, so not a function. 8701cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Simple code, with two return values, so macro rather than inline. 8711cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 8721cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * port is the sole input, in range 0..7. 8737368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * shift is one output, for use with main_irq_cause / main_irq_mask registers. 8747368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * hardport is the other output, in range 0..3. 8751cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 8761cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Note that port and hardport may be the same variable in some cases. 8771cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord */ 8781cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ 8791cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord{ \ 8801cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift = mv_hc_from_port(port) * HC_SHIFT; \ 8811cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord hardport = mv_hardport_from_port(port); \ 8821cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift += hardport * 2; \ 8831cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord} 8841cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord 885352fab701ca4753dd005b67ce5e512be944eb591Mark Lordstatic inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 886352fab701ca4753dd005b67ce5e512be944eb591Mark Lord{ 887cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 888352fab701ca4753dd005b67ce5e512be944eb591Mark Lord} 889352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 890c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline void __iomem *mv_hc_base_from_port(void __iomem *base, 891c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 892c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 893c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base(base, mv_hc_from_port(port)); 894c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 895c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 89620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 89720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 898c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base_from_port(base, port) + 8998b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik MV_SATAHC_ARBTR_REG_SZ + 900c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 90120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 90220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 903e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 904e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord{ 905e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 906e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 907e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 908e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord return hc_mmio + ofs; 909e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord} 910e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 911f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic inline void __iomem *mv_host_base(struct ata_host *host) 912f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 913f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 914f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return hpriv->base; 915f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 916f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 91720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_ap_base(struct ata_port *ap) 91820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 919f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return mv_port_base(mv_host_base(ap->host), ap->port_no); 92020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 92120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 922cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic inline int mv_get_hc_count(unsigned long port_flags) 92331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 924cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 92531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 92631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 92708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord/** 92808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * mv_save_cached_regs - (re-)initialize cached port registers 92908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @ap: the port whose registers we are caching 93008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * 93108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * Initialize the local cache of port registers, 93208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * so that reading them over and over again can 93308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * be avoided on the hotter paths of this driver. 93408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * This saves a few microseconds each time we switch 93508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * to/from EDMA mode to perform (eg.) a drive cache flush. 93608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord */ 93708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstatic void mv_save_cached_regs(struct ata_port *ap) 93808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord{ 93908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 94008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord struct mv_port_priv *pp = ap->private_data; 94108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 942cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord pp->cached.fiscfg = readl(port_mmio + FISCFG); 943cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord pp->cached.ltmode = readl(port_mmio + LTMODE); 944cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND); 945cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD); 94608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord} 94708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 94808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord/** 94908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * mv_write_cached_reg - write to a cached port register 95008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @addr: hardware address of the register 95108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @old: pointer to cached value of the register 95208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * @new: new value for the register 95308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * 95408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * Write a new value to a cached register, 95508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord * but only if the value is different from before. 95608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord */ 95708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstatic inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new) 95808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord{ 95908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord if (new != *old) { 96012f3b6d7551306c00cf834540a33184de67c9187Mark Lord unsigned long laddr; 96108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord *old = new; 96212f3b6d7551306c00cf834540a33184de67c9187Mark Lord /* 96312f3b6d7551306c00cf834540a33184de67c9187Mark Lord * Workaround for 88SX60x1-B2 FEr SATA#13: 96412f3b6d7551306c00cf834540a33184de67c9187Mark Lord * Read-after-write is needed to prevent generating 64-bit 96512f3b6d7551306c00cf834540a33184de67c9187Mark Lord * write cycles on the PCI bus for SATA interface registers 96612f3b6d7551306c00cf834540a33184de67c9187Mark Lord * at offsets ending in 0x4 or 0xc. 96712f3b6d7551306c00cf834540a33184de67c9187Mark Lord * 96812f3b6d7551306c00cf834540a33184de67c9187Mark Lord * Looks like a lot of fuss, but it avoids an unnecessary 96912f3b6d7551306c00cf834540a33184de67c9187Mark Lord * +1 usec read-after-write delay for unaffected registers. 97012f3b6d7551306c00cf834540a33184de67c9187Mark Lord */ 97112f3b6d7551306c00cf834540a33184de67c9187Mark Lord laddr = (long)addr & 0xffff; 97212f3b6d7551306c00cf834540a33184de67c9187Mark Lord if (laddr >= 0x300 && laddr <= 0x33c) { 97312f3b6d7551306c00cf834540a33184de67c9187Mark Lord laddr &= 0x000f; 97412f3b6d7551306c00cf834540a33184de67c9187Mark Lord if (laddr == 0x4 || laddr == 0xc) { 97512f3b6d7551306c00cf834540a33184de67c9187Mark Lord writelfl(new, addr); /* read after write */ 97612f3b6d7551306c00cf834540a33184de67c9187Mark Lord return; 97712f3b6d7551306c00cf834540a33184de67c9187Mark Lord } 97812f3b6d7551306c00cf834540a33184de67c9187Mark Lord } 97912f3b6d7551306c00cf834540a33184de67c9187Mark Lord writel(new, addr); /* unaffected by the errata */ 98008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord } 98108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord} 98208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord 983c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic void mv_set_edma_ptrs(void __iomem *port_mmio, 984c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_host_priv *hpriv, 985c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp) 986c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik{ 987bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 index; 988bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 989c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 990c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize request queue 991c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 992fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 993fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 994bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 995c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crqb_dma & 0x3ff); 996cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI); 997bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 998cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + EDMA_REQ_Q_IN_PTR); 999cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR); 1000c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 1001c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 1002c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize response queue 1003c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 1004fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 1005fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; 1006bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1007c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crpb_dma & 0xff); 1008cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI); 1009cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR); 1010bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 1011cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + EDMA_RSP_Q_OUT_PTR); 1012c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik} 1013c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 10142b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv) 10152b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord{ 10162b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 10172b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * When writing to the main_irq_mask in hardware, 10182b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * we must ensure exclusivity between the interrupt coalescing bits 10192b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * and the corresponding individual port DONE_IRQ bits. 10202b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * 10212b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * Note that this register is really an "IRQ enable" register, 10222b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * not an "IRQ mask" register as Marvell's naming might suggest. 10232b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 10242b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE)) 10252b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mask &= ~DONE_IRQ_0_3; 10262b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE)) 10272b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mask &= ~DONE_IRQ_4_7; 10282b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord writelfl(mask, hpriv->main_irq_mask_addr); 10292b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord} 10302b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 1031c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lordstatic void mv_set_main_irq_mask(struct ata_host *host, 1032c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 disable_bits, u32 enable_bits) 1033c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord{ 1034c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord struct mv_host_priv *hpriv = host->private_data; 1035c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 old_mask, new_mask; 1036c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 103796e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord old_mask = hpriv->main_irq_mask; 1038c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord new_mask = (old_mask & ~disable_bits) | enable_bits; 103996e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord if (new_mask != old_mask) { 104096e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord hpriv->main_irq_mask = new_mask; 10412b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_write_main_irq_mask(new_mask, hpriv); 104296e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord } 1043c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord} 1044c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 1045c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lordstatic void mv_enable_port_irqs(struct ata_port *ap, 1046c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int port_bits) 1047c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord{ 1048c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int shift, hardport, port = ap->port_no; 1049c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 disable_bits, enable_bits; 1050c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 1051c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 1052c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 1053c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord disable_bits = (DONE_IRQ | ERR_IRQ) << shift; 1054c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord enable_bits = port_bits << shift; 1055c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); 1056c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord} 1057c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord 105800b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_clear_and_enable_port_irqs(struct ata_port *ap, 105900b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord void __iomem *port_mmio, 106000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord unsigned int port_irqs) 106100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord{ 106200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 106300b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord int hardport = mv_hardport_from_port(ap->port_no); 106400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port( 106500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_host_base(ap->host), ap->port_no); 106600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord u32 hc_irq_cause; 106700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 106800b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord /* clear EDMA event indicators, if any */ 1069cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 107000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 107100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord /* clear pending irq events */ 107200b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 1073cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); 107400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 107500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord /* clear FIS IRQ Cause */ 107600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord if (IS_GEN_IIE(hpriv)) 1077cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, port_mmio + FIS_IRQ_CAUSE); 107800b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 107900b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_enable_port_irqs(ap, port_irqs); 108000b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord} 108100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord 10822b748a0a344847fe6b924407bbe153e1878c9f09Mark Lordstatic void mv_set_irq_coalescing(struct ata_host *host, 10832b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord unsigned int count, unsigned int usecs) 10842b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord{ 10852b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord struct mv_host_priv *hpriv = host->private_data; 10862b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord void __iomem *mmio = hpriv->base, *hc_mmio; 10872b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord u32 coal_enable = 0; 10882b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord unsigned long flags; 10896abf4678261218938ccdac90767d34ce9937634fMark Lord unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC; 10902b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 10912b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord ALL_PORTS_COAL_DONE; 10922b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 10932b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* Disable IRQ coalescing if either threshold is zero */ 10942b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (!usecs || !count) { 10952b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord clks = count = 0; 10962b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } else { 10972b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* Respect maximum limits of the hardware */ 10982b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord clks = usecs * COAL_CLOCKS_PER_USEC; 10992b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (clks > MAX_COAL_TIME_THRESHOLD) 11002b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord clks = MAX_COAL_TIME_THRESHOLD; 11012b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (count > MAX_COAL_IO_COUNT) 11022b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord count = MAX_COAL_IO_COUNT; 11032b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } 11042b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 11052b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord spin_lock_irqsave(&host->lock, flags); 11066abf4678261218938ccdac90767d34ce9937634fMark Lord mv_set_main_irq_mask(host, coal_disable, 0); 11072b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 11086abf4678261218938ccdac90767d34ce9937634fMark Lord if (is_dual_hc && !IS_GEN_I(hpriv)) { 11092b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 11106abf4678261218938ccdac90767d34ce9937634fMark Lord * GEN_II/GEN_IIE with dual host controllers: 11116abf4678261218938ccdac90767d34ce9937634fMark Lord * one set of global thresholds for the entire chip. 11122b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 1113cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD); 1114cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(count, mmio + IRQ_COAL_IO_THRESHOLD); 11152b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* clear leftover coal IRQ bit */ 1116cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); 11176abf4678261218938ccdac90767d34ce9937634fMark Lord if (count) 11186abf4678261218938ccdac90767d34ce9937634fMark Lord coal_enable = ALL_PORTS_COAL_DONE; 11196abf4678261218938ccdac90767d34ce9937634fMark Lord clks = count = 0; /* force clearing of regular regs below */ 11202b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } 11216abf4678261218938ccdac90767d34ce9937634fMark Lord 11222b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* 11232b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord * All chips: independent thresholds for each HC on the chip. 11242b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord */ 11252b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord hc_mmio = mv_hc_base_from_port(mmio, 0); 1126cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); 1127cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); 1128cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); 11296abf4678261218938ccdac90767d34ce9937634fMark Lord if (count) 11306abf4678261218938ccdac90767d34ce9937634fMark Lord coal_enable |= PORTS_0_3_COAL_DONE; 11316abf4678261218938ccdac90767d34ce9937634fMark Lord if (is_dual_hc) { 11322b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC); 1133cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); 1134cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); 1135cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); 11366abf4678261218938ccdac90767d34ce9937634fMark Lord if (count) 11376abf4678261218938ccdac90767d34ce9937634fMark Lord coal_enable |= PORTS_4_7_COAL_DONE; 11382b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord } 11392b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 11406abf4678261218938ccdac90767d34ce9937634fMark Lord mv_set_main_irq_mask(host, 0, coal_enable); 11412b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord spin_unlock_irqrestore(&host->lock, flags); 11422b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord} 11432b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 114405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 114500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord * mv_start_edma - Enable eDMA engine 114605b308e1df6d9d673daedb517969241f41278b52Brett Russ * @base: port base address 114705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pp: port private data 114805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 1149beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * Verify the local cache of the eDMA state is accurate with a 1150beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * WARN_ON. 115105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 115205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 115305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 115405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 115500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio, 1156721091685f853ba4e6c49f26f989db0b1a811250Mark Lord struct mv_port_priv *pp, u8 protocol) 115720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1158721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int want_ncq = (protocol == ATA_PROT_NCQ); 1159721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1160721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 1161721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 1162721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq != using_ncq) 1163b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 1164721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } 1165c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 11660c58912e192fc3a4835d772aafa40b72552b819fMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 11670c58912e192fc3a4835d772aafa40b72552b819fMark Lord 116800b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_edma_cfg(ap, want_ncq, 1); 11690c58912e192fc3a4835d772aafa40b72552b819fMark Lord 1170f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord mv_set_edma_ptrs(port_mmio, hpriv, pp); 117100b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ); 1172bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1173cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(EDMA_EN, port_mmio + EDMA_CMD); 1174afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 1175afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 117620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 117720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 11789b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lordstatic void mv_wait_for_edma_empty_idle(struct ata_port *ap) 11799b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord{ 11809b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 11819b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE); 11829b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const int per_loop = 5, timeout = (15 * 1000 / per_loop); 11839b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord int i; 11849b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 11859b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord /* 11869b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord * Wait for the EDMA engine to finish transactions in progress. 1187c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * No idea what a good "timeout" value might be, but measurements 1188c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * indicate that it often requires hundreds of microseconds 1189c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * with two drives in-use. So we use the 15msec value above 1190c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord * as a rough guess at what even more drives might require. 11919b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord */ 11929b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord for (i = 0; i < timeout; ++i) { 1193cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 edma_stat = readl(port_mmio + EDMA_STATUS); 11949b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord if ((edma_stat & empty_idle) == empty_idle) 11959b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord break; 11969b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord udelay(per_loop); 11979b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord } 11989b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */ 11999b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord} 12009b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 120105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1202e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * mv_stop_edma_engine - Disable eDMA engine 1203b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * @port_mmio: io base address 120405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 120505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 120605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 120705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 1208b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio) 120920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1210b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord int i; 121131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1212b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Disable eDMA. The disable bit auto clears. */ 1213cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(EDMA_DS, port_mmio + EDMA_CMD); 12148b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 1215b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Wait for the chip to confirm eDMA is off. */ 1216b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord for (i = 10000; i > 0; i--) { 1217cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 reg = readl(port_mmio + EDMA_CMD); 12184537deb5e90b717a725b3d74b58b4bb1d28443d0Jeff Garzik if (!(reg & EDMA_EN)) 1219b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 1220b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord udelay(10); 122131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 1222b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 122320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 122420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1225e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap) 12260ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik{ 1227b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord void __iomem *port_mmio = mv_ap_base(ap); 1228b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 122966e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord int err = 0; 12300ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 1231b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 1232b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 1233b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 12349b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord mv_wait_for_edma_empty_idle(ap); 1235b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (mv_stop_edma_engine(port_mmio)) { 1236b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); 123766e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord err = -EIO; 1238b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord } 123966e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord mv_edma_cfg(ap, 0, 0); 124066e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord return err; 12410ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik} 12420ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 12438a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#ifdef ATA_DEBUG 124431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_mem(void __iomem *start, unsigned bytes) 124520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 124631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 124731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 124831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%p: ", start + b); 124931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 12502dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", readl(start + b)); 125131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 125231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 125331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 125431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 125531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 12568a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#endif 12578a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik 125831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 125931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 126031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 126131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 126231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 dw; 126331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 126431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%02x: ", b); 126531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 12662dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik (void) pci_read_config_dword(pdev, b, &dw); 12672dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", dw); 126831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 126931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 127031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 127131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 127231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 127331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 127431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_all_regs(void __iomem *mmio_base, int port, 127531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct pci_dev *pdev) 127631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 127731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 12788b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik void __iomem *hc_base = mv_hc_base(mmio_base, 127931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port >> MV_PORT_HC_SHIFT); 128031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_base; 128131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int start_port, num_ports, p, start_hc, num_hcs, hc; 128231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 128331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (0 > port) { 128431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = start_port = 0; 128531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = 8; /* shld be benign for 4 port devs */ 128631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_hcs = 2; 128731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } else { 128831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = port >> MV_PORT_HC_SHIFT; 128931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_port = port; 129031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = num_hcs = 1; 129131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 12928b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik DPRINTK("All registers for port(s) %u-%u:\n", start_port, 129331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports > 1 ? num_ports - 1 : start_port); 129431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 129531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (NULL != pdev) { 129631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI config space regs:\n"); 129731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 129831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 129931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI regs:\n"); 130031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xc00, 0x3c); 130131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xd00, 0x34); 130231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xf00, 0x4); 130331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0x1d00, 0x6c); 130431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 1305d220c37e0a3c9a47ae00e87e044d963b3ea040bcDan Aloni hc_base = mv_hc_base(mmio_base, hc); 130631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("HC regs (HC %i):\n", hc); 130731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(hc_base, 0x1c); 130831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 130931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (p = start_port; p < start_port + num_ports; p++) { 131031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port_base = mv_port_base(mmio_base, p); 13112dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("EDMA regs (port %i):\n", p); 131231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base, 0x54); 13132dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("SATA regs (port %i):\n", p); 131431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base+0x300, 0x60); 131531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 131631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 131720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 131820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 131920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic unsigned int mv_scr_offset(unsigned int sc_reg_in) 132020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 132120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs; 132220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 132320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ switch (sc_reg_in) { 132420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_STATUS: 132520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_CONTROL: 132620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ERROR: 1327cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ofs = SATA_STATUS + (sc_reg_in * sizeof(u32)); 132820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 132920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ACTIVE: 1330cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ofs = SATA_ACTIVE; /* active is not with the others */ 133120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 133220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ default: 133320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = 0xffffffffU; 133420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 133520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 133620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return ofs; 133720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 133820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 133982ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 134020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 134120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 134220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1343da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 134482ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo *val = readl(mv_ap_base(link->ap) + ofs); 1345da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1346da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1347da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 134820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 134920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 135082ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 135120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 135220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 135320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1354da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 13552009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord void __iomem *addr = mv_ap_base(link->ap) + ofs; 13562009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord if (sc_reg_in == SCR_CONTROL) { 13572009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord /* 13582009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * Workaround for 88SX60x1 FEr SATA#26: 13592009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * 13602009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * COMRESETs have to take care not to accidently 13612009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * put the drive to sleep when writing SCR_CONTROL. 13622009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * Setting bits 12..15 prevents this problem. 13632009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * 13642009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * So if we see an outbound COMMRESET, set those bits. 13652009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * Ditto for the followup write that clears the reset. 13662009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * 13672009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * The proprietary driver does this for 13682009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord * all chip versions, and so do we. 13692009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord */ 13702009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1) 13712009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord val |= 0xf000; 13722009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord } 13732009177329ae565d9e9efd31b399d2f4ed4f0c44Mark Lord writelfl(val, addr); 1374da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1375da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1376da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 137720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 137820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1379f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *adev) 1380f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord{ 1381f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord /* 1382e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Deal with Gen-II ("mv6") hardware quirks/restrictions: 1383e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * 1384e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Gen-II does not support NCQ over a port multiplier 1385e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * (no FIS-based switching). 1386f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord */ 1387e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (adev->flags & ATA_DFLAG_NCQ) { 1388352fab701ca4753dd005b67ce5e512be944eb591Mark Lord if (sata_pmp_attached(adev->link->ap)) { 1389e49856d82a887ce365637176f9f99ab68076eae8Mark Lord adev->flags &= ~ATA_DFLAG_NCQ; 1390352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ata_dev_printk(adev, KERN_INFO, 1391352fab701ca4753dd005b67ce5e512be944eb591Mark Lord "NCQ disabled for command-based switching\n"); 1392352fab701ca4753dd005b67ce5e512be944eb591Mark Lord } 1393e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 1394f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1395f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 13963e4a139107e497a741c26f8a377a10f214d63ec1Mark Lordstatic int mv_qc_defer(struct ata_queued_cmd *qc) 13973e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord{ 13983e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct ata_link *link = qc->dev->link; 13993e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct ata_port *ap = link->ap; 14003e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord struct mv_port_priv *pp = ap->private_data; 14013e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 14023e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord /* 140329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * Don't allow new commands if we're in a delayed EH state 140429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * for NCQ and/or FIS-based switching. 140529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord */ 140629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 140729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord return ATA_DEFER_PORT; 1408159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou 1409159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou /* PIO commands need exclusive link: no other commands [DMA or PIO] 1410159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou * can run concurrently. 1411159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou * set excl_link when we want to send a PIO command in DMA mode 1412159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou * or a non-NCQ command in NCQ mode. 1413159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou * When we receive a command from that link, and there are no 1414159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou * outstanding commands, mark a flag to clear excl_link and let 1415159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou * the command go through. 1416159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou */ 1417159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou if (unlikely(ap->excl_link)) { 1418159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou if (link == ap->excl_link) { 1419159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou if (ap->nr_active_links) 1420159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou return ATA_DEFER_PORT; 1421159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou qc->flags |= ATA_QCFLAG_CLEAR_EXCL; 1422159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou return 0; 1423159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou } else 1424159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou return ATA_DEFER_PORT; 1425159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou } 1426159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou 142729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord /* 14283e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord * If the port is completely idle, then allow the new qc. 14293e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord */ 14303e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord if (ap->nr_active_links == 0) 14313e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return 0; 14323e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 14334bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo /* 14344bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * The port is operating in host queuing mode (EDMA) with NCQ 14354bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * enabled, allow multiple NCQ commands. EDMA also allows 14364bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * queueing multiple DMA commands but libata core currently 14374bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo * doesn't allow it. 14384bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo */ 14394bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) && 1440159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) { 1441159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou if (ata_is_ncq(qc->tf.protocol)) 1442159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou return 0; 1443159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou else { 1444159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou ap->excl_link = link; 1445159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou return ATA_DEFER_PORT; 1446159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou } 1447159a7ff7a13f9a02c75006f40c0561a3a81aefcdGwendal Grignou } 14484bdee6c5103696a2729d3db2f235d202191788e4Tejun Heo 14493e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord return ATA_DEFER_PORT; 14503e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord} 14513e4a139107e497a741c26f8a377a10f214d63ec1Mark Lord 145208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lordstatic void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs) 1453e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 145408da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord struct mv_port_priv *pp = ap->private_data; 145508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord void __iomem *port_mmio; 145600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 145708da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg; 145808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 ltmode, *old_ltmode = &pp->cached.ltmode; 145908da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord u32 haltcond, *old_haltcond = &pp->cached.haltcond; 146000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 146108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord ltmode = *old_ltmode & ~LTMODE_BIT8; 146208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord haltcond = *old_haltcond | EDMA_ERR_DEV; 146300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 146400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (want_fbs) { 146508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC; 146608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord ltmode = *old_ltmode | LTMODE_BIT8; 14674c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (want_ncq) 146808da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord haltcond &= ~EDMA_ERR_DEV; 14694c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord else 147008da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord fiscfg |= FISCFG_WAIT_DEV_ERR; 147108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord } else { 147208da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR); 1473e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 147400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 147508da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord port_mmio = mv_ap_base(ap); 1476cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg); 1477cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode); 1478cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond); 1479f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1480f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 1481dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lordstatic void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq) 1482dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord{ 1483dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1484dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord u32 old, new; 1485dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord 1486dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord /* workaround for 88SX60x1 FEr SATA#25 (part 1) */ 1487cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord old = readl(hpriv->base + GPIO_PORT_CTL); 1488dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord if (want_ncq) 1489dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord new = old | (1 << 22); 1490dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord else 1491dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord new = old & ~(1 << 22); 1492dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord if (new != old) 1493cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(new, hpriv->base + GPIO_PORT_CTL); 1494dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord} 1495dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord 1496c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord/** 149740f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma 149840f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * @ap: Port being initialized 1499c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * 1500c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * There are two DMA modes on these chips: basic DMA, and EDMA. 1501c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * 1502c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * Bit-0 of the "EDMA RESERVED" register enables/disables use 1503c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * of basic DMA on the GEN_IIE versions of the chips. 1504c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * 1505c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * This bit survives EDMA resets, and must be set for basic DMA 1506c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord * to function, and should be cleared when EDMA is active. 1507c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord */ 1508c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lordstatic void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma) 1509c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord{ 1510c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord struct mv_port_priv *pp = ap->private_data; 1511c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord u32 new, *old = &pp->cached.unknown_rsvd; 1512c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord 1513c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord if (enable_bmdma) 1514c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord new = *old | 1; 1515c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord else 1516c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord new = *old & ~1; 1517cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new); 1518c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord} 1519c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord 1520000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord/* 1521000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * SOC chips have an issue whereby the HDD LEDs don't always blink 1522000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * during I/O when NCQ is enabled. Enabling a special "LED blink" mode 1523000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * of the SOC takes care of it, generating a steady blink rate when 1524000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * any drive on the chip is active. 1525000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * 1526000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * Unfortunately, the blink mode is a global hardware setting for the SOC, 1527000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * so we must use it whenever at least one port on the SOC has NCQ enabled. 1528000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * 1529000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * We turn "LED blink" off when NCQ is not in use anywhere, because the normal 1530000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * LED operation works then, and provides better (more accurate) feedback. 1531000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * 1532000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord * Note that this code assumes that an SOC never has more than one HC onboard. 1533000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord */ 1534000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lordstatic void mv_soc_led_blink_enable(struct ata_port *ap) 1535000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord{ 1536000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct ata_host *host = ap->host; 1537000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct mv_host_priv *hpriv = host->private_data; 1538000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord void __iomem *hc_mmio; 1539000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord u32 led_ctrl; 1540000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1541000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN) 1542000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord return; 1543000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN; 1544000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); 1545cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord led_ctrl = readl(hc_mmio + SOC_LED_CTRL); 1546cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); 1547000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord} 1548000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1549000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lordstatic void mv_soc_led_blink_disable(struct ata_port *ap) 1550000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord{ 1551000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct ata_host *host = ap->host; 1552000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct mv_host_priv *hpriv = host->private_data; 1553000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord void __iomem *hc_mmio; 1554000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord u32 led_ctrl; 1555000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord unsigned int port; 1556000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1557000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)) 1558000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord return; 1559000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1560000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord /* disable led-blink only if no ports are using NCQ */ 1561000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord for (port = 0; port < hpriv->n_ports; port++) { 1562000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct ata_port *this_ap = host->ports[port]; 1563000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord struct mv_port_priv *pp = this_ap->private_data; 1564000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1565000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 1566000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord return; 1567000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord } 1568000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1569000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN; 1570000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); 1571cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord led_ctrl = readl(hc_mmio + SOC_LED_CTRL); 1572cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); 1573000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord} 1574000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 157500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma) 1576e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 15770c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 cfg; 1578e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_port_priv *pp = ap->private_data; 1579e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1580e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1581e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1582e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* set up non-NCQ EDMA configuration */ 15830c58912e192fc3a4835d772aafa40b72552b819fMark Lord cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 1584d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= 1585d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 1586e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 15870c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (IS_GEN_I(hpriv)) 1588e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 8); /* enab config burst size mask */ 1589e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1590dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord else if (IS_GEN_II(hpriv)) { 1591e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1592dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord mv_60x1_errata_sata25(ap, want_ncq); 1593e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1594dd2890f60f8e15f14c8eb132779b2f15c49d1203Mark Lord } else if (IS_GEN_IIE(hpriv)) { 159500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord int want_fbs = sata_pmp_attached(ap); 159600f42eabb204c68fa64ef72de834e74aca15c81fMark Lord /* 159700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * Possible future enhancement: 159800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * 159900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * The chip can use FBS with non-NCQ, if we allow it, 160000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * But first we need to have the error handling in place 160100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * for this mode (datasheet section 7.3.15.4.2.3). 160200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord * So disallow non-NCQ FBS for now. 160300f42eabb204c68fa64ef72de834e74aca15c81fMark Lord */ 160400f42eabb204c68fa64ef72de834e74aca15c81fMark Lord want_fbs &= want_ncq; 160500f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 160608da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_config_fbs(ap, want_ncq, want_fbs); 160700f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 160800f42eabb204c68fa64ef72de834e74aca15c81fMark Lord if (want_fbs) { 160900f42eabb204c68fa64ef72de834e74aca15c81fMark Lord pp->pp_flags |= MV_PP_FLAG_FBS_EN; 161000f42eabb204c68fa64ef72de834e74aca15c81fMark Lord cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ 161100f42eabb204c68fa64ef72de834e74aca15c81fMark Lord } 161200f42eabb204c68fa64ef72de834e74aca15c81fMark Lord 1613e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 161400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord if (want_edma) { 161500b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord cfg |= (1 << 22); /* enab 4-entry host queue cache */ 161600b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord if (!IS_SOC(hpriv)) 161700b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord cfg |= (1 << 18); /* enab early completion */ 161800b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord } 1619616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (hpriv->hp_flags & MV_HP_CUT_THROUGH) 1620616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ 1621c01e8a23128c746f23088db836bd4c820f3eb0b4Mark Lord mv_bmdma_enable_iie(ap, !want_edma); 1622000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord 1623000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (IS_SOC(hpriv)) { 1624000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord if (want_ncq) 1625000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord mv_soc_led_blink_enable(ap); 1626000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord else 1627000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord mv_soc_led_blink_disable(ap); 1628000b344f4ca7828ee43940255c8bbb32e2c7dbecMark Lord } 1629e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 1630e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1631721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq) { 1632721091685f853ba4e6c49f26f989db0b1a811250Mark Lord cfg |= EDMA_CFG_NCQ; 1633721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 163400b81235aa0368f84c0e704bec4142cd8c516ad5Mark Lord } 1635721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1636cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(cfg, port_mmio + EDMA_CFG); 1637e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1638e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1639da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordstatic void mv_port_free_dma_mem(struct ata_port *ap) 1640da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord{ 1641da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1642da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_port_priv *pp = ap->private_data; 1643eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord int tag; 1644da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1645da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crqb) { 1646da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1647da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = NULL; 1648da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1649da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crpb) { 1650da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1651da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = NULL; 1652da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1653eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1654eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1655eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we have one unique sg_tbl per NCQ tag. 1656eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1657eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1658eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (pp->sg_tbl[tag]) { 1659eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) 1660eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_pool_free(hpriv->sg_tbl_pool, 1661eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag], 1662eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag]); 1663eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = NULL; 1664eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1665da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1666da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord} 1667da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 166805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 166905b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_start - Port specific init/start routine. 167005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 167105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 167205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Allocate and point to DMA memory, init port private memory, 167305b308e1df6d9d673daedb517969241f41278b52Brett Russ * zero indices. 167405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 167505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 167605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 167705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 167831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap) 167931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1680cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct device *dev = ap->host->dev; 1681cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 168231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp; 1683933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord unsigned long flags; 1684dde2020754aeb14e17052d61784dcb37f252aac2James Bottomley int tag; 168531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 168624dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 16876037d6bbdff65eb5a84fe35e140f4da4f7cc103aJeff Garzik if (!pp) 168824dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return -ENOMEM; 1689da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord ap->private_data = pp; 169031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1691da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1692da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crqb) 1693da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 1694da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crqb, 0, MV_CRQB_Q_SZ); 169531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1696da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1697da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crpb) 1698da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord goto out_port_free_dma_mem; 1699da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crpb, 0, MV_CRPB_Q_SZ); 170031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 17013bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */ 17023bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) 17033bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675bMark Lord ap->flags |= ATA_FLAG_AN; 1704eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1705eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1706eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we need one unique sg_tbl per NCQ tag. 1707eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1708eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1709eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) { 1710eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1711eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1712eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (!pp->sg_tbl[tag]) 1713eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord goto out_port_free_dma_mem; 1714eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } else { 1715eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = pp->sg_tbl[0]; 1716eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1717eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1718eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1719933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord 1720933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_lock_irqsave(ap->lock, flags); 172108da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_save_cached_regs(ap); 172266e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord mv_edma_cfg(ap, 0, 0); 1723933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_unlock_irqrestore(ap->lock, flags); 1724933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord 172531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 1726da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1727da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordout_port_free_dma_mem: 1728da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 1729da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 173031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 173131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 173205b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 173305b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_stop - Port specific cleanup/stop routine. 173405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 173505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 173605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Stop DMA, cleanup port memory. 173705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 173805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 1739cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine uses the host lock to protect the DMA stop. 174005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 174131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap) 174231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1743933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord unsigned long flags; 1744933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord 1745933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_lock_irqsave(ap->lock, flags); 1746e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma(ap); 174788e675e193159b9891c1c576de4348eaf490f5d0Mark Lord mv_enable_port_irqs(ap, 0); 1748933cb8e5fcdebd4b666165e3f039f814d62b0e52Mark Lord spin_unlock_irqrestore(ap->lock, flags); 1749da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 175031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 175131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 175205b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 175305b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 175405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command whose SG list to source from 175505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 175605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Populate the SG list and mark the last entry. 175705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 175805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 175905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 176005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 17616c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzikstatic void mv_fill_sg(struct ata_queued_cmd *qc) 176231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 176331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = qc->ap->private_data; 1764972c26bdd6b58e7534473c4f7928584578cf43f4Jeff Garzik struct scatterlist *sg; 17653be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik struct mv_sg *mv_sg, *last_sg = NULL; 1766ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo unsigned int si; 176731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1768eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord mv_sg = pp->sg_tbl[qc->tag]; 1769ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 1770d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik dma_addr_t addr = sg_dma_address(sg); 1771d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik u32 sg_len = sg_dma_len(sg); 177222374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 17734007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson while (sg_len) { 17744007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 offset = addr & 0xffff; 17754007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 len = sg_len; 177622374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 177732cd11a61007511ddb38783deec8bb1aa6735789Mark Lord if (offset + len > 0x10000) 17784007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson len = 0x10000 - offset; 17794007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 17804007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 17814007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 17826c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik mv_sg->flags_size = cpu_to_le32(len & 0xffff); 178332cd11a61007511ddb38783deec8bb1aa6735789Mark Lord mv_sg->reserved = 0; 17844007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 17854007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson sg_len -= len; 17864007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson addr += len; 17874007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 17883be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg = mv_sg; 17894007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg++; 17904007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson } 179131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 17923be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik 17933be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik if (likely(last_sg)) 17943be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 179532cd11a61007511ddb38783deec8bb1aa6735789Mark Lord mb(); /* ensure data structure is visible to the chipset */ 179631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 179731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 17985796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzikstatic void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 179931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1800559eedad7f7764dacca33980127b4615011230e4Mark Lord u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 180131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ (last ? CRQB_CMD_LAST : 0); 1802559eedad7f7764dacca33980127b4615011230e4Mark Lord *cmdw = cpu_to_le16(tmp); 180331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 180431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 180505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1806da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_sff_irq_clear - Clear hardware interrupt after DMA. 1807da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @ap: Port associated with this ATA transaction. 1808da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1809da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * We need this only for ATAPI bmdma transactions, 1810da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * as otherwise we experience spurious interrupts 1811da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * after libata-sff handles the bmdma interrupts. 1812da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1813da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_sff_irq_clear(struct ata_port *ap) 1814da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1815da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ); 1816da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1817da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1818da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1819da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA. 1820da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to check for chipset/DMA compatibility. 1821da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1822da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * The bmdma engines cannot handle speculative data sizes 1823da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * (bytecount under/over flow). So only allow DMA for 1824da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * data transfer commands with known data sizes. 1825da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1826da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1827da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1828da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1829da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic int mv_check_atapi_dma(struct ata_queued_cmd *qc) 1830da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1831da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct scsi_cmnd *scmd = qc->scsicmd; 1832da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1833da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord if (scmd) { 1834da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord switch (scmd->cmnd[0]) { 1835da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case READ_6: 1836da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case READ_10: 1837da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case READ_12: 1838da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case WRITE_6: 1839da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case WRITE_10: 1840da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case WRITE_12: 1841da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case GPCMD_READ_CD: 1842da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case GPCMD_SEND_DVD_STRUCTURE: 1843da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord case GPCMD_SEND_CUE_SHEET: 1844da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord return 0; /* DMA is safe */ 1845da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord } 1846da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord } 1847da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord return -EOPNOTSUPP; /* use PIO instead */ 1848da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1849da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1850da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1851da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_setup - Set up BMDMA transaction 1852da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to prepare DMA for. 1853da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1854da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1855da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1856da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1857da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_setup(struct ata_queued_cmd *qc) 1858da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1859da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct ata_port *ap = qc->ap; 1860da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1861da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct mv_port_priv *pp = ap->private_data; 1862da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1863da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord mv_fill_sg(qc); 1864da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1865da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* clear all DMA cmd bits */ 1866cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0, port_mmio + BMDMA_CMD); 1867da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1868da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* load PRD table addr. */ 1869da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16, 1870cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + BMDMA_PRD_HIGH); 1871da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord writelfl(pp->sg_tbl_dma[qc->tag], 1872cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + BMDMA_PRD_LOW); 1873da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1874da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* issue r/w command */ 1875da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord ap->ops->sff_exec_command(ap, &qc->tf); 1876da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1877da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1878da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1879da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_start - Start a BMDMA transaction 1880da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to start DMA on. 1881da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1882da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1883da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1884da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1885da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_start(struct ata_queued_cmd *qc) 1886da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1887da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct ata_port *ap = qc->ap; 1888da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1889da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 1890da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START; 1891da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1892da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* start host DMA transaction */ 1893cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(cmd, port_mmio + BMDMA_CMD); 1894da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1895da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1896da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1897da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_stop - Stop BMDMA transfer 1898da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @qc: queued command to stop DMA on. 1899da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1900da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Clears the ATA_DMA_START flag in the bmdma control register 1901da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1902da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1903da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1904da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1905da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic void mv_bmdma_stop(struct ata_queued_cmd *qc) 1906da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1907da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord struct ata_port *ap = qc->ap; 1908da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1909da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord u32 cmd; 1910da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1911da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* clear start/stop bit */ 1912cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord cmd = readl(port_mmio + BMDMA_CMD); 1913da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord cmd &= ~ATA_DMA_START; 1914cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(cmd, port_mmio + BMDMA_CMD); 1915da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1916da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 1917da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord ata_sff_dma_pause(ap); 1918da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1919da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1920da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 1921da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * mv_bmdma_status - Read BMDMA status 1922da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * @ap: port for which to retrieve DMA status. 1923da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1924da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Read and return equivalent of the sff BMDMA status register. 1925da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * 1926da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * LOCKING: 1927da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Inherited from caller. 1928da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1929da14265e776f35067045b8555b5f5f7521e50bc4Mark Lordstatic u8 mv_bmdma_status(struct ata_port *ap) 1930da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord{ 1931da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1932da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord u32 reg, status; 1933da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1934da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord /* 1935da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * Other bits are valid only if ATA_DMA_ACTIVE==0, 1936da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord * and the ATA_DMA_INTR bit doesn't exist. 1937da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord */ 1938cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord reg = readl(port_mmio + BMDMA_STATUS); 1939da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord if (reg & ATA_DMA_ACTIVE) 1940da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord status = ATA_DMA_ACTIVE; 1941da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord else 1942da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR; 1943da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord return status; 1944da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord} 1945da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord 1946299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lordstatic void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc) 1947299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord{ 1948299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord struct ata_taskfile *tf = &qc->tf; 1949299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord /* 1950299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * Workaround for 88SX60x1 FEr SATA#24. 1951299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * 1952299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * Chip may corrupt WRITEs if multi_count >= 4kB. 1953299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * Note that READs are unaffected. 1954299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * 1955299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * It's not clear if this errata really means "4K bytes", 1956299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * or if it always happens for multi_count > 7 1957299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * regardless of device sector_size. 1958299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * 1959299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * So, for safety, any write with multi_count > 7 1960299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord * gets converted here into a regular PIO write instead: 1961299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord */ 1962299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) { 1963299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord if (qc->dev->multi_count > 7) { 1964299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord switch (tf->command) { 1965299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_CMD_WRITE_MULTI: 1966299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord tf->command = ATA_CMD_PIO_WRITE; 1967299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord break; 1968299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_CMD_WRITE_MULTI_FUA_EXT: 1969299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord tf->flags &= ~ATA_TFLAG_FUA; /* ugh */ 1970299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord /* fall through */ 1971299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_CMD_WRITE_MULTI_EXT: 1972299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord tf->command = ATA_CMD_PIO_WRITE_EXT; 1973299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord break; 1974299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord } 1975299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord } 1976299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord } 1977299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord} 1978299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord 1979da14265e776f35067045b8555b5f5f7521e50bc4Mark Lord/** 198005b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_prep - Host specific command preparation. 198105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to prepare 198205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 198305b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 198405b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it handles prep of the CRQB 198505b308e1df6d9d673daedb517969241f41278b52Brett Russ * (command request block), does some sanity checking, and calls 198605b308e1df6d9d673daedb517969241f41278b52Brett Russ * the SG load routine. 198705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 198805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 198905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 199005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 199131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc) 199231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 199331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_port *ap = qc->ap; 199431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = ap->private_data; 1995e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 *cw; 19968d2b450d0f9233f221d545f26720eebbc468e857Mark Lord struct ata_taskfile *tf = &qc->tf; 199731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u16 flags = 0; 1998a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 199931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2000299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord switch (tf->protocol) { 2001299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_PROT_DMA: 2002299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_PROT_NCQ: 2003299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord break; /* continue below */ 2004299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord case ATA_PROT_PIO: 2005299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord mv_rw_multi_errata_sata24(qc); 200631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 2007299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord default: 2008299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord return; 2009299b3f8df90a3f7416d8df121d8a42b1a2aeced4Mark Lord } 201020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 201131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Fill in command request block 201231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 20138d2b450d0f9233f221d545f26720eebbc468e857Mark Lord if (!(tf->flags & ATA_TFLAG_WRITE)) 201431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= CRQB_FLAG_READ; 2015beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 201631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= qc->tag << CRQB_TAG_SHIFT; 2017e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 201831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2019bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 2020fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 2021a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 2022a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr = 2023eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 2024a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr_hi = 2025eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 2026a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 202731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2028a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord cw = &pp->crqb[in_index].ata_cmd[0]; 202931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 203031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Sadly, the CRQB cannot accomodate all registers--there are 203131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * only 11 bytes...so we must pick and choose required 203231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * registers based on the command. So, we drop feature and 203331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * hob_feature for [RW] DMA commands, but they are needed for 2034cd12e1f7a2c28917c89d65c0d4a52d3919b4c125Mark Lord * NCQ. NCQ will drop hob_nsect, which is not needed there 2035cd12e1f7a2c28917c89d65c0d4a52d3919b4c125Mark Lord * (nsect is used only for the tag; feat/hob_feat hold true nsect). 203620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 203731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ switch (tf->command) { 203831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ: 203931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ_EXT: 204031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE: 204131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE_EXT: 2042c15d85c8f3f73b5f20aae7928e25b6996f16b328Jens Axboe case ATA_CMD_WRITE_FUA_EXT: 204331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 204431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 204531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_READ: 204631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_WRITE: 20478b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 204831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 204931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 205031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ default: 205131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* The only other commands EDMA supports in non-queued and 205231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 205331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * of which are defined/used by Linux. If we get here, this 205431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * driver needs work. 205531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * 205631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * FIXME: modify libata to give qc_prep a return value and 205731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * return error here. 205831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 205931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ BUG_ON(tf->command); 206031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 206131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 206231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 206331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 206431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 206531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 206631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 206731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 206831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 206931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 207031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 207131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2072e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 2073e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 2074e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik mv_fill_sg(qc); 2075e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 2076e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2077e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik/** 2078e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * mv_qc_prep_iie - Host specific command preparation. 2079e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * @qc: queued command to prepare 2080e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 2081e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * This routine simply redirects to the general purpose routine 2082e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * if command is not DMA. Else, it handles prep of the CRQB 2083e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * (command request block), does some sanity checking, and calls 2084e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * the SG load routine. 2085e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 2086e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * LOCKING: 2087e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * Inherited from caller. 2088e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik */ 2089e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc) 2090e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 2091e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_port *ap = qc->ap; 2092e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_port_priv *pp = ap->private_data; 2093e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_crqb_iie *crqb; 20948d2b450d0f9233f221d545f26720eebbc468e857Mark Lord struct ata_taskfile *tf = &qc->tf; 2095a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 2096e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik u32 flags = 0; 2097e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 20988d2b450d0f9233f221d545f26720eebbc468e857Mark Lord if ((tf->protocol != ATA_PROT_DMA) && 20998d2b450d0f9233f221d545f26720eebbc468e857Mark Lord (tf->protocol != ATA_PROT_NCQ)) 2100e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 2101e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2102e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* Fill in Gen IIE command request block */ 21038d2b450d0f9233f221d545f26720eebbc468e857Mark Lord if (!(tf->flags & ATA_TFLAG_WRITE)) 2104e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= CRQB_FLAG_READ; 2105e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2106beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 2107e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= qc->tag << CRQB_TAG_SHIFT; 21088c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord flags |= qc->tag << CRQB_HOSTQ_SHIFT; 2109e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 2110e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2111bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 2112fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 2113a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 2114a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 2115eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 2116eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 2117e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->flags = cpu_to_le32(flags); 2118e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2119e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[0] = cpu_to_le32( 2120e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->command << 16) | 2121e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->feature << 24) 2122e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2123e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[1] = cpu_to_le32( 2124e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbal << 0) | 2125e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbam << 8) | 2126e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbah << 16) | 2127e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->device << 24) 2128e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2129e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[2] = cpu_to_le32( 2130e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbal << 0) | 2131e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbam << 8) | 2132e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbah << 16) | 2133e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_feature << 24) 2134e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2135e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[3] = cpu_to_le32( 2136e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->nsect << 0) | 2137e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_nsect << 8) 2138e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 2139e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2140e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 214131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 214231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_fill_sg(qc); 214331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 214431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 214505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2146d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * mv_sff_check_status - fetch device status, if valid 2147d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * @ap: ATA port to fetch status from 2148d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * 2149d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * When using command issue via mv_qc_issue_fis(), 2150d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * the initial ATA_BUSY state does not show up in the 2151d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * ATA status (shadow) register. This can confuse libata! 2152d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * 2153d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * So we have a hook here to fake ATA_BUSY for that situation, 2154d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * until the first time a BUSY, DRQ, or ERR bit is seen. 2155d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * 2156d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord * The rest of the time, it simply returns the ATA status register. 2157d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord */ 2158d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lordstatic u8 mv_sff_check_status(struct ata_port *ap) 2159d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord{ 2160d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord u8 stat = ioread8(ap->ioaddr.status_addr); 2161d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord struct mv_port_priv *pp = ap->private_data; 2162d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord 2163d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) { 2164d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) 2165d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; 2166d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord else 2167d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord stat = ATA_BUSY; 2168d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord } 2169d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord return stat; 2170d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord} 2171d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord 2172d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord/** 217370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register 217470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * @fis: fis to be sent 217570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * @nwords: number of 32-bit words in the fis 217670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 217770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lordstatic unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords) 217870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord{ 217970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 218070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord u32 ifctl, old_ifctl, ifstat; 218170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord int i, timeout = 200, final_word = nwords - 1; 218270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 218370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Initiate FIS transmission mode */ 2184cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord old_ifctl = readl(port_mmio + SATA_IFCTL); 218570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ifctl = 0x100 | (old_ifctl & 0xf); 2186cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(ifctl, port_mmio + SATA_IFCTL); 218770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 218870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Send all words of the FIS except for the final word */ 218970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord for (i = 0; i < final_word; ++i) 2190cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS); 219170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 219270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Flag end-of-transmission, and then send the final word */ 2193cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL); 2194cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS); 219570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 219670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* 219770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Wait for FIS transmission to complete. 219870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * This typically takes just a single iteration. 219970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 220070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord do { 2201cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ifstat = readl(port_mmio + SATA_IFSTAT); 220270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } while (!(ifstat & 0x1000) && --timeout); 220370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 220470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* Restore original port configuration */ 2205cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(old_ifctl, port_mmio + SATA_IFCTL); 220670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 220770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* See if it worked */ 220870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if ((ifstat & 0x3000) != 0x1000) { 220970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ata_port_printk(ap, KERN_WARNING, 221070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord "%s transmission error, ifstat=%08x\n", 221170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord __func__, ifstat); 221270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return AC_ERR_OTHER; 221370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } 221470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return 0; 221570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord} 221670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 221770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord/** 221870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * mv_qc_issue_fis - Issue a command directly as a FIS 221970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * @qc: queued command to start 222070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 222170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Note that the ATA shadow registers are not updated 222270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * after command issue, so the device will appear "READY" 222370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * if polled, even while it is BUSY processing the command. 222470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 222570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * So we use a status hook to fake ATA_BUSY until the drive changes state. 222670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 222770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Note: we don't get updated shadow regs on *completion* 222870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * of non-data commands. So avoid sending them via this function, 222970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * as they will appear to have completed immediately. 223070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 223170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * GEN_IIE has special registers that we could get the result tf from, 223270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * but earlier chipsets do not. For now, we ignore those registers. 223370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 223470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lordstatic unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc) 223570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord{ 223670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct ata_port *ap = qc->ap; 223770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct mv_port_priv *pp = ap->private_data; 223870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct ata_link *link = qc->dev->link; 223970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord u32 fis[5]; 224070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord int err = 0; 224170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 224270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis); 22434c4a90fd2b9d1f5c0d33df3fcfaa8a3dae9abc53Thiago Farina err = mv_send_fis(ap, fis, ARRAY_SIZE(fis)); 224470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (err) 224570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return err; 224670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 224770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord switch (qc->tf.protocol) { 224870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord case ATAPI_PROT_PIO: 224970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; 225070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* fall through */ 225170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord case ATAPI_PROT_NODATA: 225270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST_FIRST; 225370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord break; 225470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord case ATA_PROT_PIO: 225570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; 225670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (qc->tf.flags & ATA_TFLAG_WRITE) 225770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST_FIRST; 225870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord else 225970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST; 226070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord break; 226170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord default: 226270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ap->hsm_task_state = HSM_ST_LAST; 226370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord break; 226470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } 226570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 226670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (qc->tf.flags & ATA_TFLAG_POLLING) 226770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord ata_pio_queue_task(ap, qc, 0); 226870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return 0; 226970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord} 227070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 227170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord/** 227205b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_issue - Initiate a command to the host 227305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to start 227405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 227505b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 227605b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it sanity checks our local 227705b308e1df6d9d673daedb517969241f41278b52Brett Russ * caches of the request producer/consumer indices then enables 227805b308e1df6d9d673daedb517969241f41278b52Brett Russ * DMA and bumps the request producer index. 227905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 228005b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 228105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 228205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 22839a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 228431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 2285f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord static int limit_warnings = 10; 2286c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct ata_port *ap = qc->ap; 2287c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 2288c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp = ap->private_data; 2289bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 in_index; 229042ed893d8011264f9945c2f54055b47c298ac53eMark Lord unsigned int port_irqs; 2291f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord 2292d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */ 2293d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord 2294f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord switch (qc->tf.protocol) { 2295f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATA_PROT_DMA: 2296f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATA_PROT_NCQ: 2297f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord mv_start_edma(ap, port_mmio, pp, qc->tf.protocol); 2298f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2299f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 2300f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord 2301f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord /* Write the request in pointer to kick the EDMA to life */ 2302f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 2303cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + EDMA_REQ_Q_IN_PTR); 2304f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord return 0; 230531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2306f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATA_PROT_PIO: 2307c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord /* 2308c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * Errata SATA#16, SATA#24: warn if multiple DRQs expected. 2309c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * 2310c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * Someday, we might implement special polling workarounds 2311c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * for these, but it all seems rather unnecessary since we 2312c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * normally use only DMA for commands which transfer more 2313c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * than a single block of data. 2314c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * 2315c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * Much of the time, this could just work regardless. 2316c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord * So for now, just log the incident, and allow the attempt. 2317c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord */ 2318c7843e8f565f624b0cff7cad1370fad4cb84dfbcMark Lord if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) { 2319c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord --limit_warnings; 2320c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME 2321c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord ": attempting PIO w/multiple DRQ: " 2322c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord "this may fail due to h/w errata\n"); 2323c6112bd86bc8f727bb732a47f2133e0ff12beda9Mark Lord } 2324f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord /* drop through */ 232542ed893d8011264f9945c2f54055b47c298ac53eMark Lord case ATA_PROT_NODATA: 2326f48765ccb48a62596b664aa88a2b0f943c12c0e1Mark Lord case ATAPI_PROT_PIO: 232742ed893d8011264f9945c2f54055b47c298ac53eMark Lord case ATAPI_PROT_NODATA: 232842ed893d8011264f9945c2f54055b47c298ac53eMark Lord if (ap->flags & ATA_FLAG_PIO_POLLING) 232942ed893d8011264f9945c2f54055b47c298ac53eMark Lord qc->tf.flags |= ATA_TFLAG_POLLING; 233042ed893d8011264f9945c2f54055b47c298ac53eMark Lord break; 233131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 233242ed893d8011264f9945c2f54055b47c298ac53eMark Lord 233342ed893d8011264f9945c2f54055b47c298ac53eMark Lord if (qc->tf.flags & ATA_TFLAG_POLLING) 233442ed893d8011264f9945c2f54055b47c298ac53eMark Lord port_irqs = ERR_IRQ; /* mask device interrupt when polling */ 233542ed893d8011264f9945c2f54055b47c298ac53eMark Lord else 233642ed893d8011264f9945c2f54055b47c298ac53eMark Lord port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */ 233742ed893d8011264f9945c2f54055b47c298ac53eMark Lord 233842ed893d8011264f9945c2f54055b47c298ac53eMark Lord /* 233942ed893d8011264f9945c2f54055b47c298ac53eMark Lord * We're about to send a non-EDMA capable command to the 234042ed893d8011264f9945c2f54055b47c298ac53eMark Lord * port. Turn off EDMA so there won't be problems accessing 234142ed893d8011264f9945c2f54055b47c298ac53eMark Lord * shadow block, etc registers. 234242ed893d8011264f9945c2f54055b47c298ac53eMark Lord */ 234342ed893d8011264f9945c2f54055b47c298ac53eMark Lord mv_stop_edma(ap); 234442ed893d8011264f9945c2f54055b47c298ac53eMark Lord mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs); 234542ed893d8011264f9945c2f54055b47c298ac53eMark Lord mv_pmp_select(ap, qc->dev->link->pmp); 234670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord 234770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (qc->tf.command == ATA_CMD_READ_LOG_EXT) { 234870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 234970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord /* 235070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Workaround for 88SX60x1 FEr SATA#25 (part 2). 235140f21b1124a9552bc093469280eb8239dc5f73d7Mark Lord * 235270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * After any NCQ error, the READ_LOG_EXT command 235370f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * from libata-eh *must* use mv_qc_issue_fis(). 235470f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Otherwise it might fail, due to chip errata. 235570f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * 235670f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * Rather than special-case it, we'll just *always* 235770f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * use this method here for READ_LOG_EXT, making for 235870f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord * easier testing. 235970f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord */ 236070f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord if (IS_GEN_II(hpriv)) 236170f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord return mv_qc_issue_fis(qc); 236270f8b79cf3a2eb892a01271fdfbb1903c0c982a8Mark Lord } 236342ed893d8011264f9945c2f54055b47c298ac53eMark Lord return ata_sff_qc_issue(qc); 236431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 236531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 23668f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lordstatic struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) 23678f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 23688f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct mv_port_priv *pp = ap->private_data; 23698f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc; 23708f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 23718f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 23728f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord return NULL; 23738f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord qc = ata_qc_from_tag(ap, ap->link.active_tag); 23743e4ec3443f70fbe144799ccf0b1c3797f78d1715Tejun Heo if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING)) 23753e4ec3443f70fbe144799ccf0b1c3797f78d1715Tejun Heo return qc; 23763e4ec3443f70fbe144799ccf0b1c3797f78d1715Tejun Heo return NULL; 23778f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 23788f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 237929d187bb1e30682e228ce461c487d78d945c3e4fMark Lordstatic void mv_pmp_error_handler(struct ata_port *ap) 238029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord{ 238129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int pmp, pmp_map; 238229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord struct mv_port_priv *pp = ap->private_data; 238329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord 238429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { 238529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord /* 238629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * Perform NCQ error analysis on failed PMPs 238729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * before we freeze the port entirely. 238829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * 238929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord * The failed PMPs are marked earlier by mv_pmp_eh_prep(). 239029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord */ 239129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pmp_map = pp->delayed_eh_pmp_map; 239229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; 239329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord for (pmp = 0; pmp_map != 0; pmp++) { 239429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord unsigned int this_pmp = (1 << pmp); 239529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord if (pmp_map & this_pmp) { 239629d187bb1e30682e228ce461c487d78d945c3e4fMark Lord struct ata_link *link = &ap->pmp_link[pmp]; 239729d187bb1e30682e228ce461c487d78d945c3e4fMark Lord pmp_map &= ~this_pmp; 239829d187bb1e30682e228ce461c487d78d945c3e4fMark Lord ata_eh_analyze_ncq_error(link); 239929d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 240029d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 240129d187bb1e30682e228ce461c487d78d945c3e4fMark Lord ata_port_freeze(ap); 240229d187bb1e30682e228ce461c487d78d945c3e4fMark Lord } 240329d187bb1e30682e228ce461c487d78d945c3e4fMark Lord sata_pmp_error_handler(ap); 240429d187bb1e30682e228ce461c487d78d945c3e4fMark Lord} 240529d187bb1e30682e228ce461c487d78d945c3e4fMark Lord 24064c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic unsigned int mv_get_err_pmp_map(struct ata_port *ap) 24074c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 24084c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 24094c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 2410cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord return readl(port_mmio + SATA_TESTCTL) >> 16; 24114c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 24124c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24134c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map) 24144c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 24154c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct ata_eh_info *ehi; 24164c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int pmp; 24174c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24184c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 24194c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Initialize EH info for PMPs which saw device errors 24204c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 24214c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi = &ap->link.eh_info; 24224c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord for (pmp = 0; pmp_map != 0; pmp++) { 24234c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int this_pmp = (1 << pmp); 24244c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pmp_map & this_pmp) { 24254c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct ata_link *link = &ap->pmp_link[pmp]; 24264c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24274c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pmp_map &= ~this_pmp; 24284c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi = &link->eh_info; 24294c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_ehi_clear_desc(ehi); 24304c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_ehi_push_desc(ehi, "dev err"); 24314c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi->err_mask |= AC_ERR_DEV; 24324c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ehi->action |= ATA_EH_RESET; 24334c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_link_abort(link); 24344c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24354c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24364c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 24374c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 243806aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lordstatic int mv_req_q_empty(struct ata_port *ap) 243906aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord{ 244006aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 244106aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord u32 in_ptr, out_ptr; 244206aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord 2443cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR) 244406aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2445cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR) 244606aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 244706aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord return (in_ptr == out_ptr); /* 1 == queue_is_empty */ 244806aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord} 244906aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord 24504c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_fbs_ncq_dev_err(struct ata_port *ap) 24514c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 24524c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp = ap->private_data; 24534c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord int failed_links; 24544c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord unsigned int old_map, new_map; 24554c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24564c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 24574c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device error during FBS+NCQ operation: 24584c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 24594c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Set a port flag to prevent further I/O being enqueued. 24604c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Leave the EDMA running to drain outstanding commands from this port. 24614c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Perform the post-mortem/EH only when all responses are complete. 24624c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2). 24634c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 24644c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { 24654c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; 24664c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->delayed_eh_pmp_map = 0; 24674c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24684c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord old_map = pp->delayed_eh_pmp_map; 24694c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord new_map = old_map | mv_get_err_pmp_map(ap); 24704c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24714c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (old_map != new_map) { 24724c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord pp->delayed_eh_pmp_map = new_map; 24734c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_pmp_eh_prep(ap, new_map & ~old_map); 24744c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 2475c46938ccfe35a58a0873715ee4c26fc9eb8d87b3Mark Lord failed_links = hweight16(new_map); 24764c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24774c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x " 24784c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "failed_links=%d nr_active_links=%d\n", 24794c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, pp->delayed_eh_pmp_map, 24804c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ap->qc_active, failed_links, 24814c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ap->nr_active_links); 24824c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 248306aaca3f6301d04463b1ee0eb75c0352147159f2Mark Lord if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { 24844c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_process_crpb_entries(ap, pp); 24854c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_stop_edma(ap); 24864c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_eh_freeze(ap); 24874c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__); 24884c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 1; /* handled */ 24894c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 24904c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__); 24914c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 1; /* handled */ 24924c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 24934c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 24944c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap) 24954c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 24964c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 24974c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Possible future enhancement: 24984c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 24994c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * FBS+non-NCQ operation is not yet implemented. 25004c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * See related notes in mv_edma_cfg(). 25014c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 25024c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device error during FBS+non-NCQ operation: 25034c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * 25044c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * We need to snapshot the shadow registers for each failed command. 25054c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3). 25064c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 25074c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 25084c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 25094c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 25104c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lordstatic int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause) 25114c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord{ 25124c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord struct mv_port_priv *pp = ap->private_data; 25134c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 25144c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 25154c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* EDMA was not active: not handled */ 25164c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) 25174c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* FBS was not active: not handled */ 25184c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 25194c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(edma_err_cause & EDMA_ERR_DEV)) 25204c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* non DEV error: not handled */ 25214c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT; 25224c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS)) 25234c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* other problems: not handled */ 25244c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 25254c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { 25264c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 25274c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * EDMA should NOT have self-disabled for this case. 25284c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * If it did, then something is wrong elsewhere, 25294c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * and we cannot handle it here. 25304c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 25314c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & EDMA_ERR_SELF_DIS) { 25324c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_WARNING, 25334c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "%s: err_cause=0x%x pp_flags=0x%x\n", 25344c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, edma_err_cause, pp->pp_flags); 25354c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 25364c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 25374c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return mv_handle_fbs_ncq_dev_err(ap); 25384c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } else { 25394c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 25404c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * EDMA should have self-disabled for this case. 25414c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * If it did not, then something is wrong elsewhere, 25424c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * and we cannot handle it here. 25434c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 25444c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) { 25454c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord ata_port_printk(ap, KERN_WARNING, 25464c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord "%s: err_cause=0x%x pp_flags=0x%x\n", 25474c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord __func__, edma_err_cause, pp->pp_flags); 25484c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 25494c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 25504c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return mv_handle_fbs_non_ncq_dev_err(ap); 25514c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 25524c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return 0; /* not handled */ 25534c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord} 25544c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 2555a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lordstatic void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled) 25568f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 25578f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_eh_info *ehi = &ap->link.eh_info; 2558a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord char *when = "idle"; 25598f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 25608f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_ehi_clear_desc(ehi); 25613e4ec3443f70fbe144799ccf0b1c3797f78d1715Tejun Heo if (edma_was_enabled) { 2562a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "EDMA enabled"; 25638f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } else { 25648f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 25658f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 2566a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord when = "polling"; 25678f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } 2568a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when); 25698f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->err_mask |= AC_ERR_OTHER; 25708f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->action |= ATA_EH_RESET; 25718f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_port_freeze(ap); 25728f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 25738f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 257405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 257505b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_err_intr - Handle error interrupts on the port 257605b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 257705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 25788d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Most cases require a full reset of the chip's state machine, 25798d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * which also performs a COMRESET. 25808d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Also, if the port disabled DMA, update our cached copy to match. 258105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 258205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 258305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 258405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 258537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lordstatic void mv_err_intr(struct ata_port *ap) 258631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 258731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 2588bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 edma_err_cause, eh_freeze_mask, serr = 0; 2589e40060772d85f3534d3d517197696e24bb01f45bMark Lord u32 fis_cause = 0; 2590bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 2591bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2592bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int action = 0, err_mask = 0; 25939af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_eh_info *ehi = &ap->link.eh_info; 259437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord struct ata_queued_cmd *qc; 259537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord int abort = 0; 259620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25978d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord /* 259837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Read and clear the SError and err_cause bits. 2599e40060772d85f3534d3d517197696e24bb01f45bMark Lord * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear 2600e40060772d85f3534d3d517197696e24bb01f45bMark Lord * the FIS_IRQ_CAUSE register before clearing edma_err_cause. 26018d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord */ 260237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord sata_scr_read(&ap->link, SCR_ERROR, &serr); 260337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 260437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord 2605cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE); 2606e40060772d85f3534d3d517197696e24bb01f45bMark Lord if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2607cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord fis_cause = readl(port_mmio + FIS_IRQ_CAUSE); 2608cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE); 2609e40060772d85f3534d3d517197696e24bb01f45bMark Lord } 2610cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE); 2611bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 26124c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (edma_err_cause & EDMA_ERR_DEV) { 26134c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord /* 26144c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * Device errors during FIS-based switching operation 26154c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord * require special handling. 26164c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord */ 26174c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (mv_handle_dev_err(ap, edma_err_cause)) 26184c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord return; 26194c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord } 26204c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord 262137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord qc = mv_get_active_qc(ap); 262237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_clear_desc(ehi); 262337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x", 262437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord edma_err_cause, pp->pp_flags); 2625e40060772d85f3534d3d517197696e24bb01f45bMark Lord 2626c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2627e40060772d85f3534d3d517197696e24bb01f45bMark Lord ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause); 2628cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord if (fis_cause & FIS_IRQ_CAUSE_AN) { 2629c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord u32 ec = edma_err_cause & 2630c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT); 2631c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord sata_async_notification(ap); 2632c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord if (!ec) 2633c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord return; /* Just an AN; no need for the nukes */ 2634c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord ata_ehi_push_desc(ehi, "SDB notify"); 2635c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord } 2636c443c5002b24ff5d2f4efcc25a861f0cb835130aMark Lord } 2637bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 2638352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * All generations share these EDMA error cause bits: 2639bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 264037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (edma_err_cause & EDMA_ERR_DEV) { 2641bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_DEV; 264237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord action |= ATA_EH_RESET; 264337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_ehi_push_desc(ehi, "dev error"); 264437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 2645bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 26466c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 2647bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR)) { 2648bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_ATA_BUS; 2649cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2650b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "parity error"); 2651bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2652bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 2653bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_hotplugged(ehi); 2654bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 2655b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo "dev disconnect" : "dev connect"); 2656cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2657bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2658bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2659352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 2660352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Gen-I has a different SELF_DIS bit, 2661352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * different FREEZE bits, and no SERR bit: 2662352fab701ca4753dd005b67ce5e512be944eb591Mark Lord */ 2663ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) { 2664bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE_5; 2665bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 2666bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2667b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 2668bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2669bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 2670bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE; 2671bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS) { 2672bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2673b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 2674bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2675bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SERR) { 26768d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord ata_ehi_push_desc(ehi, "SError=%08x", serr); 26778d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord err_mask |= AC_ERR_ATA_BUS; 2678cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2679bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2680afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 268120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2682bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!err_mask) { 2683bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_OTHER; 2684cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 2685bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2686bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2687bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->serror |= serr; 2688bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->action |= action; 2689bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2690bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 2691bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 2692bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 2693bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 2694bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 269537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (err_mask == AC_ERR_DEV) { 269637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* 269737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Cannot do ata_port_freeze() here, 269837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * because it would kill PIO access, 269937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * which is needed for further diagnosis. 270037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord */ 270137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord mv_eh_freeze(ap); 270237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord abort = 1; 270337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } else if (edma_err_cause & eh_freeze_mask) { 270437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* 270537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord * Note to self: ata_port_freeze() calls ata_port_abort() 270637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord */ 2707bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 270837b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } else { 270937b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord abort = 1; 271037b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 271137b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord 271237b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (abort) { 271337b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (qc) 271437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_link_abort(qc->dev->link); 271537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord else 271637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_port_abort(ap); 271737b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord } 2718bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2719bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2720fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_response(struct ata_port *ap, 2721fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response, unsigned int tag, int ncq_enabled) 2722fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord{ 2723fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag); 2724fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 2725fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (qc) { 2726fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 ata_status; 2727fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u16 edma_status = le16_to_cpu(response->flags); 2728fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 2729fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * edma_status from a response queue entry: 2730cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only). 2731fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * MSB is saved ATA status from command completion. 2732fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 2733fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (!ncq_enabled) { 2734fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; 2735fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (err_cause) { 2736fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 2737fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * Error will be seen/handled by mv_err_intr(). 2738fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * So do nothing at all here. 2739fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 2740fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord return; 2741fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2742fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2743fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; 274437b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord if (!ac_err_mask(ata_status)) 274537b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord ata_qc_complete(qc); 274637b9046a3e433a0b0c39ad1e81ec187d5be800baMark Lord /* else: leave it for mv_err_intr() */ 2747fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 2748fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n", 2749fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord __func__, tag); 2750fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 2751fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord} 2752fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 2753fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) 2754bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2755bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 2756bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2757fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u32 in_index; 2758bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik bool work_done = false; 2759fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); 2760bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2761fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Get the hardware queue position index */ 2762cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR) 2763bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2764bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2765fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Process new responses from since the last time we looked */ 2766fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord while (in_index != pp->resp_idx) { 27676c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik unsigned int tag; 2768fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response = &pp->crpb[pp->resp_idx]; 2769bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2770fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2771bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2772fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (IS_GEN_I(hpriv)) { 2773fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 50xx: no NCQ, only one command active at a time */ 27749af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo tag = ap->link.active_tag; 2775fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 2776fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Gen II/IIE: get command tag from CRPB entry */ 2777fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord tag = le16_to_cpu(response->id) & 0x1f; 2778bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2779fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord mv_process_crpb_response(ap, response, tag, ncq_enabled); 2780bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik work_done = true; 2781bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2782bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2783352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Update the software queue position index in hardware */ 2784bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (work_done) 2785bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 2786fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), 2787cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port_mmio + EDMA_RSP_Q_OUT_PTR); 278820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 278920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2790a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lordstatic void mv_port_intr(struct ata_port *ap, u32 port_cause) 2791a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord{ 2792a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord struct mv_port_priv *pp; 2793a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord int edma_was_enabled; 2794a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord 2795a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2796a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Grab a snapshot of the EDMA_EN flag setting, 2797a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * so that we have a consistent view for this port, 2798a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * even if something we call of our routines changes it. 2799a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2800a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord pp = ap->private_data; 2801a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); 2802a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2803a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Process completed CRPB response(s) before other events. 2804a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2805a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (edma_was_enabled && (port_cause & DONE_IRQ)) { 2806a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_process_crpb_entries(ap, pp); 28074c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 28084c299ca3649ccf666819e7d4a27a68c39fa174f1Mark Lord mv_handle_fbs_ncq_dev_err(ap); 2809a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2810a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord /* 2811a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Handle chip-reported errors, or continue on to handle PIO. 2812a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord */ 2813a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (unlikely(port_cause & ERR_IRQ)) { 2814a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_err_intr(ap); 2815a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } else if (!edma_was_enabled) { 2816a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord struct ata_queued_cmd *qc = mv_get_active_qc(ap); 2817a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (qc) 2818a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord ata_sff_host_intr(ap, qc); 2819a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord else 2820a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_unexpected_intr(ap, edma_was_enabled); 2821a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord } 2822a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord} 2823a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord 282405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 282505b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_host_intr - Handle all interrupts on the given host controller 2826cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * @host: host specific structure 28277368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * @main_irq_cause: Main interrupt cause register for the chip. 282805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 282905b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 283005b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 283105b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 28327368f91926a2870a8c3f9546d86535ce71ae0757Mark Lordstatic int mv_host_intr(struct ata_host *host, u32 main_irq_cause) 283320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2834f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 2835eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord void __iomem *mmio = hpriv->base, *hc_mmio; 2836a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0, port; 283720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 28382b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord /* If asserted, clear the "all ports" IRQ coalescing bit */ 28392b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (main_irq_cause & ALL_PORTS_COAL_DONE) 2840cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); 28412b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord 2842a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord for (port = 0; port < hpriv->n_ports; port++) { 2843cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_port *ap = host->ports[port]; 2844eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord unsigned int p, shift, hardport, port_cause; 2845eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord 2846a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2847a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord /* 2848eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * Each hc within the host has its own hc_irq_cause register, 2849eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * where the interrupting ports bits get ack'd. 2850a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord */ 2851eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (hardport == 0) { /* first port on this hc ? */ 2852eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND; 2853eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord u32 port_mask, ack_irqs; 2854eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord /* 2855eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * Skip this entire hc if nothing pending for any ports 2856eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord */ 2857eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (!hc_cause) { 2858eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord port += MV_PORTS_PER_HC - 1; 2859eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord continue; 2860eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord } 2861eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord /* 2862eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * We don't need/want to read the hc_irq_cause register, 2863eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * because doing so hurts performance, and 2864eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * main_irq_cause already gives us everything we need. 2865eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * 2866eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * But we do have to *write* to the hc_irq_cause to ack 2867eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * the ports that we are handling this time through. 2868eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * 2869eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * This requires that we create a bitmap for those 2870eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * ports which interrupted us, and use that bitmap 2871eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord * to ack (only) those ports via hc_irq_cause. 2872eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord */ 2873eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord ack_irqs = 0; 28742b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord if (hc_cause & PORTS_0_3_COAL_DONE) 28752b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord ack_irqs = HC_COAL_IRQ; 2876eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord for (p = 0; p < MV_PORTS_PER_HC; ++p) { 2877eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if ((port + p) >= hpriv->n_ports) 2878eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord break; 2879eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2); 2880eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord if (hc_cause & port_mask) 2881eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord ack_irqs |= (DMA_IRQ | DEV_IRQ) << p; 2882eabd5eb1cb59bfb162e7aa23007248f2bb480816Mark Lord } 2883a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord hc_mmio = mv_hc_base_from_port(mmio, port); 2884cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE); 2885a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = 1; 2886a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord } 28878f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord /* 2888a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord * Handle interrupts signalled for this port: 28898f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord */ 2890a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ); 2891a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord if (port_cause) 2892a90103298fd5ccd9a9df6d47bde9a3f371707037Mark Lord mv_port_intr(ap, port_cause); 289320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 2894a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return handled; 289520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 289620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2897a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lordstatic int mv_pci_error(struct ata_host *host, void __iomem *mmio) 2898bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 289902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 2900bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_port *ap; 2901bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 2902bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_eh_info *ehi; 2903bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int i, err_mask, printed = 0; 2904bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 err_cause; 2905bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2906cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord err_cause = readl(mmio + hpriv->irq_cause_offset); 2907bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2908bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", 2909bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_cause); 2910bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2911bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik DPRINTK("All regs @ PCI error\n"); 2912bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 2913bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2914cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, mmio + hpriv->irq_cause_offset); 2915bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2916bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik for (i = 0; i < host->n_ports; i++) { 2917bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ap = host->ports[i]; 2918936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo if (!ata_link_offline(&ap->link)) { 29199af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo ehi = &ap->link.eh_info; 2920bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 2921bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!printed++) 2922bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, 2923bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik "PCI err cause 0x%08x", err_cause); 2924bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_HOST_BUS; 2925cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo ehi->action = ATA_EH_RESET; 29269af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 2927bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 2928bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 2929bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 2930bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 2931bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2932bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 2933bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2934bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 2935a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return 1; /* handled */ 2936bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2937bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 293805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2939c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * mv_interrupt - Main interrupt event handler 294005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @irq: unused 294105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @dev_instance: private data; in this case the host structure 294205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 294305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read the read only register to determine if any host 294405b308e1df6d9d673daedb517969241f41278b52Brett Russ * controllers have pending interrupts. If so, call lower level 294505b308e1df6d9d673daedb517969241f41278b52Brett Russ * routine to handle. Also check for PCI errors which are only 294605b308e1df6d9d673daedb517969241f41278b52Brett Russ * reported here. 294705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 29488b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * LOCKING: 2949cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine holds the host lock while processing pending 295005b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts. 295105b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 29527d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t mv_interrupt(int irq, void *dev_instance) 295320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2954cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = dev_instance; 2955f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 2956a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0; 29576d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI; 295896e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord u32 main_irq_cause, pending_irqs; 295920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2960646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord spin_lock(&host->lock); 29616d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 29626d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord /* for MSI: block new interrupts while in here */ 29636d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord if (using_msi) 29642b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_write_main_irq_mask(0, hpriv); 29656d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 29667368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_cause = readl(hpriv->main_irq_cause_addr); 296796e2c487933e5f69e98fffdcae2c35c78a671c07Mark Lord pending_irqs = main_irq_cause & hpriv->main_irq_mask; 2968352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 2969352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Deal with cases where we either have nothing pending, or have read 2970352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * a bogus register value which can indicate HW removal or PCI fault. 297120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2972a44253d24a97ec3efe601267274a5fb64d8696c1Mark Lord if (pending_irqs && main_irq_cause != 0xffffffffU) { 29731f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv))) 2974a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = mv_pci_error(host, hpriv->base); 2975a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord else 2976a44253d24a97ec3efe601267274a5fb64d8696c1Mark Lord handled = mv_host_intr(host, pending_irqs); 2977bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 29786d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 29796d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord /* for MSI: unmask; interrupt cause bits will retrigger now */ 29806d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord if (using_msi) 29812b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv); 29826d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord 29839d51af7bd2f1d730cb6eeeb9ff837e3441ad4e07Mark Lord spin_unlock(&host->lock); 29849d51af7bd2f1d730cb6eeeb9ff837e3441ad4e07Mark Lord 298520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return IRQ_RETVAL(handled); 298620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 298720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2988c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic unsigned int mv5_scr_offset(unsigned int sc_reg_in) 2989c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2990c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs; 2991c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2992c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik switch (sc_reg_in) { 2993c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_STATUS: 2994c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_ERROR: 2995c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_CONTROL: 2996c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = sc_reg_in * sizeof(u32); 2997c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 2998c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik default: 2999c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = 0xffffffffU; 3000c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 3001c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 3002c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return ofs; 3003c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3004c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 300582ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 3006c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 300782ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo struct mv_host_priv *hpriv = link->ap->host->private_data; 3008f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 300982ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 3010c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 3011c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3012da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 3013da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(addr + ofs); 3014da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 3015da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 3016da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 3017c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3018c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 301982ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heostatic int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 3020c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 302182ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo struct mv_host_priv *hpriv = link->ap->host->private_data; 3022f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 302382ef04fb4c82542b3eda81cca461f0594ce9cd0bTejun Heo void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 3024c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 3025c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3026da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 30270d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo writelfl(val, addr + ofs); 3028da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 3029da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 3030da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 3031c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3032c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 30337bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 3034522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 30357bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara struct pci_dev *pdev = to_pci_dev(host->dev); 3036522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik int early_5080; 3037522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 303844c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 3039522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3040522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik if (!early_5080) { 3041522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 3042522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= (1 << 0); 3043522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 3044522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik } 3045522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 30467bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara mv_reset_pci_bus(host, mmio); 3047522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 3048522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3049522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 3050522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 3051cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x0fcfffff, mmio + FLASH_CTL); 3052522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 3053522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 305447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 3055ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 3056ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 3057c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 3058c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 3059c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3060c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 3061c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3062c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 3063c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 3064ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3065ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 306647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 3067ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 3068522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp; 3069522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3070cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0, mmio + GPIO_PORT_CTL); 3071522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3072522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 3073522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 3074522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 3075522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= ~(1 << 0); 3076522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 3077ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3078ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 30792a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 30802a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 3081bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 3082c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, port); 3083c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 3084c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 3085c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 3086c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3087c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik if (fix_apm_sq) { 3088cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(phy_mmio + MV5_LTMODE); 3089c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= (1 << 19); 3090cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(tmp, phy_mmio + MV5_LTMODE); 3091c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3092cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(phy_mmio + MV5_PHY_CTL); 3093c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~0x3; 3094c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x1; 3095cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(tmp, phy_mmio + MV5_PHY_CTL); 3096c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 3097c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3098c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 3099c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~mask; 3100c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].pre; 3101c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].amps; 3102c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_MODE); 3103bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 3104bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3105c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3106c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 3107c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, port_mmio + (reg)) 3108c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 3109c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 3110c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 3111c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 3112c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3113e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 3114c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3115c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x028); /* command */ 3116cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x11f, port_mmio + EDMA_CFG); 3117c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x004); /* timer */ 3118c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x008); /* irq err cause */ 3119c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); /* irq err mask */ 3120c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); /* rq bah */ 3121c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); /* rq inp */ 3122c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); /* rq outp */ 3123c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x01c); /* respq bah */ 3124c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x024); /* respq outp */ 3125c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x020); /* respq inp */ 3126c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x02c); /* test control */ 3127cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 3128c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3129c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 3130c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3131c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, hc_mmio + (reg)) 3132c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3133c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc) 313447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik{ 3135c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 3136c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 3137c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3138c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); 3139c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); 3140c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); 3141c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); 3142c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3143c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(hc_mmio + 0x20); 3144c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= 0x1c1c1c1c; 3145c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x03030303; 3146c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, hc_mmio + 0x20); 3147c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3148c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 3149c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3150c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3151c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 3152c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 3153c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc, port; 3154c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3155c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (hc = 0; hc < n_hc; hc++) { 3156c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (port = 0; port < MV_PORTS_PER_HC; port++) 3157c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_hc_port(hpriv, mmio, 3158c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (hc * MV_PORTS_PER_HC) + port); 3159c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3160c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_one_hc(hpriv, mmio, hc); 3161c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 3162c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3163c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return 0; 316447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik} 316547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 3166101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 3167101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#define ZERO(reg) writel(0, mmio + (reg)) 31687bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 3169101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 317002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 3171101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 3172101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3173cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(mmio + MV_PCI_MODE); 3174101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0xff00ffff; 3175cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(tmp, mmio + MV_PCI_MODE); 3176101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3177101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_DISC_TIMER); 3178101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_MSI_TRIGGER); 3179cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); 3180101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_SERR_MASK); 3181cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ZERO(hpriv->irq_cause_offset); 3182cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord ZERO(hpriv->irq_mask_offset); 3183101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_LOW_ADDRESS); 3184101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_HIGH_ADDRESS); 3185101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_ATTRIBUTE); 3186101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_COMMAND); 3187101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 3188101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 3189101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3190101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 3191101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 3192101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 3193101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3194101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik mv5_reset_flash(hpriv, mmio); 3195101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3196cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(mmio + GPIO_PORT_CTL); 3197101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0x3; 3198101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp |= (1 << 5) | (1 << 6); 3199cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(tmp, mmio + GPIO_PORT_CTL); 3200101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 3201101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3202101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik/** 3203101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * mv6_reset_hc - Perform the 6xxx global soft reset 3204101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * @mmio: base address of the HBA 3205101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 3206101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * This routine only applies to 6xxx parts. 3207101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 3208101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * LOCKING: 3209101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * Inherited from caller. 3210101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 3211c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3212c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 3213101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 3214cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord void __iomem *reg = mmio + PCI_MAIN_CMD_STS; 3215101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik int i, rc = 0; 3216101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 t; 3217101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3218101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* Following procedure defined in PCI "main command and status 3219101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * register" table. 3220101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 3221101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 3222101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | STOP_PCI_MASTER, reg); 3223101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3224101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik for (i = 0; i < 1000; i++) { 3225101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 3226101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 32272dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik if (PCI_MASTER_EMPTY & t) 3228101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik break; 3229101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3230101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(PCI_MASTER_EMPTY & t)) { 3231101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 3232101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 3233101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 3234101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3235101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3236101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* set reset */ 3237101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 3238101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 3239101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | GLOB_SFT_RST, reg); 3240101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 3241101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 3242101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 3243101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3244101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(GLOB_SFT_RST & t)) { 3245101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 3246101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 3247101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 3248101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3249101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3250101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 3251101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 3252101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 3253101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 3254101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 3255101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 3256101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while ((GLOB_SFT_RST & t) && (i-- > 0)); 3257101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 3258101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (GLOB_SFT_RST & t) { 3259101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 3260101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 3261101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 3262101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikdone: 3263101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik return rc; 3264101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 3265101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 326647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 3267ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 3268ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 3269ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *port_mmio; 3270ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik u32 tmp; 3271ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3272cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord tmp = readl(mmio + RESET_CFG); 3273ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik if ((tmp & (1 << 0)) == 0) { 327447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->signal[idx].amps = 0x7 << 8; 3275ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = 0x1 << 5; 3276ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik return; 3277ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik } 3278ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3279ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik port_mmio = mv_port_base(mmio, idx); 3280ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(port_mmio + PHY_MODE2); 3281ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3282ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3283ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3284ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3285ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 328647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 3287ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 3288cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x00000060, mmio + GPIO_PORT_CTL); 3289ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 3290ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 3291c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 32922a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 3293bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 3294c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 3295c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3296bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 329747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik int fix_phy_mode2 = 329847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 3299bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik int fix_phy_mode4 = 330047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 33018c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord u32 m2, m3; 330247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 330347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (fix_phy_mode2) { 330447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 330547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 330647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 |= (1 << 31); 330747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 330847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 330947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 331047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 331147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 331247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~((1 << 16) | (1 << 31)); 331347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 331447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 331547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 331647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 331747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 33188c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord /* 33198c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord * Gen-II/IIe PHY_MODE3 errata RM#2: 33208c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord * Achieves better receiver noise performance than the h/w default: 33218c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord */ 33228c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord m3 = readl(port_mmio + PHY_MODE3); 33238c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord m3 = (m3 & 0x1f) | (0x5555601 << 5); 3324bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 33250388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord /* Guideline 88F5182 (GL# SATA-S11) */ 33260388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord if (IS_SOC(hpriv)) 33270388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord m3 &= ~0x1c; 33280388a8c0d54aa039758a8eca68d82325a563f8dbMark Lord 3329bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (fix_phy_mode4) { 3330ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord u32 m4 = readl(port_mmio + PHY_MODE4); 3331ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord /* 3332ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * Enforce reserved-bit restrictions on GenIIe devices only. 3333ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * For earlier chipsets, force only the internal config field 3334ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord * (workaround for errata FEr SATA#10 part 1). 3335ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord */ 33368c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord if (IS_GEN_IIE(hpriv)) 3337ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES; 3338ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord else 3339ba069e376cc0801cd28352ca5986ce20413acb21Mark Lord m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE; 33408c30a8b9b574cf6c51e207464b852a6f559da153Mark Lord writel(m4, port_mmio + PHY_MODE4); 3341bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3342b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord /* 3343b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * Workaround for 60x1-B2 errata SATA#13: 3344b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3, 3345b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord * so we must always rewrite PHY_MODE3 after PHY_MODE4. 3346ba68460b8e019dfd9c73ab69f5ed163a8b24e296Mark Lord * Or ensure we use writelfl() when writing PHY_MODE4. 3347b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord */ 3348b406c7a6655da7a2fcd9f72e41262f93ff707748Mark Lord writel(m3, port_mmio + PHY_MODE3); 3349bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3350bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik /* Revert values of pre-emphasis and signal amps to the saved ones */ 3351bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 3352bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3353bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 &= ~MV_M2_PREAMP_MASK; 33542a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].amps; 33552a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].pre; 335647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 3357bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3358e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* according to mvSata 3.6.1, some IIE values are fixed */ 3359e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (IS_GEN_IIE(hpriv)) { 3360e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 &= ~0xC30FF01F; 3361e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 |= 0x0000900F; 3362e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 3363e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 3364bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 3365bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 3366bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3367f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* TODO: use the generic LED interface to configure the SATA Presence */ 3368f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* & Acitivy LEDs on the board */ 3369f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 3370f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3371f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3372f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 3373f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3374f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3375f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 3376f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3377f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3378f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio; 3379f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara u32 tmp; 3380f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3381f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara port_mmio = mv_port_base(mmio, idx); 3382f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(port_mmio + PHY_MODE2); 3383f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3384f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3385f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3386f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3387f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3388f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 3389f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, port_mmio + (reg)) 3390f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 3391f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int port) 3392f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3393f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio = mv_port_base(mmio, port); 3394f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3395e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 3396f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3397f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x028); /* command */ 3398cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0x101f, port_mmio + EDMA_CFG); 3399f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x004); /* timer */ 3400f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x008); /* irq err cause */ 3401f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); /* irq err mask */ 3402f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); /* rq bah */ 3403f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); /* rq inp */ 3404f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x018); /* rq outp */ 3405f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x01c); /* respq bah */ 3406f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x024); /* respq outp */ 3407f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x020); /* respq inp */ 3408f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x02c); /* test control */ 3409d7b0c143693bcbf391d2be235e150b97bfd8f9baSaeed Bishara writel(0x800, port_mmio + EDMA_IORDY_TMOUT); 3410f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3411f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3412f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 3413f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3414f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, hc_mmio + (reg)) 3415f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 3416f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3417f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3418f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *hc_mmio = mv_hc_base(mmio, 0); 3419f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3420f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); 3421f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); 3422f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); 3423f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3424f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3425f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3426f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 3427f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3428f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 3429f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc) 3430f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3431f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int port; 3432f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3433f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara for (port = 0; port < hpriv->n_ports; port++) 3434f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_hc_port(hpriv, mmio, port); 3435f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3436f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_one_hc(hpriv, mmio); 3437f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3438f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 3439f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3440f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3441f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 3442f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 3443f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3444f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 3445f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3446f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3447f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 3448f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 3449f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 3450f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3451f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 345229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayrstatic void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, 345329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr void __iomem *mmio, unsigned int port) 345429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr{ 345529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr void __iomem *port_mmio = mv_port_base(mmio, port); 345629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr u32 reg; 345729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 345829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg = readl(port_mmio + PHY_MODE3); 345929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */ 346029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg |= (0x1 << 27); 346129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */ 346229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg |= (0x1 << 29); 346329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr writel(reg, port_mmio + PHY_MODE3); 346429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 346529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg = readl(port_mmio + PHY_MODE4); 346629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */ 346729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg |= (0x1 << 16); 346829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr writel(reg, port_mmio + PHY_MODE4); 346929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 347029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg = readl(port_mmio + PHY_MODE9_GEN2); 347129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */ 347229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg |= 0x8; 347329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */ 347429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr writel(reg, port_mmio + PHY_MODE9_GEN2); 347529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 347629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg = readl(port_mmio + PHY_MODE9_GEN1); 347729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */ 347829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg |= 0x8; 347929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */ 348029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr writel(reg, port_mmio + PHY_MODE9_GEN1); 348129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr} 348229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 348329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr/** 348429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr * soc_is_65 - check if the soc is 65 nano device 348529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr * 348629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr * Detect the type of the SoC, this is done by reading the PHYCFG_OFS 348729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr * register, this register should contain non-zero value and it exists only 348829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr * in the 65 nano devices, when reading it from older devices we get 0. 348929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr */ 349029b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayrstatic bool soc_is_65n(struct mv_host_priv *hpriv) 349129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr{ 349229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr void __iomem *port0_mmio = mv_port_base(hpriv->base, 0); 349329b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 349429b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr if (readl(port0_mmio + PHYCFG_OFS)) 349529b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr return true; 349629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr return false; 349729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr} 349829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr 34998e7decdb8b132ee970a2636931b7653dec6af472Mark Lordstatic void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) 3500b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord{ 3501cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 ifcfg = readl(port_mmio + SATA_IFCFG); 3502b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 35038e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */ 3504b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (want_gen2i) 35058e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg |= (1 << 7); /* enable gen2i speed */ 3506cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(ifcfg, port_mmio + SATA_IFCFG); 3507b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord} 3508b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 3509e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 3510c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no) 3511c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 3512c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port_no); 3513c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 35148e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* 35158e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * The datasheet warns against setting EDMA_RESET when EDMA is active 35168e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * (but doesn't say what the problem might be). So we first try 35178e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * to disable the EDMA engine before doing the EDMA_RESET operation. 35188e7decdb8b132ee970a2636931b7653dec6af472Mark Lord */ 35190d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord mv_stop_edma_engine(port_mmio); 3520cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD); 3521c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3522b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (!IS_GEN_I(hpriv)) { 35238e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* Enable 3.0gb/s link speed: this survives EDMA_RESET */ 35248e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(port_mmio, 1); 3525c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 3526b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord /* 35278e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * Strobing EDMA_RESET here causes a hard reset of the SATA transport, 3528b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * link, and physical layers. It resets all SATA interface registers 3529cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord * (except for SATA_IFCFG), and issues a COMRESET to the dev. 3530c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik */ 3531cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD); 3532b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord udelay(25); /* allow reset propagation */ 3533cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, port_mmio + EDMA_CMD); 3534c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3535c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->ops->phy_errata(hpriv, mmio, port_no); 3536c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3537ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) 3538c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mdelay(1); 3539c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 3540c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 3541e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp) 354220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 3543e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (sata_pmp_supported(ap)) { 3544e49856d82a887ce365637176f9f99ab68076eae8Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 3545cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 reg = readl(port_mmio + SATA_IFCTL); 3546e49856d82a887ce365637176f9f99ab68076eae8Mark Lord int old = reg & 0xf; 354722374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 3548e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (old != pmp) { 3549e49856d82a887ce365637176f9f99ab68076eae8Mark Lord reg = (reg & ~0xf) | pmp; 3550cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(reg, port_mmio + SATA_IFCTL); 3551e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 355222374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik } 355320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 355420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3555e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 3556e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 355722374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik{ 3558e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 3559e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return sata_std_hardreset(link, class, deadline); 3560e49856d82a887ce365637176f9f99ab68076eae8Mark Lord} 3561bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3562e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 3563e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 3564e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 3565e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 3566e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return ata_sff_softreset(link, class, deadline); 356722374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik} 356822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 3569cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 3570bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned long deadline) 357131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 3572cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo struct ata_port *ap = link->ap; 3573bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 3574b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 3575f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 35760d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord int rc, attempts = 0, extra = 0; 35770d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord u32 sstatus; 35780d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord bool online; 357931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3580e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, ap->port_no); 3581b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 3582d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord pp->pp_flags &= 3583d16ab3f633b75aac1cf42b00355cd9aa65033dccMark Lord ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 3584bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 35850d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Workaround for errata FEr SATA#10 (part 2) */ 35860d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord do { 358717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord const unsigned long *timing = 358817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord sata_ehc_deb_timing(&link->eh_context); 3589bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 359017c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord rc = sata_link_hardreset(link, timing, deadline + extra, 359117c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord &online, NULL); 35929dcffd99d0b1c0c1b8b2c0f85d240e791eca1055Mark Lord rc = online ? -EAGAIN : rc; 359317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord if (rc) 35940d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord return rc; 35950d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord sata_scr_read(link, SCR_STATUS, &sstatus); 35960d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 35970d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Force 1.5gb/s link speed and try again */ 35988e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(mv_ap_base(ap), 0); 35990d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (time_after(jiffies + HZ, deadline)) 36000d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord extra = HZ; /* only extend it once, max */ 36010d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } 36020d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); 360308da175937a35d34a83eaefbb3458472eb1a89d4Mark Lord mv_save_cached_regs(ap); 360466e57a2cb0c538d4f84a7233c224735fe1eaa672Mark Lord mv_edma_cfg(ap, 0, 0); 3605bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 360617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord return rc; 3607bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 3608bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3609bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap) 3610bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 36111cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord mv_stop_edma(ap); 3612c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_enable_port_irqs(ap, 0); 3613bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 3614bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3615bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap) 3616bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 3617f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 3618c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int port = ap->port_no; 3619c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord unsigned int hardport = mv_hardport_from_port(port); 36201cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); 3621bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 3622c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord u32 hc_irq_cause; 3623bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3624bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA errors on this port */ 3625cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 3626bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 3627bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear pending irq events */ 3628cae6edc3b5a536119374a5439d9b253cb26f05e1Mark Lord hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 3629cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); 3630bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 363188e675e193159b9891c1c576de4348eaf490f5d0Mark Lord mv_enable_port_irqs(ap, ERR_IRQ); 363231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 363331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 363405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 363505b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_init - Perform some early initialization on a single port. 363605b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port: libata data structure storing shadow register addresses 363705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port_mmio: base address of the port 363805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 363905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Initialize shadow register mmio addresses, clear outstanding 364005b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts on the port, and unmask interrupts for the future 364105b308e1df6d9d673daedb517969241f41278b52Brett Russ * start of the port. 364205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 364305b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 364405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 364505b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 364631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 364720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 3648cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord void __iomem *serr, *shd_base = port_mmio + SHD_BLK; 364931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 36508b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik /* PIO related setup 365131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 365231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 36538b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->error_addr = 365431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 365531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 365631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 365731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 365831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 365931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 36608b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->status_addr = 366131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 366231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* special case: control/altstatus doesn't have ATA_REG_ address */ 3663cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST; 366431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 366531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding port interrupt conditions */ 3666cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord serr = port_mmio + mv_scr_offset(SCR_ERROR); 3667cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(readl(serr), serr); 3668cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 366931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3670646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord /* unmask all non-transient EDMA error interrupts */ 3671cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK); 367220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 36738b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 3674cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(port_mmio + EDMA_CFG), 3675cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(port_mmio + EDMA_ERR_IRQ_CAUSE), 3676cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(port_mmio + EDMA_ERR_IRQ_MASK)); 367720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 367820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3679616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic unsigned int mv_in_pcix_mode(struct ata_host *host) 3680616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 3681616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 3682616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 3683616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 3684616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 36851f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (IS_SOC(hpriv) || !IS_PCIE(hpriv)) 3686616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not PCI-X capable */ 3687cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord reg = readl(mmio + MV_PCI_MODE); 3688616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if ((reg & MV_PCI_MODE_MASK) == 0) 3689616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* conventional PCI mode */ 3690616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* chip is in PCI-X mode */ 3691616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 3692616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 3693616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic int mv_pci_cut_through_okay(struct ata_host *host) 3694616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 3695616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 3696616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 3697616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 3698616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 3699616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (!mv_in_pcix_mode(host)) { 3700cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord reg = readl(mmio + MV_PCI_COMMAND); 3701cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord if (reg & MV_PCI_COMMAND_MRDTRIG) 3702616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not okay */ 3703616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord } 3704616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* okay */ 3705616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 3706616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 370765ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lordstatic void mv_60x1b2_errata_pci7(struct ata_host *host) 370865ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord{ 370965ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord struct mv_host_priv *hpriv = host->private_data; 371065ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord void __iomem *mmio = hpriv->base; 371165ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord 371265ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord /* workaround for 60x1-B2 errata PCI#7 */ 371365ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord if (mv_in_pcix_mode(host)) { 3714cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord u32 reg = readl(mmio + MV_PCI_COMMAND); 3715cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND); 371665ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord } 371765ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord} 371865ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord 37194447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_chip_id(struct ata_host *host, unsigned int board_idx) 3720bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 37214447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 37224447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 3723bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 3724bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 37255796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik switch (board_idx) { 372647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case chip_5080: 372747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 3728ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 372947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 373044c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 373147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x1: 373247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 373347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 373447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 373547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 373647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 373747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 373847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 373947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying 50XXB2 workarounds to unknown rev\n"); 374047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 374147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 374247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 374347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 374447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 3745bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_504x: 3746bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_508x: 374747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 3748ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 3749bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 375044c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 375147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x0: 375247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 375347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 375447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 375547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 375647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 375747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 375847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 375947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 376047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 376147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 3762bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3763bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3764bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3765bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_604x: 3766bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_608x: 376747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv6xxx_ops; 3768ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_II; 376947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 377044c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 377147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x7: 377265ad7fef10b50b6c06d6165fa847e2d3636b0a66Mark Lord mv_60x1b2_errata_pci7(host); 377347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 377447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 377547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x9: 377647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3777bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3778bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 3779bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 378047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 378147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 3782bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3783bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3784bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 3785bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3786e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_7042: 3787616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH; 3788306b30f74d37f289033c696285e07ce0158a5d7bMark Lord if (pdev->vendor == PCI_VENDOR_ID_TTI && 3789306b30f74d37f289033c696285e07ce0158a5d7bMark Lord (pdev->device == 0x2300 || pdev->device == 0x2310)) 3790306b30f74d37f289033c696285e07ce0158a5d7bMark Lord { 37914e5200334e03e5620aa19d538300c13db270a063Mark Lord /* 37924e5200334e03e5620aa19d538300c13db270a063Mark Lord * Highpoint RocketRAID PCIe 23xx series cards: 37934e5200334e03e5620aa19d538300c13db270a063Mark Lord * 37944e5200334e03e5620aa19d538300c13db270a063Mark Lord * Unconfigured drives are treated as "Legacy" 37954e5200334e03e5620aa19d538300c13db270a063Mark Lord * by the BIOS, and it overwrites sector 8 with 37964e5200334e03e5620aa19d538300c13db270a063Mark Lord * a "Lgcy" metadata block prior to Linux boot. 37974e5200334e03e5620aa19d538300c13db270a063Mark Lord * 37984e5200334e03e5620aa19d538300c13db270a063Mark Lord * Configured drives (RAID or JBOD) leave sector 8 37994e5200334e03e5620aa19d538300c13db270a063Mark Lord * alone, but instead overwrite a high numbered 38004e5200334e03e5620aa19d538300c13db270a063Mark Lord * sector for the RAID metadata. This sector can 38014e5200334e03e5620aa19d538300c13db270a063Mark Lord * be determined exactly, by truncating the physical 38024e5200334e03e5620aa19d538300c13db270a063Mark Lord * drive capacity to a nice even GB value. 38034e5200334e03e5620aa19d538300c13db270a063Mark Lord * 38044e5200334e03e5620aa19d538300c13db270a063Mark Lord * RAID metadata is at: (dev->n_sectors & ~0xfffff) 38054e5200334e03e5620aa19d538300c13db270a063Mark Lord * 38064e5200334e03e5620aa19d538300c13db270a063Mark Lord * Warn the user, lest they think we're just buggy. 38074e5200334e03e5620aa19d538300c13db270a063Mark Lord */ 38084e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 38094e5200334e03e5620aa19d538300c13db270a063Mark Lord " BIOS CORRUPTS DATA on all attached drives," 38104e5200334e03e5620aa19d538300c13db270a063Mark Lord " regardless of if/how they are configured." 38114e5200334e03e5620aa19d538300c13db270a063Mark Lord " BEWARE!\n"); 38124e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": For data safety, do not" 38134e5200334e03e5620aa19d538300c13db270a063Mark Lord " use sectors 8-9 on \"Legacy\" drives," 38144e5200334e03e5620aa19d538300c13db270a063Mark Lord " and avoid the final two gigabytes on" 38154e5200334e03e5620aa19d538300c13db270a063Mark Lord " all RocketRAID BIOS initialized drives.\n"); 3816306b30f74d37f289033c696285e07ce0158a5d7bMark Lord } 38178e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* drop through */ 3818e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_6042: 3819e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hpriv->ops = &mv6xxx_ops; 3820e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_GEN_IIE; 3821616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (board_idx == chip_6042 && mv_pci_cut_through_okay(host)) 3822616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_CUT_THROUGH; 3823e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 382444c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 38255cf73bfb061552aa18d816d2859409be9ace5306Mark Lord case 0x2: /* Rev.B0: the first/only public release */ 3826e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3827e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3828e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik default: 3829e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 3830e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik "Applying 60X1C0 workarounds to unknown rev\n"); 3831e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 3832e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3833e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 3834e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 3835f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara case chip_soc: 383629b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr if (soc_is_65n(hpriv)) 383729b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr hpriv->ops = &mv_soc_65n_ops; 383829b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr else 383929b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr hpriv->ops = &mv_soc_ops; 3840eb3a55a9f43f0f8e770c2abf70e65bdda2d5ff1eSaeed Bishara hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE | 3841eb3a55a9f43f0f8e770c2abf70e65bdda2d5ff1eSaeed Bishara MV_HP_ERRATA_60X1C0; 3842f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara break; 3843e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 3844bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 3845f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_ERR, host->dev, 38465796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik "BUG: invalid board index %u\n", board_idx); 3847bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 1; 3848bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 3849bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3850bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik hpriv->hp_flags = hp_flags; 385102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord if (hp_flags & MV_HP_PCIE) { 3852cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->irq_cause_offset = PCIE_IRQ_CAUSE; 3853cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->irq_mask_offset = PCIE_IRQ_MASK; 385402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 385502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } else { 3856cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->irq_cause_offset = PCI_IRQ_CAUSE; 3857cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->irq_mask_offset = PCI_IRQ_MASK; 385802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 385902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } 3860bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 3861bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 0; 3862bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 3863bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 386405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 386547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik * mv_init_host - Perform some early initialization of the host. 38664447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to initialize 386705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 386805b308e1df6d9d673daedb517969241f41278b52Brett Russ * If possible, do an early global reset of the host. Then do 386905b308e1df6d9d673daedb517969241f41278b52Brett Russ * our port init and clear/unmask all/relevant host interrupts. 387005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 387105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 387205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 387305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 38741bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bisharastatic int mv_init_host(struct ata_host *host) 387520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 387620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ int rc = 0, n_hc, port, hc; 38774447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 3878f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 387947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 38801bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bishara rc = mv_chip_id(host, hpriv->board_idx); 3881bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (rc) 3882352fab701ca4753dd005b67ce5e512be944eb591Mark Lord goto done; 3883f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 38841f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord if (IS_SOC(hpriv)) { 3885cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE; 3886cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK; 38871f39847255a02c69190ae30c33b8ccf4c10840dfMark Lord } else { 3888cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE; 3889cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK; 3890f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 3891352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 38925d0fb2e730e2085021cf5c8b6d14983e92aea75bThomas Reitmayr /* initialize shadow irq mask with register's value */ 38935d0fb2e730e2085021cf5c8b6d14983e92aea75bThomas Reitmayr hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr); 38945d0fb2e730e2085021cf5c8b6d14983e92aea75bThomas Reitmayr 3895352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* global interrupt mask: 0 == mask everything */ 3896c4de573b14d78ac83861d81d12977457d1e9cb6dMark Lord mv_set_main_irq_mask(host, ~0, 0); 3897bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 38984447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_hc = mv_get_hc_count(host->ports[0]->flags); 3899bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 39004447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) 390129b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr if (hpriv->ops->read_preamp) 390229b7e43c310bdc20d240c7674d9073f6c1c12a3fMartin Michlmayr hpriv->ops->read_preamp(hpriv, port, mmio); 390320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3904c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 390547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (rc) 390620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ goto done; 390720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3908522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik hpriv->ops->reset_flash(hpriv, mmio); 39097bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara hpriv->ops->reset_bus(host, mmio); 391047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->enable_leds(hpriv, mmio); 391120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 39124447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) { 3913cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo struct ata_port *ap = host->ports[port]; 39142a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 3915cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 3916cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo mv_port_init(&ap->ioaddr, port_mmio); 391720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 391820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 391920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hc; hc++) { 392031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 392131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 392231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 392331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ "(before clear)=0x%08x\n", hc, 3924cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(hc_mmio + HC_CFG), 3925cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord readl(hc_mmio + HC_IRQ_CAUSE)); 392631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 392731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding hc interrupt conditions */ 3928cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, hc_mmio + HC_IRQ_CAUSE); 392920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 393020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 393144c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord if (!IS_SOC(hpriv)) { 393244c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord /* Clear any currently outstanding host interrupt conditions */ 3933cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(0, mmio + hpriv->irq_cause_offset); 393431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 393544c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord /* and unmask interrupt generation for host regs */ 3936cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset); 393744c65d169c5d2e5c872581ebc65f12710d7c3b71Mark Lord } 393851de32d200b21333950abc52ea1e589bc4eecef7Mark Lord 39396be96ac15e4d913e1f48299db083ada5321803b2Mark Lord /* 39406be96ac15e4d913e1f48299db083ada5321803b2Mark Lord * enable only global host interrupts for now. 39416be96ac15e4d913e1f48299db083ada5321803b2Mark Lord * The per-port interrupts get done later as ports are set up. 39426be96ac15e4d913e1f48299db083ada5321803b2Mark Lord */ 39436be96ac15e4d913e1f48299db083ada5321803b2Mark Lord mv_set_main_irq_mask(host, 0, PCI_ERR); 39442b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord mv_set_irq_coalescing(host, irq_coalescing_io_count, 39452b748a0a344847fe6b924407bbe153e1878c9f09Mark Lord irq_coalescing_usecs); 3946f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharadone: 3947f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3948f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 3949fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik 3950fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradleystatic int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 3951fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley{ 3952fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 3953fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRQB_Q_SZ, 0); 3954fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crqb_pool) 3955fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3956fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3957fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 3958fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRPB_Q_SZ, 0); 3959fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crpb_pool) 3960fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3961fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3962fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 3963fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_SG_TBL_SZ, 0); 3964fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->sg_tbl_pool) 3965fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 3966fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 3967fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return 0; 3968fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley} 3969fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 397015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhekstatic void mv_conf_mbus_windows(struct mv_host_priv *hpriv, 397115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_target_info *dram) 397215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek{ 397315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek int i; 397415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 397515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < 4; i++) { 397615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_CTRL(i)); 397715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_BASE(i)); 397815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 397915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 398015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < dram->num_cs; i++) { 398115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_window *cs = dram->cs + i; 398215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 398315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(((cs->size - 1) & 0xffff0000) | 398415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (cs->mbus_attr << 8) | 398515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (dram->mbus_dram_target_id << 4) | 1, 398615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek hpriv->base + WINDOW_CTRL(i)); 398715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(cs->base, hpriv->base + WINDOW_BASE(i)); 398815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 398915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek} 399015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 3991f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/** 3992f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_probe - handle a positive probe of an soc Marvell 3993f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * host 3994f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device found 3995f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 3996f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * LOCKING: 3997f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Inherited from caller. 3998f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 3999f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev) 4000f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 4001f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara static int printed_version; 4002f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct mv_sata_platform_data *mv_platform_data; 4003f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct ata_port_info *ppi[] = 4004f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { &mv_port_info[chip_soc], NULL }; 4005f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host; 4006f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv; 4007f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct resource *res; 4008f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports, rc; 400920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4010f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!printed_version++) 4011f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 4012bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 4013f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 4014f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Simple resource validation .. 4015f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 4016f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (unlikely(pdev->num_resources != 2)) { 4017f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_err(&pdev->dev, "invalid number of resources\n"); 4018f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 4019f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 4020f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4021f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 4022f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Get the register base first 4023f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 4024f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4025f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (res == NULL) 4026f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 4027f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4028f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* allocate host */ 4029f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_platform_data = pdev->dev.platform_data; 4030f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara n_ports = mv_platform_data->n_ports; 4031f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4032f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 4033f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 4034f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4035f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!host || !hpriv) 4036f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -ENOMEM; 4037f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->private_data = hpriv; 4038f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 40391bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bishara hpriv->board_idx = chip_soc; 4040f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4041f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->iomap = NULL; 4042f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara hpriv->base = devm_ioremap(&pdev->dev, res->start, 4043041b5eac254107cd3ba60034c38a411531cc64eeJulia Lawall resource_size(res)); 4044cae5a29d3c4ec7c4214966021c9ee827e66bd67bMark Lord hpriv->base -= SATAHC0_REG_BASE; 4045f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4046c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#if defined(CONFIG_HAVE_CLK) 4047c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara hpriv->clk = clk_get(&pdev->dev, NULL); 4048c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara if (IS_ERR(hpriv->clk)) 4049c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara dev_notice(&pdev->dev, "cannot get clkdev\n"); 4050c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara else 4051c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara clk_enable(hpriv->clk); 4052c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#endif 4053c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara 405415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek /* 405515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek * (Re-)program MBUS remapping windows if we are asked to. 405615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek */ 405715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek if (mv_platform_data->dram != NULL) 405815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek mv_conf_mbus_windows(hpriv, mv_platform_data->dram); 405915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 4060fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley rc = mv_create_dma_pools(hpriv, &pdev->dev); 4061fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (rc) 4062c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara goto err; 4063fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 4064f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* initialize adapter */ 40651bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bishara rc = mv_init_host(host); 4066f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc) 4067c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara goto err; 4068f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4069f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, 4070f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, 4071f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->n_ports); 4072f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4073f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, 4074f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara IRQF_SHARED, &mv6_sht); 4075c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bisharaerr: 4076c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#if defined(CONFIG_HAVE_CLK) 4077c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara if (!IS_ERR(hpriv->clk)) { 4078c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara clk_disable(hpriv->clk); 4079c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara clk_put(hpriv->clk); 4080c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara } 4081c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#endif 4082c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara 4083c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara return rc; 4084f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 4085f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4086f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* 4087f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 4088f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_remove - unplug a platform interface 4089f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device 4090f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 4091f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * A platform bus SATA device has been unplugged. Perform the needed 4092f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * cleanup. Also called on module unload for any active devices. 4093f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 4094f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev) 4095f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 4096f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct device *dev = &pdev->dev; 4097f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host = dev_get_drvdata(dev); 4098c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#if defined(CONFIG_HAVE_CLK) 4099c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 4100c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#endif 4101f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_host_detach(host); 4102c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara 4103c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#if defined(CONFIG_HAVE_CLK) 4104c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara if (!IS_ERR(hpriv->clk)) { 4105c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara clk_disable(hpriv->clk); 4106c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara clk_put(hpriv->clk); 4107c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara } 4108c77a2f4e6b76c9094182dfa653ece4243f6df80cSaeed Bishara#endif 4109f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 411020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 411120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 41126481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara#ifdef CONFIG_PM 41136481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bisharastatic int mv_platform_suspend(struct platform_device *pdev, pm_message_t state) 41146481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara{ 41156481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara struct ata_host *host = dev_get_drvdata(&pdev->dev); 41166481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara if (host) 41176481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara return ata_host_suspend(host, state); 41186481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara else 41196481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara return 0; 41206481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara} 41216481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara 41226481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bisharastatic int mv_platform_resume(struct platform_device *pdev) 41236481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara{ 41246481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara struct ata_host *host = dev_get_drvdata(&pdev->dev); 41256481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara int ret; 41266481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara 41276481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara if (host) { 41286481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 41296481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara const struct mv_sata_platform_data *mv_platform_data = \ 41306481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara pdev->dev.platform_data; 41316481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara /* 41326481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara * (Re-)program MBUS remapping windows if we are asked to. 41336481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara */ 41346481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara if (mv_platform_data->dram != NULL) 41356481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara mv_conf_mbus_windows(hpriv, mv_platform_data->dram); 41366481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara 41376481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara /* initialize adapter */ 41381bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bishara ret = mv_init_host(host); 41396481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara if (ret) { 41406481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara printk(KERN_ERR DRV_NAME ": Error during HW init\n"); 41416481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara return ret; 41426481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara } 41436481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara ata_host_resume(host); 41446481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara } 41456481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara 41466481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara return 0; 41476481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara} 41486481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara#else 41496481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara#define mv_platform_suspend NULL 41506481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara#define mv_platform_resume NULL 41516481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara#endif 41526481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara 4153f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic struct platform_driver mv_platform_driver = { 4154f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_platform_probe, 4155f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .remove = __devexit_p(mv_platform_remove), 41566481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara .suspend = mv_platform_suspend, 41576481f2b52cd5411ea6342b749daf0e4f3b390d7bSaeed Bishara .resume = mv_platform_resume, 4158f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .driver = { 4159f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .name = DRV_NAME, 4160f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .owner = THIS_MODULE, 4161f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 4162f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 4163f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4164f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 41657bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 4166f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 4167f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent); 4168b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara#ifdef CONFIG_PM 4169b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bisharastatic int mv_pci_device_resume(struct pci_dev *pdev); 4170b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara#endif 4171f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 41727bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 41737bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic struct pci_driver mv_pci_driver = { 41747bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .name = DRV_NAME, 41757bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .id_table = mv_pci_tbl, 4176f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_pci_init_one, 41777bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .remove = ata_pci_remove_one, 4178b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara#ifdef CONFIG_PM 4179b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara .suspend = ata_pci_device_suspend, 4180b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara .resume = mv_pci_device_resume, 4181b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara#endif 4182b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara 41837bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara}; 41847bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 41857bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* move to PCI layer or libata core? */ 41867bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int pci_go_64(struct pci_dev *pdev) 41877bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara{ 41887bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc; 41897bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 41906a35528a8346f6e6fd32ed7e51f04d1fa4ca2c01Yang Hongyang if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 41916a35528a8346f6e6fd32ed7e51f04d1fa4ca2c01Yang Hongyang rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 41927bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 4193284901a90a9e0b812ca3f5f852cbbfb60d10249dYang Hongyang rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 41947bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 41957bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 41967bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "64-bit DMA enable failed\n"); 41977bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 41987bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 41997bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 42007bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } else { 4201284901a90a9e0b812ca3f5f852cbbfb60d10249dYang Hongyang rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 42027bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 42037bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 42047bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit DMA enable failed\n"); 42057bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 42067bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 4207284901a90a9e0b812ca3f5f852cbbfb60d10249dYang Hongyang rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 42087bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 42097bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 42107bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit consistent DMA enable failed\n"); 42117bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 42127bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 42137bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 42147bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 42157bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 42167bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara} 42177bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 421805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 421905b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_print_info - Dump key info to kernel log for perusal. 42204447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to print info about 422105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 422205b308e1df6d9d673daedb517969241f41278b52Brett Russ * FIXME: complete this. 422305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 422405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 422505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 422605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 42274447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic void mv_print_info(struct ata_host *host) 422831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 42294447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 42304447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 423144c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok u8 scc; 4232c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik const char *scc_s, *gen; 423331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 423431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Use this to determine the HW stepping of the chip so we know 423531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * what errata to workaround 423631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 423731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 423831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (scc == 0) 423931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "SCSI"; 424031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else if (scc == 0x01) 424131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "RAID"; 424231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else 4243c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik scc_s = "?"; 4244c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik 4245c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik if (IS_GEN_I(hpriv)) 4246c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "I"; 4247c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_II(hpriv)) 4248c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "II"; 4249c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_IIE(hpriv)) 4250c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "IIE"; 4251c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else 4252c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "?"; 425331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 4254a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, 4255c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 4256c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 425731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 425831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 425931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 426005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 4261f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_pci_init_one - handle a positive probe of a PCI Marvell host 426205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pdev: PCI device found 426305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ent: PCI device ID entry for the matched host 426405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 426505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 426605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 426705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 4268f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 4269f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent) 427020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 42712dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik static int printed_version; 427220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int board_idx = (unsigned int)ent->driver_data; 42734447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 42744447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct ata_host *host; 42754447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv; 4276c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara int n_ports, port, rc; 427720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4278a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik if (!printed_version++) 4279a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 428020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 42814447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* allocate host */ 42824447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 42834447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 42844447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 42854447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 42864447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (!host || !hpriv) 42874447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return -ENOMEM; 42884447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->private_data = hpriv; 4289f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 42901bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bishara hpriv->board_idx = board_idx; 42914447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 42924447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* acquire resources */ 429324dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo rc = pcim_enable_device(pdev); 429424dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 429520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return rc; 429620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 42970d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 42980d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc == -EBUSY) 429924dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pcim_pin_device(pdev); 43000d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc) 430124dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 43024447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->iomap = pcim_iomap_table(pdev); 4303f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base = host->iomap[MV_PRIMARY_BAR]; 430420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4305d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik rc = pci_go_64(pdev); 4306d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik if (rc) 4307d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik return rc; 4308d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik 4309da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord rc = mv_create_dma_pools(hpriv, &pdev->dev); 4310da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (rc) 4311da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return rc; 4312da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 4313c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara for (port = 0; port < host->n_ports; port++) { 4314c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara struct ata_port *ap = host->ports[port]; 4315c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara void __iomem *port_mmio = mv_port_base(hpriv->base, port); 4316c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara unsigned int offset = port_mmio - hpriv->base; 4317c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara 4318c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 4319c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 4320c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara } 4321c4bc7d7310a40c8c0b917e88983dc4a8e6b59e38Saeed Bishara 432220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* initialize adapter */ 43231bfeff03f8a52eb896e5aad33d52e2451437bb0bSaeed Bishara rc = mv_init_host(host); 432424dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 432524dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 432620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 43276d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord /* Enable message-switched interrupts, if requested */ 43286d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord if (msi && pci_enable_msi(pdev) == 0) 43296d3c30efc964fadf2e6270e6fceaeca3ce50027aMark Lord hpriv->hp_flags |= MV_HP_FLAG_MSI; 433020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 433131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 43324447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo mv_print_info(host); 433320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 43344447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo pci_set_master(pdev); 4335ea8b4db97aa41a66c05daa4055a1974692ccd52dJeff Garzik pci_try_set_mwi(pdev); 43364447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 4337c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 433820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 4339b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara 4340b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara#ifdef CONFIG_PM 4341b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bisharastatic int mv_pci_device_resume(struct pci_dev *pdev) 4342b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara{ 4343b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara struct ata_host *host = dev_get_drvdata(&pdev->dev); 4344b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara int rc; 4345b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara 4346b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara rc = ata_pci_device_do_resume(pdev); 4347b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara if (rc) 4348b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara return rc; 4349b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara 4350b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara /* initialize adapter */ 4351b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara rc = mv_init_host(host); 4352b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara if (rc) 4353b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara return rc; 4354b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara 4355b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara ata_host_resume(host); 4356b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara 4357b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara return 0; 4358b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara} 4359b2dec48ccaad004fc706352f82725d43369d9bd7Saeed Bishara#endif 43607bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 436120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 4362f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev); 4363f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev); 4364f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 436520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic int __init mv_init(void) 436620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 43677bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc = -ENODEV; 43687bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 43697bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_register_driver(&mv_pci_driver); 4370f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 4371f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 4372f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#endif 4373f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = platform_driver_register(&mv_platform_driver); 4374f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 4375f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#ifdef CONFIG_PCI 4376f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 4377f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara pci_unregister_driver(&mv_pci_driver); 43787bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 43797bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 438020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 438120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 438220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic void __exit mv_exit(void) 438320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 43847bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 438520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ pci_unregister_driver(&mv_pci_driver); 43867bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 4387f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara platform_driver_unregister(&mv_platform_driver); 438820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 438920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 439020f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_AUTHOR("Brett Russ"); 439120f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 439220f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_LICENSE("GPL"); 439320f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DEVICE_TABLE(pci, mv_pci_tbl); 439420f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_VERSION(DRV_VERSION); 439517c5aab5b34e351531466e35b154ca86db7d46a9Mark LordMODULE_ALIAS("platform:" DRV_NAME); 439620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 439720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_init(mv_init); 439820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_exit(mv_exit); 4399