sata_mv.c revision 8f767f8a02e6c65d393fd0f2ca19a91c9898cc2d
120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * sata_mv.c - Marvell SATA support 320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 4e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * Copyright 2008: Marvell Corporation, all rights reserved. 58b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * Copyright 2005: EMC Corporation, all rights reserved. 6e2b1be56c5656902744c2b52e8304126a40bb609Jeff Garzik * Copyright 2005 Red Hat, Inc. All rights reserved. 720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is free software; you can redistribute it and/or modify 1120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * it under the terms of the GNU General Public License as published by 1220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * the Free Software Foundation; version 2 of the License. 1320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is distributed in the hope that it will be useful, 1520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * but WITHOUT ANY WARRANTY; without even the implied warranty of 1620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * GNU General Public License for more details. 1820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * You should have received a copy of the GNU General Public License 2020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * along with this program; if not, write to the Free Software 2120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 2220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 254a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik/* 264a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik sata_mv TODO list: 274a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 284a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 1) Needs a full errata audit for all chipsets. I implemented most 294a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik of the errata workarounds found in the Marvell vendor driver, but 304a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik I distinctly remember a couple workarounds (one related to PCI-X) 314a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik are still needed. 324a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 331fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 2) Improve/fix IRQ and error handling sequences. 341fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 351fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 3) ATAPI support (Marvell claims the 60xx/70xx chips can do it). 361fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 371fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord 4) Think about TCQ support here, and for libata in general 381fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord with controllers that suppport it via host-queuing hardware 391fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord (a software-only implementation could be a nightmare). 404a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 414a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 5) Investigate problems with PCI Message Signalled Interrupts (MSI). 424a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 43e49856d82a887ce365637176f9f99ab68076eae8Mark Lord 6) Cache frequently-accessed registers in mv_port_priv to reduce overhead. 444a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 4540f0bc2d77d2d9ead3812f4eec2eefc11455e5deMark Lord 7) Fix/reenable hot plug/unplug (should happen as a side-effect of (2) above). 464a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 474a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 8) Develop a low-power-consumption strategy, and implement it. 484a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 494a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 9) [Experiment, low priority] See if ATAPI can be supported using 504a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik "unknown FIS" or "vendor-specific FIS" support, or something creative 514a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik like that. 524a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 534a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 10) [Experiment, low priority] Investigate interrupt coalescing. 544a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik Quite often, especially with PCI Message Signalled Interrupts (MSI), 554a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik the overhead reduced by interrupt mitigation is quite often not 564a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik worth the latency cost. 574a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 584a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 11) [Experiment, Marvell value added] Is it possible to use target 594a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik mode to cross-connect two Linux boxes with Marvell cards? If so, 604a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik creating LibATA target mode support would be very interesting. 614a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 624a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik Target mode, for those without docs, is the ability to directly 634a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik connect two SATA controllers. 644a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 654a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik*/ 664a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 6720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/kernel.h> 6820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/module.h> 6920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/pci.h> 7020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/init.h> 7120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/blkdev.h> 7220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/delay.h> 7320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/interrupt.h> 748d8b60046d6a2328ca4b9031b4948084f775f607Andrew Morton#include <linux/dmapool.h> 7520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/dma-mapping.h> 76a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik#include <linux/device.h> 77f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/platform_device.h> 78f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/ata_platform.h> 7915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#include <linux/mbus.h> 8020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <scsi/scsi_host.h> 81193515d51ccb363165d6b09e9ba5c21089e34badJeff Garzik#include <scsi/scsi_cmnd.h> 826c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik#include <scsi/scsi_device.h> 8320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/libata.h> 8420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#define DRV_NAME "sata_mv" 861fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord#define DRV_VERSION "1.20" 8720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russenum { 8920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* BAR's are enumerated in terms of pci_resource_start() terms */ 9020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 9120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IO_BAR = 2, /* offset 0x18: IO space */ 9220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 9320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 9420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 9520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 9620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 9720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_BASE = 0, 9820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ 99615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08), 100615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88), 101615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c), 102615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc), 103615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0), 104615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 10520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC0_REG_BASE = 0x20000, 106522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_FLASH_CTL = 0x1046c, 107bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_GPIO_PORT_CTL = 0x104f0, 108bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_RESET_CFG = 0x180d8, 10920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 11020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 11120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 11220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 11320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 11420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 11531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH = 32, 11631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 11731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 11831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* CRQB needs alignment on a 1KB boundary. Size == 1KB 11931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * CRPB needs alignment on a 256B boundary. Size == 256B 12031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 12131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 12231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 12331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 124da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord MV_MAX_SG_CT = 256, 12531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 12631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 127352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ 12820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_HC_SHIFT = 2, 129352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ 130352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ 131352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ 13220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 13320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Host Flags */ 13420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 13520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ 1367bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara /* SoC integrated controllers, no PCI interface */ 137e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord MV_FLAG_SOC = (1 << 28), 1387bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 139c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 140bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI | 141bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ATA_FLAG_PIO_POLLING, 14247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE, 14320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 14431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_FLAG_READ = (1 << 0), 14531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_TAG_SHIFT = 1, 146c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 147e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 148c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 14931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_ADDR_SHIFT = 8, 15031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_CS = (0x2 << 11), 15131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_LAST = (1 << 15), 15231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRPB_FLAG_STATUS_SHIFT = 8, 154c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 155c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 15631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EPRD_FLAG_END_OF_TBL = (1 << 31), 15831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* PCI interface registers */ 16020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 16131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ PCI_COMMAND_OFS = 0xc00, 16231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 16320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MAIN_CMD_STS_OFS = 0xd30, 16420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ STOP_PCI_MASTER = (1 << 2), 16520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MASTER_EMPTY = (1 << 3), 16620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GLOB_SFT_RST = (1 << 4), 16720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 168522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MODE = 0xd00, 169522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 170522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_DISC_TIMER = 0xd04, 171522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MSI_TRIGGER = 0xc38, 172522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_SERR_MASK = 0xc28, 173522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_XBAR_TMOUT = 0x1d04, 174522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 175522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 176522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_ATTRIBUTE = 0x1d48, 177522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_COMMAND = 0x1d50, 178522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 17902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_CAUSE_OFS = 0x1d58, 18002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_MASK_OFS = 0x1d5c, 18120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 18220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 18302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_CAUSE_OFS = 0x1900, 18402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_MASK_OFS = 0x1910, 185646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 18602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 18720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, 18820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_IRQ_MASK_OFS = 0x1d64, 189f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_SOC_MAIN_IRQ_CAUSE_OFS = 0x20020, 190f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_SOC_MAIN_IRQ_MASK_OFS = 0x20024, 191352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ERR_IRQ = (1 << 0), /* shift by port # */ 192352fab701ca4753dd005b67ce5e512be944eb591Mark Lord DONE_IRQ = (1 << 1), /* shift by port # */ 19320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 19420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 19520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_ERR = (1 << 18), 19620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */ 19720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */ 198fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_0_3_COAL_DONE = (1 << 8), 199fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_4_7_COAL_DONE = (1 << 17), 20020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */ 20120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GPIO_INT = (1 << 22), 20220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SELF_INT = (1 << 23), 20320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TWSI_INT = (1 << 24), 20420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 205fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 206e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 2078b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | 208f9f7fe014fc7197a5f36f9d9859cbb27c3bdd2abMark Lord PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 20920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT | 21020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD), 211fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 212fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5), 213f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC), 21420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATAHC registers */ 21620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_CFG_OFS = 0, 21720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_IRQ_CAUSE_OFS = 0x14, 219352fab701ca4753dd005b67ce5e512be944eb591Mark Lord DMA_IRQ = (1 << 0), /* shift by port # */ 220352fab701ca4753dd005b67ce5e512be944eb591Mark Lord HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ 22120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ DEV_IRQ = (1 << 8), /* shift by port # */ 22220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 22320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Shadow block registers */ 22431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_BLK_OFS = 0x100, 22531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ 22620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 22720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATA registers */ 22820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ 22920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_ACTIVE_OFS = 0x350, 2300c58912e192fc3a4835d772aafa40b72552b819fMark Lord SATA_FIS_IRQ_CAUSE_OFS = 0x364, 23117c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 232e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord LTMODE_OFS = 0x30c, 23317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 23417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 23547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik PHY_MODE3 = 0x310, 236bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE4 = 0x314, 237bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE2 = 0x330, 238e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFCTL_OFS = 0x344, 239e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFSTAT_OFS = 0x34c, 240e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord VENDOR_UNIQUE_FIS_OFS = 0x35c, 24117c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 242e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord FIS_CFG_OFS = 0x360, 24317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord FIS_CFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 24417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 245c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_MODE = 0x74, 246c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_LT_MODE = 0x30, 247c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_CTL = 0x0C, 248e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_INTERFACE_CFG = 0x050, 249bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 250bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_M2_PREAMP_MASK = 0x7e0, 25120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Port registers */ 25320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_CFG_OFS = 0, 2540c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 2550c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 2560c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 2570c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 2580c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 259e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 260e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 26120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 26220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_CAUSE_OFS = 0x8, 26320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_MASK_OFS = 0xc, 2646c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 2656c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 2666c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV = (1 << 2), /* device error */ 2676c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 2686c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 2696c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 270c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 271c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 2726c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 273c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 2746c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 2756c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 2766c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 2776c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 278646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2796c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 280646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 281646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 282646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 283646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 284646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2856c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 286646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2876c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 288646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 289646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 290646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 291646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 292646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 293646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2946c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 295646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2966c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 297c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_OVERRUN_5 = (1 << 5), 298c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_UNDERRUN_5 = (1 << 6), 299646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 300646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 301646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 | 302646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 | 30340f0bc2d77d2d9ead3812f4eec2eefc11455e5deMark Lord EDMA_ERR_LNK_CTRL_TX | 30440f0bc2d77d2d9ead3812f4eec2eefc11455e5deMark Lord /* temporary, until we fix hotplug: */ 30540f0bc2d77d2d9ead3812f4eec2eefc11455e5deMark Lord (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON), 306646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 307bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 308bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 309bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 310bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 311bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SERR | 312bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS | 3136c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 314bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 315bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 316bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY | 317bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_CTRL_RX_2 | 318bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_RX | 319bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_TX | 320bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_TRANS_PROTO, 321e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 322bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 323bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 324bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 325bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 326bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_OVERRUN_5 | 327bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_UNDERRUN_5 | 328bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS_5 | 3296c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 330bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 331bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 332bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY, 33320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 33431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_BASE_HI_OFS = 0x10, 33531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ 33631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 33731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_OUT_PTR_OFS = 0x18, 33831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_PTR_SHIFT = 5, 33931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 34031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_BASE_HI_OFS = 0x1c, 34131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_IN_PTR_OFS = 0x20, 34231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ 34331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_PTR_SHIFT = 3, 34431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3450ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_CMD_OFS = 0x28, /* EDMA command register */ 3460ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_EN = (1 << 0), /* enable EDMA */ 3470ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 3480ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik ATA_RST = (1 << 2), /* reset trans/link/phy */ 34920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 350c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik EDMA_IORDY_TMOUT = 0x34, 351bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik EDMA_ARB_CFG = 0x38, 352bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 353352fab701ca4753dd005b67ce5e512be944eb591Mark Lord GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */ 354352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 35531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Host private flags (hp_flags) */ 35631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_HP_FLAG_MSI = (1 << 0), 35747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB0 = (1 << 1), 35847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB2 = (1 << 2), 35947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1B2 = (1 << 3), 36047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1C0 = (1 << 4), 361e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik MV_HP_ERRATA_XX42A0 = (1 << 5), 3620ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 3630ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 3640ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 36502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 36620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 36731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Port private flags (pp_flags) */ 3680ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 369721091685f853ba4e6c49f26f989db0b1a811250Mark Lord MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 37020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 37120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 372ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 373ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 374e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 3757bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC)) 376bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 37715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 37815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_BASE(i) (0x20034 + ((i) << 4)) 37915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 380095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzikenum { 381baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik /* DMA boundary 0xffff is required by the s/g splitting 382baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik * we need on /length/ in mv_fill-sg(). 383baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik */ 384baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik MV_DMA_BOUNDARY = 0xffffU, 385095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3860ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* mask of register bits containing lower 32 bits 3870ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik * of EDMA request queue DMA address 3880ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik */ 389095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 390095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3910ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* ditto, for response queue */ 392095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 393095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik}; 394095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 395522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikenum chip_type { 396522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_504x, 397522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_508x, 398522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_5080, 399522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_604x, 400522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_608x, 401e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_6042, 402e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_7042, 403f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara chip_soc, 404522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik}; 405522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 40631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ReQuest Block: 32B */ 40731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crqb { 408e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr; 409e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr_hi; 410e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ctrl_flags; 411e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ata_cmd[11]; 41231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 41320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 414e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstruct mv_crqb_iie { 415e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 416e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 417e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags; 418e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 len; 419e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 ata_cmd[4]; 420e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 421e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 42231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ResPonse Block: 8B */ 42331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crpb { 424e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 id; 425e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 flags; 426e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 tmstmp; 42720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 42820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 42931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 43031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_sg { 431e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 432e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags_size; 433e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 434e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 reserved; 43531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 43620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 43731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_port_priv { 43831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crqb *crqb; 43931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crqb_dma; 44031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crpb *crpb; 44131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crpb_dma; 442eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 443eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 444bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 445bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int req_idx; 446bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int resp_idx; 447bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 44831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 pp_flags; 44931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 45031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 451bca1c4eb9411533d613123618c0d127fae532595Jeff Garzikstruct mv_port_signal { 452bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 amps; 453bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 pre; 454bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik}; 455bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 45602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lordstruct mv_host_priv { 45702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 hp_flags; 45802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_port_signal signal[8]; 45902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord const struct mv_hw_ops *ops; 460f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports; 461f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *base; 462f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *main_cause_reg_addr; 463f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *main_mask_reg_addr; 46402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_cause_ofs; 46502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_mask_ofs; 46602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 unmask_all_irqs; 467da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord /* 468da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * These consistent DMA memory pools give us guaranteed 469da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * alignment for hardware-accessed data structures, 470da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * and less memory waste in accomplishing the alignment. 471da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord */ 472da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crqb_pool; 473da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crpb_pool; 474da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *sg_tbl_pool; 47502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord}; 47602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 47747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstruct mv_hw_ops { 4782a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 4792a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 48047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 48147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 48247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 483c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 484c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 485522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 4867bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 48747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 48847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 489da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 490da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 491da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 492da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 49331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap); 49431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap); 49531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc); 496e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc); 4979a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 498a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 499a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo unsigned long deadline); 500bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap); 501bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap); 502f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *dev); 50320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 5042a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5052a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 50647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 50747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 50847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 509c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 510c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 511522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 5127bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 51347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 5142a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5152a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 51647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 51747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 51847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 519c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 520c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 521522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 522f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 523f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 524f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 525f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 526f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 527f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc); 528f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 529f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 530f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 5317bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 532e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 533c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no); 534e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap); 535b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio); 536e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq); 53747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 538e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp); 539e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 540e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 541e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 542e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 54347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 544eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 545eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * because we have to allow room for worst case splitting of 546eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * PRDs for 64K boundaries in mv_fill_sg(). 547eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 548c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv5_sht = { 54968d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BASE_SHT(DRV_NAME), 550baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 551c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .dma_boundary = MV_DMA_BOUNDARY, 552c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik}; 553c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 554c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv6_sht = { 55568d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_NCQ_SHT(DRV_NAME), 556138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .can_queue = MV_MAX_Q_DEPTH - 1, 557baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 55820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .dma_boundary = MV_DMA_BOUNDARY, 55920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 56020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 561029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv5_ops = { 562029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &ata_sff_port_ops, 563c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 564c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_prep = mv_qc_prep, 565c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_issue = mv_qc_issue, 566c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 567bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .freeze = mv_eh_freeze, 568bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .thaw = mv_eh_thaw, 569a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .hardreset = mv_hardreset, 570a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .error_handler = ata_std_error_handler, /* avoid SFF EH */ 571029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .post_internal_cmd = ATA_OP_NULL, 572bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 573c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_read = mv5_scr_read, 574c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_write = mv5_scr_write, 575c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 576c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_start = mv_port_start, 577c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_stop = mv_port_stop, 578c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik}; 579c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 580029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv6_ops = { 581029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv5_ops, 582e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .qc_defer = sata_pmp_qc_defer_cmd_switch, 583f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord .dev_config = mv6_dev_config, 58420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_read = mv_scr_read, 58520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_write = mv_scr_write, 58620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 587e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_hardreset = mv_pmp_hardreset, 588e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_softreset = mv_softreset, 589e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .softreset = mv_softreset, 590e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .error_handler = sata_pmp_error_handler, 59120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 59220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 593029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv_iie_ops = { 594029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv6_ops, 595e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .qc_defer = ata_std_qc_defer, /* FIS-based switching */ 596029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .dev_config = ATA_OP_NULL, 597e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .qc_prep = mv_qc_prep_iie, 598e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 599e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 60098ac62defe529d04a192688f40d801a2d8fbcf98Arjan van de Venstatic const struct ata_port_info mv_port_info[] = { 60120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_504x */ 602cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik .flags = MV_COMMON_FLAGS, 60331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 604bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 605c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 60620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 60720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_508x */ 608c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 60931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 610bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 611c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 61220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 61347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik { /* chip_5080 */ 614c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 61547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 616bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 617c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 61847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik }, 61920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_604x */ 620138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 621e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 622138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 62331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 624bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 625c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 62620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 62720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_608x */ 628c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 629e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 630138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ | MV_FLAG_DUAL_HC, 63131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 632bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 633c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 63420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 635e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_6042 */ 636138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 637e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 638138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 639e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 640bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 641e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 642e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 643e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_7042 */ 644138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 645e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 646138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 647e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 648bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 649e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 650e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 651f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { /* chip_soc */ 65202c1f32f1c524d2a389989f2482121f7c7d9b164Mark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 653e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 65402c1f32f1c524d2a389989f2482121f7c7d9b164Mark Lord ATA_FLAG_NCQ | MV_FLAG_SOC, 65517c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .pio_mask = 0x1f, /* pio0-4 */ 65617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .udma_mask = ATA_UDMA6, 65717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .port_ops = &mv_iie_ops, 658f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 65920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 66020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 6613b7d697dfb7d03edb87e50b743a7ecff029618e9Jeff Garzikstatic const struct pci_device_id mv_pci_tbl[] = { 6622d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 6632d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 6642d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 6652d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 666cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox /* RocketRAID 1740/174x have different identifiers */ 667cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox { PCI_VDEVICE(TTI, 0x1740), chip_508x }, 668cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox { PCI_VDEVICE(TTI, 0x1742), chip_508x }, 6692d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 6702d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 6712d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 6722d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 6732d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 6742d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 6752d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 6762d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 6772d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 678d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger /* Adaptec 1430SA */ 679d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 680d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger 68102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Marvell 7042 support */ 6826a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 6836a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom 68402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Highpoint RocketRAID PCIe series */ 68502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 68602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 68702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 6882d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { } /* terminate list */ 68920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 69020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 69147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv5xxx_ops = { 69247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv5_phy_errata, 69347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv5_enable_leds, 69447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv5_read_preamp, 69547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv5_reset_hc, 696522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv5_reset_flash, 697522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv5_reset_bus, 69847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 69947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 70047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv6xxx_ops = { 70147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv6_phy_errata, 70247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv6_enable_leds, 70347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv6_read_preamp, 70447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv6_reset_hc, 705522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv6_reset_flash, 706522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv_reset_pci_bus, 70747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 70847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 709f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic const struct mv_hw_ops mv_soc_ops = { 710f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .phy_errata = mv6_phy_errata, 711f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .enable_leds = mv_soc_enable_leds, 712f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .read_preamp = mv_soc_read_preamp, 713f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_hc = mv_soc_reset_hc, 714f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_flash = mv_soc_reset_flash, 715f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_bus = mv_soc_reset_bus, 716f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 717f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 71820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 71920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Functions 72020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 72120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 72220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void writelfl(unsigned long data, void __iomem *addr) 72320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 72420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writel(data, addr); 72520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ (void) readl(addr); /* flush to avoid PCI posted write */ 72620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 72720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 728c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hc_from_port(unsigned int port) 729c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 730c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port >> MV_PORT_HC_SHIFT; 731c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 732c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 733c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hardport_from_port(unsigned int port) 734c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 735c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port & MV_PORT_MASK; 736c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 737c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 7381cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord/* 7391cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Consolidate some rather tricky bit shift calculations. 7401cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * This is hot-path stuff, so not a function. 7411cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Simple code, with two return values, so macro rather than inline. 7421cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 7431cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * port is the sole input, in range 0..7. 7441cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * shift is one output, for use with the main_cause and main_mask registers. 7451cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * hardport is the other output, in range 0..3 7461cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 7471cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Note that port and hardport may be the same variable in some cases. 7481cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord */ 7491cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ 7501cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord{ \ 7511cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift = mv_hc_from_port(port) * HC_SHIFT; \ 7521cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord hardport = mv_hardport_from_port(port); \ 7531cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift += hardport * 2; \ 7541cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord} 7551cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord 756352fab701ca4753dd005b67ce5e512be944eb591Mark Lordstatic inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 757352fab701ca4753dd005b67ce5e512be944eb591Mark Lord{ 758352fab701ca4753dd005b67ce5e512be944eb591Mark Lord return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 759352fab701ca4753dd005b67ce5e512be944eb591Mark Lord} 760352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 761c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline void __iomem *mv_hc_base_from_port(void __iomem *base, 762c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 763c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 764c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base(base, mv_hc_from_port(port)); 765c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 766c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 76720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 76820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 769c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base_from_port(base, port) + 7708b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik MV_SATAHC_ARBTR_REG_SZ + 771c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 77220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 77320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 774e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 775e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord{ 776e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 777e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 778e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 779e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord return hc_mmio + ofs; 780e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord} 781e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 782f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic inline void __iomem *mv_host_base(struct ata_host *host) 783f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 784f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 785f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return hpriv->base; 786f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 787f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 78820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_ap_base(struct ata_port *ap) 78920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 790f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return mv_port_base(mv_host_base(ap->host), ap->port_no); 79120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 79220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 793cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic inline int mv_get_hc_count(unsigned long port_flags) 79431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 795cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 79631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 79731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 798c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic void mv_set_edma_ptrs(void __iomem *port_mmio, 799c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_host_priv *hpriv, 800c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp) 801c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik{ 802bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 index; 803bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 804c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 805c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize request queue 806c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 807fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 808fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 809bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 810c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crqb_dma & 0x3ff); 811c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); 812bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 813c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 814c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 815c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) 816bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & 0xffffffff) | index, 817c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 818c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik else 819bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 820c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 821c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 822c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize response queue 823c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 824fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 825fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; 826bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 827c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crpb_dma & 0xff); 828c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); 829c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 830c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) 831bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & 0xffffffff) | index, 832c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 833c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik else 834bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 835c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 836bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 837c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 838c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik} 839c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 84005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 84105b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_start_dma - Enable eDMA engine 84205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @base: port base address 84305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pp: port private data 84405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 845beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * Verify the local cache of the eDMA state is accurate with a 846beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * WARN_ON. 84705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 84805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 84905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 85005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 8510c58912e192fc3a4835d772aafa40b72552b819fMark Lordstatic void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio, 852721091685f853ba4e6c49f26f989db0b1a811250Mark Lord struct mv_port_priv *pp, u8 protocol) 85320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 854721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int want_ncq = (protocol == ATA_PROT_NCQ); 855721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 856721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 857721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 858721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq != using_ncq) 859b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 860721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } 861c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 8620c58912e192fc3a4835d772aafa40b72552b819fMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 863352fab701ca4753dd005b67ce5e512be944eb591Mark Lord int hardport = mv_hardport_from_port(ap->port_no); 8640c58912e192fc3a4835d772aafa40b72552b819fMark Lord void __iomem *hc_mmio = mv_hc_base_from_port( 865352fab701ca4753dd005b67ce5e512be944eb591Mark Lord mv_host_base(ap->host), hardport); 8660c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 hc_irq_cause, ipending; 8670c58912e192fc3a4835d772aafa40b72552b819fMark Lord 868bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA event indicators, if any */ 869f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 870bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 8710c58912e192fc3a4835d772aafa40b72552b819fMark Lord /* clear EDMA interrupt indicator, if any */ 8720c58912e192fc3a4835d772aafa40b72552b819fMark Lord hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 873352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ipending = (DEV_IRQ | DMA_IRQ) << hardport; 8740c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (hc_irq_cause & ipending) { 8750c58912e192fc3a4835d772aafa40b72552b819fMark Lord writelfl(hc_irq_cause & ~ipending, 8760c58912e192fc3a4835d772aafa40b72552b819fMark Lord hc_mmio + HC_IRQ_CAUSE_OFS); 8770c58912e192fc3a4835d772aafa40b72552b819fMark Lord } 8780c58912e192fc3a4835d772aafa40b72552b819fMark Lord 879e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_edma_cfg(ap, want_ncq); 8800c58912e192fc3a4835d772aafa40b72552b819fMark Lord 8810c58912e192fc3a4835d772aafa40b72552b819fMark Lord /* clear FIS IRQ Cause */ 8820c58912e192fc3a4835d772aafa40b72552b819fMark Lord writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 8830c58912e192fc3a4835d772aafa40b72552b819fMark Lord 884f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord mv_set_edma_ptrs(port_mmio, hpriv, pp); 885bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 886f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS); 887afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 888afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 88920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 89020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 89105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 892e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * mv_stop_edma_engine - Disable eDMA engine 893b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * @port_mmio: io base address 89405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 89505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 89605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 89705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 898b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio) 89920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 900b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord int i; 90131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 902b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Disable eDMA. The disable bit auto clears. */ 903b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); 9048b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 905b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Wait for the chip to confirm eDMA is off. */ 906b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord for (i = 10000; i > 0; i--) { 907b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord u32 reg = readl(port_mmio + EDMA_CMD_OFS); 9084537deb5e90b717a725b3d74b58b4bb1d28443d0Jeff Garzik if (!(reg & EDMA_EN)) 909b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 910b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord udelay(10); 91131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 912b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 91320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 91420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 915e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap) 9160ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik{ 917b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord void __iomem *port_mmio = mv_ap_base(ap); 918b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 9190ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 920b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 921b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 922b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 923b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (mv_stop_edma_engine(port_mmio)) { 924b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); 925b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 926b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord } 927b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 9280ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik} 9290ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 9308a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#ifdef ATA_DEBUG 93131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_mem(void __iomem *start, unsigned bytes) 93220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 93331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 93431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 93531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%p: ", start + b); 93631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 9372dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", readl(start + b)); 93831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 93931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 94031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 94131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 94231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 9438a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#endif 9448a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik 94531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 94631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 94731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 94831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 94931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 dw; 95031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 95131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%02x: ", b); 95231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 9532dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik (void) pci_read_config_dword(pdev, b, &dw); 9542dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", dw); 95531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 95631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 95731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 95831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 95931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 96031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 96131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_all_regs(void __iomem *mmio_base, int port, 96231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct pci_dev *pdev) 96331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 96431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 9658b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik void __iomem *hc_base = mv_hc_base(mmio_base, 96631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port >> MV_PORT_HC_SHIFT); 96731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_base; 96831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int start_port, num_ports, p, start_hc, num_hcs, hc; 96931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 97031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (0 > port) { 97131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = start_port = 0; 97231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = 8; /* shld be benign for 4 port devs */ 97331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_hcs = 2; 97431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } else { 97531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = port >> MV_PORT_HC_SHIFT; 97631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_port = port; 97731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = num_hcs = 1; 97831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 9798b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik DPRINTK("All registers for port(s) %u-%u:\n", start_port, 98031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports > 1 ? num_ports - 1 : start_port); 98131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 98231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (NULL != pdev) { 98331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI config space regs:\n"); 98431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 98531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 98631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI regs:\n"); 98731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xc00, 0x3c); 98831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xd00, 0x34); 98931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xf00, 0x4); 99031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0x1d00, 0x6c); 99131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 992d220c37e0a3c9a47ae00e87e044d963b3ea040bcDan Aloni hc_base = mv_hc_base(mmio_base, hc); 99331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("HC regs (HC %i):\n", hc); 99431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(hc_base, 0x1c); 99531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 99631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (p = start_port; p < start_port + num_ports; p++) { 99731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port_base = mv_port_base(mmio_base, p); 9982dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("EDMA regs (port %i):\n", p); 99931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base, 0x54); 10002dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("SATA regs (port %i):\n", p); 100131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base+0x300, 0x60); 100231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 100331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 100420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 100520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 100620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic unsigned int mv_scr_offset(unsigned int sc_reg_in) 100720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 100820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs; 100920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 101020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ switch (sc_reg_in) { 101120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_STATUS: 101220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_CONTROL: 101320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ERROR: 101420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); 101520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 101620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ACTIVE: 101720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_ACTIVE_OFS; /* active is not with the others */ 101820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 101920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ default: 102020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = 0xffffffffU; 102120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 102220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 102320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return ofs; 102420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 102520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1026da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 102720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 102820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 102920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1030da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 1031da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(mv_ap_base(ap) + ofs); 1032da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1033da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1034da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 103520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 103620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1037da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 103820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 103920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 104020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1041da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 104220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writelfl(val, mv_ap_base(ap) + ofs); 1043da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1044da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1045da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 104620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 104720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1048f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *adev) 1049f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord{ 1050f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord /* 1051e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Deal with Gen-II ("mv6") hardware quirks/restrictions: 1052e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * 1053e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Gen-II does not support NCQ over a port multiplier 1054e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * (no FIS-based switching). 1055e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * 1056f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord * We don't have hob_nsect when doing NCQ commands on Gen-II. 1057f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord * See mv_qc_prep() for more info. 1058f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord */ 1059e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (adev->flags & ATA_DFLAG_NCQ) { 1060352fab701ca4753dd005b67ce5e512be944eb591Mark Lord if (sata_pmp_attached(adev->link->ap)) { 1061e49856d82a887ce365637176f9f99ab68076eae8Mark Lord adev->flags &= ~ATA_DFLAG_NCQ; 1062352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ata_dev_printk(adev, KERN_INFO, 1063352fab701ca4753dd005b67ce5e512be944eb591Mark Lord "NCQ disabled for command-based switching\n"); 1064352fab701ca4753dd005b67ce5e512be944eb591Mark Lord } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) { 1065352fab701ca4753dd005b67ce5e512be944eb591Mark Lord adev->max_sectors = GEN_II_NCQ_MAX_SECTORS; 1066352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ata_dev_printk(adev, KERN_INFO, 1067352fab701ca4753dd005b67ce5e512be944eb591Mark Lord "max_sectors limited to %u for NCQ\n", 1068352fab701ca4753dd005b67ce5e512be944eb591Mark Lord adev->max_sectors); 1069352fab701ca4753dd005b67ce5e512be944eb591Mark Lord } 1070e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 1071f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1072f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 1073e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_config_fbs(void __iomem *port_mmio, int enable_fbs) 1074e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 1075e49856d82a887ce365637176f9f99ab68076eae8Mark Lord u32 old_fcfg, new_fcfg, old_ltmode, new_ltmode; 1076e49856d82a887ce365637176f9f99ab68076eae8Mark Lord /* 1077e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Various bit settings required for operation 1078e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * in FIS-based switching (fbs) mode on GenIIe: 1079e49856d82a887ce365637176f9f99ab68076eae8Mark Lord */ 1080e49856d82a887ce365637176f9f99ab68076eae8Mark Lord old_fcfg = readl(port_mmio + FIS_CFG_OFS); 1081e49856d82a887ce365637176f9f99ab68076eae8Mark Lord old_ltmode = readl(port_mmio + LTMODE_OFS); 1082e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (enable_fbs) { 1083e49856d82a887ce365637176f9f99ab68076eae8Mark Lord new_fcfg = old_fcfg | FIS_CFG_SINGLE_SYNC; 1084e49856d82a887ce365637176f9f99ab68076eae8Mark Lord new_ltmode = old_ltmode | LTMODE_BIT8; 1085e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } else { /* disable fbs */ 1086e49856d82a887ce365637176f9f99ab68076eae8Mark Lord new_fcfg = old_fcfg & ~FIS_CFG_SINGLE_SYNC; 1087e49856d82a887ce365637176f9f99ab68076eae8Mark Lord new_ltmode = old_ltmode & ~LTMODE_BIT8; 1088e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 1089e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (new_fcfg != old_fcfg) 1090e49856d82a887ce365637176f9f99ab68076eae8Mark Lord writelfl(new_fcfg, port_mmio + FIS_CFG_OFS); 1091e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (new_ltmode != old_ltmode) 1092e49856d82a887ce365637176f9f99ab68076eae8Mark Lord writelfl(new_ltmode, port_mmio + LTMODE_OFS); 1093f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1094f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 1095e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq) 1096e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 10970c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 cfg; 1098e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_port_priv *pp = ap->private_data; 1099e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1100e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1101e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1102e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* set up non-NCQ EDMA configuration */ 11030c58912e192fc3a4835d772aafa40b72552b819fMark Lord cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 1104e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 11050c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (IS_GEN_I(hpriv)) 1106e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 8); /* enab config burst size mask */ 1107e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 11080c58912e192fc3a4835d772aafa40b72552b819fMark Lord else if (IS_GEN_II(hpriv)) 1109e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1110e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1111e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik else if (IS_GEN_IIE(hpriv)) { 1112e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 1113e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 22); /* enab 4-entry host queue cache */ 1114e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 18); /* enab early completion */ 1115e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */ 1116e49856d82a887ce365637176f9f99ab68076eae8Mark Lord 1117e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (want_ncq && sata_pmp_attached(ap)) { 1118e49856d82a887ce365637176f9f99ab68076eae8Mark Lord cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ 1119e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_config_fbs(port_mmio, 1); 1120e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } else { 1121e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_config_fbs(port_mmio, 0); 1122e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 1123e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 1124e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1125721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq) { 1126721091685f853ba4e6c49f26f989db0b1a811250Mark Lord cfg |= EDMA_CFG_NCQ; 1127721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 1128721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } else 1129721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN; 1130721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1131e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik writelfl(cfg, port_mmio + EDMA_CFG_OFS); 1132e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1133e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1134da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordstatic void mv_port_free_dma_mem(struct ata_port *ap) 1135da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord{ 1136da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1137da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_port_priv *pp = ap->private_data; 1138eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord int tag; 1139da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1140da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crqb) { 1141da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1142da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = NULL; 1143da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1144da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crpb) { 1145da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1146da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = NULL; 1147da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1148eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1149eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1150eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we have one unique sg_tbl per NCQ tag. 1151eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1152eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1153eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (pp->sg_tbl[tag]) { 1154eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) 1155eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_pool_free(hpriv->sg_tbl_pool, 1156eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag], 1157eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag]); 1158eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = NULL; 1159eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1160da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1161da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord} 1162da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 116305b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 116405b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_start - Port specific init/start routine. 116505b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 116605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 116705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Allocate and point to DMA memory, init port private memory, 116805b308e1df6d9d673daedb517969241f41278b52Brett Russ * zero indices. 116905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 117005b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 117105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 117205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 117331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap) 117431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1175cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct device *dev = ap->host->dev; 1176cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 117731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp; 1178dde2020754aeb14e17052d61784dcb37f252aac2James Bottomley int tag; 117931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 118024dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 11816037d6bbdff65eb5a84fe35e140f4da4f7cc103aJeff Garzik if (!pp) 118224dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return -ENOMEM; 1183da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord ap->private_data = pp; 118431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1185da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1186da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crqb) 1187da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 1188da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crqb, 0, MV_CRQB_Q_SZ); 118931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1190da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1191da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crpb) 1192da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord goto out_port_free_dma_mem; 1193da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crpb, 0, MV_CRPB_Q_SZ); 119431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1195eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1196eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1197eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we need one unique sg_tbl per NCQ tag. 1198eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1199eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1200eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) { 1201eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1202eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1203eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (!pp->sg_tbl[tag]) 1204eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord goto out_port_free_dma_mem; 1205eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } else { 1206eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = pp->sg_tbl[0]; 1207eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1208eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1209eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 121031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 1211da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1212da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordout_port_free_dma_mem: 1213da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 1214da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 121531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 121631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 121705b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 121805b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_stop - Port specific cleanup/stop routine. 121905b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 122005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 122105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Stop DMA, cleanup port memory. 122205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 122305b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 1224cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine uses the host lock to protect the DMA stop. 122505b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 122631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap) 122731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1228e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma(ap); 1229da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 123031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 123131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 123205b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 123305b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 123405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command whose SG list to source from 123505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 123605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Populate the SG list and mark the last entry. 123705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 123805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 123905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 124005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 12416c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzikstatic void mv_fill_sg(struct ata_queued_cmd *qc) 124231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 124331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = qc->ap->private_data; 1244972c26bdd6b58e7534473c4f7928584578cf43f4Jeff Garzik struct scatterlist *sg; 12453be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik struct mv_sg *mv_sg, *last_sg = NULL; 1246ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo unsigned int si; 124731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1248eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord mv_sg = pp->sg_tbl[qc->tag]; 1249ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 1250d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik dma_addr_t addr = sg_dma_address(sg); 1251d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik u32 sg_len = sg_dma_len(sg); 125222374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 12534007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson while (sg_len) { 12544007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 offset = addr & 0xffff; 12554007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 len = sg_len; 125622374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 12574007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson if ((offset + sg_len > 0x10000)) 12584007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson len = 0x10000 - offset; 12594007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 12604007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 12614007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 12626c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik mv_sg->flags_size = cpu_to_le32(len & 0xffff); 12634007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 12644007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson sg_len -= len; 12654007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson addr += len; 12664007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 12673be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg = mv_sg; 12684007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg++; 12694007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson } 127031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 12713be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik 12723be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik if (likely(last_sg)) 12733be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 127431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 127531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 12765796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzikstatic void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 127731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1278559eedad7f7764dacca33980127b4615011230e4Mark Lord u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 127931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ (last ? CRQB_CMD_LAST : 0); 1280559eedad7f7764dacca33980127b4615011230e4Mark Lord *cmdw = cpu_to_le16(tmp); 128131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 128231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 128305b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 128405b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_prep - Host specific command preparation. 128505b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to prepare 128605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 128705b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 128805b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it handles prep of the CRQB 128905b308e1df6d9d673daedb517969241f41278b52Brett Russ * (command request block), does some sanity checking, and calls 129005b308e1df6d9d673daedb517969241f41278b52Brett Russ * the SG load routine. 129105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 129205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 129305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 129405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 129531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc) 129631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 129731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_port *ap = qc->ap; 129831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = ap->private_data; 1299e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 *cw; 130031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_taskfile *tf; 130131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u16 flags = 0; 1302a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 130331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1304138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1305138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 130631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 130720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 130831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Fill in command request block 130931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1310e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 131131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= CRQB_FLAG_READ; 1312beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 131331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= qc->tag << CRQB_TAG_SHIFT; 1314e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 131531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1316bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1317fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 1318a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1319a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr = 1320eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1321a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr_hi = 1322eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1323a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 132431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1325a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord cw = &pp->crqb[in_index].ata_cmd[0]; 132631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ tf = &qc->tf; 132731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 132831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Sadly, the CRQB cannot accomodate all registers--there are 132931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * only 11 bytes...so we must pick and choose required 133031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * registers based on the command. So, we drop feature and 133131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * hob_feature for [RW] DMA commands, but they are needed for 133231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * NCQ. NCQ will drop hob_nsect. 133320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 133431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ switch (tf->command) { 133531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ: 133631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ_EXT: 133731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE: 133831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE_EXT: 1339c15d85c8f3f73b5f20aae7928e25b6996f16b328Jens Axboe case ATA_CMD_WRITE_FUA_EXT: 134031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 134131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 134231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_READ: 134331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_WRITE: 13448b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 134531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 134631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 134731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ default: 134831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* The only other commands EDMA supports in non-queued and 134931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 135031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * of which are defined/used by Linux. If we get here, this 135131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * driver needs work. 135231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * 135331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * FIXME: modify libata to give qc_prep a return value and 135431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * return error here. 135531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 135631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ BUG_ON(tf->command); 135731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 135831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 135931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 136031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 136131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 136231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 136331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 136431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 136531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 136631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 136731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 136831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1369e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 1370e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1371e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik mv_fill_sg(qc); 1372e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1373e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1374e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik/** 1375e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * mv_qc_prep_iie - Host specific command preparation. 1376e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * @qc: queued command to prepare 1377e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1378e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * This routine simply redirects to the general purpose routine 1379e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * if command is not DMA. Else, it handles prep of the CRQB 1380e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * (command request block), does some sanity checking, and calls 1381e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * the SG load routine. 1382e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1383e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * LOCKING: 1384e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * Inherited from caller. 1385e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik */ 1386e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc) 1387e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 1388e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_port *ap = qc->ap; 1389e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_port_priv *pp = ap->private_data; 1390e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_crqb_iie *crqb; 1391e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_taskfile *tf; 1392a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 1393e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik u32 flags = 0; 1394e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1395138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1396138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 1397e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1398e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1399e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* Fill in Gen IIE command request block */ 1400e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 1401e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= CRQB_FLAG_READ; 1402e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1403beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 1404e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= qc->tag << CRQB_TAG_SHIFT; 14058c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord flags |= qc->tag << CRQB_HOSTQ_SHIFT; 1406e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 1407e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1408bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1409fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 1410a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1411a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 1412eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1413eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1414e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->flags = cpu_to_le32(flags); 1415e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1416e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik tf = &qc->tf; 1417e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[0] = cpu_to_le32( 1418e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->command << 16) | 1419e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->feature << 24) 1420e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1421e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[1] = cpu_to_le32( 1422e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbal << 0) | 1423e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbam << 8) | 1424e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbah << 16) | 1425e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->device << 24) 1426e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1427e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[2] = cpu_to_le32( 1428e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbal << 0) | 1429e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbam << 8) | 1430e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbah << 16) | 1431e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_feature << 24) 1432e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1433e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[3] = cpu_to_le32( 1434e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->nsect << 0) | 1435e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_nsect << 8) 1436e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1437e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1438e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 143931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 144031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_fill_sg(qc); 144131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 144231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 144305b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 144405b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_issue - Initiate a command to the host 144505b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to start 144605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 144705b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 144805b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it sanity checks our local 144905b308e1df6d9d673daedb517969241f41278b52Brett Russ * caches of the request producer/consumer indices then enables 145005b308e1df6d9d673daedb517969241f41278b52Brett Russ * DMA and bumps the request producer index. 145105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 145205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 145305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 145405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 14559a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 145631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1457c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct ata_port *ap = qc->ap; 1458c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 1459c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1460bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 in_index; 146131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1462138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1463138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) { 146417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord /* 146517c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord * We're about to send a non-EDMA capable command to the 146631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * port. Turn off EDMA so there won't be problems accessing 146731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * shadow block, etc registers. 146831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1469b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 1470e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(ap, qc->dev->link->pmp); 14719363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo return ata_sff_qc_issue(qc); 147231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 147331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1474721091685f853ba4e6c49f26f989db0b1a811250Mark Lord mv_start_dma(ap, port_mmio, pp, qc->tf.protocol); 1475bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1476fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; 1477fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 147831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 147931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* and write the request in pointer to kick the EDMA to life */ 1480bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 1481bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 148231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 148331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 148431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 148531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14868f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lordstatic struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) 14878f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 14888f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct mv_port_priv *pp = ap->private_data; 14898f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc; 14908f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 14918f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 14928f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord return NULL; 14938f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord qc = ata_qc_from_tag(ap, ap->link.active_tag); 14948f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 14958f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord qc = NULL; 14968f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord return qc; 14978f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 14988f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 14998f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lordstatic void mv_unexpected_intr(struct ata_port *ap) 15008f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 15018f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct mv_port_priv *pp = ap->private_data; 15028f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_eh_info *ehi = &ap->link.eh_info; 15038f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord char *when = ""; 15048f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 15058f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord /* 15068f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord * We got a device interrupt from something that 15078f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord * was supposed to be using EDMA or polling. 15088f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord */ 15098f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_ehi_clear_desc(ehi); 15108f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 15118f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord when = " while EDMA enabled"; 15128f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } else { 15138f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 15148f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 15158f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord when = " while polling"; 15168f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } 15178f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_ehi_push_desc(ehi, "unexpected device interrupt%s", when); 15188f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->err_mask |= AC_ERR_OTHER; 15198f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->action |= ATA_EH_RESET; 15208f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_port_freeze(ap); 15218f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 15228f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 152305b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 152405b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_err_intr - Handle error interrupts on the port 152505b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 15269b358e305c1d783c8a4ebf00344e95deb9e38f3dMark Lord * @reset_allowed: bool: 0 == don't trigger from reset here 152705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 152805b308e1df6d9d673daedb517969241f41278b52Brett Russ * In most cases, just clear the interrupt and move on. However, 1529e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * some cases require an eDMA reset, which also performs a COMRESET. 1530e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * The SERR case requires a clear of pending errors in the SATA 1531e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * SERROR register. Finally, if the port disabled DMA, 1532e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * update our cached copy to match. 153305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 153405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 153505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 153605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 1537bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc) 153831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 153931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 1540bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 edma_err_cause, eh_freeze_mask, serr = 0; 1541bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1542bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 1543bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int edma_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); 1544bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int action = 0, err_mask = 0; 15459af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_eh_info *ehi = &ap->link.eh_info; 154620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1547bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 154820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1549bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!edma_enabled) { 1550bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* just a guess: do we need to do this? should we 1551bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik * expand this, and do it in all cases? 1552bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1553936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_read(&ap->link, SCR_ERROR, &serr); 1554936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 155520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 1556bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1557bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 1558bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1559352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ata_ehi_push_desc(ehi, "edma_err_cause=%08x", edma_err_cause); 1560bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1561bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 1562352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * All generations share these EDMA error cause bits: 1563bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1564bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_DEV) 1565bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_DEV; 1566bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 15676c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 1568bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR)) { 1569bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_ATA_BUS; 1570cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1571b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "parity error"); 1572bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1573bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 1574bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_hotplugged(ehi); 1575bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 1576b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo "dev disconnect" : "dev connect"); 1577cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1578bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1579bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1580352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 1581352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Gen-I has a different SELF_DIS bit, 1582352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * different FREEZE bits, and no SERR bit: 1583352fab701ca4753dd005b67ce5e512be944eb591Mark Lord */ 1584ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) { 1585bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE_5; 1586bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 1587bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1588b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 1589bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1590bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 1591bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE; 1592bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS) { 1593bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1594b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 1595bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1596bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SERR) { 1597936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_read(&ap->link, SCR_ERROR, &serr); 1598936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 1599bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_ATA_BUS; 1600cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1601bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1602afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 160320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 160420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Clear EDMA now that SERR cleanup done */ 16053606a380692cf958355a40fc1aa336800c17baf1Mark Lord writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 160620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1607bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!err_mask) { 1608bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_OTHER; 1609cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1610bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1611bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1612bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->serror |= serr; 1613bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->action |= action; 1614bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1615bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 1616bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 1617bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1618bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 1619bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1620bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & eh_freeze_mask) 1621bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 1622bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1623bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_abort(ap); 1624bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1625bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1626fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_response(struct ata_port *ap, 1627fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response, unsigned int tag, int ncq_enabled) 1628fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord{ 1629fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag); 1630fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 1631fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (qc) { 1632fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 ata_status; 1633fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u16 edma_status = le16_to_cpu(response->flags); 1634fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 1635fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * edma_status from a response queue entry: 1636fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only). 1637fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * MSB is saved ATA status from command completion. 1638fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 1639fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (!ncq_enabled) { 1640fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; 1641fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (err_cause) { 1642fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 1643fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * Error will be seen/handled by mv_err_intr(). 1644fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * So do nothing at all here. 1645fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 1646fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord return; 1647fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 1648fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 1649fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; 1650fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord qc->err_mask |= ac_err_mask(ata_status); 1651fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_qc_complete(qc); 1652fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 1653fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n", 1654fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord __func__, tag); 1655fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 1656fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord} 1657fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 1658fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) 1659bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 1660bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 1661bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 1662fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u32 in_index; 1663bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik bool work_done = false; 1664fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); 1665bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1666fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Get the hardware queue position index */ 1667bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) 1668bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 1669bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1670fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Process new responses from since the last time we looked */ 1671fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord while (in_index != pp->resp_idx) { 16726c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik unsigned int tag; 1673fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response = &pp->crpb[pp->resp_idx]; 1674bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1675fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; 1676bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1677fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (IS_GEN_I(hpriv)) { 1678fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 50xx: no NCQ, only one command active at a time */ 16799af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo tag = ap->link.active_tag; 1680fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 1681fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Gen II/IIE: get command tag from CRPB entry */ 1682fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord tag = le16_to_cpu(response->id) & 0x1f; 1683bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1684fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord mv_process_crpb_response(ap, response, tag, ncq_enabled); 1685bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik work_done = true; 1686bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1687bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1688352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Update the software queue position index in hardware */ 1689bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (work_done) 1690bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 1691fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), 1692bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 169320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 169420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 169505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 169605b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_host_intr - Handle all interrupts on the given host controller 1697cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * @host: host specific structure 16988f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord * @main_cause: Main interrupt cause register for the chip. 169905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 170005b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 170105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 170205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 1703a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lordstatic int mv_host_intr(struct ata_host *host, u32 main_cause) 170420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1705f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 1706a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord void __iomem *mmio = hpriv->base, *hc_mmio = NULL; 1707a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord u32 hc_irq_cause = 0; 1708a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0, port; 170920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1710a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord for (port = 0; port < hpriv->n_ports; port++) { 1711cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_port *ap = host->ports[port]; 17128f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu struct mv_port_priv *pp; 1713a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int shift, hardport, port_cause; 1714a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord /* 1715a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * When we move to the second hc, flag our cached 1716a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * copies of hc_mmio (and hc_irq_cause) as invalid again. 1717a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord */ 1718a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord if (port == MV_PORTS_PER_HC) 1719a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord hc_mmio = NULL; 1720a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord /* 1721a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * Do nothing if port is not interrupting or is disabled: 1722a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord */ 1723a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 1724a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord port_cause = (main_cause >> shift) & (DONE_IRQ | ERR_IRQ); 1725a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord if (!port_cause || !ap || (ap->flags & ATA_FLAG_DISABLED)) 1726a2c91a8819e315e9fd1aef3ff57badb6c1be3f80Jeff Garzik continue; 1727a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord /* 1728a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * Each hc within the host has its own hc_irq_cause register. 1729a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * We defer reading it until we know we need it, right now: 1730a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * 1731a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * FIXME later: we don't really need to read this register 1732a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * (some logic changes required below if we go that way), 1733a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * because it doesn't tell us anything new. But we do need 1734a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * to write to it, outside the top of this loop, 1735a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * to reset the interrupt triggers for next time. 1736a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord */ 1737a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord if (!hc_mmio) { 1738a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord hc_mmio = mv_hc_base_from_port(mmio, port); 1739a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 1740a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 1741a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = 1; 1742a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord } 17438f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord /* 17448f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord * Process completed CRPB response(s) before other events. 17458f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord */ 1746a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord pp = ap->private_data; 17478f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (hc_irq_cause & (DMA_IRQ << hardport)) { 17488f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) 1749fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord mv_process_crpb_entries(ap, pp); 17508f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } 17518f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord /* 17528f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord * Handle chip-reported errors, or continue on to handle PIO. 17538f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord */ 17548f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (unlikely(port_cause & ERR_IRQ)) { 17558f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord mv_err_intr(ap, mv_get_active_qc(ap)); 17568f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } else if (hc_irq_cause & (DEV_IRQ << hardport)) { 17578f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 17588f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc = mv_get_active_qc(ap); 17598f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (qc) { 17608f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_sff_host_intr(ap, qc); 17618f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord continue; 17628f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } 17638f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } 17648f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord mv_unexpected_intr(ap); 176520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 176620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 1767a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return handled; 176820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 176920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1770a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lordstatic int mv_pci_error(struct ata_host *host, void __iomem *mmio) 1771bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 177202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 1773bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_port *ap; 1774bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 1775bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_eh_info *ehi; 1776bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int i, err_mask, printed = 0; 1777bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 err_cause; 1778bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 177902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord err_cause = readl(mmio + hpriv->irq_cause_ofs); 1780bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1781bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", 1782bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_cause); 1783bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1784bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik DPRINTK("All regs @ PCI error\n"); 1785bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 1786bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 178702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord writelfl(0, mmio + hpriv->irq_cause_ofs); 1788bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1789bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik for (i = 0; i < host->n_ports; i++) { 1790bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ap = host->ports[i]; 1791936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo if (!ata_link_offline(&ap->link)) { 17929af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo ehi = &ap->link.eh_info; 1793bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 1794bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!printed++) 1795bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, 1796bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik "PCI err cause 0x%08x", err_cause); 1797bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_HOST_BUS; 1798cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo ehi->action = ATA_EH_RESET; 17999af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 1800bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 1801bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 1802bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1803bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 1804bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1805bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 1806bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1807bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1808a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return 1; /* handled */ 1809bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1810bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 181105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1812c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * mv_interrupt - Main interrupt event handler 181305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @irq: unused 181405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @dev_instance: private data; in this case the host structure 181505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 181605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read the read only register to determine if any host 181705b308e1df6d9d673daedb517969241f41278b52Brett Russ * controllers have pending interrupts. If so, call lower level 181805b308e1df6d9d673daedb517969241f41278b52Brett Russ * routine to handle. Also check for PCI errors which are only 181905b308e1df6d9d673daedb517969241f41278b52Brett Russ * reported here. 182005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 18218b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * LOCKING: 1822cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine holds the host lock while processing pending 182305b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts. 182405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 18257d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t mv_interrupt(int irq, void *dev_instance) 182620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1827cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = dev_instance; 1828f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 1829a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0; 1830352fab701ca4753dd005b67ce5e512be944eb591Mark Lord u32 main_cause, main_mask; 183120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1832646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord spin_lock(&host->lock); 1833352fab701ca4753dd005b67ce5e512be944eb591Mark Lord main_cause = readl(hpriv->main_cause_reg_addr); 1834352fab701ca4753dd005b67ce5e512be944eb591Mark Lord main_mask = readl(hpriv->main_mask_reg_addr); 1835352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 1836352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Deal with cases where we either have nothing pending, or have read 1837352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * a bogus register value which can indicate HW removal or PCI fault. 183820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 1839a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord if ((main_cause & main_mask) && (main_cause != 0xffffffffU)) { 1840a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord if (unlikely((main_cause & PCI_ERR) && HAS_PCI(host))) 1841a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = mv_pci_error(host, hpriv->base); 1842a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord else 1843a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = mv_host_intr(host, main_cause); 1844bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1845cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik spin_unlock(&host->lock); 184620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return IRQ_RETVAL(handled); 184720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 184820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1849c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic unsigned int mv5_scr_offset(unsigned int sc_reg_in) 1850c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1851c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs; 1852c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1853c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik switch (sc_reg_in) { 1854c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_STATUS: 1855c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_ERROR: 1856c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_CONTROL: 1857c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = sc_reg_in * sizeof(u32); 1858c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 1859c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik default: 1860c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = 0xffffffffU; 1861c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 1862c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 1863c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return ofs; 1864c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1865c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1866da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 1867c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1868f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 1869f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 18700d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 1871c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 1872c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1873da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 1874da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(addr + ofs); 1875da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1876da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1877da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 1878c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1879c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1880da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 1881c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1882f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 1883f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 18840d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 1885c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 1886c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1887da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 18880d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo writelfl(val, addr + ofs); 1889da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1890da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1891da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 1892c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1893c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 18947bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 1895522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 18967bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara struct pci_dev *pdev = to_pci_dev(host->dev); 1897522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik int early_5080; 1898522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 189944c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 1900522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1901522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik if (!early_5080) { 1902522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 1903522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= (1 << 0); 1904522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 1905522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik } 1906522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 19077bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara mv_reset_pci_bus(host, mmio); 1908522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 1909522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1910522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 1911522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 1912522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(0x0fcfffff, mmio + MV_FLASH_CTL); 1913522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 1914522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 191547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 1916ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 1917ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 1918c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 1919c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 1920c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1921c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 1922c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1923c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 1924c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 1925ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 1926ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 192747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 1928ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 1929522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp; 1930522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1931522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(0, mmio + MV_GPIO_PORT_CTL); 1932522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1933522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 1934522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1935522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 1936522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= ~(1 << 0); 1937522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 1938ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 1939ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 19402a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 19412a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 1942bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 1943c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, port); 1944c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 1945c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 1946c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 1947c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1948c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik if (fix_apm_sq) { 1949c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_LT_MODE); 1950c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= (1 << 19); 1951c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_LT_MODE); 1952c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1953c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_CTL); 1954c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~0x3; 1955c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x1; 1956c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_CTL); 1957c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 1958c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1959c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 1960c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~mask; 1961c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].pre; 1962c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].amps; 1963c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_MODE); 1964bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 1965bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 1966c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1967c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 1968c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, port_mmio + (reg)) 1969c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 1970c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 1971c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1972c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 1973c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1974b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* 1975b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * The datasheet warns against setting ATA_RST when EDMA is active 1976b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * (but doesn't say what the problem might be). So we first try 1977b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * to disable the EDMA engine before doing the ATA_RST operation. 1978b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord */ 1979e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 1980c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1981c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x028); /* command */ 1982c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(0x11f, port_mmio + EDMA_CFG_OFS); 1983c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x004); /* timer */ 1984c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x008); /* irq err cause */ 1985c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); /* irq err mask */ 1986c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); /* rq bah */ 1987c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); /* rq inp */ 1988c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); /* rq outp */ 1989c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x01c); /* respq bah */ 1990c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x024); /* respq outp */ 1991c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x020); /* respq inp */ 1992c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x02c); /* test control */ 1993c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 1994c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1995c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 1996c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1997c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, hc_mmio + (reg)) 1998c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 1999c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc) 200047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik{ 2001c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 2002c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 2003c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2004c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); 2005c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); 2006c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); 2007c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); 2008c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2009c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(hc_mmio + 0x20); 2010c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= 0x1c1c1c1c; 2011c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x03030303; 2012c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, hc_mmio + 0x20); 2013c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2014c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 2015c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2016c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2017c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 2018c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2019c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc, port; 2020c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2021c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (hc = 0; hc < n_hc; hc++) { 2022c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (port = 0; port < MV_PORTS_PER_HC; port++) 2023c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_hc_port(hpriv, mmio, 2024c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (hc * MV_PORTS_PER_HC) + port); 2025c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2026c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_one_hc(hpriv, mmio, hc); 2027c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2028c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2029c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return 0; 203047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik} 203147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 2032101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 2033101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#define ZERO(reg) writel(0, mmio + (reg)) 20347bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 2035101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 203602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 2037101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 2038101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2039101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp = readl(mmio + MV_PCI_MODE); 2040101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0xff00ffff; 2041101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(tmp, mmio + MV_PCI_MODE); 2042101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2043101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_DISC_TIMER); 2044101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_MSI_TRIGGER); 2045101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); 2046101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(HC_MAIN_IRQ_MASK_OFS); 2047101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_SERR_MASK); 204802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_cause_ofs); 204902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_mask_ofs); 2050101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_LOW_ADDRESS); 2051101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_HIGH_ADDRESS); 2052101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_ATTRIBUTE); 2053101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_COMMAND); 2054101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2055101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 2056101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2057101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 2058101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 2059101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 2060101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2061101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik mv5_reset_flash(hpriv, mmio); 2062101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2063101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp = readl(mmio + MV_GPIO_PORT_CTL); 2064101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0x3; 2065101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp |= (1 << 5) | (1 << 6); 2066101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(tmp, mmio + MV_GPIO_PORT_CTL); 2067101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2068101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2069101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik/** 2070101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * mv6_reset_hc - Perform the 6xxx global soft reset 2071101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * @mmio: base address of the HBA 2072101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2073101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * This routine only applies to 6xxx parts. 2074101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2075101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * LOCKING: 2076101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * Inherited from caller. 2077101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2078c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2079c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 2080101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 2081101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; 2082101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik int i, rc = 0; 2083101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 t; 2084101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2085101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* Following procedure defined in PCI "main command and status 2086101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * register" table. 2087101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2088101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2089101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | STOP_PCI_MASTER, reg); 2090101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2091101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik for (i = 0; i < 1000; i++) { 2092101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2093101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 20942dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik if (PCI_MASTER_EMPTY & t) 2095101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik break; 2096101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2097101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(PCI_MASTER_EMPTY & t)) { 2098101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 2099101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2100101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2101101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2102101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2103101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* set reset */ 2104101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2105101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2106101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | GLOB_SFT_RST, reg); 2107101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2108101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2109101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 2110101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2111101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(GLOB_SFT_RST & t)) { 2112101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 2113101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2114101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2115101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2116101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2117101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 2118101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2119101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2120101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 2121101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2122101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2123101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while ((GLOB_SFT_RST & t) && (i-- > 0)); 2124101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2125101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (GLOB_SFT_RST & t) { 2126101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 2127101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2128101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2129094e50b2f74146d8ee924fea4808e58c4ed2f163Mark Lord /* 2130094e50b2f74146d8ee924fea4808e58c4ed2f163Mark Lord * Temporary: wait 3 seconds before port-probing can happen, 2131094e50b2f74146d8ee924fea4808e58c4ed2f163Mark Lord * so that we don't miss finding sleepy SilXXXX port-multipliers. 2132094e50b2f74146d8ee924fea4808e58c4ed2f163Mark Lord * This can go away once hotplug is fully/correctly implemented. 2133094e50b2f74146d8ee924fea4808e58c4ed2f163Mark Lord */ 2134094e50b2f74146d8ee924fea4808e58c4ed2f163Mark Lord if (rc == 0) 2135094e50b2f74146d8ee924fea4808e58c4ed2f163Mark Lord msleep(3000); 2136101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikdone: 2137101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik return rc; 2138101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2139101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 214047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 2141ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 2142ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 2143ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *port_mmio; 2144ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik u32 tmp; 2145ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2146ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(mmio + MV_RESET_CFG); 2147ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik if ((tmp & (1 << 0)) == 0) { 214847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->signal[idx].amps = 0x7 << 8; 2149ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = 0x1 << 5; 2150ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik return; 2151ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik } 2152ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2153ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik port_mmio = mv_port_base(mmio, idx); 2154ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(port_mmio + PHY_MODE2); 2155ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2156ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2157ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2158ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2159ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 216047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 2161ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 216247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(0x00000060, mmio + MV_GPIO_PORT_CTL); 2163ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2164ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2165c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 21662a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 2167bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 2168c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2169c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2170bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 217147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik int fix_phy_mode2 = 217247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 2173bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik int fix_phy_mode4 = 217447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 217547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik u32 m2, tmp; 217647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 217747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (fix_phy_mode2) { 217847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 217947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 218047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 |= (1 << 31); 218147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 218247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 218347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 218447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 218547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 218647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~((1 << 16) | (1 << 31)); 218747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 218847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 218947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 219047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 219147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 219247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik /* who knows what this magic does */ 219347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp = readl(port_mmio + PHY_MODE3); 219447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp &= ~0x7F800000; 219547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp |= 0x2A800000; 219647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(tmp, port_mmio + PHY_MODE3); 2197bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2198bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (fix_phy_mode4) { 219947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik u32 m4; 2200bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2201bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m4 = readl(port_mmio + PHY_MODE4); 220247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 220347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (hp_flags & MV_HP_ERRATA_60X1B2) 2204e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord tmp = readl(port_mmio + PHY_MODE3); 2205bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2206e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* workaround for errata FEr SATA#10 (part 1) */ 2207bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m4 = (m4 & ~(1 << 1)) | (1 << 0); 2208bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2209bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m4, port_mmio + PHY_MODE4); 221047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 221147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (hp_flags & MV_HP_ERRATA_60X1B2) 2212e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord writel(tmp, port_mmio + PHY_MODE3); 2213bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2214bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2215bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik /* Revert values of pre-emphasis and signal amps to the saved ones */ 2216bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 2217bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2218bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 &= ~MV_M2_PREAMP_MASK; 22192a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].amps; 22202a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].pre; 222147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 2222bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2223e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* according to mvSata 3.6.1, some IIE values are fixed */ 2224e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (IS_GEN_IIE(hpriv)) { 2225e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 &= ~0xC30FF01F; 2226e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 |= 0x0000900F; 2227e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 2228e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2229bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 2230bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2231bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2232f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* TODO: use the generic LED interface to configure the SATA Presence */ 2233f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* & Acitivy LEDs on the board */ 2234f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 2235f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2236f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2237f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2238f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2239f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2240f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 2241f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2242f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2243f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio; 2244f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara u32 tmp; 2245f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2246f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara port_mmio = mv_port_base(mmio, idx); 2247f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(port_mmio + PHY_MODE2); 2248f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2249f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2250f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2251f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2252f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2253f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2254f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, port_mmio + (reg)) 2255f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 2256f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int port) 2257f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2258f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio = mv_port_base(mmio, port); 2259f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2260b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* 2261b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * The datasheet warns against setting ATA_RST when EDMA is active 2262b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * (but doesn't say what the problem might be). So we first try 2263b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * to disable the EDMA engine before doing the ATA_RST operation. 2264b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord */ 2265e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 2266f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2267f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x028); /* command */ 2268f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0x101f, port_mmio + EDMA_CFG_OFS); 2269f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x004); /* timer */ 2270f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x008); /* irq err cause */ 2271f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); /* irq err mask */ 2272f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); /* rq bah */ 2273f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); /* rq inp */ 2274f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x018); /* rq outp */ 2275f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x01c); /* respq bah */ 2276f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x024); /* respq outp */ 2277f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x020); /* respq inp */ 2278f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x02c); /* test control */ 2279f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 2280f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2281f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2282f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2283f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2284f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, hc_mmio + (reg)) 2285f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 2286f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2287f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2288f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *hc_mmio = mv_hc_base(mmio, 0); 2289f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2290f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); 2291f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); 2292f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); 2293f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2294f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2295f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2296f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2297f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2298f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 2299f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc) 2300f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2301f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int port; 2302f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2303f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara for (port = 0; port < hpriv->n_ports; port++) 2304f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_hc_port(hpriv, mmio, port); 2305f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2306f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_one_hc(hpriv, mmio); 2307f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2308f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 2309f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2310f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2311f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 2312f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2313f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2314f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2315f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2316f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2317f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 2318f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2319f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2320f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2321f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2322b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lordstatic void mv_setup_ifctl(void __iomem *port_mmio, int want_gen2i) 2323b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord{ 2324b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord u32 ifctl = readl(port_mmio + SATA_INTERFACE_CFG); 2325b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 2326b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord ifctl = (ifctl & 0xf7f) | 0x9b1000; /* from chip spec */ 2327b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (want_gen2i) 2328b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord ifctl |= (1 << 7); /* enable gen2i speed */ 2329b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord writelfl(ifctl, port_mmio + SATA_INTERFACE_CFG); 2330b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord} 2331b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 2332b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord/* 2333b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * Caller must ensure that EDMA is not active, 2334b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * by first doing mv_stop_edma() where needed. 2335b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord */ 2336e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 2337c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no) 2338c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2339c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port_no); 2340c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 23410d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord mv_stop_edma_engine(port_mmio); 2342c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); 2343c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2344b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (!IS_GEN_I(hpriv)) { 2345b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord /* Enable 3.0gb/s link speed */ 2346b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord mv_setup_ifctl(port_mmio, 1); 2347c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2348b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord /* 2349b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * Strobing ATA_RST here causes a hard reset of the SATA transport, 2350b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * link, and physical layers. It resets all SATA interface registers 2351b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev. 2352c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik */ 2353b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); 2354b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord udelay(25); /* allow reset propagation */ 2355c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writelfl(0, port_mmio + EDMA_CMD_OFS); 2356c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2357c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->ops->phy_errata(hpriv, mmio, port_no); 2358c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2359ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) 2360c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mdelay(1); 2361c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2362c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2363e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp) 236420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2365e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (sata_pmp_supported(ap)) { 2366e49856d82a887ce365637176f9f99ab68076eae8Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 2367e49856d82a887ce365637176f9f99ab68076eae8Mark Lord u32 reg = readl(port_mmio + SATA_IFCTL_OFS); 2368e49856d82a887ce365637176f9f99ab68076eae8Mark Lord int old = reg & 0xf; 236922374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 2370e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (old != pmp) { 2371e49856d82a887ce365637176f9f99ab68076eae8Mark Lord reg = (reg & ~0xf) | pmp; 2372e49856d82a887ce365637176f9f99ab68076eae8Mark Lord writelfl(reg, port_mmio + SATA_IFCTL_OFS); 2373e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 237422374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik } 237520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 237620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2377e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 2378e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 237922374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik{ 2380e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 2381e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return sata_std_hardreset(link, class, deadline); 2382e49856d82a887ce365637176f9f99ab68076eae8Mark Lord} 2383bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2384e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 2385e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 2386e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 2387e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 2388e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return ata_sff_softreset(link, class, deadline); 238922374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik} 239022374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 2391cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 2392bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned long deadline) 239331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 2394cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo struct ata_port *ap = link->ap; 2395bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2396b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 2397f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 23980d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord int rc, attempts = 0, extra = 0; 23990d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord u32 sstatus; 24000d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord bool online; 240131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2402e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, ap->port_no); 2403b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2404bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 24050d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Workaround for errata FEr SATA#10 (part 2) */ 24060d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord do { 240717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord const unsigned long *timing = 240817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord sata_ehc_deb_timing(&link->eh_context); 2409bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 241017c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord rc = sata_link_hardreset(link, timing, deadline + extra, 241117c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord &online, NULL); 241217c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord if (rc) 24130d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord return rc; 24140d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord sata_scr_read(link, SCR_STATUS, &sstatus); 24150d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 24160d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Force 1.5gb/s link speed and try again */ 24170d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord mv_setup_ifctl(mv_ap_base(ap), 0); 24180d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (time_after(jiffies + HZ, deadline)) 24190d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord extra = HZ; /* only extend it once, max */ 24200d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } 24210d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); 2422bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 242317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord return rc; 2424bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2425bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2426bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap) 2427bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2428f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 24291cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord unsigned int shift, hardport, port = ap->port_no; 2430352fab701ca4753dd005b67ce5e512be944eb591Mark Lord u32 main_mask; 2431bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2432bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* FIXME: handle coalescing completion events properly */ 2433bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 24341cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord mv_stop_edma(ap); 24351cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2436bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2437bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* disable assertion of portN err, done events */ 2438352fab701ca4753dd005b67ce5e512be944eb591Mark Lord main_mask = readl(hpriv->main_mask_reg_addr); 2439352fab701ca4753dd005b67ce5e512be944eb591Mark Lord main_mask &= ~((DONE_IRQ | ERR_IRQ) << shift); 2440352fab701ca4753dd005b67ce5e512be944eb591Mark Lord writelfl(main_mask, hpriv->main_mask_reg_addr); 2441bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2442bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2443bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap) 2444bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2445f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 24461cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord unsigned int shift, hardport, port = ap->port_no; 24471cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); 2448bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 2449352fab701ca4753dd005b67ce5e512be944eb591Mark Lord u32 main_mask, hc_irq_cause; 2450bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2451bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* FIXME: handle coalescing completion events properly */ 2452bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 24531cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2454bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2455bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA errors on this port */ 2456bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2457bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2458bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear pending irq events */ 2459bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 24601cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport); 24611cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 2462bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2463bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* enable assertion of portN err, done events */ 2464352fab701ca4753dd005b67ce5e512be944eb591Mark Lord main_mask = readl(hpriv->main_mask_reg_addr); 2465352fab701ca4753dd005b67ce5e512be944eb591Mark Lord main_mask |= ((DONE_IRQ | ERR_IRQ) << shift); 2466352fab701ca4753dd005b67ce5e512be944eb591Mark Lord writelfl(main_mask, hpriv->main_mask_reg_addr); 246731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 246831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 246905b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 247005b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_init - Perform some early initialization on a single port. 247105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port: libata data structure storing shadow register addresses 247205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port_mmio: base address of the port 247305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 247405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Initialize shadow register mmio addresses, clear outstanding 247505b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts on the port, and unmask interrupts for the future 247605b308e1df6d9d673daedb517969241f41278b52Brett Russ * start of the port. 247705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 247805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 247905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 248005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 248131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 248220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 24830d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *shd_base = port_mmio + SHD_BLK_OFS; 248431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ unsigned serr_ofs; 248531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 24868b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik /* PIO related setup 248731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 248831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 24898b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->error_addr = 249031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 249131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 249231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 249331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 249431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 249531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 24968b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->status_addr = 249731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 249831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* special case: control/altstatus doesn't have ATA_REG_ address */ 249931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; 250031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 250131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* unused: */ 25028d9db2d2fbae9e05022825c32f86e00c8e342860Randy Dunlap port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; 250320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 250431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding port interrupt conditions */ 250531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ serr_ofs = mv_scr_offset(SCR_ERROR); 250631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); 250731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 250831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2509646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord /* unmask all non-transient EDMA error interrupts */ 2510646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS); 251120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25128b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 251331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_CFG_OFS), 251431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), 251531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); 251620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 251720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25184447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_chip_id(struct ata_host *host, unsigned int board_idx) 2519bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 25204447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 25214447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 2522bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 2523bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 25245796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik switch (board_idx) { 252547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case chip_5080: 252647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 2527ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 252847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 252944c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 253047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x1: 253147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 253247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 253347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 253447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 253547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 253647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 253747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 253847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying 50XXB2 workarounds to unknown rev\n"); 253947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 254047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 254147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 254247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 254347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 2544bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_504x: 2545bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_508x: 254647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 2547ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 2548bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 254944c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 255047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x0: 255147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 255247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 255347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 255447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 255547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 255647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 255747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 255847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 255947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 256047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 2561bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2562bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2563bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2564bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_604x: 2565bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_608x: 256647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv6xxx_ops; 2567ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_II; 256847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 256944c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 257047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x7: 257147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 257247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 257347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x9: 257447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2575bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2576bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 2577bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 257847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 257947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 2580bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2581bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2582bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2583bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2584e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_7042: 258502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hp_flags |= MV_HP_PCIE; 2586306b30f74d37f289033c696285e07ce0158a5d7bMark Lord if (pdev->vendor == PCI_VENDOR_ID_TTI && 2587306b30f74d37f289033c696285e07ce0158a5d7bMark Lord (pdev->device == 0x2300 || pdev->device == 0x2310)) 2588306b30f74d37f289033c696285e07ce0158a5d7bMark Lord { 25894e5200334e03e5620aa19d538300c13db270a063Mark Lord /* 25904e5200334e03e5620aa19d538300c13db270a063Mark Lord * Highpoint RocketRAID PCIe 23xx series cards: 25914e5200334e03e5620aa19d538300c13db270a063Mark Lord * 25924e5200334e03e5620aa19d538300c13db270a063Mark Lord * Unconfigured drives are treated as "Legacy" 25934e5200334e03e5620aa19d538300c13db270a063Mark Lord * by the BIOS, and it overwrites sector 8 with 25944e5200334e03e5620aa19d538300c13db270a063Mark Lord * a "Lgcy" metadata block prior to Linux boot. 25954e5200334e03e5620aa19d538300c13db270a063Mark Lord * 25964e5200334e03e5620aa19d538300c13db270a063Mark Lord * Configured drives (RAID or JBOD) leave sector 8 25974e5200334e03e5620aa19d538300c13db270a063Mark Lord * alone, but instead overwrite a high numbered 25984e5200334e03e5620aa19d538300c13db270a063Mark Lord * sector for the RAID metadata. This sector can 25994e5200334e03e5620aa19d538300c13db270a063Mark Lord * be determined exactly, by truncating the physical 26004e5200334e03e5620aa19d538300c13db270a063Mark Lord * drive capacity to a nice even GB value. 26014e5200334e03e5620aa19d538300c13db270a063Mark Lord * 26024e5200334e03e5620aa19d538300c13db270a063Mark Lord * RAID metadata is at: (dev->n_sectors & ~0xfffff) 26034e5200334e03e5620aa19d538300c13db270a063Mark Lord * 26044e5200334e03e5620aa19d538300c13db270a063Mark Lord * Warn the user, lest they think we're just buggy. 26054e5200334e03e5620aa19d538300c13db270a063Mark Lord */ 26064e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 26074e5200334e03e5620aa19d538300c13db270a063Mark Lord " BIOS CORRUPTS DATA on all attached drives," 26084e5200334e03e5620aa19d538300c13db270a063Mark Lord " regardless of if/how they are configured." 26094e5200334e03e5620aa19d538300c13db270a063Mark Lord " BEWARE!\n"); 26104e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": For data safety, do not" 26114e5200334e03e5620aa19d538300c13db270a063Mark Lord " use sectors 8-9 on \"Legacy\" drives," 26124e5200334e03e5620aa19d538300c13db270a063Mark Lord " and avoid the final two gigabytes on" 26134e5200334e03e5620aa19d538300c13db270a063Mark Lord " all RocketRAID BIOS initialized drives.\n"); 2614306b30f74d37f289033c696285e07ce0158a5d7bMark Lord } 2615e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_6042: 2616e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hpriv->ops = &mv6xxx_ops; 2617e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_GEN_IIE; 2618e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 261944c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 2620e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case 0x0: 2621e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_XX42A0; 2622e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2623e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case 0x1: 2624e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2625e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2626e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik default: 2627e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 2628e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik "Applying 60X1C0 workarounds to unknown rev\n"); 2629e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2630e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2631e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 2632e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2633f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara case chip_soc: 2634f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->ops = &mv_soc_ops; 2635f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hp_flags |= MV_HP_ERRATA_60X1C0; 2636f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara break; 2637e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2638bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 2639f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_ERR, host->dev, 26405796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik "BUG: invalid board index %u\n", board_idx); 2641bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 1; 2642bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2643bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2644bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik hpriv->hp_flags = hp_flags; 264502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord if (hp_flags & MV_HP_PCIE) { 264602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS; 264702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS; 264802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 264902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } else { 265002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS; 265102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS; 265202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 265302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } 2654bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2655bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 0; 2656bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2657bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 265805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 265947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik * mv_init_host - Perform some early initialization of the host. 26604447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to initialize 26614447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @board_idx: controller index 266205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 266305b308e1df6d9d673daedb517969241f41278b52Brett Russ * If possible, do an early global reset of the host. Then do 266405b308e1df6d9d673daedb517969241f41278b52Brett Russ * our port init and clear/unmask all/relevant host interrupts. 266505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 266605b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 266705b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 266805b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 26694447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_init_host(struct ata_host *host, unsigned int board_idx) 267020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 267120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ int rc = 0, n_hc, port, hc; 26724447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 2673f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 267447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 26754447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_chip_id(host, board_idx); 2676bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (rc) 2677352fab701ca4753dd005b67ce5e512be944eb591Mark Lord goto done; 2678f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2679f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2680352fab701ca4753dd005b67ce5e512be944eb591Mark Lord hpriv->main_cause_reg_addr = mmio + HC_MAIN_IRQ_CAUSE_OFS; 2681352fab701ca4753dd005b67ce5e512be944eb591Mark Lord hpriv->main_mask_reg_addr = mmio + HC_MAIN_IRQ_MASK_OFS; 2682f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } else { 2683352fab701ca4753dd005b67ce5e512be944eb591Mark Lord hpriv->main_cause_reg_addr = mmio + HC_SOC_MAIN_IRQ_CAUSE_OFS; 2684352fab701ca4753dd005b67ce5e512be944eb591Mark Lord hpriv->main_mask_reg_addr = mmio + HC_SOC_MAIN_IRQ_MASK_OFS; 2685f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2686352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 2687352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* global interrupt mask: 0 == mask everything */ 2688f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0, hpriv->main_mask_reg_addr); 2689bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 26904447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_hc = mv_get_hc_count(host->ports[0]->flags); 2691bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 26924447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) 269347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->read_preamp(hpriv, port, mmio); 269420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2695c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 269647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (rc) 269720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ goto done; 269820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2699522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik hpriv->ops->reset_flash(hpriv, mmio); 27007bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara hpriv->ops->reset_bus(host, mmio); 270147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->enable_leds(hpriv, mmio); 270220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 27034447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) { 2704cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo struct ata_port *ap = host->ports[port]; 27052a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2706cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 2707cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo mv_port_init(&ap->ioaddr, port_mmio); 2708cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 27097bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 2710f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2711f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int offset = port_mmio - mmio; 2712f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 2713f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 2714f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 27157bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 271620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 271720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 271820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hc; hc++) { 271931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 272031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 272131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 272231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ "(before clear)=0x%08x\n", hc, 272331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_CFG_OFS), 272431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_IRQ_CAUSE_OFS)); 272531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 272631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding hc interrupt conditions */ 272731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); 272820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 272920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2730f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2731f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* Clear any currently outstanding host interrupt conditions */ 2732f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(0, mmio + hpriv->irq_cause_ofs); 273331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2734f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* and unmask interrupt generation for host regs */ 2735f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs); 2736f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (IS_GEN_I(hpriv)) 2737f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS_5, 2738f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr); 2739f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara else 2740f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS, 2741f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr); 2742f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2743f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x " 2744f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "PCI int cause/mask=0x%08x/0x%08x\n", 2745f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_cause_reg_addr), 2746f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_mask_reg_addr), 2747f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(mmio + hpriv->irq_cause_ofs), 2748f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(mmio + hpriv->irq_mask_ofs)); 2749f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } else { 2750f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS_SOC, 2751f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->main_mask_reg_addr); 2752f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n", 2753f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_cause_reg_addr), 2754f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(hpriv->main_mask_reg_addr)); 2755f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2756f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharadone: 2757f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 2758f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2759fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik 2760fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradleystatic int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 2761fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley{ 2762fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 2763fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRQB_Q_SZ, 0); 2764fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crqb_pool) 2765fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2766fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2767fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 2768fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRPB_Q_SZ, 0); 2769fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crpb_pool) 2770fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2771fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2772fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 2773fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_SG_TBL_SZ, 0); 2774fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->sg_tbl_pool) 2775fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2776fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2777fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return 0; 2778fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley} 2779fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 278015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhekstatic void mv_conf_mbus_windows(struct mv_host_priv *hpriv, 278115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_target_info *dram) 278215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek{ 278315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek int i; 278415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 278515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < 4; i++) { 278615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_CTRL(i)); 278715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_BASE(i)); 278815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 278915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 279015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < dram->num_cs; i++) { 279115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_window *cs = dram->cs + i; 279215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 279315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(((cs->size - 1) & 0xffff0000) | 279415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (cs->mbus_attr << 8) | 279515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (dram->mbus_dram_target_id << 4) | 1, 279615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek hpriv->base + WINDOW_CTRL(i)); 279715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(cs->base, hpriv->base + WINDOW_BASE(i)); 279815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 279915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek} 280015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 2801f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/** 2802f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_probe - handle a positive probe of an soc Marvell 2803f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * host 2804f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device found 2805f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2806f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * LOCKING: 2807f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Inherited from caller. 2808f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2809f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev) 2810f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2811f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara static int printed_version; 2812f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct mv_sata_platform_data *mv_platform_data; 2813f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct ata_port_info *ppi[] = 2814f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { &mv_port_info[chip_soc], NULL }; 2815f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host; 2816f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv; 2817f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct resource *res; 2818f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports, rc; 281920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2820f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!printed_version++) 2821f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 2822bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2823f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 2824f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Simple resource validation .. 2825f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2826f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (unlikely(pdev->num_resources != 2)) { 2827f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_err(&pdev->dev, "invalid number of resources\n"); 2828f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 2829f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2830f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2831f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 2832f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Get the register base first 2833f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2834f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2835f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (res == NULL) 2836f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 2837f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2838f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* allocate host */ 2839f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_platform_data = pdev->dev.platform_data; 2840f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara n_ports = mv_platform_data->n_ports; 2841f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2842f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 2843f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 2844f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2845f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!host || !hpriv) 2846f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -ENOMEM; 2847f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->private_data = hpriv; 2848f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 2849f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2850f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->iomap = NULL; 2851f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara hpriv->base = devm_ioremap(&pdev->dev, res->start, 2852f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara res->end - res->start + 1); 2853f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base -= MV_SATAHC0_REG_BASE; 2854f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 285515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek /* 285615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek * (Re-)program MBUS remapping windows if we are asked to. 285715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek */ 285815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek if (mv_platform_data->dram != NULL) 285915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek mv_conf_mbus_windows(hpriv, mv_platform_data->dram); 286015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 2861fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley rc = mv_create_dma_pools(hpriv, &pdev->dev); 2862fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (rc) 2863fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return rc; 2864fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2865f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* initialize adapter */ 2866f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = mv_init_host(host, chip_soc); 2867f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc) 2868f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 2869f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2870f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, 2871f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, 2872f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->n_ports); 2873f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2874f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, 2875f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara IRQF_SHARED, &mv6_sht); 2876f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2877f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2878f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* 2879f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2880f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_remove - unplug a platform interface 2881f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device 2882f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2883f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * A platform bus SATA device has been unplugged. Perform the needed 2884f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * cleanup. Also called on module unload for any active devices. 2885f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2886f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev) 2887f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2888f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct device *dev = &pdev->dev; 2889f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host = dev_get_drvdata(dev); 2890f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2891f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_host_detach(host); 2892f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 289320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 289420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2895f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic struct platform_driver mv_platform_driver = { 2896f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_platform_probe, 2897f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .remove = __devexit_p(mv_platform_remove), 2898f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .driver = { 2899f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .name = DRV_NAME, 2900f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .owner = THIS_MODULE, 2901f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 2902f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 2903f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2904f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 29057bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 2906f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 2907f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent); 2908f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 29097bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29107bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic struct pci_driver mv_pci_driver = { 29117bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .name = DRV_NAME, 29127bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .id_table = mv_pci_tbl, 2913f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_pci_init_one, 29147bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .remove = ata_pci_remove_one, 29157bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara}; 29167bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29177bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* 29187bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara * module options 29197bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara */ 29207bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int msi; /* Use PCI msi; either zero (off, default) or non-zero */ 29217bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29227bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29237bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* move to PCI layer or libata core? */ 29247bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int pci_go_64(struct pci_dev *pdev) 29257bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara{ 29267bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc; 29277bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29287bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 29297bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 29307bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29317bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 29327bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29337bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 29347bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "64-bit DMA enable failed\n"); 29357bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29367bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29377bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29387bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } else { 29397bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 29407bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29417bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 29427bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit DMA enable failed\n"); 29437bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29447bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29457bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 29467bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29477bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 29487bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit consistent DMA enable failed\n"); 29497bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29507bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29517bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29527bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29537bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29547bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara} 29557bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 295605b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 295705b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_print_info - Dump key info to kernel log for perusal. 29584447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to print info about 295905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 296005b308e1df6d9d673daedb517969241f41278b52Brett Russ * FIXME: complete this. 296105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 296205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 296305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 296405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 29654447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic void mv_print_info(struct ata_host *host) 296631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 29674447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 29684447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 296944c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok u8 scc; 2970c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik const char *scc_s, *gen; 297131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 297231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Use this to determine the HW stepping of the chip so we know 297331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * what errata to workaround 297431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 297531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 297631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (scc == 0) 297731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "SCSI"; 297831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else if (scc == 0x01) 297931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "RAID"; 298031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else 2981c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik scc_s = "?"; 2982c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik 2983c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik if (IS_GEN_I(hpriv)) 2984c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "I"; 2985c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_II(hpriv)) 2986c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "II"; 2987c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_IIE(hpriv)) 2988c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "IIE"; 2989c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else 2990c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "?"; 299131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2992a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, 2993c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 2994c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 299531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 299631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 299731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 299805b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 2999f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_pci_init_one - handle a positive probe of a PCI Marvell host 300005b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pdev: PCI device found 300105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ent: PCI device ID entry for the matched host 300205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 300305b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 300405b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 300505b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 3006f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 3007f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent) 300820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 30092dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik static int printed_version; 301020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int board_idx = (unsigned int)ent->driver_data; 30114447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 30124447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct ata_host *host; 30134447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv; 30144447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo int n_ports, rc; 301520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3016a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik if (!printed_version++) 3017a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 301820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30194447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* allocate host */ 30204447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 30214447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 30224447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 30234447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 30244447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (!host || !hpriv) 30254447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return -ENOMEM; 30264447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->private_data = hpriv; 3027f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 30284447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 30294447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* acquire resources */ 303024dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo rc = pcim_enable_device(pdev); 303124dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 303220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return rc; 303320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30340d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 30350d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc == -EBUSY) 303624dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pcim_pin_device(pdev); 30370d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc) 303824dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 30394447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->iomap = pcim_iomap_table(pdev); 3040f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base = host->iomap[MV_PRIMARY_BAR]; 304120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3042d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik rc = pci_go_64(pdev); 3043d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik if (rc) 3044d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik return rc; 3045d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik 3046da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord rc = mv_create_dma_pools(hpriv, &pdev->dev); 3047da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (rc) 3048da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return rc; 3049da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 305020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* initialize adapter */ 30514447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_init_host(host, board_idx); 305224dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 305324dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 305420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 305531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Enable interrupts */ 30566a59dcf8678cbc4106a8a6e158d7408a87691358Tejun Heo if (msi && pci_enable_msi(pdev)) 305731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_intx(pdev, 1); 305820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 305931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 30604447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo mv_print_info(host); 306120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30624447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo pci_set_master(pdev); 3063ea8b4db97aa41a66c05daa4055a1974692ccd52dJeff Garzik pci_try_set_mwi(pdev); 30644447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 3065c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 306620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 30677bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 306820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3069f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev); 3070f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev); 3071f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 307220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic int __init mv_init(void) 307320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 30747bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc = -ENODEV; 30757bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 30767bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_register_driver(&mv_pci_driver); 3077f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 3078f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3079f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#endif 3080f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = platform_driver_register(&mv_platform_driver); 3081f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3082f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#ifdef CONFIG_PCI 3083f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 3084f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara pci_unregister_driver(&mv_pci_driver); 30857bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 30867bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 308720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 308820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 308920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic void __exit mv_exit(void) 309020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 30917bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 309220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ pci_unregister_driver(&mv_pci_driver); 30937bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 3094f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara platform_driver_unregister(&mv_platform_driver); 309520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 309620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 309720f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_AUTHOR("Brett Russ"); 309820f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 309920f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_LICENSE("GPL"); 310020f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DEVICE_TABLE(pci, mv_pci_tbl); 310120f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_VERSION(DRV_VERSION); 310217c5aab5b34e351531466e35b154ca86db7d46a9Mark LordMODULE_ALIAS("platform:" DRV_NAME); 310320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 31047bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 3105ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzikmodule_param(msi, int, 0444); 3106ddef9bb367b19383df627e388cb4c01c86ddba6cJeff GarzikMODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 31077bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 3108ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzik 310920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_init(mv_init); 311020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_exit(mv_exit); 3111