sata_mv.c revision 9b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0
120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * sata_mv.c - Marvell SATA support 320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 4e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * Copyright 2008: Marvell Corporation, all rights reserved. 58b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * Copyright 2005: EMC Corporation, all rights reserved. 6e2b1be56c5656902744c2b52e8304126a40bb609Jeff Garzik * Copyright 2005 Red Hat, Inc. All rights reserved. 720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is free software; you can redistribute it and/or modify 1120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * it under the terms of the GNU General Public License as published by 1220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * the Free Software Foundation; version 2 of the License. 1320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * This program is distributed in the hope that it will be useful, 1520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * but WITHOUT ANY WARRANTY; without even the implied warranty of 1620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * GNU General Public License for more details. 1820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 1920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * You should have received a copy of the GNU General Public License 2020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * along with this program; if not, write to the Free Software 2120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 2220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * 2320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 2420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 254a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik/* 2685afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * sata_mv TODO list: 2785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 2885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Errata workaround for NCQ device errors. 2985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> More errata workarounds for PCI-X. 3185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3285afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Complete a full errata audit for all chipsets to identify others. 3385afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3485afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it). 3585afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3685afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Investigate problems with PCI Message Signalled Interrupts (MSI). 3785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 3885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead. 3985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 4085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> Develop a low-power-consumption strategy, and implement it. 4185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 4285afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> [Experiment, low priority] Investigate interrupt coalescing. 4385afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * Quite often, especially with PCI Message Signalled Interrupts (MSI), 4485afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * the overhead reduced by interrupt mitigation is quite often not 4585afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * worth the latency cost. 4685afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 4785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * --> [Experiment, Marvell value added] Is it possible to use target 4885afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * mode to cross-connect two Linux boxes with Marvell cards? If so, 4985afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * creating LibATA target mode support would be very interesting. 5085afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * 5185afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * Target mode, for those without docs, is the ability to directly 5285afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord * connect two SATA ports. 5385afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord */ 544a05e2091709dbb22b86a1b3343cd3fa3c0d7a6bJeff Garzik 5520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/kernel.h> 5620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/module.h> 5720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/pci.h> 5820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/init.h> 5920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/blkdev.h> 6020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/delay.h> 6120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/interrupt.h> 628d8b60046d6a2328ca4b9031b4948084f775f607Andrew Morton#include <linux/dmapool.h> 6320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/dma-mapping.h> 64a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik#include <linux/device.h> 65f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/platform_device.h> 66f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#include <linux/ata_platform.h> 6715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#include <linux/mbus.h> 6820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <scsi/scsi_host.h> 69193515d51ccb363165d6b09e9ba5c21089e34badJeff Garzik#include <scsi/scsi_cmnd.h> 706c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik#include <scsi/scsi_device.h> 7120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#include <linux/libata.h> 7220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ#define DRV_NAME "sata_mv" 741fd2e1c242acb4a589d59c77853897bdbb599186Mark Lord#define DRV_VERSION "1.20" 7520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 7620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russenum { 7720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* BAR's are enumerated in terms of pci_resource_start() terms */ 7820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 7920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IO_BAR = 2, /* offset 0x18: IO space */ 8020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 8120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 8320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 8420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_BASE = 0, 8620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ 87615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08), 88615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88), 89615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c), 90615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc), 91615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0), 92615ab95342f6245026d8974b9724f7ea57d9a184Mark Lord 9320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC0_REG_BASE = 0x20000, 948e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_FLASH_CTL_OFS = 0x1046c, 958e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_GPIO_PORT_CTL_OFS = 0x104f0, 968e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_RESET_CFG_OFS = 0x180d8, 9720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 9820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 9920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 10020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 10120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 10220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 10331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH = 32, 10431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 10531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 10631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* CRQB needs alignment on a 1KB boundary. Size == 1KB 10731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * CRPB needs alignment on a 256B boundary. Size == 256B 10831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 10931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 11031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 11131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 112da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord MV_MAX_SG_CT = 256, 11331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 11431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 115352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ 11620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_PORT_HC_SHIFT = 2, 117352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ 118352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ 119352fab701ca4753dd005b67ce5e512be944eb591Mark Lord MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ 12020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 12120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Host Flags */ 12220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 12320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ 1247bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara /* SoC integrated controllers, no PCI interface */ 125e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord MV_FLAG_SOC = (1 << 28), 1267bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 127c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 128bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI | 129bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ATA_FLAG_PIO_POLLING, 13047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE, 13120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 13231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_FLAG_READ = (1 << 0), 13331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_TAG_SHIFT = 1, 134c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 135e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 136c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 13731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_ADDR_SHIFT = 8, 13831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_CS = (0x2 << 11), 13931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRQB_CMD_LAST = (1 << 15), 14031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ CRPB_FLAG_STATUS_SHIFT = 8, 142c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 143c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 14431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EPRD_FLAG_END_OF_TBL = (1 << 31), 14631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 14720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* PCI interface registers */ 14820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 14931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ PCI_COMMAND_OFS = 0xc00, 1508e7decdb8b132ee970a2636931b7653dec6af472Mark Lord PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */ 15131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MAIN_CMD_STS_OFS = 0xd30, 15320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ STOP_PCI_MASTER = (1 << 2), 15420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_MASTER_EMPTY = (1 << 3), 15520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GLOB_SFT_RST = (1 << 4), 15620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1578e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_MODE_OFS = 0xd00, 1588e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_MODE_MASK = 0x30, 1598e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 160522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 161522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_DISC_TIMER = 0xd04, 162522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_MSI_TRIGGER = 0xc38, 163522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_SERR_MASK = 0xc28, 1648e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV_PCI_XBAR_TMOUT_OFS = 0x1d04, 165522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 166522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 167522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_ATTRIBUTE = 0x1d48, 168522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik MV_PCI_ERR_COMMAND = 0x1d50, 169522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 17002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_CAUSE_OFS = 0x1d58, 17102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCI_IRQ_MASK_OFS = 0x1d5c, 17220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 17320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 17402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_CAUSE_OFS = 0x1900, 17502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord PCIE_IRQ_MASK_OFS = 0x1910, 176646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 17702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 1787368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */ 1797368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, 1807368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64, 1817368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020, 1827368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024, 183352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ERR_IRQ = (1 << 0), /* shift by port # */ 184352fab701ca4753dd005b67ce5e512be944eb591Mark Lord DONE_IRQ = (1 << 1), /* shift by port # */ 18520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 18620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 18720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PCI_ERR = (1 << 18), 18820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */ 18920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */ 190fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_0_3_COAL_DONE = (1 << 8), 191fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik PORTS_4_7_COAL_DONE = (1 << 17), 19220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */ 19320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ GPIO_INT = (1 << 22), 19420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SELF_INT = (1 << 23), 19520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ TWSI_INT = (1 << 24), 19620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 197fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 198e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 1998b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | 200f9f7fe014fc7197a5f36f9d9859cbb27c3bdd2abMark Lord PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 20120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT | 20220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_MAIN_RSVD), 203fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 204fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik HC_MAIN_RSVD_5), 205f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC), 20620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 20720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATAHC registers */ 20820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_CFG_OFS = 0, 20920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ HC_IRQ_CAUSE_OFS = 0x14, 211352fab701ca4753dd005b67ce5e512be944eb591Mark Lord DMA_IRQ = (1 << 0), /* shift by port # */ 212352fab701ca4753dd005b67ce5e512be944eb591Mark Lord HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ 21320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ DEV_IRQ = (1 << 8), /* shift by port # */ 21420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Shadow block registers */ 21631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_BLK_OFS = 0x100, 21731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ 21820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 21920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* SATA registers */ 22020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ 22120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ SATA_ACTIVE_OFS = 0x350, 2220c58912e192fc3a4835d772aafa40b72552b819fMark Lord SATA_FIS_IRQ_CAUSE_OFS = 0x364, 22317c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 224e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord LTMODE_OFS = 0x30c, 22517c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 22617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 22747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik PHY_MODE3 = 0x310, 228bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE4 = 0x314, 229bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik PHY_MODE2 = 0x330, 230e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFCTL_OFS = 0x344, 2318e7decdb8b132ee970a2636931b7653dec6af472Mark Lord SATA_TESTCTL_OFS = 0x348, 232e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord SATA_IFSTAT_OFS = 0x34c, 233e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord VENDOR_UNIQUE_FIS_OFS = 0x35c, 23417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 2358e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_OFS = 0x360, 2368e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */ 2378e7decdb8b132ee970a2636931b7653dec6af472Mark Lord FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 23817c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord 239c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik MV5_PHY_MODE = 0x74, 2408e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV5_LTMODE_OFS = 0x30, 2418e7decdb8b132ee970a2636931b7653dec6af472Mark Lord MV5_PHY_CTL_OFS = 0x0C, 2428e7decdb8b132ee970a2636931b7653dec6af472Mark Lord SATA_INTERFACE_CFG_OFS = 0x050, 243bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 244bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik MV_M2_PREAMP_MASK = 0x7e0, 24520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 24620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* Port registers */ 24720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_CFG_OFS = 0, 2480c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 2490c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 2500c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 2510c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 2520c58912e192fc3a4835d772aafa40b72552b819fMark Lord EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 253e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 254e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 25520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_CAUSE_OFS = 0x8, 25720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ EDMA_ERR_IRQ_MASK_OFS = 0xc, 2586c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 2596c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 2606c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV = (1 << 2), /* device error */ 2616c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 2626c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 2636c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 264c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 265c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 2666c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 267c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 2686c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 2696c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 2706c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 2716c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 272646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2736c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 274646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 275646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 276646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 277646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 278646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2796c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 280646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2816c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 282646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 283646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 284646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 285646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 286646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 287646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2886c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 289646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 2906c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 291c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_OVERRUN_5 = (1 << 5), 292c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik EDMA_ERR_UNDERRUN_5 = (1 << 6), 293646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 294646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 295646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_1 | 296646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord EDMA_ERR_LNK_CTRL_RX_3 | 29785afb934575abdff1b2ac8ea4d522d1355f22a89Mark Lord EDMA_ERR_LNK_CTRL_TX, 298646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord 299bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 300bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 301bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 302bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 303bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SERR | 304bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS | 3056c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 306bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 307bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 308bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY | 309bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_CTRL_RX_2 | 310bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_RX | 311bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_LNK_DATA_TX | 312bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_TRANS_PROTO, 313e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 314bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 315bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_PRD_PAR | 316bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_DCON | 317bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_DEV_CON | 318bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_OVERRUN_5 | 319bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_UNDERRUN_5 | 320bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_SELF_DIS_5 | 3216c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | 322bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_CRPB_PAR | 323bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR | 324bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_IORDY, 32520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 32631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_BASE_HI_OFS = 0x10, 32731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ 32831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 32931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_OUT_PTR_OFS = 0x18, 33031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_REQ_Q_PTR_SHIFT = 5, 33131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 33231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_BASE_HI_OFS = 0x1c, 33331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_IN_PTR_OFS = 0x20, 33431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ 33531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ EDMA_RSP_Q_PTR_SHIFT = 3, 33631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3370ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_CMD_OFS = 0x28, /* EDMA command register */ 3380ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_EN = (1 << 0), /* enable EDMA */ 3390ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 3408e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */ 3418e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 3428e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_OFS = 0x30, /* EDMA engine status */ 3438e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */ 3448e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */ 34520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3468e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_IORDY_TMOUT_OFS = 0x34, 3478e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_ARB_CFG_OFS = 0x38, 3488e7decdb8b132ee970a2636931b7653dec6af472Mark Lord 3498e7decdb8b132ee970a2636931b7653dec6af472Mark Lord EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */ 350bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 351352fab701ca4753dd005b67ce5e512be944eb591Mark Lord GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */ 352352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 35331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Host private flags (hp_flags) */ 35431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ MV_HP_FLAG_MSI = (1 << 0), 35547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB0 = (1 << 1), 35647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_50XXB2 = (1 << 2), 35747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1B2 = (1 << 3), 35847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik MV_HP_ERRATA_60X1C0 = (1 << 4), 359e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik MV_HP_ERRATA_XX42A0 = (1 << 5), 3600ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 3610ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 3620ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 36302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 364616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ 36520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 36631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Port private flags (pp_flags) */ 3670ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 368721091685f853ba4e6c49f26f989db0b1a811250Mark Lord MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 36920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 37020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 371ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 372ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 373e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 3748e7decdb8b132ee970a2636931b7653dec6af472Mark Lord#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) 3757bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC)) 376bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 37715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 37815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek#define WINDOW_BASE(i) (0x20034 + ((i) << 4)) 37915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 380095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzikenum { 381baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik /* DMA boundary 0xffff is required by the s/g splitting 382baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik * we need on /length/ in mv_fill-sg(). 383baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik */ 384baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik MV_DMA_BOUNDARY = 0xffffU, 385095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3860ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* mask of register bits containing lower 32 bits 3870ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik * of EDMA request queue DMA address 3880ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik */ 389095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 390095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 3910ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik /* ditto, for response queue */ 392095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 393095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik}; 394095fec887eaa1c38d17c0c929a6733c744a9fa1fJeff Garzik 395522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikenum chip_type { 396522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_504x, 397522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_508x, 398522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_5080, 399522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_604x, 400522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik chip_608x, 401e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_6042, 402e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik chip_7042, 403f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara chip_soc, 404522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik}; 405522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 40631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ReQuest Block: 32B */ 40731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crqb { 408e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr; 409e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 sg_addr_hi; 410e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ctrl_flags; 411e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 ata_cmd[11]; 41231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 41320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 414e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstruct mv_crqb_iie { 415e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 416e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 417e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags; 418e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 len; 419e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 ata_cmd[4]; 420e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 421e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 42231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* Command ResPonse Block: 8B */ 42331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_crpb { 424e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 id; 425e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 flags; 426e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 tmstmp; 42720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 42820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 42931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 43031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_sg { 431e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr; 432e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 flags_size; 433e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 addr_hi; 434e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le32 reserved; 43531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 43620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 43731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstruct mv_port_priv { 43831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crqb *crqb; 43931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crqb_dma; 44031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_crpb *crpb; 44131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ dma_addr_t crpb_dma; 442eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 443eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 444bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 445bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int req_idx; 446bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int resp_idx; 447bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 44831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 pp_flags; 44931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ}; 45031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 451bca1c4eb9411533d613123618c0d127fae532595Jeff Garzikstruct mv_port_signal { 452bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 amps; 453bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 pre; 454bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik}; 455bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 45602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lordstruct mv_host_priv { 45702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 hp_flags; 45802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_port_signal signal[8]; 45902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord const struct mv_hw_ops *ops; 460f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports; 461f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *base; 4627368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_cause_addr; 4637368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord void __iomem *main_irq_mask_addr; 46402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_cause_ofs; 46502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 irq_mask_ofs; 46602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord u32 unmask_all_irqs; 467da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord /* 468da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * These consistent DMA memory pools give us guaranteed 469da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * alignment for hardware-accessed data structures, 470da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord * and less memory waste in accomplishing the alignment. 471da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord */ 472da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crqb_pool; 473da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *crpb_pool; 474da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct dma_pool *sg_tbl_pool; 47502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord}; 47602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 47747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstruct mv_hw_ops { 4782a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 4792a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 48047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 48147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 48247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 483c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 484c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 485522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 4867bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 48747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 48847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 489da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 490da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 491da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val); 492da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); 49331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap); 49431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap); 49531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc); 496e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc); 4979a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 498a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 499a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo unsigned long deadline); 500bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap); 501bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap); 502f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *dev); 50320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 5042a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5052a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 50647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 50747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 50847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 509c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 510c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 511522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 5127bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 51347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 5142a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 5152a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port); 51647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 51747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 51847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik void __iomem *mmio); 519c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 520c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc); 521522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 522f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 523f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 524f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 525f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 526f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 527f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc); 528f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 529f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio); 530f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 5317bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 532e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 533c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no); 534e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap); 535b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio); 536e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq); 53747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 538e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp); 539e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 540e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 541e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 542e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline); 54347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 544eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 545eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * because we have to allow room for worst case splitting of 546eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * PRDs for 64K boundaries in mv_fill_sg(). 547eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 548c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv5_sht = { 54968d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BASE_SHT(DRV_NAME), 550baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 551c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .dma_boundary = MV_DMA_BOUNDARY, 552c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik}; 553c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 554c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic struct scsi_host_template mv6_sht = { 55568d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_NCQ_SHT(DRV_NAME), 556138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .can_queue = MV_MAX_Q_DEPTH - 1, 557baf14aa14efcfdb5a74d5cf804691086c6bec743Jeff Garzik .sg_tablesize = MV_MAX_SG_CT / 2, 55820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .dma_boundary = MV_DMA_BOUNDARY, 55920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 56020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 561029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv5_ops = { 562029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &ata_sff_port_ops, 563c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 564c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_prep = mv_qc_prep, 565c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .qc_issue = mv_qc_issue, 566c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 567bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .freeze = mv_eh_freeze, 568bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik .thaw = mv_eh_thaw, 569a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .hardreset = mv_hardreset, 570a1efdaba2dbd6fb89e23a87b66d3f4dd92c9f5afTejun Heo .error_handler = ata_std_error_handler, /* avoid SFF EH */ 571029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .post_internal_cmd = ATA_OP_NULL, 572bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 573c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_read = mv5_scr_read, 574c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .scr_write = mv5_scr_write, 575c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 576c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_start = mv_port_start, 577c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_stop = mv_port_stop, 578c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik}; 579c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 580029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv6_ops = { 581029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv5_ops, 582e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .qc_defer = sata_pmp_qc_defer_cmd_switch, 583f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord .dev_config = mv6_dev_config, 58420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_read = mv_scr_read, 58520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ .scr_write = mv_scr_write, 58620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 587e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_hardreset = mv_pmp_hardreset, 588e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .pmp_softreset = mv_softreset, 589e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .softreset = mv_softreset, 590e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .error_handler = sata_pmp_error_handler, 59120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 59220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 593029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic struct ata_port_operations mv_iie_ops = { 594029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &mv6_ops, 595e49856d82a887ce365637176f9f99ab68076eae8Mark Lord .qc_defer = ata_std_qc_defer, /* FIS-based switching */ 596029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .dev_config = ATA_OP_NULL, 597e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .qc_prep = mv_qc_prep_iie, 598e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik}; 599e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 60098ac62defe529d04a192688f40d801a2d8fbcf98Arjan van de Venstatic const struct ata_port_info mv_port_info[] = { 60120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_504x */ 602cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik .flags = MV_COMMON_FLAGS, 60331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 604bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 605c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 60620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 60720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_508x */ 608c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 60931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 610bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 611c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 61220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 61347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik { /* chip_5080 */ 614c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 61547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 616bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 617c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv5_ops, 61847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik }, 61920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_604x */ 620138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 621e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 622138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 62331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 624bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 625c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 62620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 62720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ { /* chip_608x */ 628c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 629e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 630138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ | MV_FLAG_DUAL_HC, 63131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ .pio_mask = 0x1f, /* pio0-4 */ 632bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 633c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik .port_ops = &mv6_ops, 63420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ }, 635e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_6042 */ 636138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 637e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 638138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 639e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 640bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 641e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 642e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 643e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik { /* chip_7042 */ 644138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 645e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 646138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord ATA_FLAG_NCQ, 647e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .pio_mask = 0x1f, /* pio0-4 */ 648bf6263a853c9c143bf03f0a6fdcc68ab714fb5f5Jeff Garzik .udma_mask = ATA_UDMA6, 649e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik .port_ops = &mv_iie_ops, 650e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik }, 651f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { /* chip_soc */ 65202c1f32f1c524d2a389989f2482121f7c7d9b164Mark Lord .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 653e49856d82a887ce365637176f9f99ab68076eae8Mark Lord ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 65402c1f32f1c524d2a389989f2482121f7c7d9b164Mark Lord ATA_FLAG_NCQ | MV_FLAG_SOC, 65517c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .pio_mask = 0x1f, /* pio0-4 */ 65617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .udma_mask = ATA_UDMA6, 65717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord .port_ops = &mv_iie_ops, 658f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 65920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 66020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 6613b7d697dfb7d03edb87e50b743a7ecff029618e9Jeff Garzikstatic const struct pci_device_id mv_pci_tbl[] = { 6622d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 6632d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 6642d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 6652d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 666cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox /* RocketRAID 1740/174x have different identifiers */ 667cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox { PCI_VDEVICE(TTI, 0x1740), chip_508x }, 668cfbf723eb7928879292ee71fa0d118fc4e37b8c9Alan Cox { PCI_VDEVICE(TTI, 0x1742), chip_508x }, 6692d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 6702d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 6712d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 6722d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 6732d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 6742d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 6752d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 6762d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 6772d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 678d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger /* Adaptec 1430SA */ 679d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 680d9f9c6bc91c14f53ffa782ffcd42259ecae1d38cFlorian Attenberger 68102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Marvell 7042 support */ 6826a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 6836a3d586d8e8a50e4cfd7f8c36d82a53c5614e05bMorrison, Tom 68402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord /* Highpoint RocketRAID PCIe series */ 68502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 68602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 68702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord 6882d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { } /* terminate list */ 68920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ}; 69020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 69147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv5xxx_ops = { 69247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv5_phy_errata, 69347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv5_enable_leds, 69447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv5_read_preamp, 69547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv5_reset_hc, 696522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv5_reset_flash, 697522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv5_reset_bus, 69847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 69947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 70047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic const struct mv_hw_ops mv6xxx_ops = { 70147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .phy_errata = mv6_phy_errata, 70247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .enable_leds = mv6_enable_leds, 70347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .read_preamp = mv6_read_preamp, 70447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik .reset_hc = mv6_reset_hc, 705522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_flash = mv6_reset_flash, 706522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik .reset_bus = mv_reset_pci_bus, 70747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik}; 70847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 709f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic const struct mv_hw_ops mv_soc_ops = { 710f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .phy_errata = mv6_phy_errata, 711f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .enable_leds = mv_soc_enable_leds, 712f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .read_preamp = mv_soc_read_preamp, 713f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_hc = mv_soc_reset_hc, 714f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_flash = mv_soc_reset_flash, 715f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .reset_bus = mv_soc_reset_bus, 716f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 717f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 71820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ/* 71920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ * Functions 72020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 72120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 72220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void writelfl(unsigned long data, void __iomem *addr) 72320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 72420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writel(data, addr); 72520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ (void) readl(addr); /* flush to avoid PCI posted write */ 72620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 72720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 728c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hc_from_port(unsigned int port) 729c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 730c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port >> MV_PORT_HC_SHIFT; 731c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 732c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 733c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline unsigned int mv_hardport_from_port(unsigned int port) 734c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 735c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return port & MV_PORT_MASK; 736c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 737c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 7381cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord/* 7391cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Consolidate some rather tricky bit shift calculations. 7401cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * This is hot-path stuff, so not a function. 7411cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Simple code, with two return values, so macro rather than inline. 7421cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 7431cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * port is the sole input, in range 0..7. 7447368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * shift is one output, for use with main_irq_cause / main_irq_mask registers. 7457368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * hardport is the other output, in range 0..3. 7461cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * 7471cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord * Note that port and hardport may be the same variable in some cases. 7481cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord */ 7491cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ 7501cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord{ \ 7511cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift = mv_hc_from_port(port) * HC_SHIFT; \ 7521cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord hardport = mv_hardport_from_port(port); \ 7531cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord shift += hardport * 2; \ 7541cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord} 7551cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord 756352fab701ca4753dd005b67ce5e512be944eb591Mark Lordstatic inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 757352fab701ca4753dd005b67ce5e512be944eb591Mark Lord{ 758352fab701ca4753dd005b67ce5e512be944eb591Mark Lord return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 759352fab701ca4753dd005b67ce5e512be944eb591Mark Lord} 760352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 761c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic inline void __iomem *mv_hc_base_from_port(void __iomem *base, 762c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 763c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 764c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base(base, mv_hc_from_port(port)); 765c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 766c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 76720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 76820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 769c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return mv_hc_base_from_port(base, port) + 7708b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik MV_SATAHC_ARBTR_REG_SZ + 771c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 77220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 77320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 774e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 775e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord{ 776e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 777e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 778e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 779e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord return hc_mmio + ofs; 780e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord} 781e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord 782f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic inline void __iomem *mv_host_base(struct ata_host *host) 783f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 784f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 785f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return hpriv->base; 786f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 787f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 78820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic inline void __iomem *mv_ap_base(struct ata_port *ap) 78920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 790f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return mv_port_base(mv_host_base(ap->host), ap->port_no); 79120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 79220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 793cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzikstatic inline int mv_get_hc_count(unsigned long port_flags) 79431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 795cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 79631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 79731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 798c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzikstatic void mv_set_edma_ptrs(void __iomem *port_mmio, 799c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_host_priv *hpriv, 800c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp) 801c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik{ 802bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 index; 803bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 804c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 805c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize request queue 806c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 807fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 808fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 809bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 810c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crqb_dma & 0x3ff); 811c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); 812bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 813c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 814c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 815c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) 816bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & 0xffffffff) | index, 817c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 818c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik else 819bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 820c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 821c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik /* 822c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * initialize response queue 823c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik */ 824fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 825fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; 826bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 827c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik WARN_ON(pp->crpb_dma & 0xff); 828c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); 829c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 830c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) 831bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & 0xffffffff) | index, 832c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 833c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik else 834bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 835c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 836bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 837c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 838c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik} 839c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik 84005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 84105b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_start_dma - Enable eDMA engine 84205b308e1df6d9d673daedb517969241f41278b52Brett Russ * @base: port base address 84305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pp: port private data 84405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 845beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * Verify the local cache of the eDMA state is accurate with a 846beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo * WARN_ON. 84705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 84805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 84905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 85005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 8510c58912e192fc3a4835d772aafa40b72552b819fMark Lordstatic void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio, 852721091685f853ba4e6c49f26f989db0b1a811250Mark Lord struct mv_port_priv *pp, u8 protocol) 85320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 854721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int want_ncq = (protocol == ATA_PROT_NCQ); 855721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 856721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 857721091685f853ba4e6c49f26f989db0b1a811250Mark Lord int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 858721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq != using_ncq) 859b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 860721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } 861c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 8620c58912e192fc3a4835d772aafa40b72552b819fMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 863352fab701ca4753dd005b67ce5e512be944eb591Mark Lord int hardport = mv_hardport_from_port(ap->port_no); 8640c58912e192fc3a4835d772aafa40b72552b819fMark Lord void __iomem *hc_mmio = mv_hc_base_from_port( 865352fab701ca4753dd005b67ce5e512be944eb591Mark Lord mv_host_base(ap->host), hardport); 8660c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 hc_irq_cause, ipending; 8670c58912e192fc3a4835d772aafa40b72552b819fMark Lord 868bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA event indicators, if any */ 869f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 870bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 8710c58912e192fc3a4835d772aafa40b72552b819fMark Lord /* clear EDMA interrupt indicator, if any */ 8720c58912e192fc3a4835d772aafa40b72552b819fMark Lord hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 873352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ipending = (DEV_IRQ | DMA_IRQ) << hardport; 8740c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (hc_irq_cause & ipending) { 8750c58912e192fc3a4835d772aafa40b72552b819fMark Lord writelfl(hc_irq_cause & ~ipending, 8760c58912e192fc3a4835d772aafa40b72552b819fMark Lord hc_mmio + HC_IRQ_CAUSE_OFS); 8770c58912e192fc3a4835d772aafa40b72552b819fMark Lord } 8780c58912e192fc3a4835d772aafa40b72552b819fMark Lord 879e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_edma_cfg(ap, want_ncq); 8800c58912e192fc3a4835d772aafa40b72552b819fMark Lord 8810c58912e192fc3a4835d772aafa40b72552b819fMark Lord /* clear FIS IRQ Cause */ 8820c58912e192fc3a4835d772aafa40b72552b819fMark Lord writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 8830c58912e192fc3a4835d772aafa40b72552b819fMark Lord 884f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord mv_set_edma_ptrs(port_mmio, hpriv, pp); 885bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 886f630d562829fcd8160a118f98c1e5b9cdb4e703eMark Lord writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS); 887afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 888afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 88920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 89020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 8919b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lordstatic void mv_wait_for_edma_empty_idle(struct ata_port *ap) 8929b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord{ 8939b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 8949b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE); 8959b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord const int per_loop = 5, timeout = (15 * 1000 / per_loop); 8969b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord int i; 8979b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 8989b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord /* 8999b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord * Wait for the EDMA engine to finish transactions in progress. 9009b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord */ 9019b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord for (i = 0; i < timeout; ++i) { 9029b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS); 9039b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord if ((edma_stat & empty_idle) == empty_idle) 9049b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord break; 9059b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord udelay(per_loop); 9069b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord } 9079b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */ 9089b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord} 9099b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord 91005b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 911e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord * mv_stop_edma_engine - Disable eDMA engine 912b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord * @port_mmio: io base address 91305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 91405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 91505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 91605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 917b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lordstatic int mv_stop_edma_engine(void __iomem *port_mmio) 91820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 919b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord int i; 92031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 921b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Disable eDMA. The disable bit auto clears. */ 922b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); 9238b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik 924b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord /* Wait for the chip to confirm eDMA is off. */ 925b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord for (i = 10000; i > 0; i--) { 926b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord u32 reg = readl(port_mmio + EDMA_CMD_OFS); 9274537deb5e90b717a725b3d74b58b4bb1d28443d0Jeff Garzik if (!(reg & EDMA_EN)) 928b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 929b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord udelay(10); 93031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 931b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 93220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 93320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 934e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic int mv_stop_edma(struct ata_port *ap) 9350ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik{ 936b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord void __iomem *port_mmio = mv_ap_base(ap); 937b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 9380ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 939b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 940b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 941b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 9429b2c4e0bae854fb5e88c9cacc0dacf21631c5cb0Mark Lord mv_wait_for_edma_empty_idle(ap); 943b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord if (mv_stop_edma_engine(port_mmio)) { 944b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); 945b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return -EIO; 946b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord } 947b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord return 0; 9480ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik} 9490ea9e179f436f153fc19fdaef7abbc1e0da20762Jeff Garzik 9508a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#ifdef ATA_DEBUG 95131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_mem(void __iomem *start, unsigned bytes) 95220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 95331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 95431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 95531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%p: ", start + b); 95631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 9572dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", readl(start + b)); 95831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 95931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 96031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 96131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 96231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 9638a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik#endif 9648a70f8dc08dd40b7f8ac77280eaa99a8c6bc46f4Jeff Garzik 96531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 96631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 96731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 96831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int b, w; 96931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u32 dw; 97031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (b = 0; b < bytes; ) { 97131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("%02x: ", b); 97231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (w = 0; b < bytes && w < 4; w++) { 9732dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik (void) pci_read_config_dword(pdev, b, &dw); 9742dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik printk("%08x ", dw); 97531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ b += sizeof(u32); 97631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 97731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ printk("\n"); 97831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 97931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 98031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 98131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_dump_all_regs(void __iomem *mmio_base, int port, 98231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct pci_dev *pdev) 98331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 98431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#ifdef ATA_DEBUG 9858b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik void __iomem *hc_base = mv_hc_base(mmio_base, 98631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port >> MV_PORT_HC_SHIFT); 98731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_base; 98831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ int start_port, num_ports, p, start_hc, num_hcs, hc; 98931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 99031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (0 > port) { 99131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = start_port = 0; 99231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = 8; /* shld be benign for 4 port devs */ 99331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_hcs = 2; 99431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } else { 99531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_hc = port >> MV_PORT_HC_SHIFT; 99631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ start_port = port; 99731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports = num_hcs = 1; 99831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 9998b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik DPRINTK("All registers for port(s) %u-%u:\n", start_port, 100031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ num_ports > 1 ? num_ports - 1 : start_port); 100131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 100231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (NULL != pdev) { 100331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI config space regs:\n"); 100431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 100531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 100631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("PCI regs:\n"); 100731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xc00, 0x3c); 100831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xd00, 0x34); 100931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0xf00, 0x4); 101031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(mmio_base+0x1d00, 0x6c); 101131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 1012d220c37e0a3c9a47ae00e87e044d963b3ea040bcDan Aloni hc_base = mv_hc_base(mmio_base, hc); 101331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ DPRINTK("HC regs (HC %i):\n", hc); 101431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(hc_base, 0x1c); 101531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 101631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ for (p = start_port; p < start_port + num_ports; p++) { 101731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port_base = mv_port_base(mmio_base, p); 10182dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("EDMA regs (port %i):\n", p); 101931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base, 0x54); 10202dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik DPRINTK("SATA regs (port %i):\n", p); 102131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_mem(port_base+0x300, 0x60); 102231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 102331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ#endif 102420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 102520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 102620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic unsigned int mv_scr_offset(unsigned int sc_reg_in) 102720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 102820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs; 102920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 103020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ switch (sc_reg_in) { 103120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_STATUS: 103220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_CONTROL: 103320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ERROR: 103420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); 103520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 103620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ case SCR_ACTIVE: 103720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = SATA_ACTIVE_OFS; /* active is not with the others */ 103820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 103920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ default: 104020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ ofs = 0xffffffffU; 104120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ break; 104220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 104320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return ofs; 104420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 104520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1046da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 104720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 104820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 104920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1050da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 1051da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(mv_ap_base(ap) + ofs); 1052da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1053da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1054da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 105520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 105620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1057da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 105820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 105920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int ofs = mv_scr_offset(sc_reg_in); 106020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1061da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 106220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ writelfl(val, mv_ap_base(ap) + ofs); 1063da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1064da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1065da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 106620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 106720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1068f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lordstatic void mv6_dev_config(struct ata_device *adev) 1069f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord{ 1070f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord /* 1071e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Deal with Gen-II ("mv6") hardware quirks/restrictions: 1072e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * 1073e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Gen-II does not support NCQ over a port multiplier 1074e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * (no FIS-based switching). 1075e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * 1076f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord * We don't have hob_nsect when doing NCQ commands on Gen-II. 1077f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord * See mv_qc_prep() for more info. 1078f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord */ 1079e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (adev->flags & ATA_DFLAG_NCQ) { 1080352fab701ca4753dd005b67ce5e512be944eb591Mark Lord if (sata_pmp_attached(adev->link->ap)) { 1081e49856d82a887ce365637176f9f99ab68076eae8Mark Lord adev->flags &= ~ATA_DFLAG_NCQ; 1082352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ata_dev_printk(adev, KERN_INFO, 1083352fab701ca4753dd005b67ce5e512be944eb591Mark Lord "NCQ disabled for command-based switching\n"); 1084352fab701ca4753dd005b67ce5e512be944eb591Mark Lord } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) { 1085352fab701ca4753dd005b67ce5e512be944eb591Mark Lord adev->max_sectors = GEN_II_NCQ_MAX_SECTORS; 1086352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ata_dev_printk(adev, KERN_INFO, 1087352fab701ca4753dd005b67ce5e512be944eb591Mark Lord "max_sectors limited to %u for NCQ\n", 1088352fab701ca4753dd005b67ce5e512be944eb591Mark Lord adev->max_sectors); 1089352fab701ca4753dd005b67ce5e512be944eb591Mark Lord } 1090e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 1091f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1092f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 1093e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_config_fbs(void __iomem *port_mmio, int enable_fbs) 1094e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 10958e7decdb8b132ee970a2636931b7653dec6af472Mark Lord u32 old_fiscfg, new_fiscfg, old_ltmode, new_ltmode; 1096e49856d82a887ce365637176f9f99ab68076eae8Mark Lord /* 1097e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * Various bit settings required for operation 1098e49856d82a887ce365637176f9f99ab68076eae8Mark Lord * in FIS-based switching (fbs) mode on GenIIe: 1099e49856d82a887ce365637176f9f99ab68076eae8Mark Lord */ 11008e7decdb8b132ee970a2636931b7653dec6af472Mark Lord old_fiscfg = readl(port_mmio + FISCFG_OFS); 1101e49856d82a887ce365637176f9f99ab68076eae8Mark Lord old_ltmode = readl(port_mmio + LTMODE_OFS); 1102e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (enable_fbs) { 11038e7decdb8b132ee970a2636931b7653dec6af472Mark Lord new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC; 1104e49856d82a887ce365637176f9f99ab68076eae8Mark Lord new_ltmode = old_ltmode | LTMODE_BIT8; 1105e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } else { /* disable fbs */ 11068e7decdb8b132ee970a2636931b7653dec6af472Mark Lord new_fiscfg = old_fiscfg & ~FISCFG_SINGLE_SYNC; 1107e49856d82a887ce365637176f9f99ab68076eae8Mark Lord new_ltmode = old_ltmode & ~LTMODE_BIT8; 1108e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 11098e7decdb8b132ee970a2636931b7653dec6af472Mark Lord if (new_fiscfg != old_fiscfg) 11108e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(new_fiscfg, port_mmio + FISCFG_OFS); 1111e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (new_ltmode != old_ltmode) 1112e49856d82a887ce365637176f9f99ab68076eae8Mark Lord writelfl(new_ltmode, port_mmio + LTMODE_OFS); 1113f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord} 1114f273827e2aadcf2f74a7bdc9ad715a1b20ea7ddaMark Lord 1115e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_edma_cfg(struct ata_port *ap, int want_ncq) 1116e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 11170c58912e192fc3a4835d772aafa40b72552b819fMark Lord u32 cfg; 1118e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_port_priv *pp = ap->private_data; 1119e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1120e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 1121e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1122e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* set up non-NCQ EDMA configuration */ 11230c58912e192fc3a4835d772aafa40b72552b819fMark Lord cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 1124e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 11250c58912e192fc3a4835d772aafa40b72552b819fMark Lord if (IS_GEN_I(hpriv)) 1126e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= (1 << 8); /* enab config burst size mask */ 1127e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 11280c58912e192fc3a4835d772aafa40b72552b819fMark Lord else if (IS_GEN_II(hpriv)) 1129e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1130e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1131e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik else if (IS_GEN_IIE(hpriv)) { 1132e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 1133e728eabea110da90e69c05855e3a11174edb77efJeff Garzik cfg |= (1 << 22); /* enab 4-entry host queue cache */ 1134616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (HAS_PCI(ap->host)) 1135616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord cfg |= (1 << 18); /* enab early completion */ 1136616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (hpriv->hp_flags & MV_HP_CUT_THROUGH) 1137616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ 1138e49856d82a887ce365637176f9f99ab68076eae8Mark Lord 1139e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (want_ncq && sata_pmp_attached(ap)) { 1140e49856d82a887ce365637176f9f99ab68076eae8Mark Lord cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ 1141e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_config_fbs(port_mmio, 1); 1142e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } else { 1143e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_config_fbs(port_mmio, 0); 1144e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 1145e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 1146e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1147721091685f853ba4e6c49f26f989db0b1a811250Mark Lord if (want_ncq) { 1148721091685f853ba4e6c49f26f989db0b1a811250Mark Lord cfg |= EDMA_CFG_NCQ; 1149721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 1150721091685f853ba4e6c49f26f989db0b1a811250Mark Lord } else 1151721091685f853ba4e6c49f26f989db0b1a811250Mark Lord pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN; 1152721091685f853ba4e6c49f26f989db0b1a811250Mark Lord 1153e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik writelfl(cfg, port_mmio + EDMA_CFG_OFS); 1154e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1155e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1156da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordstatic void mv_port_free_dma_mem(struct ata_port *ap) 1157da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord{ 1158da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_host_priv *hpriv = ap->host->private_data; 1159da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord struct mv_port_priv *pp = ap->private_data; 1160eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord int tag; 1161da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1162da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crqb) { 1163da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1164da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = NULL; 1165da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1166da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (pp->crpb) { 1167da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1168da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = NULL; 1169da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1170eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1171eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1172eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we have one unique sg_tbl per NCQ tag. 1173eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1174eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1175eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (pp->sg_tbl[tag]) { 1176eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) 1177eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord dma_pool_free(hpriv->sg_tbl_pool, 1178eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag], 1179eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag]); 1180eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = NULL; 1181eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1182da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord } 1183da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord} 1184da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 118505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 118605b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_start - Port specific init/start routine. 118705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 118805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 118905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Allocate and point to DMA memory, init port private memory, 119005b308e1df6d9d673daedb517969241f41278b52Brett Russ * zero indices. 119105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 119205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 119305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 119405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 119531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic int mv_port_start(struct ata_port *ap) 119631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1197cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct device *dev = ap->host->dev; 1198cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 119931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp; 1200dde2020754aeb14e17052d61784dcb37f252aac2James Bottomley int tag; 120131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 120224dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 12036037d6bbdff65eb5a84fe35e140f4da4f7cc103aJeff Garzik if (!pp) 120424dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return -ENOMEM; 1205da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord ap->private_data = pp; 120631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1207da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1208da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crqb) 1209da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 1210da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crqb, 0, MV_CRQB_Q_SZ); 121131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1212da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1213da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (!pp->crpb) 1214da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord goto out_port_free_dma_mem; 1215da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord memset(pp->crpb, 0, MV_CRPB_Q_SZ); 121631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1217eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord /* 1218eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1219eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord * For later hardware, we need one unique sg_tbl per NCQ tag. 1220eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord */ 1221eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1222eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (tag == 0 || !IS_GEN_I(hpriv)) { 1223eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1224eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1225eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord if (!pp->sg_tbl[tag]) 1226eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord goto out_port_free_dma_mem; 1227eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } else { 1228eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl[tag] = pp->sg_tbl[0]; 1229eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1230eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 1231eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord } 123231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 1233da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 1234da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lordout_port_free_dma_mem: 1235da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 1236da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return -ENOMEM; 123731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 123831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 123905b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 124005b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_stop - Port specific cleanup/stop routine. 124105b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 124205b308e1df6d9d673daedb517969241f41278b52Brett Russ * 124305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Stop DMA, cleanup port memory. 124405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 124505b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 1246cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine uses the host lock to protect the DMA stop. 124705b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 124831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_stop(struct ata_port *ap) 124931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1250e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_stop_edma(ap); 1251da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord mv_port_free_dma_mem(ap); 125231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 125331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 125405b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 125505b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 125605b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command whose SG list to source from 125705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 125805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Populate the SG list and mark the last entry. 125905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 126005b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 126105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 126205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 12636c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzikstatic void mv_fill_sg(struct ata_queued_cmd *qc) 126431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 126531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = qc->ap->private_data; 1266972c26bdd6b58e7534473c4f7928584578cf43f4Jeff Garzik struct scatterlist *sg; 12673be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik struct mv_sg *mv_sg, *last_sg = NULL; 1268ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo unsigned int si; 126931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1270eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord mv_sg = pp->sg_tbl[qc->tag]; 1271ff2aeb1eb64c8a4770a6304f9addbae9f9828646Tejun Heo for_each_sg(qc->sg, sg, qc->n_elem, si) { 1272d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik dma_addr_t addr = sg_dma_address(sg); 1273d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik u32 sg_len = sg_dma_len(sg); 127422374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 12754007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson while (sg_len) { 12764007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 offset = addr & 0xffff; 12774007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson u32 len = sg_len; 127822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 12794007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson if ((offset + sg_len > 0x10000)) 12804007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson len = 0x10000 - offset; 12814007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 12824007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 12834007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 12846c08772e49622e90d39903e7ff0be1a0f463ac86Jeff Garzik mv_sg->flags_size = cpu_to_le32(len & 0xffff); 12854007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 12864007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson sg_len -= len; 12874007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson addr += len; 12884007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson 12893be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg = mv_sg; 12904007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson mv_sg++; 12914007b493ee6e4a52c2b618ab8361847fba5bf116Olof Johansson } 129231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 12933be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik 12943be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik if (likely(last_sg)) 12953be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7Jeff Garzik last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 129631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 129731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 12985796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzikstatic void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 129931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1300559eedad7f7764dacca33980127b4615011230e4Mark Lord u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 130131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ (last ? CRQB_CMD_LAST : 0); 1302559eedad7f7764dacca33980127b4615011230e4Mark Lord *cmdw = cpu_to_le16(tmp); 130331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 130431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 130505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 130605b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_prep - Host specific command preparation. 130705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to prepare 130805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 130905b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 131005b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it handles prep of the CRQB 131105b308e1df6d9d673daedb517969241f41278b52Brett Russ * (command request block), does some sanity checking, and calls 131205b308e1df6d9d673daedb517969241f41278b52Brett Russ * the SG load routine. 131305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 131405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 131505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 131605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 131731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_qc_prep(struct ata_queued_cmd *qc) 131831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 131931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_port *ap = qc->ap; 132031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct mv_port_priv *pp = ap->private_data; 1321e14698745dd0de1ddbf5cd0cca4313a90f8c1cc1Mark Lord __le16 *cw; 132231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ struct ata_taskfile *tf; 132331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ u16 flags = 0; 1324a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 132531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1326138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1327138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 132831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 132920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 133031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Fill in command request block 133131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1332e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 133331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= CRQB_FLAG_READ; 1334beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 133531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ flags |= qc->tag << CRQB_TAG_SHIFT; 1336e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 133731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1338bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1339fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 1340a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1341a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr = 1342eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1343a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].sg_addr_hi = 1344eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1345a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 134631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1347a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord cw = &pp->crqb[in_index].ata_cmd[0]; 134831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ tf = &qc->tf; 134931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 135031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Sadly, the CRQB cannot accomodate all registers--there are 135131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * only 11 bytes...so we must pick and choose required 135231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * registers based on the command. So, we drop feature and 135331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * hob_feature for [RW] DMA commands, but they are needed for 135431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * NCQ. NCQ will drop hob_nsect. 135520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 135631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ switch (tf->command) { 135731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ: 135831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_READ_EXT: 135931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE: 136031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_WRITE_EXT: 1361c15d85c8f3f73b5f20aae7928e25b6996f16b328Jens Axboe case ATA_CMD_WRITE_FUA_EXT: 136231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 136331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 136431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_READ: 136531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ case ATA_CMD_FPDMA_WRITE: 13668b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 136731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 136831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 136931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ default: 137031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* The only other commands EDMA supports in non-queued and 137131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 137231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * of which are defined/used by Linux. If we get here, this 137331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * driver needs work. 137431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * 137531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * FIXME: modify libata to give qc_prep a return value and 137631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * return error here. 137731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 137831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ BUG_ON(tf->command); 137931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ break; 138031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 138131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 138231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 138331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 138431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 138531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 138631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 138731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 138831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 138931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 139031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1391e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 1392e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1393e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik mv_fill_sg(qc); 1394e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik} 1395e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1396e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik/** 1397e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * mv_qc_prep_iie - Host specific command preparation. 1398e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * @qc: queued command to prepare 1399e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1400e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * This routine simply redirects to the general purpose routine 1401e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * if command is not DMA. Else, it handles prep of the CRQB 1402e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * (command request block), does some sanity checking, and calls 1403e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * the SG load routine. 1404e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * 1405e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * LOCKING: 1406e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik * Inherited from caller. 1407e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik */ 1408e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzikstatic void mv_qc_prep_iie(struct ata_queued_cmd *qc) 1409e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik{ 1410e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_port *ap = qc->ap; 1411e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_port_priv *pp = ap->private_data; 1412e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct mv_crqb_iie *crqb; 1413e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik struct ata_taskfile *tf; 1414a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord unsigned in_index; 1415e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik u32 flags = 0; 1416e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1417138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1418138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) 1419e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik return; 1420e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1421e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* Fill in Gen IIE command request block */ 1422e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 1423e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= CRQB_FLAG_READ; 1424e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1425beec7dbc6ff003bbc94de62b3323519c878fb2acTejun Heo WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 1426e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik flags |= qc->tag << CRQB_TAG_SHIFT; 14278c0aeb4a483334613336ef895f34cecc0ecbbfa6Mark Lord flags |= qc->tag << CRQB_HOSTQ_SHIFT; 1428e49856d82a887ce365637176f9f99ab68076eae8Mark Lord flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 1429e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1430bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* get current queue index from software */ 1431fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx; 1432a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord 1433a6432436c5e14b416f27c8f87c5bf0bc36771f49Mark Lord crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 1434eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1435eb73d558d1c1c931de0b3a86af962c77d74ef688Mark Lord crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1436e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->flags = cpu_to_le32(flags); 1437e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1438e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik tf = &qc->tf; 1439e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[0] = cpu_to_le32( 1440e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->command << 16) | 1441e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->feature << 24) 1442e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1443e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[1] = cpu_to_le32( 1444e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbal << 0) | 1445e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbam << 8) | 1446e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->lbah << 16) | 1447e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->device << 24) 1448e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1449e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[2] = cpu_to_le32( 1450e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbal << 0) | 1451e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbam << 8) | 1452e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_lbah << 16) | 1453e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_feature << 24) 1454e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1455e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik crqb->ata_cmd[3] = cpu_to_le32( 1456e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->nsect << 0) | 1457e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik (tf->hob_nsect << 8) 1458e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik ); 1459e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 1460e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 146131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return; 146231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_fill_sg(qc); 146331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 146431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 146505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 146605b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_qc_issue - Initiate a command to the host 146705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @qc: queued command to start 146805b308e1df6d9d673daedb517969241f41278b52Brett Russ * 146905b308e1df6d9d673daedb517969241f41278b52Brett Russ * This routine simply redirects to the general purpose routine 147005b308e1df6d9d673daedb517969241f41278b52Brett Russ * if command is not DMA. Else, it sanity checks our local 147105b308e1df6d9d673daedb517969241f41278b52Brett Russ * caches of the request producer/consumer indices then enables 147205b308e1df6d9d673daedb517969241f41278b52Brett Russ * DMA and bumps the request producer index. 147305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 147405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 147505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 147605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 14779a3d9eb0177eb10500d49cd283b35576082a522dTejun Heostatic unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 147831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 1479c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct ata_port *ap = qc->ap; 1480c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 1481c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1482bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 in_index; 148331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1484138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord if ((qc->tf.protocol != ATA_PROT_DMA) && 1485138bfdd03f2c08cc62b6af3900fb7be1c696315bMark Lord (qc->tf.protocol != ATA_PROT_NCQ)) { 148617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord /* 148717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord * We're about to send a non-EDMA capable command to the 148831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * port. Turn off EDMA so there won't be problems accessing 148931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * shadow block, etc registers. 149031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 1491b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord mv_stop_edma(ap); 1492e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(ap, qc->dev->link->pmp); 14939363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo return ata_sff_qc_issue(qc); 149431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ } 149531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 1496721091685f853ba4e6c49f26f989db0b1a811250Mark Lord mv_start_dma(ap, port_mmio, pp, qc->tf.protocol); 1497bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1498fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; 1499fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 150031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 150131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* and write the request in pointer to kick the EDMA to life */ 1502bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 1503bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 150431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 150531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ return 0; 150631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 150731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 15088f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lordstatic struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) 15098f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 15108f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct mv_port_priv *pp = ap->private_data; 15118f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc; 15128f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 15138f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 15148f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord return NULL; 15158f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord qc = ata_qc_from_tag(ap, ap->link.active_tag); 15168f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 15178f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord qc = NULL; 15188f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord return qc; 15198f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 15208f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 15218f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lordstatic void mv_unexpected_intr(struct ata_port *ap) 15228f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord{ 15238f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct mv_port_priv *pp = ap->private_data; 15248f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_eh_info *ehi = &ap->link.eh_info; 15258f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord char *when = ""; 15268f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 15278f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord /* 15288f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord * We got a device interrupt from something that 15298f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord * was supposed to be using EDMA or polling. 15308f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord */ 15318f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_ehi_clear_desc(ehi); 15328f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 15338f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord when = " while EDMA enabled"; 15348f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } else { 15358f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 15368f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 15378f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord when = " while polling"; 15388f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } 15398f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_ehi_push_desc(ehi, "unexpected device interrupt%s", when); 15408f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->err_mask |= AC_ERR_OTHER; 15418f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ehi->action |= ATA_EH_RESET; 15428f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_port_freeze(ap); 15438f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord} 15448f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord 154505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 154605b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_err_intr - Handle error interrupts on the port 154705b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ap: ATA channel to manipulate 15488d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * @qc: affected command (non-NCQ), or NULL 154905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 15508d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Most cases require a full reset of the chip's state machine, 15518d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * which also performs a COMRESET. 15528d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Also, if the port disabled DMA, update our cached copy to match. 155305b308e1df6d9d673daedb517969241f41278b52Brett Russ * 155405b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 155505b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 155605b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 1557bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc) 155831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 155931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *port_mmio = mv_ap_base(ap); 1560bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 edma_err_cause, eh_freeze_mask, serr = 0; 1561bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_port_priv *pp = ap->private_data; 1562bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 1563bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int action = 0, err_mask = 0; 15649af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo struct ata_eh_info *ehi = &ap->link.eh_info; 156520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1566bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 156720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 15688d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord /* 15698d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Read and clear the err_cause bits. This won't actually 15708d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * clear for some errors (eg. SError), but we will be doing 15718d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * a hard reset in those cases regardless, which *will* clear it. 15728d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord */ 1573bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 15748d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 1575bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1576352fab701ca4753dd005b67ce5e512be944eb591Mark Lord ata_ehi_push_desc(ehi, "edma_err_cause=%08x", edma_err_cause); 1577bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1578bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* 1579352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * All generations share these EDMA error cause bits: 1580bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik */ 1581bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_DEV) 1582bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_DEV; 1583bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 15846c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 1585bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik EDMA_ERR_INTRL_PAR)) { 1586bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask |= AC_ERR_ATA_BUS; 1587cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1588b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "parity error"); 1589bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1590bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 1591bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_hotplugged(ehi); 1592bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 1593b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo "dev disconnect" : "dev connect"); 1594cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1595bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1596bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1597352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 1598352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Gen-I has a different SELF_DIS bit, 1599352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * different FREEZE bits, and no SERR bit: 1600352fab701ca4753dd005b67ce5e512be944eb591Mark Lord */ 1601ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) { 1602bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE_5; 1603bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 1604bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1605b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 1606bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1607bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } else { 1608bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik eh_freeze_mask = EDMA_EH_FREEZE; 1609bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SELF_DIS) { 1610bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1611b64bbc39f2122a2276578e40144af69ef01decd4Tejun Heo ata_ehi_push_desc(ehi, "EDMA self-disable"); 1612bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1613bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & EDMA_ERR_SERR) { 16148d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord /* 16158d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Ensure that we read our own SCR, not a pmp link SCR: 16168d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord */ 16178d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord ap->ops->scr_read(ap, SCR_ERROR, &serr); 16188d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord /* 16198d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord * Don't clear SError here; leave it for libata-eh: 16208d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord */ 16218d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord ata_ehi_push_desc(ehi, "SError=%08x", serr); 16228d07379d251ab24d937e6cb0748b71106dddbc74Mark Lord err_mask |= AC_ERR_ATA_BUS; 1623cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1624bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1625afb0edd922c7ed6e73678730921dfcccebec17e8Brett Russ } 162620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1627bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!err_mask) { 1628bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_OTHER; 1629cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo action |= ATA_EH_RESET; 1630bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1631bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1632bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->serror |= serr; 1633bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->action |= action; 1634bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1635bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 1636bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 1637bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1638bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 1639bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1640bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (edma_err_cause & eh_freeze_mask) 1641bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 1642bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1643bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_abort(ap); 1644bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1645bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1646fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_response(struct ata_port *ap, 1647fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response, unsigned int tag, int ncq_enabled) 1648fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord{ 1649fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag); 1650fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 1651fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (qc) { 1652fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 ata_status; 1653fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u16 edma_status = le16_to_cpu(response->flags); 1654fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 1655fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * edma_status from a response queue entry: 1656fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only). 1657fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * MSB is saved ATA status from command completion. 1658fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 1659fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (!ncq_enabled) { 1660fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; 1661fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (err_cause) { 1662fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 1663fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * Error will be seen/handled by mv_err_intr(). 1664fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord * So do nothing at all here. 1665fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord */ 1666fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord return; 1667fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 1668fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 1669fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; 1670fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord qc->err_mask |= ac_err_mask(ata_status); 1671fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_qc_complete(qc); 1672fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 1673fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n", 1674fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord __func__, tag); 1675fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } 1676fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord} 1677fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord 1678fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lordstatic void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) 1679bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 1680bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 1681bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 1682fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord u32 in_index; 1683bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik bool work_done = false; 1684fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); 1685bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1686fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Get the hardware queue position index */ 1687bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) 1688bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 1689bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1690fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Process new responses from since the last time we looked */ 1691fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord while (in_index != pp->resp_idx) { 16926c1153e00af8de755ec278d873a97c9ce2a72d10Jeff Garzik unsigned int tag; 1693fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord struct mv_crpb *response = &pp->crpb[pp->resp_idx]; 1694bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1695fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; 1696bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1697fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord if (IS_GEN_I(hpriv)) { 1698fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* 50xx: no NCQ, only one command active at a time */ 16999af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo tag = ap->link.active_tag; 1700fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord } else { 1701fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord /* Gen II/IIE: get command tag from CRPB entry */ 1702fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord tag = le16_to_cpu(response->id) & 0x1f; 1703bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1704fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord mv_process_crpb_response(ap, response, tag, ncq_enabled); 1705bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik work_done = true; 1706bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1707bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1708352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* Update the software queue position index in hardware */ 1709bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (work_done) 1710bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 1711fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), 1712bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 171320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 171420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 171505b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 171605b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_host_intr - Handle all interrupts on the given host controller 1717cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * @host: host specific structure 17187368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord * @main_irq_cause: Main interrupt cause register for the chip. 171905b308e1df6d9d673daedb517969241f41278b52Brett Russ * 172005b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 172105b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 172205b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 17237368f91926a2870a8c3f9546d86535ce71ae0757Mark Lordstatic int mv_host_intr(struct ata_host *host, u32 main_irq_cause) 172420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1725f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 1726a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord void __iomem *mmio = hpriv->base, *hc_mmio = NULL; 1727a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord u32 hc_irq_cause = 0; 1728a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0, port; 172920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1730a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord for (port = 0; port < hpriv->n_ports; port++) { 1731cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_port *ap = host->ports[port]; 17328f71efe25f8718200027b547a3e749ae3300fe60Yinghai Lu struct mv_port_priv *pp; 1733a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int shift, hardport, port_cause; 1734a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord /* 1735a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * When we move to the second hc, flag our cached 1736a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * copies of hc_mmio (and hc_irq_cause) as invalid again. 1737a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord */ 1738a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord if (port == MV_PORTS_PER_HC) 1739a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord hc_mmio = NULL; 1740a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord /* 1741a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * Do nothing if port is not interrupting or is disabled: 1742a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord */ 1743a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 17447368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ); 1745a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord if (!port_cause || !ap || (ap->flags & ATA_FLAG_DISABLED)) 1746a2c91a8819e315e9fd1aef3ff57badb6c1be3f80Jeff Garzik continue; 1747a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord /* 1748a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * Each hc within the host has its own hc_irq_cause register. 1749a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * We defer reading it until we know we need it, right now: 1750a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * 1751a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * FIXME later: we don't really need to read this register 1752a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * (some logic changes required below if we go that way), 1753a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * because it doesn't tell us anything new. But we do need 1754a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * to write to it, outside the top of this loop, 1755a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord * to reset the interrupt triggers for next time. 1756a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord */ 1757a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord if (!hc_mmio) { 1758a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord hc_mmio = mv_hc_base_from_port(mmio, port); 1759a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 1760a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 1761a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = 1; 1762a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord } 17638f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord /* 17648f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord * Process completed CRPB response(s) before other events. 17658f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord */ 1766a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord pp = ap->private_data; 17678f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (hc_irq_cause & (DMA_IRQ << hardport)) { 17688f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) 1769fcfb1f77cea81f74d865b4d33f2e452ffa1973e8Mark Lord mv_process_crpb_entries(ap, pp); 17708f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } 17718f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord /* 17728f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord * Handle chip-reported errors, or continue on to handle PIO. 17738f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord */ 17748f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (unlikely(port_cause & ERR_IRQ)) { 17758f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord mv_err_intr(ap, mv_get_active_qc(ap)); 17768f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } else if (hc_irq_cause & (DEV_IRQ << hardport)) { 17778f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 17788f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord struct ata_queued_cmd *qc = mv_get_active_qc(ap); 17798f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord if (qc) { 17808f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord ata_sff_host_intr(ap, qc); 17818f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord continue; 17828f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } 17838f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord } 17848f767f8a02e6c65d393fd0f2ca19a91c9898cc2dMark Lord mv_unexpected_intr(ap); 178520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 178620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 1787a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return handled; 178820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 178920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1790a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lordstatic int mv_pci_error(struct ata_host *host, void __iomem *mmio) 1791bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 179202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 1793bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_port *ap; 1794bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_queued_cmd *qc; 1795bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct ata_eh_info *ehi; 1796bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned int i, err_mask, printed = 0; 1797bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik u32 err_cause; 1798bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 179902a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord err_cause = readl(mmio + hpriv->irq_cause_ofs); 1800bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1801bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", 1802bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_cause); 1803bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1804bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik DPRINTK("All regs @ PCI error\n"); 1805bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 1806bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 180702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord writelfl(0, mmio + hpriv->irq_cause_ofs); 1808bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1809bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik for (i = 0; i < host->n_ports; i++) { 1810bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ap = host->ports[i]; 1811936fd7328657884d5a69a55666c74a55aa83ca27Tejun Heo if (!ata_link_offline(&ap->link)) { 18129af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo ehi = &ap->link.eh_info; 1813bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_clear_desc(ehi); 1814bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (!printed++) 1815bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_ehi_push_desc(ehi, 1816bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik "PCI err cause 0x%08x", err_cause); 1817bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik err_mask = AC_ERR_HOST_BUS; 1818cf48062658e7ab3bc55e10c65676c3c73c16f8bfTejun Heo ehi->action = ATA_EH_RESET; 18199af5c9c97dc9d599281778864c72b385f0c63341Tejun Heo qc = ata_qc_from_tag(ap, ap->link.active_tag); 1820bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik if (qc) 1821bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik qc->err_mask |= err_mask; 1822bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik else 1823bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ehi->err_mask |= err_mask; 1824bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 1825bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik ata_port_freeze(ap); 1826bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1827bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1828a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord return 1; /* handled */ 1829bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 1830bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 183105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 1832c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik * mv_interrupt - Main interrupt event handler 183305b308e1df6d9d673daedb517969241f41278b52Brett Russ * @irq: unused 183405b308e1df6d9d673daedb517969241f41278b52Brett Russ * @dev_instance: private data; in this case the host structure 183505b308e1df6d9d673daedb517969241f41278b52Brett Russ * 183605b308e1df6d9d673daedb517969241f41278b52Brett Russ * Read the read only register to determine if any host 183705b308e1df6d9d673daedb517969241f41278b52Brett Russ * controllers have pending interrupts. If so, call lower level 183805b308e1df6d9d673daedb517969241f41278b52Brett Russ * routine to handle. Also check for PCI errors which are only 183905b308e1df6d9d673daedb517969241f41278b52Brett Russ * reported here. 184005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 18418b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik * LOCKING: 1842cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik * This routine holds the host lock while processing pending 184305b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts. 184405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 18457d12e780e003f93433d49ce78cfedf4b4c52adc5David Howellsstatic irqreturn_t mv_interrupt(int irq, void *dev_instance) 184620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 1847cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik struct ata_host *host = dev_instance; 1848f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = host->private_data; 1849a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord unsigned int handled = 0; 18507368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord u32 main_irq_cause, main_irq_mask; 185120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1852646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord spin_lock(&host->lock); 18537368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_cause = readl(hpriv->main_irq_cause_addr); 18547368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_mask = readl(hpriv->main_irq_mask_addr); 1855352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* 1856352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * Deal with cases where we either have nothing pending, or have read 1857352fab701ca4753dd005b67ce5e512be944eb591Mark Lord * a bogus register value which can indicate HW removal or PCI fault. 185820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ */ 18597368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord if ((main_irq_cause & main_irq_mask) && (main_irq_cause != 0xffffffffU)) { 18607368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord if (unlikely((main_irq_cause & PCI_ERR) && HAS_PCI(host))) 1861a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord handled = mv_pci_error(host, hpriv->base); 1862a3718c1f230240361ed92d3e53342df0ff7efa8cMark Lord else 18637368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord handled = mv_host_intr(host, main_irq_cause); 1864bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik } 1865cca3974e48607c3775dc73b544a5700b2e37c21aJeff Garzik spin_unlock(&host->lock); 186620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return IRQ_RETVAL(handled); 186720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 186820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 1869c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic unsigned int mv5_scr_offset(unsigned int sc_reg_in) 1870c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1871c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs; 1872c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1873c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik switch (sc_reg_in) { 1874c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_STATUS: 1875c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_ERROR: 1876c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik case SCR_CONTROL: 1877c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = sc_reg_in * sizeof(u32); 1878c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 1879c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik default: 1880c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ofs = 0xffffffffU; 1881c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik break; 1882c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 1883c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return ofs; 1884c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1885c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1886da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val) 1887c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1888f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 1889f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 18900d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 1891c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 1892c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1893da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 1894da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo *val = readl(addr + ofs); 1895da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1896da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1897da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 1898c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1899c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1900da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heostatic int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) 1901c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1902f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 1903f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 19040d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *addr = mv5_phy_base(mmio, ap->port_no); 1905c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int ofs = mv5_scr_offset(sc_reg_in); 1906c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1907da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo if (ofs != 0xffffffffU) { 19080d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo writelfl(val, addr + ofs); 1909da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return 0; 1910da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo } else 1911da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9dTejun Heo return -EINVAL; 1912c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 1913c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 19147bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 1915522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 19167bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara struct pci_dev *pdev = to_pci_dev(host->dev); 1917522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik int early_5080; 1918522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 191944c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 1920522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1921522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik if (!early_5080) { 1922522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 1923522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= (1 << 0); 1924522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 1925522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik } 1926522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 19277bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara mv_reset_pci_bus(host, mmio); 1928522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 1929522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1930522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzikstatic void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 1931522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik{ 19328e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS); 1933522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik} 1934522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 193547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 1936ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 1937ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 1938c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 1939c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 1940c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1941c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 1942c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1943c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 1944c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 1945ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 1946ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 194747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 1948ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 1949522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik u32 tmp; 1950522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 19518e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0, mmio + MV_GPIO_PORT_CTL_OFS); 1952522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1953522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 1954522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik 1955522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 1956522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik tmp |= ~(1 << 0); 1957522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 1958ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 1959ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 19602a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzikstatic void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 19612a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 1962bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 1963c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *phy_mmio = mv5_phy_base(mmio, port); 1964c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 1965c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 1966c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 1967c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1968c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik if (fix_apm_sq) { 19698e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(phy_mmio + MV5_LTMODE_OFS); 1970c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= (1 << 19); 19718e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, phy_mmio + MV5_LTMODE_OFS); 1972c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 19738e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(phy_mmio + MV5_PHY_CTL_OFS); 1974c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~0x3; 1975c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x1; 19768e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, phy_mmio + MV5_PHY_CTL_OFS); 1977c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 1978c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1979c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(phy_mmio + MV5_PHY_MODE); 1980c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= ~mask; 1981c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].pre; 1982c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= hpriv->signal[port].amps; 1983c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, phy_mmio + MV5_PHY_MODE); 1984bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 1985bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 1986c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1987c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 1988c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, port_mmio + (reg)) 1989c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 1990c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port) 1991c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 1992c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 1993c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1994e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 1995c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 1996c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x028); /* command */ 1997c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(0x11f, port_mmio + EDMA_CFG_OFS); 1998c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x004); /* timer */ 1999c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x008); /* irq err cause */ 2000c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); /* irq err mask */ 2001c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); /* rq bah */ 2002c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); /* rq inp */ 2003c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); /* rq outp */ 2004c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x01c); /* respq bah */ 2005c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x024); /* respq outp */ 2006c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x020); /* respq inp */ 2007c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x02c); /* test control */ 20088e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS); 2009c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2010c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 2011c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2012c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#define ZERO(reg) writel(0, hc_mmio + (reg)) 2013c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2014c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc) 201547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik{ 2016c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *hc_mmio = mv_hc_base(mmio, hc); 2017c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik u32 tmp; 2018c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2019c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x00c); 2020c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x010); 2021c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x014); 2022c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik ZERO(0x018); 2023c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2024c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp = readl(hc_mmio + 0x20); 2025c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp &= 0x1c1c1c1c; 2026c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik tmp |= 0x03030303; 2027c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writel(tmp, hc_mmio + 0x20); 2028c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2029c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik#undef ZERO 2030c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2031c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2032c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 2033c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2034c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int hc, port; 2035c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2036c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (hc = 0; hc < n_hc; hc++) { 2037c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik for (port = 0; port < MV_PORTS_PER_HC; port++) 2038c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_hc_port(hpriv, mmio, 2039c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik (hc * MV_PORTS_PER_HC) + port); 2040c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2041c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mv5_reset_one_hc(hpriv, mmio, hc); 2042c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2043c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2044c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik return 0; 204547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik} 204647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 2047101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 2048101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#define ZERO(reg) writel(0, mmio + (reg)) 20497bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 2050101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 205102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord struct mv_host_priv *hpriv = host->private_data; 2052101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 2053101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 20548e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(mmio + MV_PCI_MODE_OFS); 2055101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0xff00ffff; 20568e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, mmio + MV_PCI_MODE_OFS); 2057101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2058101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_DISC_TIMER); 2059101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_MSI_TRIGGER); 20608e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS); 20617368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord ZERO(PCI_HC_MAIN_IRQ_MASK_OFS); 2062101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_SERR_MASK); 206302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_cause_ofs); 206402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord ZERO(hpriv->irq_mask_ofs); 2065101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_LOW_ADDRESS); 2066101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_HIGH_ADDRESS); 2067101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_ATTRIBUTE); 2068101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik ZERO(MV_PCI_ERR_COMMAND); 2069101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2070101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik#undef ZERO 2071101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2072101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikstatic void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 2073101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 2074101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 tmp; 2075101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2076101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik mv5_reset_flash(hpriv, mmio); 2077101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 20788e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS); 2079101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp &= 0x3; 2080101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik tmp |= (1 << 5) | (1 << 6); 20818e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS); 2082101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2083101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2084101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik/** 2085101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * mv6_reset_hc - Perform the 6xxx global soft reset 2086101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * @mmio: base address of the HBA 2087101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2088101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * This routine only applies to 6xxx parts. 2089101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * 2090101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * LOCKING: 2091101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * Inherited from caller. 2092101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2093c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2094c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int n_hc) 2095101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik{ 2096101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; 2097101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik int i, rc = 0; 2098101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik u32 t; 2099101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2100101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* Following procedure defined in PCI "main command and status 2101101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik * register" table. 2102101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik */ 2103101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2104101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | STOP_PCI_MASTER, reg); 2105101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2106101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik for (i = 0; i < 1000; i++) { 2107101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2108101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 21092dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik if (PCI_MASTER_EMPTY & t) 2110101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik break; 2111101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2112101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(PCI_MASTER_EMPTY & t)) { 2113101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 2114101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2115101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2116101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2117101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2118101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* set reset */ 2119101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2120101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2121101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t | GLOB_SFT_RST, reg); 2122101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2123101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2124101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 2125101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2126101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (!(GLOB_SFT_RST & t)) { 2127101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 2128101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2129101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik goto done; 2130101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2131101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2132101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 2133101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik i = 5; 2134101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik do { 2135101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 2136101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik t = readl(reg); 2137101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik udelay(1); 2138101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } while ((GLOB_SFT_RST & t) && (i-- > 0)); 2139101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 2140101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik if (GLOB_SFT_RST & t) { 2141101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 2142101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik rc = 1; 2143101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik } 2144101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzikdone: 2145101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik return rc; 2146101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik} 2147101ffae26c23ea928fce6d31a8b4901327d91a15Jeff Garzik 214847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 2149ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *mmio) 2150ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 2151ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik void __iomem *port_mmio; 2152ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik u32 tmp; 2153ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 21548e7decdb8b132ee970a2636931b7653dec6af472Mark Lord tmp = readl(mmio + MV_RESET_CFG_OFS); 2155ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik if ((tmp & (1 << 0)) == 0) { 215647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->signal[idx].amps = 0x7 << 8; 2157ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = 0x1 << 5; 2158ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik return; 2159ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik } 2160ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2161ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik port_mmio = mv_port_base(mmio, idx); 2162ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik tmp = readl(port_mmio + PHY_MODE2); 2163ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2164ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2165ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2166ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2167ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 216847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzikstatic void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 2169ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik{ 21708e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS); 2171ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik} 2172ba3fe8fb6a469390a14379519915f3c39a973d99Jeff Garzik 2173c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzikstatic void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 21742a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik unsigned int port) 2175bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 2176c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2177c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2178bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 217947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik int fix_phy_mode2 = 218047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 2181bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik int fix_phy_mode4 = 218247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 218347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik u32 m2, tmp; 218447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 218547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (fix_phy_mode2) { 218647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 218747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 218847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 |= (1 << 31); 218947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 219047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 219147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 219247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 219347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 219447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~((1 << 16) | (1 << 31)); 219547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 219647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 219747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik udelay(200); 219847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 219947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 220047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik /* who knows what this magic does */ 220147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp = readl(port_mmio + PHY_MODE3); 220247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp &= ~0x7F800000; 220347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik tmp |= 0x2A800000; 220447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik writel(tmp, port_mmio + PHY_MODE3); 2205bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2206bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (fix_phy_mode4) { 220747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik u32 m4; 2208bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2209bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m4 = readl(port_mmio + PHY_MODE4); 221047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 221147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (hp_flags & MV_HP_ERRATA_60X1B2) 2212e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord tmp = readl(port_mmio + PHY_MODE3); 2213bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2214e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord /* workaround for errata FEr SATA#10 (part 1) */ 2215bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m4 = (m4 & ~(1 << 1)) | (1 << 0); 2216bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2217bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m4, port_mmio + PHY_MODE4); 221847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 221947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (hp_flags & MV_HP_ERRATA_60X1B2) 2220e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord writel(tmp, port_mmio + PHY_MODE3); 2221bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2222bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2223bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik /* Revert values of pre-emphasis and signal amps to the saved ones */ 2224bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 = readl(port_mmio + PHY_MODE2); 2225bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2226bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik m2 &= ~MV_M2_PREAMP_MASK; 22272a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].amps; 22282a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik m2 |= hpriv->signal[port].pre; 222947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik m2 &= ~(1 << 16); 2230bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2231e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik /* according to mvSata 3.6.1, some IIE values are fixed */ 2232e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik if (IS_GEN_IIE(hpriv)) { 2233e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 &= ~0xC30FF01F; 2234e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik m2 |= 0x0000900F; 2235e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 2236e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2237bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik writel(m2, port_mmio + PHY_MODE2); 2238bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2239bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2240f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* TODO: use the generic LED interface to configure the SATA Presence */ 2241f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* & Acitivy LEDs on the board */ 2242f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_enable_leds(struct mv_host_priv *hpriv, 2243f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2244f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2245f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2246f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2247f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2248f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 2249f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2250f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2251f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio; 2252f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara u32 tmp; 2253f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2254f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara port_mmio = mv_port_base(mmio, idx); 2255f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara tmp = readl(port_mmio + PHY_MODE2); 2256f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2257f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2258f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2259f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2260f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2261f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2262f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, port_mmio + (reg)) 2263f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 2264f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int port) 2265f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2266f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *port_mmio = mv_port_base(mmio, port); 2267f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2268e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, port); 2269f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2270f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x028); /* command */ 2271f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writel(0x101f, port_mmio + EDMA_CFG_OFS); 2272f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x004); /* timer */ 2273f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x008); /* irq err cause */ 2274f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); /* irq err mask */ 2275f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); /* rq bah */ 2276f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); /* rq inp */ 2277f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x018); /* rq outp */ 2278f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x01c); /* respq bah */ 2279f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x024); /* respq outp */ 2280f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x020); /* respq inp */ 2281f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x02c); /* test control */ 22828e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS); 2283f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2284f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2285f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2286f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2287f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#define ZERO(reg) writel(0, hc_mmio + (reg)) 2288f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 2289f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2290f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2291f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *hc_mmio = mv_hc_base(mmio, 0); 2292f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2293f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x00c); 2294f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x010); 2295f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ZERO(0x014); 2296f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2297f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2298f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2299f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#undef ZERO 2300f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2301f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_soc_reset_hc(struct mv_host_priv *hpriv, 2302f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio, unsigned int n_hc) 2303f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2304f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int port; 2305f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2306f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara for (port = 0; port < hpriv->n_ports; port++) 2307f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_hc_port(hpriv, mmio, port); 2308f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2309f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_soc_reset_one_hc(hpriv, mmio); 2310f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2311f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 2312f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2313f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2314f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_flash(struct mv_host_priv *hpriv, 2315f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio) 2316f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2317f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2318f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2319f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2320f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 2321f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2322f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return; 2323f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2324f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 23258e7decdb8b132ee970a2636931b7653dec6af472Mark Lordstatic void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) 2326b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord{ 23278e7decdb8b132ee970a2636931b7653dec6af472Mark Lord u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS); 2328b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 23298e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */ 2330b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (want_gen2i) 23318e7decdb8b132ee970a2636931b7653dec6af472Mark Lord ifcfg |= (1 << 7); /* enable gen2i speed */ 23328e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS); 2333b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord} 2334b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord 2335e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lordstatic void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 2336c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik unsigned int port_no) 2337c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik{ 2338c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port_no); 2339c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 23408e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* 23418e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * The datasheet warns against setting EDMA_RESET when EDMA is active 23428e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * (but doesn't say what the problem might be). So we first try 23438e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * to disable the EDMA engine before doing the EDMA_RESET operation. 23448e7decdb8b132ee970a2636931b7653dec6af472Mark Lord */ 23450d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord mv_stop_edma_engine(port_mmio); 23468e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS); 2347c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2348b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord if (!IS_GEN_I(hpriv)) { 23498e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* Enable 3.0gb/s link speed: this survives EDMA_RESET */ 23508e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(port_mmio, 1); 2351c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik } 2352b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord /* 23538e7decdb8b132ee970a2636931b7653dec6af472Mark Lord * Strobing EDMA_RESET here causes a hard reset of the SATA transport, 2354b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * link, and physical layers. It resets all SATA interface registers 2355b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev. 2356c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik */ 23578e7decdb8b132ee970a2636931b7653dec6af472Mark Lord writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS); 2358b67a1064cb1c1d3b43e01e8b43a6a8dcdefed733Mark Lord udelay(25); /* allow reset propagation */ 2359c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik writelfl(0, port_mmio + EDMA_CMD_OFS); 2360c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2361c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik hpriv->ops->phy_errata(hpriv, mmio, port_no); 2362c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2363ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik if (IS_GEN_I(hpriv)) 2364c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik mdelay(1); 2365c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik} 2366c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik 2367e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic void mv_pmp_select(struct ata_port *ap, int pmp) 236820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 2369e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (sata_pmp_supported(ap)) { 2370e49856d82a887ce365637176f9f99ab68076eae8Mark Lord void __iomem *port_mmio = mv_ap_base(ap); 2371e49856d82a887ce365637176f9f99ab68076eae8Mark Lord u32 reg = readl(port_mmio + SATA_IFCTL_OFS); 2372e49856d82a887ce365637176f9f99ab68076eae8Mark Lord int old = reg & 0xf; 237322374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 2374e49856d82a887ce365637176f9f99ab68076eae8Mark Lord if (old != pmp) { 2375e49856d82a887ce365637176f9f99ab68076eae8Mark Lord reg = (reg & ~0xf) | pmp; 2376e49856d82a887ce365637176f9f99ab68076eae8Mark Lord writelfl(reg, port_mmio + SATA_IFCTL_OFS); 2377e49856d82a887ce365637176f9f99ab68076eae8Mark Lord } 237822374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik } 237920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 238020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2381e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 2382e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 238322374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik{ 2384e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 2385e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return sata_std_hardreset(link, class, deadline); 2386e49856d82a887ce365637176f9f99ab68076eae8Mark Lord} 2387bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2388e49856d82a887ce365637176f9f99ab68076eae8Mark Lordstatic int mv_softreset(struct ata_link *link, unsigned int *class, 2389e49856d82a887ce365637176f9f99ab68076eae8Mark Lord unsigned long deadline) 2390e49856d82a887ce365637176f9f99ab68076eae8Mark Lord{ 2391e49856d82a887ce365637176f9f99ab68076eae8Mark Lord mv_pmp_select(link->ap, sata_srst_pmp(link)); 2392e49856d82a887ce365637176f9f99ab68076eae8Mark Lord return ata_sff_softreset(link, class, deadline); 239322374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik} 239422374677d18c5eeefd3a283431d312b8c44fef02Jeff Garzik 2395cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic int mv_hardreset(struct ata_link *link, unsigned int *class, 2396bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik unsigned long deadline) 239731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 2398cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo struct ata_port *ap = link->ap; 2399bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik struct mv_host_priv *hpriv = ap->host->private_data; 2400b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord struct mv_port_priv *pp = ap->private_data; 2401f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 24020d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord int rc, attempts = 0, extra = 0; 24030d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord u32 sstatus; 24040d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord bool online; 240531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2406e12bef50b7660cf7c19d1cd3eac381b9eff734d7Mark Lord mv_reset_channel(hpriv, mmio, ap->port_no); 2407b562468cc3bd0c81decba1f5f39a7173f839e57eMark Lord pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2408bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 24090d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Workaround for errata FEr SATA#10 (part 2) */ 24100d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord do { 241117c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord const unsigned long *timing = 241217c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord sata_ehc_deb_timing(&link->eh_context); 2413bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 241417c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord rc = sata_link_hardreset(link, timing, deadline + extra, 241517c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord &online, NULL); 241617c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord if (rc) 24170d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord return rc; 24180d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord sata_scr_read(link, SCR_STATUS, &sstatus); 24190d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 24200d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord /* Force 1.5gb/s link speed and try again */ 24218e7decdb8b132ee970a2636931b7653dec6af472Mark Lord mv_setup_ifcfg(mv_ap_base(ap), 0); 24220d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord if (time_after(jiffies + HZ, deadline)) 24230d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord extra = HZ; /* only extend it once, max */ 24240d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } 24250d8be5cbff8fd95da72d749a64e150b851f470c6Mark Lord } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); 2426bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 242717c5aab5b34e351531466e35b154ca86db7d46a9Mark Lord return rc; 2428bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2429bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2430bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_freeze(struct ata_port *ap) 2431bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2432f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 24331cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord unsigned int shift, hardport, port = ap->port_no; 24347368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord u32 main_irq_mask; 2435bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2436bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* FIXME: handle coalescing completion events properly */ 2437bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 24381cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord mv_stop_edma(ap); 24391cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2440bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2441bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* disable assertion of portN err, done events */ 24427368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_mask = readl(hpriv->main_irq_mask_addr); 24437368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_mask &= ~((DONE_IRQ | ERR_IRQ) << shift); 24447368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord writelfl(main_irq_mask, hpriv->main_irq_mask_addr); 2445bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik} 2446bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2447bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzikstatic void mv_eh_thaw(struct ata_port *ap) 2448bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik{ 2449f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv = ap->host->private_data; 24501cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord unsigned int shift, hardport, port = ap->port_no; 24511cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); 2452bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik void __iomem *port_mmio = mv_ap_base(ap); 24537368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord u32 main_irq_mask, hc_irq_cause; 2454bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2455bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* FIXME: handle coalescing completion events properly */ 2456bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 24571cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2458bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2459bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear EDMA errors on this port */ 2460bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2461bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2462bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* clear pending irq events */ 2463bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 24641cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport); 24651cfd19aeb8c8b6291a9d11143b4d8f3dac508ed4Mark Lord writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 2466bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik 2467bdd4dddee325a7dce3e84cf48201a06aa8508aa4Jeff Garzik /* enable assertion of portN err, done events */ 24687368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_mask = readl(hpriv->main_irq_mask_addr); 24697368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord main_irq_mask |= ((DONE_IRQ | ERR_IRQ) << shift); 24707368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord writelfl(main_irq_mask, hpriv->main_irq_mask_addr); 247131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 247231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 247305b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 247405b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_port_init - Perform some early initialization on a single port. 247505b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port: libata data structure storing shadow register addresses 247605b308e1df6d9d673daedb517969241f41278b52Brett Russ * @port_mmio: base address of the port 247705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 247805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Initialize shadow register mmio addresses, clear outstanding 247905b308e1df6d9d673daedb517969241f41278b52Brett Russ * interrupts on the port, and unmask interrupts for the future 248005b308e1df6d9d673daedb517969241f41278b52Brett Russ * start of the port. 248105b308e1df6d9d673daedb517969241f41278b52Brett Russ * 248205b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 248305b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 248405b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 248531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russstatic void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 248620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 24870d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo void __iomem *shd_base = port_mmio + SHD_BLK_OFS; 248831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ unsigned serr_ofs; 248931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 24908b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik /* PIO related setup 249131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 249231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 24938b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->error_addr = 249431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 249531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 249631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 249731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 249831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 249931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 25008b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik port->status_addr = 250131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 250231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* special case: control/altstatus doesn't have ATA_REG_ address */ 250331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; 250431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 250531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* unused: */ 25068d9db2d2fbae9e05022825c32f86e00c8e342860Randy Dunlap port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; 250720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 250831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding port interrupt conditions */ 250931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ serr_ofs = mv_scr_offset(SCR_ERROR); 251031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); 251131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 251231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2513646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord /* unmask all non-transient EDMA error interrupts */ 2514646a4da514f2555298481cb00dc5b3eb02b21b72Mark Lord writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS); 251520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 25168b260248d9e0e8b64bb72fd4dee03ad86984c344Jeff Garzik VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 251731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_CFG_OFS), 251831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), 251931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); 252020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 252120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2522616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic unsigned int mv_in_pcix_mode(struct ata_host *host) 2523616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 2524616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 2525616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 2526616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 2527616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 2528616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (!HAS_PCI(host) || !IS_PCIE(hpriv)) 2529616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not PCI-X capable */ 2530616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord reg = readl(mmio + MV_PCI_MODE_OFS); 2531616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if ((reg & MV_PCI_MODE_MASK) == 0) 2532616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* conventional PCI mode */ 2533616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* chip is in PCI-X mode */ 2534616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 2535616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 2536616d4a98ad8749ebe17a8fcac67df65c321350acMark Lordstatic int mv_pci_cut_through_okay(struct ata_host *host) 2537616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord{ 2538616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord struct mv_host_priv *hpriv = host->private_data; 2539616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord void __iomem *mmio = hpriv->base; 2540616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord u32 reg; 2541616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 2542616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (!mv_in_pcix_mode(host)) { 2543616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord reg = readl(mmio + PCI_COMMAND_OFS); 2544616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (reg & PCI_COMMAND_MRDTRIG) 2545616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 0; /* not okay */ 2546616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord } 2547616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord return 1; /* okay */ 2548616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord} 2549616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord 25504447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_chip_id(struct ata_host *host, unsigned int board_idx) 2551bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik{ 25524447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 25534447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 2554bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik u32 hp_flags = hpriv->hp_flags; 2555bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 25565796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik switch (board_idx) { 255747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case chip_5080: 255847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 2559ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 256047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 256144c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 256247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x1: 256347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 256447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 256547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 256647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 256747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 256847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 256947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 257047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying 50XXB2 workarounds to unknown rev\n"); 257147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 257247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 257347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik } 257447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 257547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 2576bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_504x: 2577bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_508x: 257847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv5xxx_ops; 2579ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_I; 2580bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 258144c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 258247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x0: 258347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB0; 258447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 258547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x3: 258647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 258747c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 258847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik default: 258947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 259047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 259147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_50XXB2; 259247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 2593bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2594bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2595bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2596bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_604x: 2597bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik case chip_608x: 259847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops = &mv6xxx_ops; 2599ee9ccdf70163ca6408f6965e0fbc65baeac7312cJeff Garzik hp_flags |= MV_HP_GEN_II; 260047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 260144c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 260247c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x7: 260347c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 260447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik break; 260547c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik case 0x9: 260647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2607bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2608bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 2609bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 261047c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik "Applying B2 workarounds to unknown rev\n"); 261147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hp_flags |= MV_HP_ERRATA_60X1B2; 2612bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2613bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2614bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik break; 2615bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2616e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_7042: 2617616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH; 2618306b30f74d37f289033c696285e07ce0158a5d7bMark Lord if (pdev->vendor == PCI_VENDOR_ID_TTI && 2619306b30f74d37f289033c696285e07ce0158a5d7bMark Lord (pdev->device == 0x2300 || pdev->device == 0x2310)) 2620306b30f74d37f289033c696285e07ce0158a5d7bMark Lord { 26214e5200334e03e5620aa19d538300c13db270a063Mark Lord /* 26224e5200334e03e5620aa19d538300c13db270a063Mark Lord * Highpoint RocketRAID PCIe 23xx series cards: 26234e5200334e03e5620aa19d538300c13db270a063Mark Lord * 26244e5200334e03e5620aa19d538300c13db270a063Mark Lord * Unconfigured drives are treated as "Legacy" 26254e5200334e03e5620aa19d538300c13db270a063Mark Lord * by the BIOS, and it overwrites sector 8 with 26264e5200334e03e5620aa19d538300c13db270a063Mark Lord * a "Lgcy" metadata block prior to Linux boot. 26274e5200334e03e5620aa19d538300c13db270a063Mark Lord * 26284e5200334e03e5620aa19d538300c13db270a063Mark Lord * Configured drives (RAID or JBOD) leave sector 8 26294e5200334e03e5620aa19d538300c13db270a063Mark Lord * alone, but instead overwrite a high numbered 26304e5200334e03e5620aa19d538300c13db270a063Mark Lord * sector for the RAID metadata. This sector can 26314e5200334e03e5620aa19d538300c13db270a063Mark Lord * be determined exactly, by truncating the physical 26324e5200334e03e5620aa19d538300c13db270a063Mark Lord * drive capacity to a nice even GB value. 26334e5200334e03e5620aa19d538300c13db270a063Mark Lord * 26344e5200334e03e5620aa19d538300c13db270a063Mark Lord * RAID metadata is at: (dev->n_sectors & ~0xfffff) 26354e5200334e03e5620aa19d538300c13db270a063Mark Lord * 26364e5200334e03e5620aa19d538300c13db270a063Mark Lord * Warn the user, lest they think we're just buggy. 26374e5200334e03e5620aa19d538300c13db270a063Mark Lord */ 26384e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 26394e5200334e03e5620aa19d538300c13db270a063Mark Lord " BIOS CORRUPTS DATA on all attached drives," 26404e5200334e03e5620aa19d538300c13db270a063Mark Lord " regardless of if/how they are configured." 26414e5200334e03e5620aa19d538300c13db270a063Mark Lord " BEWARE!\n"); 26424e5200334e03e5620aa19d538300c13db270a063Mark Lord printk(KERN_WARNING DRV_NAME ": For data safety, do not" 26434e5200334e03e5620aa19d538300c13db270a063Mark Lord " use sectors 8-9 on \"Legacy\" drives," 26444e5200334e03e5620aa19d538300c13db270a063Mark Lord " and avoid the final two gigabytes on" 26454e5200334e03e5620aa19d538300c13db270a063Mark Lord " all RocketRAID BIOS initialized drives.\n"); 2646306b30f74d37f289033c696285e07ce0158a5d7bMark Lord } 26478e7decdb8b132ee970a2636931b7653dec6af472Mark Lord /* drop through */ 2648e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case chip_6042: 2649e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hpriv->ops = &mv6xxx_ops; 2650e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_GEN_IIE; 2651616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord if (board_idx == chip_6042 && mv_pci_cut_through_okay(host)) 2652616d4a98ad8749ebe17a8fcac67df65c321350acMark Lord hp_flags |= MV_HP_CUT_THROUGH; 2653e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 265444c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok switch (pdev->revision) { 2655e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case 0x0: 2656e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_XX42A0; 2657e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2658e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik case 0x1: 2659e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2660e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2661e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik default: 2662e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik dev_printk(KERN_WARNING, &pdev->dev, 2663e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik "Applying 60X1C0 workarounds to unknown rev\n"); 2664e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik hp_flags |= MV_HP_ERRATA_60X1C0; 2665e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2666e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik } 2667e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik break; 2668f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara case chip_soc: 2669f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->ops = &mv_soc_ops; 2670f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hp_flags |= MV_HP_ERRATA_60X1C0; 2671f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara break; 2672e4e7b89280d1d666e2c09e5ad36cf071796c4c7eJeff Garzik 2673bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik default: 2674f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_ERR, host->dev, 26755796d1c4c89efff823259fda35b08ea66ebf8b23Jeff Garzik "BUG: invalid board index %u\n", board_idx); 2676bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 1; 2677bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik } 2678bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2679bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik hpriv->hp_flags = hp_flags; 268002a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord if (hp_flags & MV_HP_PCIE) { 268102a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS; 268202a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS; 268302a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 268402a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } else { 268502a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS; 268602a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS; 268702a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 268802a121da5a53d415b6596bc19cc6999d295d32a4Mark Lord } 2689bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2690bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik return 0; 2691bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik} 2692bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 269305b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 269447c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik * mv_init_host - Perform some early initialization of the host. 26954447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to initialize 26964447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @board_idx: controller index 269705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 269805b308e1df6d9d673daedb517969241f41278b52Brett Russ * If possible, do an early global reset of the host. Then do 269905b308e1df6d9d673daedb517969241f41278b52Brett Russ * our port init and clear/unmask all/relevant host interrupts. 270005b308e1df6d9d673daedb517969241f41278b52Brett Russ * 270105b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 270205b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 270305b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 27044447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic int mv_init_host(struct ata_host *host, unsigned int board_idx) 270520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 270620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ int rc = 0, n_hc, port, hc; 27074447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 2708f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara void __iomem *mmio = hpriv->base; 270947c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik 27104447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_chip_id(host, board_idx); 2711bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik if (rc) 2712352fab701ca4753dd005b67ce5e512be944eb591Mark Lord goto done; 2713f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2714f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 27157368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS; 27167368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS; 2717f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } else { 27187368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS; 27197368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS; 2720f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2721352fab701ca4753dd005b67ce5e512be944eb591Mark Lord 2722352fab701ca4753dd005b67ce5e512be944eb591Mark Lord /* global interrupt mask: 0 == mask everything */ 27237368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord writel(0, hpriv->main_irq_mask_addr); 2724bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 27254447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_hc = mv_get_hc_count(host->ports[0]->flags); 2726bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 27274447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) 272847c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->read_preamp(hpriv, port, mmio); 272920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2730c9d39130123238ac18478a42e25cb7996eacfcc0Jeff Garzik rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 273147c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik if (rc) 273220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ goto done; 273320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2734522479fb98c6667f081e75f87e298e413c0b1db8Jeff Garzik hpriv->ops->reset_flash(hpriv, mmio); 27357bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara hpriv->ops->reset_bus(host, mmio); 273647c2b677daeed9c79ecb7167c211ff36876ea611Jeff Garzik hpriv->ops->enable_leds(hpriv, mmio); 273720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 27384447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo for (port = 0; port < host->n_ports; port++) { 2739cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo struct ata_port *ap = host->ports[port]; 27402a47ce06d534692f9bd2bf4e90a20fc9b1054c39Jeff Garzik void __iomem *port_mmio = mv_port_base(mmio, port); 2741cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 2742cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo mv_port_init(&ap->ioaddr, port_mmio); 2743cbcdd87593a1d85c5c4b259945a3a09eee12814dTejun Heo 27447bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 2745f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2746f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara unsigned int offset = port_mmio - mmio; 2747f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 2748f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 2749f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 27507bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 275120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 275220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 275320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ for (hc = 0; hc < n_hc; hc++) { 275431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ void __iomem *hc_mmio = mv_hc_base(mmio, hc); 275531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 275631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 275731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ "(before clear)=0x%08x\n", hc, 275831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_CFG_OFS), 275931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ readl(hc_mmio + HC_IRQ_CAUSE_OFS)); 276031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 276131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Clear any currently outstanding hc interrupt conditions */ 276231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); 276320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ } 276420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2765f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (HAS_PCI(host)) { 2766f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* Clear any currently outstanding host interrupt conditions */ 2767f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(0, mmio + hpriv->irq_cause_ofs); 276831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 2769f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* and unmask interrupt generation for host regs */ 2770f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs); 2771f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (IS_GEN_I(hpriv)) 2772f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS_5, 27737368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_mask_addr); 2774f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara else 2775f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS, 27767368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_mask_addr); 2777f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2778f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x " 2779f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "PCI int cause/mask=0x%08x/0x%08x\n", 27807368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord readl(hpriv->main_irq_cause_addr), 27817368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord readl(hpriv->main_irq_mask_addr), 2782f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(mmio + hpriv->irq_cause_ofs), 2783f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara readl(mmio + hpriv->irq_mask_ofs)); 2784f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } else { 2785f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara writelfl(~HC_MAIN_MASKED_IRQS_SOC, 27867368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord hpriv->main_irq_mask_addr); 2787f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n", 27887368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord readl(hpriv->main_irq_cause_addr), 27897368f91926a2870a8c3f9546d86535ce71ae0757Mark Lord readl(hpriv->main_irq_mask_addr)); 2790f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2791f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharadone: 2792f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 2793f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2794fb621e2fde735abab854586d52c96c5624bcb5b8Jeff Garzik 2795fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradleystatic int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 2796fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley{ 2797fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 2798fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRQB_Q_SZ, 0); 2799fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crqb_pool) 2800fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2801fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2802fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 2803fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_CRPB_Q_SZ, 0); 2804fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->crpb_pool) 2805fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2806fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2807fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 2808fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley MV_SG_TBL_SZ, 0); 2809fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (!hpriv->sg_tbl_pool) 2810fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return -ENOMEM; 2811fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2812fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return 0; 2813fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley} 2814fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 281515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhekstatic void mv_conf_mbus_windows(struct mv_host_priv *hpriv, 281615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_target_info *dram) 281715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek{ 281815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek int i; 281915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 282015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < 4; i++) { 282115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_CTRL(i)); 282215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(0, hpriv->base + WINDOW_BASE(i)); 282315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 282415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 282515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek for (i = 0; i < dram->num_cs; i++) { 282615a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek struct mbus_dram_window *cs = dram->cs + i; 282715a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 282815a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(((cs->size - 1) & 0xffff0000) | 282915a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (cs->mbus_attr << 8) | 283015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek (dram->mbus_dram_target_id << 4) | 1, 283115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek hpriv->base + WINDOW_CTRL(i)); 283215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek writel(cs->base, hpriv->base + WINDOW_BASE(i)); 283315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek } 283415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek} 283515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 2836f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/** 2837f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_probe - handle a positive probe of an soc Marvell 2838f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * host 2839f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device found 2840f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2841f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * LOCKING: 2842f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Inherited from caller. 2843f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2844f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev) 2845f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2846f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara static int printed_version; 2847f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct mv_sata_platform_data *mv_platform_data; 2848f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct ata_port_info *ppi[] = 2849f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara { &mv_port_info[chip_soc], NULL }; 2850f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host; 2851f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct mv_host_priv *hpriv; 2852f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct resource *res; 2853f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara int n_ports, rc; 285420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2855f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!printed_version++) 2856f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 2857bca1c4eb9411533d613123618c0d127fae532595Jeff Garzik 2858f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 2859f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Simple resource validation .. 2860f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2861f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (unlikely(pdev->num_resources != 2)) { 2862f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_err(&pdev->dev, "invalid number of resources\n"); 2863f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 2864f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara } 2865f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2866f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* 2867f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * Get the register base first 2868f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2869f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2870f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (res == NULL) 2871f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -EINVAL; 2872f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2873f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* allocate host */ 2874f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara mv_platform_data = pdev->dev.platform_data; 2875f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara n_ports = mv_platform_data->n_ports; 2876f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2877f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 2878f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 2879f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2880f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (!host || !hpriv) 2881f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return -ENOMEM; 2882f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->private_data = hpriv; 2883f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 2884f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2885f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->iomap = NULL; 2886f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara hpriv->base = devm_ioremap(&pdev->dev, res->start, 2887f1cb0ea12fee23018ad1865bf789cbd463f13747Saeed Bishara res->end - res->start + 1); 2888f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base -= MV_SATAHC0_REG_BASE; 2889f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 289015a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek /* 289115a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek * (Re-)program MBUS remapping windows if we are asked to. 289215a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek */ 289315a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek if (mv_platform_data->dram != NULL) 289415a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek mv_conf_mbus_windows(hpriv, mv_platform_data->dram); 289515a32632d94011911497052a96cdbf3b905b325dLennert Buytenhek 2896fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley rc = mv_create_dma_pools(hpriv, &pdev->dev); 2897fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley if (rc) 2898fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley return rc; 2899fbf14e2f2d674e6a2ff0fb2aa569e7f6687483a3Byron Bradley 2900f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara /* initialize adapter */ 2901f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = mv_init_host(host, chip_soc); 2902f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc) 2903f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 2904f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2905f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara dev_printk(KERN_INFO, &pdev->dev, 2906f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, 2907f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara host->n_ports); 2908f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2909f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, 2910f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara IRQF_SHARED, &mv6_sht); 2911f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara} 2912f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2913f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara/* 2914f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2915f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_platform_remove - unplug a platform interface 2916f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * @pdev: platform device 2917f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * 2918f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * A platform bus SATA device has been unplugged. Perform the needed 2919f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * cleanup. Also called on module unload for any active devices. 2920f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara */ 2921f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev) 2922f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara{ 2923f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct device *dev = &pdev->dev; 2924f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara struct ata_host *host = dev_get_drvdata(dev); 2925f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2926f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara ata_host_detach(host); 2927f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return 0; 292820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 292920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 2930f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic struct platform_driver mv_platform_driver = { 2931f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_platform_probe, 2932f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .remove = __devexit_p(mv_platform_remove), 2933f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .driver = { 2934f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .name = DRV_NAME, 2935f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .owner = THIS_MODULE, 2936f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara }, 2937f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara}; 2938f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 2939f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 29407bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 2941f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 2942f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent); 2943f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 29447bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29457bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic struct pci_driver mv_pci_driver = { 29467bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .name = DRV_NAME, 29477bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .id_table = mv_pci_tbl, 2948f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara .probe = mv_pci_init_one, 29497bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara .remove = ata_pci_remove_one, 29507bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara}; 29517bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29527bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* 29537bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara * module options 29547bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara */ 29557bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int msi; /* Use PCI msi; either zero (off, default) or non-zero */ 29567bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29577bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29587bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara/* move to PCI layer or libata core? */ 29597bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bisharastatic int pci_go_64(struct pci_dev *pdev) 29607bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara{ 29617bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc; 29627bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29637bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 29647bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 29657bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29667bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 29677bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29687bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 29697bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "64-bit DMA enable failed\n"); 29707bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29717bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29727bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29737bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } else { 29747bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 29757bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29767bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 29777bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit DMA enable failed\n"); 29787bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29797bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29807bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 29817bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara if (rc) { 29827bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara dev_printk(KERN_ERR, &pdev->dev, 29837bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara "32-bit consistent DMA enable failed\n"); 29847bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29857bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29867bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara } 29877bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 29887bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 29897bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara} 29907bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara 299105b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 299205b308e1df6d9d673daedb517969241f41278b52Brett Russ * mv_print_info - Dump key info to kernel log for perusal. 29934447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo * @host: ATA host to print info about 299405b308e1df6d9d673daedb517969241f41278b52Brett Russ * 299505b308e1df6d9d673daedb517969241f41278b52Brett Russ * FIXME: complete this. 299605b308e1df6d9d673daedb517969241f41278b52Brett Russ * 299705b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 299805b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 299905b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 30004447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heostatic void mv_print_info(struct ata_host *host) 300131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ{ 30024447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct pci_dev *pdev = to_pci_dev(host->dev); 30034447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv = host->private_data; 300444c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok u8 scc; 3005c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik const char *scc_s, *gen; 300631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 300731961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Use this to determine the HW stepping of the chip so we know 300831961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ * what errata to workaround 300931961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ */ 301031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 301131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ if (scc == 0) 301231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "SCSI"; 301331961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else if (scc == 0x01) 301431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s = "RAID"; 301531961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ else 3016c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik scc_s = "?"; 3017c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik 3018c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik if (IS_GEN_I(hpriv)) 3019c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "I"; 3020c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_II(hpriv)) 3021c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "II"; 3022c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else if (IS_GEN_IIE(hpriv)) 3023c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "IIE"; 3024c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik else 3025c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen = "?"; 302631961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 3027a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, 3028c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 3029c1e4fe711a410a139095e6b3e3ce3f07f466063cJeff Garzik gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 303031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 303131961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ} 303231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ 303305b308e1df6d9d673daedb517969241f41278b52Brett Russ/** 3034f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara * mv_pci_init_one - handle a positive probe of a PCI Marvell host 303505b308e1df6d9d673daedb517969241f41278b52Brett Russ * @pdev: PCI device found 303605b308e1df6d9d673daedb517969241f41278b52Brett Russ * @ent: PCI device ID entry for the matched host 303705b308e1df6d9d673daedb517969241f41278b52Brett Russ * 303805b308e1df6d9d673daedb517969241f41278b52Brett Russ * LOCKING: 303905b308e1df6d9d673daedb517969241f41278b52Brett Russ * Inherited from caller. 304005b308e1df6d9d673daedb517969241f41278b52Brett Russ */ 3041f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_pci_init_one(struct pci_dev *pdev, 3042f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara const struct pci_device_id *ent) 304320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 30442dcb407e61458ded17503d6bd12b8c064965368bJeff Garzik static int printed_version; 304520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ unsigned int board_idx = (unsigned int)ent->driver_data; 30464447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 30474447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct ata_host *host; 30484447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo struct mv_host_priv *hpriv; 30494447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo int n_ports, rc; 305020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3051a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik if (!printed_version++) 3052a9524a76f70f3343e4be27f95a7e92a8ba5f9009Jeff Garzik dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 305320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30544447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* allocate host */ 30554447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 30564447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 30574447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 30584447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 30594447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo if (!host || !hpriv) 30604447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return -ENOMEM; 30614447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->private_data = hpriv; 3062f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->n_ports = n_ports; 30634447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo 30644447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo /* acquire resources */ 306524dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo rc = pcim_enable_device(pdev); 306624dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 306720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ return rc; 306820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30690d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 30700d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc == -EBUSY) 307124dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo pcim_pin_device(pdev); 30720d5ff566779f894ca9937231a181eb31e4adff0eTejun Heo if (rc) 307324dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 30744447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo host->iomap = pcim_iomap_table(pdev); 3075f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara hpriv->base = host->iomap[MV_PRIMARY_BAR]; 307620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3077d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik rc = pci_go_64(pdev); 3078d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik if (rc) 3079d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik return rc; 3080d88184fb2348a50f7c34f5d49a901c875b2e0114Jeff Garzik 3081da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord rc = mv_create_dma_pools(hpriv, &pdev->dev); 3082da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord if (rc) 3083da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord return rc; 3084da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0eMark Lord 308520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ /* initialize adapter */ 30864447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo rc = mv_init_host(host, board_idx); 308724dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo if (rc) 308824dc5f33ea4b504cfbd23fa159a4cacba8e4d800Tejun Heo return rc; 308920f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 309031961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ /* Enable interrupts */ 30916a59dcf8678cbc4106a8a6e158d7408a87691358Tejun Heo if (msi && pci_enable_msi(pdev)) 309231961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ pci_intx(pdev, 1); 309320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 309431961943e3110c5a1c36b1e0069c29f7c4380e51Brett Russ mv_dump_pci_cfg(pdev, 0x68); 30954447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo mv_print_info(host); 309620f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 30974447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo pci_set_master(pdev); 3098ea8b4db97aa41a66c05daa4055a1974692ccd52dJeff Garzik pci_try_set_mwi(pdev); 30994447d35156169cf136e829eb6b5cac2d6370f2d9Tejun Heo return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 3100c5d3e45a2200a0905dc45b72714726b7aac3aaf1Jeff Garzik IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 310120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 31027bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 310320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 3104f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int mv_platform_probe(struct platform_device *pdev); 3105f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bisharastatic int __devexit mv_platform_remove(struct platform_device *pdev); 3106f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 310720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic int __init mv_init(void) 310820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 31097bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara int rc = -ENODEV; 31107bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 31117bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara rc = pci_register_driver(&mv_pci_driver); 3112f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 3113f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara return rc; 3114f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#endif 3115f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara rc = platform_driver_register(&mv_platform_driver); 3116f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara 3117f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara#ifdef CONFIG_PCI 3118f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara if (rc < 0) 3119f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara pci_unregister_driver(&mv_pci_driver); 31207bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 31217bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara return rc; 312220f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 312320f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 312420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russstatic void __exit mv_exit(void) 312520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ{ 31267bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 312720f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ pci_unregister_driver(&mv_pci_driver); 31287bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 3129f351b2d638c3cb0b95adde3549b7bfaf3f991dfaSaeed Bishara platform_driver_unregister(&mv_platform_driver); 313020f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ} 313120f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 313220f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_AUTHOR("Brett Russ"); 313320f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 313420f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_LICENSE("GPL"); 313520f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_DEVICE_TABLE(pci, mv_pci_tbl); 313620f733e7d75a16bffc34842b7682c9247dd5f954Brett RussMODULE_VERSION(DRV_VERSION); 313717c5aab5b34e351531466e35b154ca86db7d46a9Mark LordMODULE_ALIAS("platform:" DRV_NAME); 313820f733e7d75a16bffc34842b7682c9247dd5f954Brett Russ 31397bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#ifdef CONFIG_PCI 3140ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzikmodule_param(msi, int, 0444); 3141ddef9bb367b19383df627e388cb4c01c86ddba6cJeff GarzikMODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 31427bb3c5290ca0ec9e65947c907495c2b56e895e46Saeed Bishara#endif 3143ddef9bb367b19383df627e388cb4c01c86ddba6cJeff Garzik 314420f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_init(mv_init); 314520f733e7d75a16bffc34842b7682c9247dd5f954Brett Russmodule_exit(mv_exit); 3146